KR20180074169A - Shift register and display apparatus comprising the same - Google Patents

Abstract

The present invention provides a shift register having a reduced circuit area and a display device including the same. The shift register comprises first to m^th stages which are driven by a gate start signal and sequentially output two output signals, wherein each of the first to m^th stages includes a first node, a second node and a third node which have voltage levels different from a voltage level of the first node, a node controller which controls a first node voltage and a second node voltage, a signal output circuit which sequentially outputs two clock signals to first and second output nodes according to the first node voltage, a first discharge circuit which sequentially discharges voltages of the first output node and the second output node according to the second node voltage and a third node voltage, and a second discharge circuit which discharges the first node voltage according to the third node voltage of the third node.

Description

[0001] SHIFT REGISTER AND DISPLAY APPARATUS INCLUDING THE SAME [0002]

The present application relates to a shift register and a display device including the shift register.

In recent years, the importance of display devices has been increasing with the development of multimedia. In response to this, flat panel display devices such as a liquid crystal display device, an organic light emitting display device, and a light emitting diode display device have been commercialized. Among such flat panel display devices, the liquid crystal display device and the organic light emitting display device are excellent in characteristics such as thinness, light weight, and low power consumption, and thus they can be used as electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, UMPC A portable electronic device such as a mobile phone, a smart phone, a smart watch, a personal computer, a watch phone, and a mobile communication terminal as well as a display of a television, a notebook, It is widely used as a screen.

The liquid crystal display device and the organic light emitting display device may include a display panel including a plurality of pixels having a thin film transistor connected to a data line and a gate line, a data driving circuit for supplying a data voltage to the data line, And a gate driver circuit composed of a shift register for supplying the gate driver.

Typically, the data driving circuit and the gate driving circuit are implemented as an integrated circuit, and each of the data integrated circuit and the gate integrated circuit is mounted on a flexible circuit film such as a tape carrier package or a chip on film And is attached to the display panel.

Recently, in order to simplify the structure of the circuit components, reduce the manufacturing cost, and reduce the width of the bezel, transistors of the shift registers constituting the gate driving circuit simultaneously with the manufacturing process of the thin film transistor of each pixel, A display device of a GIP (Gate In Panel) structure built in a non-display area of the display device is used.

1 is a view for explaining a shift register of a general GIP structure.

1, a shift register of a general GIP structure is selectively connected to first to fourth clock signal lines to which first to fourth clock signals CLK1 to CLK4 are supplied, And n stages (ST1 to STn) driven in a dependent manner.

The gate start signal Vst is supplied to the first stage ST1. Each of the second to n-th stages ST2 to STn receives the output signal of the previous single stage ST1 to STn-1 as the gate start signal Vst.

Each of the n stages ST1 to STn is switched according to the voltage of the first node and receives only one of the first to fourth clock signals CLK1 to CLK4 to generate a gate- Down thin film transistor which is switched in accordance with the voltage of the first node to discharge the voltage charged in the gate line GL and a pull-down thin film transistor which is turned on in response to the voltage of the first node and the second node And a node control section composed of a plurality of thin film transistors for node control.

Each of the n stages ST1 to STn receives the gate start signal Vst as a start signal and outputs the first to the n th stages ST1 to STn through a pull- Down which is turned on according to the voltage of the second node under the control of the node controller after supplying a gate signal corresponding to one of the clock signals CLK1 to CLK4 to the corresponding gate line GL, And discharges the charged voltage of the corresponding gate line GL to the low potential driving voltage VSS through the thin film transistor.

Such a shift register of a general GIP structure, a gate driving circuit including the shift register, and a display device have the following problems.

First, since one output signal is output in one stage, the area occupied by the gate driving circuit increases, thereby increasing the bezel width of the display panel.

Secondly, when amorphous silicon is used as a semiconductor layer of a thin film transistor constituting a shift register, the size of the thin film transistor increases due to the low current movement of the amorphous silicon, thereby further increasing the area occupied by the gate driving circuit. The width of the bezel of the display panel is further increased.

Third, in the case of a pull-up thin film transistor having a semiconductor layer made of amorphous silicon, due to the threshold voltage shift of the pull-up thin film transistor due to bias temperature stress, The driving reliability of the integrated circuit lowers.

SUMMARY OF THE INVENTION The present invention provides a shift register having a reduced circuit area and a display device including the shift register.

It is another object of the present invention to provide a shift register in which deterioration of a pull-up thin film transistor can be prevented and a display device including the shift register.

According to an aspect of the present invention, there is provided a shift register including a first to an m-th stages that are driven by a gate start signal and sequentially output two output signals, A second node and a third node having different voltage levels from the first node, a node controller for controlling a first node voltage and a second node voltage, and a second node voltage generator for sequentially generating two clock signals according to the first node voltage A first discharging circuit for sequentially discharging the voltages of the first output node and the second output node in accordance with the voltages of the second node voltage and the third node, And a second discharging circuit for discharging the voltage of the first node according to the third node voltage of the node.

According to an aspect of the present invention, there is provided a shift register including a display panel including a plurality of gate lines and a plurality of data lines, a data driving circuit for converting input pixel data into a plurality of data lines, And a gate driving circuit having a shift register for supplying a gate signal to each of the plurality of gate lines, wherein the shift register is driven by a gate start signal, and the first to m-th Wherein each of the first through m-th stages includes a first node, a second node and a third node having different voltage levels from the first node, a node controller controlling the first node voltage and the second node voltage, A signal output that sequentially outputs two clock signals to the first and second output nodes according to the voltage of one node A first discharging circuit for sequentially discharging the voltages of the first output node and the second output node according to the second node voltage and the voltage of the third node and a second discharging circuit for sequentially discharging the voltages of the first node and the second node according to the third node voltage of the third node, And a second discharging circuit for discharging the voltage of the second discharging circuit.

In one example, the second node of the stage 2i-1 (i is a natural number from 1 to m / 2) of the first through m-th stages is connected to the third node of the second i- The third node of the stage and the second node of the second i stage are connected to each other.

In one example, each of the first through m-th stages may receive two clock signals sequentially shifted out of four sequentially shifted clock signals.

In one example, each of the four clock signals cyclically repeats a cycle of a gate-on voltage level of one horizontal period and a gate-off voltage level of three horizontal periods, and the first clock signal of the four clock signals is synchronized with the gate- The phase difference of the period can be obtained.

According to the solution of the above problem, the shift register according to the present application and the display device including the shift register can reduce the number of stages, thereby reducing the circuit area, The threshold voltage shift of the up-film transistor can be minimized.

In addition to the effects of the present application discussed above, other features and advantages of the present application will be set forth below, or may be apparent to those skilled in the art to which the present application belongs from such description and description.

1 is a view for explaining a shift register of a general GIP structure.
2 is a view for explaining a shift register according to an example of the present application.
FIG. 3 is a circuit diagram showing the configurations of the (2i-1) th and the (2i) th stages of the plurality of stages shown in FIG.
4 is a driving waveform diagram for forward driving of the 2 < i-1 > and 2 < i > stages shown in Fig.
Fig. 5 is a driving waveform diagram for reverse driving of the (2i-1) th and (2i-th) stages shown in Fig.
6 is a view schematically showing a display device according to an example of the present application.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, And the scope of the invention is to be defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, preferred embodiments of a shift register and a display device including the shift register according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the constituent elements of the drawings, the same constituent elements may have the same sign as possible even if they are displayed on different drawings

2 is a view for explaining a shift register according to an example of the present application.

Referring to FIG. 2, a shift register according to an exemplary embodiment is embedded in a display panel of a display device. The shift register includes first through m-th (m) -th shift registers sequentially outputting two output signals sequentially shifted using two clock signals shifted sequentially And stages ST [1] to ST [m].

The first to m-th stages ST [1] to ST [m] selectively connect to the first to fourth clock signal lines to which the first to fourth clock signals CLK1 to CLK4 are sequentially shifted And outputs two output signals which are successively shifted by being driven depending on the gate start signal.

The gate start signal has a first voltage level and a second voltage level lower than the first voltage level as a signal indicating the start of one frame at the time of driving the display panel. At this time, the gate start signal of the first voltage level has a pulse width corresponding to one horizontal period of the display panel. The gate start signal is divided into a forward gate start signal Vst1 and a reverse gate start signal Vst2 according to the driving direction of the display panel. The forward gate start signal Vst1 is supplied to the first stage ST [1] and the reverse gate start signal Vst2 is supplied to the m-th stage ST [m]. Each of the second to m-th stages ST [2] to ST [m] receives the first output signal of the previous single stage as a gate start signal, and supplies the second output signal of the next stage as a reset signal Receive. As described above, each of the forward gate start signal Vst1 and the reverse gate start signal Vst2 has a phase difference between the first clock signal CLK1 and one horizontal period.

Each of the first to fourth clock signals CLK1 to CLK4 has a gate-on voltage level having a pulse width corresponding to one horizontal period of the display panel and a pulse width corresponding to three horizontal periods of the display panel, Cycle repeatedly. That is, one period of each of the first to fourth clock signals CLK1 to CLK4 is composed of a gate-on voltage level of one horizontal period and a gate-off voltage level of three horizontal periods. The phase of each of the first to fourth clock signals CLK1 to CLK4 is shifted by one horizontal period unit. Accordingly, the rising edge of the second clock signal CLK2 is the falling edge of the first clock signal CLK1, the rising edge of the third clock signal CLK3 is the falling edge of the falling edge of the second clock signal CLK2, The rising edge of the fourth clock signal CLK4 may be synchronized with the rising edge of the third clock signal CLK3 and the falling edge of the fourth clock signal CLK4 may be synchronized with the rising edge of the first clock signal CLK1, have.

The gate-on voltage level according to an example may be set to a voltage level for turning on the thin film transistor provided in the pixel of the display panel. The gate-off voltage level according to an example may be set to a voltage level for turning off the thin-film transistor provided in the pixel.

Each of the first to m-th stages ST [1] to ST [m] includes a first driving voltage Vdd1, a second driving voltage Vdd2, a forward driving voltage FWD, a reverse driving voltage BWD, And the low potential driving voltage Vss, respectively.

The first driving voltage Vdd1 has a high voltage level during a first driving period and a low voltage level during a second driving period. Here, each of the first driving period and the second driving period of the first driving voltage Vdd1 may be set to at least one frame or more. The first driving voltage Vdd1 is supplied to each of the first to m-th stages ST [1] to ST [m] through the first driving voltage line.

The second driving voltage Vdd2 has a voltage level opposite to the first driving voltage Vddl. For example, during the first driving period of the first driving voltage Vdd1, the second driving voltage Vdd2 has a low voltage level, and during the second driving period of the first driving voltage Vdd1, the second driving voltage Vdd2 Has a high voltage level. This second driving voltage Vdd2 is supplied to each of the first to m-th stages ST [1] to ST [m] through the second driving voltage line.

The forward driving voltage FWD has a gate-on voltage level or a gate-off voltage level according to a driving direction of a shift register according to a video display direction of the display panel. For example, the forward driving voltage FWD has a gate-on voltage level when the shift register is forward-driven and has a gate-off voltage level when the shift register is reverse-driven. This forward driving voltage FWD is supplied to each of the first to m-th stages ST [1] to ST [m] through the forward driving voltage line.

The reverse driving voltage BWD has a voltage level opposite to the forward driving voltage FWD. For example, the reverse drive voltage BWD has a gate-on voltage level when the shift register is driven backward and has a gate-off voltage level when the shift register is driven in a positive direction. This reverse drive voltage BWD is supplied to each of the first to m-th stages ST [1] to ST [m] via the reverse drive voltage line.

The low-potential driving voltage Vss may have a voltage level or a gate-off voltage level that is relatively lower than the first and second driving voltages Vdd1 and Vdd2. This low potential driving voltage Vss is supplied to each of the first to m-th stages ST [1] to ST [m] via the low potential driving voltage supply line.

Each of the first to m-th stages ST [1] to ST [m] successively outputs two output signals sequentially shifted by using two clock signals shifted by one horizontal period.

The first stage ST [1] is driven by the gate start signal Vst and generates the first and second clock signals CLK1 and CLK2 using the first and second clock signals CLK1 and CLK2. And sequentially supplies the respective gate-on voltage levels to the first and second gate lines as first and second gate signals.

The second stage ST [2] receives the second gate signal output from the first stage ST [1] as the gate start signal Vst and starts driving, and the third and fourth clock signals CLK3 , And CLK4 to sequentially supply the gate-on voltage levels of the third and fourth clock signals CLK3 and CLK4 to the third and fourth gate lines as the third and fourth gate signals, respectively.

As a result, each of the stages 2i-1 (where i is a natural number from 1 to m / 2) of the first to m-th stages ST [1] to ST [m] The gate signal is sequentially supplied to the (4i-3) th and (4i-2) th gate lines using the clock signals CLK1 and CLK2. Each of the second i stages of the first through m-th stages ST1 through STm sequentially supplies the gate signal to the 4i-1 and 4i gate lines using the third and fourth clock signals CLK3 and CLK4 do.

FIG. 3 is a circuit diagram showing the configurations of the (2i-1) th and the (2i) th stages of the plurality of stages shown in FIG.

M] stages ST [1] to ST [2i], taking the example of the second i-1 and the second stage ST [2i-1] m] will be described as follows.

Each of the first through m-th stages ST [1] through ST [m] according to an example includes a first node Q1, a second node Q2, a third node Q3, (130), a first discharge circuit (150), and a second discharge circuit (170).

The first node Q1 is for switching the signal output circuit 130 for sequentially outputting two clock signals shifted by one horizontal period to the first output node No1 and the second output node No2 Is used.

The second node Q2 is used for switching the first discharging circuit 150 to supply the low potential driving voltage Vss to the first output node No1 and the second output node No2, respectively.

The third node Q3 is used for switching the second discharging circuit 170 to supply the low potential driving voltage Vss to the first node Q1.

The second node Q2 of the second i-th stage ST [2i-1] of the first to m-th stages ST [1] to ST [m] The third node Q3 is connected to each other. The third node Q3 of the second i-1 stage ST [2i-1] and the second node Q2 of the second i-th stage ST [2i] are connected to each other. That is, the second node Q2 of the second i-1 stage ST [2i-1] is shared with the third node Q3 of the second i-th stage ST [2i] The third node Q3 of the first i-th stage [2i-1] is shared with the second node Q2 of the second i-th stage ST [2i].

The node control unit controls the first node voltage of the first node (Q1) and the second node voltage of the second node (Q2), respectively. Each of the node controllers of the first to m-th stages ST [1] to ST [m] according to an example has a first node controller 111 for controlling the first node voltage of the first node Q1, And a second node controller 113 for controlling the second node voltage of the node Q2.

The first node controller 111 of each of the first to m-th stages ST [1] to ST [m] includes a first switching circuit 111a and a second switching circuit 111b.

The first switching circuit 111a according to the example has the output signals GP [4i-5] and GP [4i-3] supplied from the forward gate start signal Vst1 or the first output node No1 of the previous single stage, And supplies the forward driving voltage FWD to the first node No1 in response to the first control signal. The first switching circuit 111a according to an example includes a first transistor T1.

The first transistor T1 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The first transistor T1 according to an example includes a gate electrode for receiving a gate start signal, a drain electrode for receiving a forward driving voltage FWD, and a source electrode connected to the first node Q1. This first transistor T1 is connected to the output signals GP [4i-5] and GP [4i-3] of the gate-on voltage level supplied from the forward gate start signal Vst1 or the first output node No1 of the previous single stage, ] To supply the forward driving voltage FWD to the first node Q1 to precharge the first node Q1 to the forward driving voltage FWD during the forward precharging period of each stage.

The second switching circuit 111b outputs the second node voltage of the second node Q2 and the output signals GP [4i], GP [4i + 2] supplied from the second output node No2 of the next stage, And controls the voltage of the first node (Q1). The second switching circuit 111b according to an example includes a second transistor T2 and a third transistor T3.

The second transistor T2 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The second transistor T2 according to an example includes a gate electrode connected to the second node Q2, a drain electrode connected to the first node Q1, and a source electrode connected to the low potential voltage line LVL. The second transistor T2 is turned on in response to the second node voltage of the second node Q2 to supply the low potential driving voltage Vss to the first node Q1 or the first node Q1 And discharges the first node voltage of the first node Q1 to the low potential voltage line LVL by connecting to the potential voltage line LVL.

The third transistor T3 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The third transistor T3 according to an example has a gate electrode receiving the output signals GP [4i], GP [4i + 2] supplied from the second output node No2 of the next stage, And a source electrode for receiving a reverse driving voltage (BWD). The third transistor T3 is turned on according to the output signals GP [4i] and GP [4i + 2] of the gate-on voltage level supplied from the second output node No2 of the next stage, The first node Q1 is precharged to the backward driving voltage BWD or the voltage of the first node Q1 is discharged by supplying the voltage BWD to the first node Q1.

The second node controller 113 of each of the first to m-th stages ST [1] to ST [m] includes a third switching circuit 113a and a fourth switching circuit 113b.

The third switching circuit 113a of the second i-1 stage ST [2i-1] is turned on in response to the first node voltage of the first node Q1 and the first driving voltage Vdd1, ). The third switching circuit 113a of the second i-1 stage ST [2i-1] according to an example may be an inverter circuit. For example, the third switching circuit 113a of the second i-1 stage ST [2i-1] includes the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, And a transistor T7.

The fourth transistor T4 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The fourth transistor T4 according to an example includes a gate electrode and a drain electrode connected together to the first driving voltage line DPL1, and a source electrode connected to the internal node Ni. That is, the fourth transistor T4 may be a diode-type transistor connected in a diode form to the first driving voltage line DPL1. The fourth transistor T4 outputs the first driving voltage Vdd1 to the internal node Ni according to the first driving voltage Vdd1.

The fifth transistor T5 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The fifth transistor T5 according to an example includes a gate electrode connected to the internal node Ni, a drain electrode connected to the first driving voltage line DPL1, and a source electrode connected to the second node Q2. The fifth transistor T5 is turned on according to the voltage of the internal node Ni to output the first driving voltage Vdd1 to the second node Q2.

The fourth transistor T4 and the fifth transistor T5 have the same size.

The sixth transistor T6 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The sixth transistor T6 according to an example includes a gate electrode connected to the first node Q1, a drain electrode connected to the internal node Ni, and a source electrode on the low potential voltage line LVL. The sixth transistor T6 is turned on according to the first node voltage of the first node Q1 to connect the internal node Ni to the low potential voltage line LVL, Discharges to the potential voltage line LVL, thereby turning off the fifth transistor T5.

The sixth transistor T6 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The sixth transistor T6 according to an example includes a gate electrode connected to the first node Q1, a drain electrode connected to the second node Q2, and a source electrode on the low potential voltage line LVL. The sixth transistor T6 is turned on according to the first node voltage of the first node Q1 to connect the second node Q2 to the low potential voltage line LVL, To the low potential voltage line (LVL), thereby setting the voltage of the second node (Q2) to the low potential driving voltage (Vss).

The sixth transistor T6 and the sixth transistor T6 have the same size and a relatively larger size than the fourth transistor T4 and the fifth transistor T5, respectively.

The third switching circuit 113a of the second i-th stage ST [2i] is connected to the fourth to seventh transistors (i) and (ii) similarly to the third switching circuit 113a of the second i- T4, T5, T6 and T7, and the second and fourth transistors T4 and T5 are supplied with the second driving voltage Vdd2. Thus, the third switching circuit 113a of the second i-th stage ST [2i] is turned on in response to the first node voltage of the first node Q1 and the second driving voltage Vdd2, Is the same as the third switching circuit 113a of the (2i-1) th stage ST [2i-1] except that the voltage is controlled, so a duplicate description thereof will be omitted.

The fourth switching circuit 113b of the second i-1 stage ST [2i-1] outputs the voltage of the second node Q2 in response to the first node voltage and the second driving voltage Vdd2 of the next stage, . The fourth switching circuit 113b of the second i-1 stage ST [2i-1] according to an example includes the eighth transistor T8 and the ninth transistor T9.

The eighth transistor T8 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The eighth transistor T8 according to an example includes a gate electrode connected to the first node Q1 of the next stage, a drain electrode connected to the second node Q2, and a source electrode connected to the low potential voltage line LVL do. The eighth transistor T8 is turned on in accordance with the first node voltage of the first node Q1 of the next stage to connect the second node Q2 to the low potential voltage line LVL, Q2 to the low potential voltage line LVL, thereby setting the voltage of the second node Q2 to the low potential driving voltage Vss.

The ninth transistor T9 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The ninth transistor T9 according to an example includes a gate electrode connected to the second driving voltage line DPL2, a drain electrode connected to the second node Q2, and a source electrode at the low potential voltage line LVL. The ninth transistor T9 is turned on in accordance with the second driving voltage Vdd2 to connect the second node Q2 to the low potential voltage line LVL to turn the voltage of the second node Q2 to the low potential voltage Line LVL, thereby setting the voltage of the second node Q2 to the low potential driving voltage Vss.

The fourth switching circuit 113b of the second i-th stage ST [2i] is connected to the eighth and ninth transistors (n-1, n-2) similarly to the fourth switching circuit 113b of the The gate electrode of the eighth transistor T8 is connected to the first node Q1 of the previous stage and the first driving voltage Vdd1 is connected to the gate electrode of the ninth transistor T9 . Thus, the fourth switching circuit 113b of the second i-th stage ST [2i] is turned on in response to the first node voltage of the first node Q1 of the previous single stage and the first driving voltage Vdd1, Is the same as the fourth switching circuit 113b of the (2i-1) th stage ST [2i-1] except that the voltage of the second switching transistor Q2 is controlled. Therefore, redundant description thereof will be omitted.

The signal output circuit 130 of each of the first to m-th stages ST [1] to ST [m] outputs two clock signals according to the first node voltage of the first node Q1 to the first output node No1) and the second output node (No2). The signal output circuit 130 according to an example includes a first output circuit 131 and a second output circuit 133.

The first output circuit 131 of the second i-1 stage ST [2i-1] outputs either one of the two clock signals according to the first node voltage of the first node Q1 to the first output node No1 . For example, the first output circuit 131 outputs the first clock signal CLK1 to the first output node No1 according to the first node voltage of the first node Q1. The first output circuit 131 of the second i-1 stage ST [2i-1] according to an example includes a tenth transistor T10, a first capacitor C1, and an eleventh transistor T11 .

The tenth transistor T10 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The tenth transistor T10 according to an example includes a gate electrode connected to the first capacitor C1, a drain electrode connected to the first gate node Ng1, and a source electrode connected to the first node Q1. This tenth transistor T10 is turned on according to the first node voltage of the first node Q1 to supply the first node voltage of the first node Q1 to the first gate node Ng1, The voltage of the node Ng1 is set to the same voltage level as the first node voltage of the first node Q1.

The first capacitor C1 is connected between the first node Q1 and the gate electrode of the tenth transistor T10. That is, the first capacitor C1 may be provided in the overlap region between the first node Q1 and the gate electrode of the tenth transistor T10, or may be provided in the overlapped region between the gate electrode and the source electrode of the tenth transistor T10. . The first capacitor C1 maintains a constant voltage between the gate electrode and the source electrode of the tenth transistor T10 so that the voltage of the first node Q1 supplied to the first gate node Ng1 through the tenth transistor T10 ) Is kept constant. In particular, the first capacitor C1 biases the eleventh transistor T11, which is a pull-up thin film transistor, only in a part of the period.

The eleventh transistor T11 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The eleventh transistor T11 according to an exemplary embodiment includes a gate electrode connected to the first gate node Ng1, a drain electrode receiving the first clock signal CLK1, and a source electrode connected to the first output node No1 do. The eleventh transistor T11 is a pull-up transistor and is turned on according to the voltage of the first gate node Ng1 to output the first clock signal CLK1 to the first output node No1. In particular, the eleventh transistor T11 is biased only during a part of the period in which the clock signal of the gate-on voltage level is output by the first capacitor C1, so that the shift of the threshold voltage due to the bias temperature stress can be minimized have.

The first output circuit 131 of the second i-th stage ST [2i] is connected to the tenth and eleventh transistors ST1 (2i-1) in the same manner as the first output circuit 131 of the second i- T10 and T11, and outputs the third clock signal CLK3 to the first output node No1 according to the first node voltage of the first node Q1. Thus, the first output circuit 131 of the second i-th stage ST [2i] outputs the third clock signal CLK3 to the first output node No1 according to the first node voltage of the first node Q1 1 stage (ST [2i-1]), except for the output of the first stage (ST [2i-1]).

The second output circuit 133 of the second i-1 stage ST [2i-1] outputs the other one of the two clock signals to the second output node No2 . For example, the second output circuit 133 outputs the second clock signal CLK2 to the second output node No2 in accordance with the first node voltage of the first node Q1. The second output circuit 133 of the second i-1 stage ST [2i-1] according to an example includes a twelfth transistor T12, a second capacitor C2, and a thirteenth transistor T13 .

The twelfth transistor T12 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The twelfth transistor T12 according to an example includes a gate electrode connected to the second capacitor C2, a drain electrode connected to the second gate node Ng2, and a source electrode connected to the first node Q1. The twelfth transistor T12 is turned on according to the first node voltage of the first node Q1 to supply the first node voltage of the first node Q1 to the second gate node Ng2, The voltage of the node Ng2 is set to the same voltage level as the first node voltage of the first node Q1.

The second capacitor C2 is connected between the first node Q1 and the gate electrode of the twelfth transistor T12. That is, the second capacitor C2 may be provided in the overlap region between the first node Q1 and the gate electrode of the twelfth transistor T12, or may be provided in the overlap region between the gate electrode and the source electrode of the twelfth transistor T12. . The second capacitor C2 maintains a constant voltage between the gate electrode and the source electrode of the twelfth transistor T12 so that the first node Q1 supplied to the second gate node Ng2 through the twelfth transistor T12 ) Is kept constant. In particular, the second capacitor C2 biases the thirteenth transistor T13, which is a pull-up thin film transistor, only for a part of the period.

The thirteenth transistor T13 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The thirteenth transistor T13 according to an example includes a gate electrode connected to the second gate node Ng2, a drain electrode receiving the second clock signal CLK2, and a source electrode connected to the second output node No2 do. The thirteenth transistor T13 is a pull-up transistor and is turned on according to the voltage of the second gate node Ng2 to output the second clock signal CLK2 to the second output node No2. In particular, the thirteenth transistor T13 can be biased only by a part of the period of outputting the clock signal of the gate-on voltage level by the second capacitor C2, so that the shift of the threshold voltage due to the bias temperature stress can be minimized.

The second output circuit 133 of the second i-th stage ST [2i] is connected to the twelfth and thirteenth transistors (i < i [pi]) as in the second output circuit 133 of the T12 and T13, and outputs the fourth clock signal CLK4 to the second output node No2 in accordance with the first node voltage of the first node Q1. Thus, the second output circuit 133 of the second i-th stage ST [2i] outputs the fourth clock signal CLK4 to the second output node No2 in accordance with the first node voltage of the first node Q1 1 stage (ST [2i-1]) except for outputting the same as the second output circuit 133 of the (2i-1) th stage ST [2i-1].

The first discharge circuit 150 of each of the first to m-th stages ST [1] to ST [m] is connected between the second node voltage of the second node Q2 and the third node Q2 of the third node Q3, And sequentially discharges the voltages of the first output node No1 and the second output node No2 according to the voltage. The first discharge circuit 150 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17.

The fourteenth transistor T14 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The fourteenth transistor T14 according to an example includes a gate electrode connected to the second node Q2, a drain electrode connected to the first output node No1 and a source electrode on the low potential voltage line LVL. The fourteenth transistor T14 is turned on according to the second node voltage of the second node Q2 to connect the first output node No1 to the low potential voltage line LVL, To the low potential voltage line LVL, thereby setting the voltage of the first output node No1 to the low potential driving voltage Vss.

The fifteenth transistor T15 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The fifteenth transistor T15 according to an example includes a gate electrode connected to the third node Q3, a drain electrode connected to the first output node No1, and a source electrode on the low potential voltage line LVL. The fifteenth transistor T15 is turned on according to the third node voltage of the third node Q3 to connect the first output node No1 to the first output node No1 by connecting the first output node No1 to the low potential voltage line LVL, To the low potential voltage line LVL, thereby setting the voltage of the first output node No1 to the low potential driving voltage Vss.

The fourteenth transistor T14 and the fifteenth transistor T15 are alternately switched or alternately switched to each other so that deterioration due to a bias temperature shift due to a bias temperature stress can be prevented. That is, the threshold voltages of the fourteenth transistor T14 and the fifteenth transistor T15 are shifted in the positive polarity direction in operation and shifted in the negative polarity direction generated in the non-polarity operation mode. Accordingly, each of the fourteenth transistor T14 and the fifteenth transistor T15 is turned on by the threshold voltage shift in the negative direction generated in the non-operating state of the threshold voltage shift in the positive direction generated during the operation. Therefore, in this example, by alternately driving the fourteenth transistor T14 and the fifteenth transistor T15, it is possible to prevent the deterioration of the fourteenth transistor T14 and the fifteenth transistor T15 due to the threshold voltage shift.

The sixteenth transistor T16 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The sixteenth transistor T16 according to an example includes a gate electrode connected to the second node Q2, a drain electrode connected to the second output node No2 and a source electrode on the low potential voltage line LVL. The sixteenth transistor T16 is turned on according to the second node voltage of the second node Q2 to connect the second output node No2 to the low output voltage line LVL, To the low potential voltage line LVL, thereby setting the voltage of the second output node No2 to the low potential driving voltage Vss.

The seventeenth transistor T17 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The seventeenth transistor T17 according to an example includes a gate electrode connected to the third node Q3, a drain electrode connected to the second output node No2, and a source electrode on the low potential voltage line LVL. The seventeenth transistor T17 is turned on according to the third node voltage of the third node Q3 to connect the second output node No2 to the low potential voltage line LVL, To the low potential voltage line LVL, thereby setting the voltage of the second output node No2 to the low potential driving voltage Vss.

The sixteenth transistor T16 and the seventeenth transistor T17 are alternately switched or alternately switched to each other so that deterioration due to threshold voltage shift due to bias temperature stress can be prevented. That is, the threshold voltages of the sixteenth transistor T16 and the seventeenth transistor T17 are shifted in the positive polarity direction in operation and shifted in the negative polarity direction generated in the non-polarity operation mode. Accordingly, each of the sixteenth transistor T16 and the seventeenth transistor T17 is turned on by the threshold voltage shift in the negative direction generated in the non-operating state of the threshold voltage shift in the positive direction generated during operation. Therefore, in this example, by alternately driving the sixteenth transistor T16 and the seventeenth transistor T17, it is possible to prevent the deterioration of the sixteenth transistor T16 and the seventeenth transistor T17 due to the threshold voltage shift.

The second discharge circuit 170 of each of the first to m-th stages ST [1] to ST [m] supplies the voltage of the first node Q1 according to the third node voltage of the third node Q3 Discharge. The second discharge circuit 170 according to an example includes the eighteenth transistor T18.

First, the third node Q3 of the second i-1 stage ST [2i-1] is connected to the second node Q2 of the second i-th stage ST [2i] The third node Q3 of the first stage [2i] is connected to the second node Q2 of the second i-1 stage ST [2i-1]. Accordingly, in this example, the configuration of the node control unit for controlling the third node voltages of the first to m-th stages ST [1] to ST [m] can be omitted, .

The eighteenth transistor T18 may be an amorphous thin film transistor including a semiconductor layer made of amorphous silicon. The 18th transistor T18 according to an example includes a gate electrode connected to the third node Q3, a drain electrode connected to the first node Q1, and a source electrode on the low potential voltage line LVL. The eighteenth transistor T18 is turned on according to the third node voltage of the third node Q3 to connect the first node Q1 to the low potential voltage line LVL, To the low potential voltage line (LVL), thereby setting the voltage of the first node (Q1) to the low potential driving voltage (Vss).

4 is a driving waveform diagram for forward driving of the 2 < i-1 > and 2 < i > stages shown in Fig.

The forward driving method of the (2i-1) th and (2i) th stages will be described with reference to FIGS. 3 and 4 as follows.

Each of the second i-1 and second i-th stages ST [2i-1] and ST [2i] operates in the first to eighth periods t1 to t8 and is shifted by one horizontal period of the display panel (GP [4i-3], GP [4i-2]), GP [4i-1] and GP [4i]).

In the forward driving, the first driving voltage Vdd1 is a high voltage level VH, the second driving voltage Vdd2 is a low voltage level VL, the forward driving voltage FWD is a gate-on voltage level Von, And the reverse driving voltage BWD may be set to the gate-off voltage level Voff, respectively.

During the first period t1, in the second i-1 stage ST [2i-1], the forward gate start signal Vst1 having the gate-on voltage level or the first output signal GP [4i The first node Q1 of the first node controller 111 is turned on according to the gate-on voltage level Von supplied through the first transistor T1 And is precharged with the forward drive voltage FWD. The first gate node Ng1 of the first signal output unit 131 is connected to the first node Q1 supplied through the tenth transistor T10 turned on by the precharging voltage of the first node Q1 And the second gate node Ng2 of the second signal output section 133 is charged with the same voltage as the precharging voltage and the twelfth transistor T12 turned on by the precharging voltage of the first node Q1 Is charged to the same voltage as the precharging voltage of the first node (Q1) supplied through the first node (Q1). Accordingly, the eleventh transistor T11 of the first signal output unit 131 is turned on by the voltage precharged to the first gate node Ng1, thereby generating the first clock signal (Voff) having the gate- CLK1 to the first output node No1 and at the same time the thirteenth transistor T13 of the second signal output section 133 is turned on by the precharged voltage to the second gate node Ng2 And outputs the second clock signal CLK2 having the gate-off voltage Voff to the second output node No2. The first clock signal CLK1 of the gate-off voltage level Voff output to the first output node No1 is supplied to the corresponding gate line as the (4i-3) th gate signal GP [4i-3] The second clock signal CLK2 of the gate-off voltage level Voff output to the second output node No2 is supplied to the corresponding gate line as the (4i-2) th gate signal GP [4i-2].

In the first period t1, the second node Q2 of the second i-1 stage ST [2i-1] is turned on in response to the first drive voltage Vdd1 of the high voltage level VH, Is held at the low potential driving voltage (Vss) because it is connected to the low potential voltage line (LVL) by the third switching 113a of the node control unit 113. [ The second node Q2 of the second i stage ST2i is connected to the ninth transistor T3 of the second node controller 113 turned on by the first driving voltage Vdd1 of the high voltage level VH T9 of the second node controller 113 connected to the low potential voltage line LVL and turned on by the voltage of the first node Q1 of the second i-1 stage ST [2i-1] And is set to the low potential driving voltage Vss by being connected to the low potential voltage line LVL through the eighth transistor T8. Thus, since the third node Q3 of the second i-1 stage ST [2i-1] is connected to the second node Q2 of the second i-th stage ST [2i] Vss).

In the first period t1, the third switching circuit 113a of the second i-1 stage ST [2i-1] is turned on by the precharging voltage of the first node Q1, T4 and T5 are turned on and the sixth and seventh transistors T6 and T7 are turned on by the first driving voltage Vdd1 of the high voltage level VH, The second node Q2 is connected to the low potential voltage line LVL by the turn-on of the sixth transistor T6 having a relatively large size, and the second node Q2 is connected to the low- The voltage of the second node Q2 is set to the low potential driving voltage Vss by being connected to the low potential voltage line LVL by turn-on.

Then, during the second period t2, the second i-1 stage ST [2i-1] and the second i stage ST [2i] maintain the operating state of the first period t1. That is, since the forward gate start signal Vst1 of the gate-on voltage level Von has one horizontal period and a phase difference between the first clock signal CLK1 and one horizontal period, the second i-1 stage ST [ (T1) until the first clock signal CLK1 is increased from the gate-off voltage level Voff to the gate-on level Von in the first period t1 Keep the operating state as it is.

Then, during the third period (t3), in the second i-1 stage ST [2i-1], the first signal output section 131 The voltage of each of the first node Q1 and the first gate node Ng1 and the second gate node Ng2 is boosted by the bootstrapping generated at the gate-on voltage level of the first clock signal CLK1 (Von). That is, the gate voltage of the eleventh transistor T11 provided in the first signal output unit 131 is set such that the first clock signal CLK1 of the gate-on voltage level Von is supplied to the source electrode of the eleventh transistor T11 Due to the coupling phenomenon due to the parasitic capacitance between the gate electrode and the source electrode, the first clock signal CLK1 is synchronized with the voltage rise of the first clock signal CLK1 supplied to the source electrode. Accordingly, the first clock signal CLK1 of the gate-on voltage level Von is supplied to the eleventh transistor T11 completely turned on in accordance with the voltage of the first gate node Ng1 provided in the first signal output section 131 And the first clock signal CLK1 of the gate-on voltage level Von supplied to the first output node No1 is output to the first output node No1 through the fourth i-3 gate signal GP [4i -3]) to the corresponding gate line. At the same time, the second clock signal CLK2 of the gate-off voltage level Voff is turned on in accordance with the voltage of the second gate node Ng2 provided in the second signal output section 133, And the second clock signal CLK2 of the gate-off voltage level Voff supplied to the second output node No2 is output to the second output node No2 through the fourth i-2 gate signal GP [4i -2]) to the corresponding gate line. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

In the third period t3, each of the second node Q2 and the third node Q3 of the second i-1 stage ST [2i-1] maintains the voltage state of the second period t2 do.

During the third period t3, the second i-th stage ST [2i] receives the gate-on voltage level Von output to the first output node No1 of the second i-1 stage ST [2i-1] 1 stage ST [2i-1]) by receiving the output signal GP [4i-3] of the gate-on voltage Voff To the first output node No1 and outputs the fourth clock signal CLK4 having the gate off voltage Voff to the second output node No2. Thus, the third clock signal CLK3 having the gate-off voltage Voff supplied to the first output node No1 is supplied to the corresponding gate line as the (4i-1) th gate signal GP [4i-1] And the fourth clock signal CLK4 having the gate off voltage Voff supplied to the second output node No2 is supplied to the corresponding gate line as the fourth i gate signal GP [4i].

At the same time, during the third period t3, the voltage of the second node Q2 of the second i-th stage ST [2i] is set to the low potential driving voltage Vss by the third switching circuit 113a , The third node Q3 of the second i-th stage ST [2i] is connected to the second node Q2 of the second i-1 stage ST [2i-1] .

Subsequently, during the fourth period t4, the first node Q1 and the first gate node Ng1 and the second gate node Ng2 in the second i-1 stage ST [2i-1] The voltage is maintained at the voltage level (Von + Von) of the previous period t3 according to the polling of the first clock signal CLK1 and the rising of the second clock signal CLK2. That is, the voltages of the first node Q1, the first gate node Ng1, and the second gate node Ng2 are lower than the gate-off voltage level Voff of the first clock signal CLK1 and the second clock signal CLK2 The gate-on voltage level Von of the first clock signal CLK2 is not lowered due to the polling of the first clock signal CLK1 but is not increased by the rising of the second clock signal CLK2 and remains unchanged. Accordingly, the first clock signal CLK1 of the gate-off voltage level Voff is held at the eleventh transistor (the first clock signal CLK1) of the first signal output section 131, which maintains the turn-on state according to the voltage of the first gate node Ng1 T11 to the first output node No1 and supplied to the corresponding gate line as the (4i-3) th gate signal GP [4i-3] having the gate off voltage level Voff. At the same time, the second clock signal CLK2 of the gate-on voltage level Von passes through the thirteenth transistor T13 turned on in accordance with the voltage of the second gate node Ng2 of the second signal output section 133 Is outputted to the second output node No2 and is supplied to the corresponding gate line as the (4i-2) th gate signal GP [4i-2] having the gate-on voltage level Von. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

During the fourth period t4, the second i-th stage ST [2i] maintains the operating state of the previous period t3. That is, the second i-th stage ST [2i] is turned on by the pre-charged voltage to the first node Q1 precharged in the third period t3 and the first and second gate nodes Ng1 and Ng2, The third clock signal CLK3 having the gate off voltage Voff is outputted to the first output node No1 through the eleventh transistor T11 and the thirteenth transistor T13 which are kept in the ON state, And outputs the fourth clock signal CLK4 having the off voltage Voff to the second output node No2.

Subsequently, during the fifth period (t5), the voltages of the first node (Q1) and the second gate node (Ng2) at the second i-1 stage (ST [2i-1] Off voltage level Voff and the second clock signal CLK2 of the gate-off voltage level Voff is lowered by the voltage of the second gate node Ng2 in accordance with the second clock signal CLK2 of the second gate node Ng2 - 2 gate signal having the gate-off voltage level (Voff) is output to the second output node (No2) through the thirteenth transistor T13 of the second signal output section 133, (GP [4i-2]). At the same time, the first clock signal CLK1 of the gate-off voltage level Voff is supplied to the eleventh transistor (N1) of the first signal output section 131, which is kept turned on by the voltage of the first gate node Ng1 T11 to the first output node No1 and is continuously supplied to the corresponding gate line as the (4i-3) th gate signal GP [4i-3] having the gate off voltage level Voff.

During the fifth period t5, the second i-th stage ST [2i] is driven in the same manner as the third period t3 of the second i-1 stage ST [2i-1]. That is, in the second i-th stage ST [2i], the bootstrapping generated in the first signal output section 131 according to the third clock signal CLK3 of the gate-on voltage level Von causes the first node Q1 and the voltages of the first gate node Ng1 and the second gate node Ng2 rise further by the gate-on voltage level Von of the third clock signal CLK3. Accordingly, the third clock signal CLK3 of the gate-on voltage level Von is supplied to the eleventh transistor T11 completely turned on in accordance with the voltage of the first gate node Ng1 provided in the first signal output section 131 ) To the first output node No1 and supplied to the corresponding gate line as the (4i-1) th gate signal GP [4i-1] having the gate-on voltage level Von. At the same time, the fourth clock signal CLK4 of the gate-off voltage level Voff is held in the thirteenth transistor (N1) of the second signal output section 133, which is kept turned on by the voltage of the second gate node Ng2 T13 to the second output node No2, which is continuously supplied to the corresponding gate line as the fourth i-th gate signal GP [4i] having the gate-off voltage level Voff. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

During the fifth period t5, each of the second node Q2 and the third node Q3 of the second i-1 stage ST [2i-1] maintains the voltage state of the fourth period t4 do.

Then, during the sixth period t6, the voltages of the first node Q1, the first gate node Ng1, and the second gate node Ng2 in the second i-th stage ST [2i] (Von + Von) of the previous period t5 according to the polling of the signal CLK3 and the rising of the fourth clock signal CLK4. That is, the voltages of the first node Q1, the first gate node Ng1, and the second gate node Ng2 are lower than the gate-off voltage level Voff of the third clock signal CLK3 and the fourth clock signal CLK4 The gate-on voltage level Von of the first clock signal CLK2 is not lowered by the polling of the third clock signal CLK3 but is not raised by the rising of the fourth clock signal CLK4 and is maintained as it is. Accordingly, the third clock signal CLK3 of the gate-off voltage level Voff is supplied to the eleventh transistor (N1) of the first signal output section 131 which maintains the turn-on state according to the voltage of the first gate node Ng1 T11 to the first output node No1 and supplied to the corresponding gate line as the (4i-1) th gate signal GP [4i-1] having the gate-off voltage level Voff. At the same time, the fourth clock signal CLK4 of the gate-on voltage level Von is supplied to the second signal output unit 133 through the thirteenth transistor T13 turned on in accordance with the voltage of the second gate node Ng2 And is output to the second output node No2, which is supplied to the corresponding gate line as the fourth i-th gate signal GP [4i] having the gate-on voltage level Von. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

During the sixth period t6, the second i-1 stage ST [2i-1] outputs the gate-on voltage level Von output to the second output node No2 of the second i-th stage ST [2i] (Or discharges) the voltage of the first node Q1 by receiving the output signal GP [4i] of the first node Q1 as a reset signal. That is, during the sixth period t6, the output signal GP [4i (2i-1)] from the second output node No2 of the second i-th stage ST [2i] The third transistor T3 provided in the second switching circuit 111b of the first node controller 111 is turned on and the reverse driving voltage BWD is supplied to the first node Q1, The voltage of the node Q1 drops to the low voltage level VL and at the same time the voltages of the first gate node Ng1 and the second gate node Ng2 of the signal output circuit 130 are also at the low voltage level VL, So that the eleventh transistor T11 and the thirteenth transistor T13 of the signal output circuit 130 are turned off. Therefore, each of the first and second output nodes No1 and No2 of the second i-1 stage ST [2i-1] maintains the gate off voltage level Voff which is the voltage state of the previous period t5.

Next, during the seventh period (t7), in the second i-th stage ST [2i], the voltage of each of the first node Q1 and the second gate node Ng2 is lowered to the fourth Off state by the gate-off voltage level Voff in accordance with the clock signal CLK4 and the fourth clock signal CLK4 of the gate-off voltage level Voff is turned on by the voltage of the second gate node Ng2 The fourth output signal is output to the second output node No2 through the thirteenth transistor T13 of the second signal output unit 133 for holding the fourth i gate signal GP [4i] having the gate off voltage level Voff, Is supplied to the corresponding gate line.

At the same time, during the seventh period t7, in the second i-1 stage ST [2i-1], the gate-off voltage level O2 outputted to the second output node No2 of the second i- The third transistor T3 provided in the second switching circuit 111b of the first node control unit 111 is turned off according to the output signal GP [4i] of the first node Q1 The voltage of the first node Q1 gradually decreases in the voltage state of the previous period t6 because no voltage is supplied to the first node Q1.

During the seventh period t7, each of the second node Q2 and the third node Q3 of each of the second i-th stage ST [2i] and the second i-th stage ST [2i-1] The voltage state of the sixth period t6 is maintained as it is.

Next, during the eighth period t8, the second i-th stage ST [2i] outputs the gate-on voltage level ((i)) output to the second output node No2 of the (2i + 1) The voltage of the first node Q1 is reset (or discharged) by receiving the output signal GP [4i + 2] of the first node Q1 as the reset signal. That is, during the eighth period t8, the second i stage ST [2i] outputs the output signal GP [4i] from the second output node No2 of the second i + 1 stage ST [2i + 1] +2]), the third transistor T3 provided in the second switching circuit 111b of the first node controller 111 is turned on and the reverse driving voltage BWD is supplied to the first node Q1 The voltage of the first node Q1 drops to the low voltage level VL and at the same time the voltages of the first gate node Ng1 and the second gate node Ng2 of the signal output circuit 130 are also at the low voltage level VL). As a result, the eleventh transistor T11 and the thirteenth transistor T13 of the signal output circuit 130 are turned off. Thus, each of the first and second output nodes No1 and No2 of the second i-th stage ST [2i] maintains the gate off voltage level Voff which is the voltage state of the previous period t7.

At the same time, in the eighth period (t8), the first node voltage (V [i]) of the second i stage (ST [2i]) lowered to the low voltage level The eighth transistor T8 of the second node control unit 113 is turned off by the first node N1 and the second node Q2 is turned off by the first driving voltage Vdd1, The first driving voltage Vdd1 of the high voltage level VH supplied through the fourth and fifth transistors T4 and T5 of the node control unit 113 and the high voltage The fourteenth and sixteenth transistors T14 and T16 of the first discharging circuit 150 are turned on by the first driving voltage Vdd1 of the level VH. Accordingly, the voltage of each of the first and second output nodes No1 and No2 is discharged to the low potential voltage line LVL through the respective turned-on fourteenth and sixteenth transistors T14 and T16, The voltage of each of the gate lines connected to each of the two output nodes No1 and No2 is set to the low potential voltage level Vss, that is, the gate off voltage level Voff.

At the same time, in the eighth period t8, in the second i-th stage ST [2i], the third node Q3 is connected to the second node Q2 of the second i-1 stage ST [2i-1] The fifteenth and seventeenth transistors T15 and T17 of the first discharge circuit 150 and the eighteenth transistor T18 of the second discharge circuit 170 are connected to the second i-1 stage ST [2i -1] of the high voltage level VH supplied through the second node Q2 of the first driving voltage Vdd1. Accordingly, the voltage of each of the first and second output nodes No1 and No2 is discharged to the low potential voltage line LVL through the turned-on fifteenth and seventeenth transistors T15 and T17, respectively, The voltage of each of the gate lines connected to each of the two output nodes No1 and No2 is set to the low potential voltage level Vss or the gate off voltage level Voff and the voltage of the first node Q1 is turned on Is discharged to the low potential voltage line LVL through the eighteenth transistor T18 and is set to the low potential voltage level Vss, that is, the gate off voltage level Voff.

Next, after the eighth period (t8), each of the second i-1 stage ST [2i-1] and the second i-th stage ST [2i] outputs the forward gate start signal Vst1 or the first output The operation state of the eighth period t8 is maintained as it is until the output signal from the node is supplied.

Fig. 5 is a driving waveform diagram for reverse driving of the (2i-1) th and (2i-th) stages shown in Fig.

The reverse driving method of the (2i-1) th and (2i) th stages will be described with reference to FIGS. 3 and 5 as follows.

Each of the second i-1 and second i-th stages ST [2i-1] and ST [2i] operates in the first to eighth periods t1 to t8 and is shifted by one horizontal period of the display panel (GP [4i], GP [4i-1]), GP [4i-2], and GP [4i-3]).

In the backward driving, the first driving voltage Vdd1 is at a low voltage level VL, the second driving voltage Vdd2 is at a high voltage level VH, the forward driving voltage FWD is at a gateoff voltage level Voff, And the reverse drive voltage BWD are set to the gate-on voltage level Voff, respectively.

During the first period t1, the gate start signal Vst having the gate-on voltage level or the second output signal GP [4i + 2] of the next stage in the second i-th stage ST [2i] The third transistor T3 of the first node control unit 111 is turned on so that the first node Q1 is turned on by the reverse driving voltage BWD of the gate-on voltage level Von supplied through the third transistor T3 ). The first gate node Ng1 of the first signal output unit 131 is connected to the first node Q1 supplied through the tenth transistor T10 turned on by the precharging voltage of the first node Q1 And the second gate node Ng2 of the second signal output section 133 is charged with the same voltage as the precharging voltage and the twelfth transistor T12 turned on by the precharging voltage of the first node Q1 Is charged to the same voltage as the precharging voltage of the first node (Q1) supplied through the first node (Q1). Thus, the thirteenth transistor T13 of the second signal output unit 133 is turned on by the precharged voltage to the second gate node Ng2, thereby generating the fourth clock signal (Voff) having the gate- CLK4 to the second output node No2 and at the same time the eleventh transistor T11 of the first signal output section 131 is turned on by the precharged voltage to the first gate node Ng1 And outputs the first clock signal CLK1 having the gate-off voltage Voff to the first output node No1. The fourth clock signal CLK4 of the gate-off voltage level Voff output to the second output node No2 is supplied to the corresponding gate line as the fourth i-th gate signal GP [4i] The third clock signal CLK3 of the gate-off voltage level Voff output to the first gate-on voltage No1 is supplied to the corresponding gate line as the (4i-1) -th gate signal GP [4i-1].

In the first period t1, the second node Q2 of the second i-th stage ST [2i] is connected to the second node controller 113 (second node) that is switched in accordance with the second drive voltage Vdd2 of the high voltage level VH Is held at the low potential driving voltage Vss because it is connected to the low potential voltage line LVL by the third switching 113a. The second node Q2 of the second i-1 stage ST [2i-1] is connected to the second node controller 113 which is turned on by the second drive voltage Vdd2 of the high voltage level VH The second node controller 113 connected to the low potential voltage line LVL through the ninth transistor T9 and turned on by the voltage of the first node Q1 of the second i stage ST [2i] And is set to the low potential driving voltage Vss by being connected to the low potential voltage line LVL through the eighth transistor T8. Thus, since the third node Q3 of the second i-th stage ST [2i] is connected to the second node Q2 of the second i-1stage ST [2i-1], the low potential driving voltage Vss).

In the first period t1, the third switching circuit 113a of the second i-th stage ST [2i] receives the fourth and fifth transistors T4 and T5 by the precharging voltage of the first node Q1, The sixth and seventh transistors T6 and T7 are turned on by the second driving voltage Vdd2 of the high voltage level VH at the same time that the internal node Ni is turned on, And the second node Q2 is connected to the low potential voltage line LVL by the turn-on of the sixth transistor T6 having the large size, and the seventh transistor T7 having the relatively large magnitude is turned on The voltage of the second node Q2 is set to the low potential driving voltage Vss by being connected to the low potential voltage line LVL.

Then, during the second period t2, the second i-th stage ST [2i] and the second i-1st stage ST [2i-1] maintain the operating state of the first period t1. That is, since the gate-on reset signal Vst2 having the gate-on voltage level Von has one horizontal period and a phase difference between the fourth clock signal CLK4 and one horizontal period, the second i-th stage ST [2i] ) And the (2i-1) th stage ST [2i-1] of the first period t1 until the fourth clock signal CLK4 is increased from the gate-off voltage level Voff to the gate- Keep the operating state as it is.

Then, during the third period t3, in the second i-th stage ST [2i], the second clock signal CLK2 generated at the second signal output portion 133 in accordance with the fourth clock signal CLK4 of the gate- The voltage of each of the first node Q1 and the first gate node Ng1 and the second gate node Ng2 is reduced by bootstrapping by the gate on voltage level Von of the fourth clock signal CLK4 Further increase. That is, the gate voltage of the thirteenth transistor T13 provided in the second signal output section 133 is such that the fourth clock signal CLK4 of the gate-on voltage level Von is supplied to the source electrode of the thirteenth transistor T13 Due to the coupling phenomenon due to the parasitic capacitance between the gate electrode and the source electrode, the fourth clock signal (CLK4) supplied to the source electrode rises in synchronization with the voltage rise. Accordingly, the fourth clock signal CLK4 having the gate-on voltage level Von is turned on in accordance with the voltage of the second gate node Ng2 provided in the second signal output section 133, The fourth clock signal CLK4 of the gate-on voltage level Von supplied to the second output node No2 is output to the second output node No2 through the fourth gate signal GP [4i] Is supplied to the corresponding gate line. At the same time, the third clock signal CLK3 of the gate-off voltage level Voff is supplied to the eleventh transistor T11 completely turned on in accordance with the voltage of the first gate node Ng1 provided in the first signal output section 131 And the second clock signal CLK2 of the gate-off voltage level Voff supplied to the first output node No1 is output to the first output node No1 through the fourth i-1 gate signal GP [4i -1]) to the corresponding gate line. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

In the third period t3, each of the second node Q2 and the third node Q3 of the second i-th stage ST [2i] maintains the voltage state of the second period t2.

During the third period t3, the second i-1 stage ST [2i-1] outputs the gate-on voltage level Von output to the second output node No2 of the second i- The second clock signal CLK is supplied to the reverse gate start signal in the same manner as the first period t1 of the second i-th stage ST [2i] Outputs the signal CLK2 to the second output node No2 and outputs the first clock signal CLK1 having the gate off voltage Voff to the first output node No1. Thus, the second clock signal CLK2 having the gate-off voltage Voff supplied to the second output node No2 is supplied to the corresponding gate line as the (4i-2) th gate signal GP [4i-2] And the first clock signal CLK1 having the gate-off voltage Voff supplied to the first output node No1 is supplied to the corresponding gate line as the (4i-3) th gate signal GP [4i-3] .

At the same time, during the third period t3, the second node Q2 of the second i-1 stage ST [2i-1] is set to the low potential driving voltage Vss by the third switching circuit 113a And the third node Q3 of the second i-1 stage ST [2i-1] is connected to the second node Q2 of the second i-th stage ST [2i] ).

During the fourth period (t4), the voltages of the first node (Q1), the first gate node (Ng1) and the second gate node (Ng2) in the second i stage (ST [2i] Von of the previous period t3 according to the polling of the clock signal CLK4 and the rising of the third clock signal CLK3. That is, the voltages of the first node Q1, the first gate node Ng1, and the second gate node Ng2 are lower than the gate-off voltage level Voff of the fourth clock signal CLK4 and the third clock signal CLK3 The gate-on voltage level Von of the third clock signal CLK2 is not lowered by the polling of the fourth clock signal CLK4 but held by the rising of the third clock signal CLK3. Accordingly, the fourth clock signal CLK4 of the gate-off voltage level Voff is maintained at the level corresponding to the voltage of the second gate node Ng2, T13 to the second output node No2 and supplied to the corresponding gate line as the fourth i-th gate signal GP [4i] having the gate-off voltage level Voff. At the same time, the third clock signal CLK3 of the gate-on voltage level Von is supplied through the eleventh transistor T11 turned on in accordance with the voltage of the first gate node Ng1 of the first signal output section 131 Is output to the first output node No1 and supplied to the corresponding gate line as the (4i-1) th gate signal GP [4i-1] having the gate-on voltage level Von. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

During the fourth period t4, the second i-1 stage ST [2i-1] maintains the operating state of the previous period t3. That is, the second i-1 stage ST [2i-1] is precharged to the first node Q1 and the first and second gate nodes Ng1 and Ng2 precharged in the third period t3 The second clock signal CLK2 having the gate-off voltage Voff through each of the eleventh transistor T11 and the thirteenth transistor T13 which maintains the turn-on state by the voltage to the second output node No2 And outputs the first clock signal CLK1 having the gate-off voltage Voff to the first output node No1.

Next, during the fifth period (t5), the voltage of each of the first node (Q1) and the second gate node (Ng2) in the second i-th stage (ST [2i] And falls by the gate-off voltage level Voff in accordance with the clock signal CLK3. Accordingly, the third clock signal CLK3 of the gate-off voltage level Voff is supplied to the eleventh transistor (N1) of the first signal output section 131, which is kept turned on by the voltage of the first gate node Ng1 T11 to the first output node No1 and supplied to the corresponding gate line as the (4i-1) th gate signal GP [4i-1] having the gate-off voltage level Voff. At the same time, the fourth clock signal CLK4 of the gate-off voltage level Voff is held in the thirteenth transistor (N1) of the second signal output section 133, which is kept turned on by the voltage of the second gate node Ng2 T13 to the second output node No2, which is continuously supplied to the corresponding gate line as the fourth i-th gate signal GP [4i] having the gate-off voltage level Voff.

During the fifth period t5, the second i-1 stage ST [2i-1] is driven in the same manner as the third period t3 of the second i-th stage ST [2i]. That is, in the second i-1 stage ST [2i-1], by the bootstrapping generated in the second signal output portion 133 in accordance with the second clock signal CLK2 of the gate- The voltages of the first node Q1 and the first gate node Ng1 and the second gate node Ng2 respectively increase further by the gate on voltage level Von of the second clock signal CLK2. Accordingly, the second clock signal CLK2 of the gate-on voltage level Von is supplied to the thirteenth transistor T13 (T13) which is completely turned on in accordance with the voltage of the second gate node Ng2 provided in the second signal output section 133 To the second output node No2 and supplied to the corresponding gate line as the fourth i-2 gate signal GP [4i-2] having the gate-on voltage level Von. At the same time, the first clock signal CLK1 of the gate-off voltage level Voff is supplied to the eleventh transistor (N1) of the first signal output section 131, which is kept turned on by the voltage of the first gate node Ng1 T11 to the first output node No1 and is continuously supplied to the corresponding gate line as the (4i-3) th gate signal GP [4i-3] having the gate off voltage level Voff. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

During the fifth period t5, each of the second node Q2 and the third node Q3 of the second i-1 stage ST [2i-1] maintains the voltage state of the fourth period t4 do.

Then, during the sixth period t6, the voltage of the first node Q1, the voltage of the first gate node Ng1 and the voltage of the second gate node Ng2 in the second i-1 stage ST [2i-1] Is maintained at the voltage level (Von + Von) of the previous period t5 according to the polling of the second clock signal CLK2 and the rising of the first clock signal CLK1. That is, the voltages of the first node Q1, the first gate node Ng1, and the second gate node Ng2 are lower than the gate-off voltage level Voff of the second clock signal CLK2 and the first clock signal CLK1 The gate-on voltage level Von of the first clock signal CLK2 is not lowered by the polling of the second clock signal CLK2 but is not increased by the rising of the first clock signal CLK1 and is maintained as it is. Thus, the second clock signal CLK2 of the gate-off voltage level Voff is maintained at the same level as the thirteenth transistor (N2) of the second signal output section 133, which maintains the turn-on state according to the voltage of the second gate node Ng2 T13 to the second output node No2 and supplied to the corresponding gate line as the fourth i-2 gate signal GP [4i-2] having the gate off voltage level Voff. At the same time, the first clock signal CLK1 of the gate-on voltage level Von is supplied to the first signal output unit 131 through the eleventh transistor T11 turned on according to the voltage of the first gate node Ng1 Is output to the first output node No1 and supplied to the corresponding gate line as the (4i-3) th gate signal GP [4i-3] having the gate-on voltage level Von. At this time, the first capacitor C1 of the first signal output unit 131 stably maintains the turn-on state of the tenth transistor T10 using the charged voltage, and the first capacitor C1 of the second signal output unit 131 2 capacitor C2 also maintains the turn-on state of the twelfth transistor T12 stably using the charged voltage.

During the sixth period t6, the second i-th stage ST [2i] receives the gate-on voltage level Von output to the first output node No1 of the second i-1 stage ST [2i-1] (Or discharges) the voltage of the first node Q1 by receiving the output signal GP [4i-3] of the first node Q1 as a reset signal. That is, during the sixth period t6, the output signal GP [4i-1] from the first output node No1 of the second i-1 stage ST [2i- 3], the first transistor T1 provided in the first switching circuit 111a of the first node controller 111 is turned on and the forward driving voltage FWD is supplied to the first node Q1 The voltage of the first node Q1 drops to the low voltage level VL and at the same time the voltages of the first gate node Ng1 and the second gate node Ng2 of the signal output circuit 130 are also at the low voltage level VL). As a result, the eleventh transistor T11 and the thirteenth transistor T13 of the signal output circuit 130 are turned off. Therefore, each of the first and second output nodes No1 and No2 of the second i-th stage ST [2i] maintains the gate off voltage level Voff which is the voltage state of the previous period t5.

Subsequently, during the seventh period (t7), the voltage of each of the first node (Q1) and the second gate node (Ng2) in the (2i-1) Off voltage level Voff and the first clock signal CLK1 of the gate-off voltage level Voff is lowered by the voltage of the first gate node Ng1 - 4th gate signal having the gate-off voltage level (Voff), and is output to the first output node (No1) through the eleventh transistor T11 of the first signal output section 131 which maintains the ON- (GP [4i-3]).

At the same time, during the seventh period (t7), in the second i-th stage ST [2i], the gate-off voltage level outputted to the first output node No1 of the (2i-1) The first transistor T1 provided in the first switching circuit 111a of the first node control unit 111 is turned off according to the output signal GP [4i-3] of the first node Voff, Since no voltage is supplied to the first node Q1, the voltage of the first node Q1 gradually decreases in the voltage state of the previous period t6.

During the seventh period (t7), each of the second node (Q2) and the third node (Q3) of each of the second i-1 stage (ST [2i-1] The voltage state of the sixth period t6 is maintained as it is.

The second i-1 stage ST [2i-1] is connected to the first output node No1 of the second i-2 stage ST [2i-2] during the eighth period t8, (Or discharges) the voltage of the first node Q1 by receiving the output signal GP [4i-5] of the on-voltage level Von as the reset signal. That is, during the eighth period t8, the second i-1 stage ST [2i-1] outputs the output signal No1 from the first output node No1 of the second i- The first transistor T1 provided in the first switching circuit 111a of the first node control unit 111 is turned on in response to the forward drive voltage FWD (4i-5) The voltage of the first node Q1 drops to the low voltage level VL and at the same time the voltage of the first gate node Ng1 and the second gate node Ng2 of the signal output circuit 130 And the eleventh transistor T11 and the thirteenth transistor T13 of the signal output circuit 130 are turned off as a result. Therefore, each of the first and second output nodes No1 and No2 of the second i-1 stage ST [2i-1] maintains the gate off voltage level Voff which is the voltage state of the previous period t7.

At the same time, in the eighth period t8, the second node i of the second i-1 stage ST [2i-1] which is lowered to the low voltage level VL in the second i-th stage ST [2i] The eighth transistor T8 of the second node control unit 113 is turned off by the second driving voltage Vdd2 so that the second node Q2 is turned on by the second driving voltage Vdd2, The second driving voltage Vdd2 of the high voltage level VH supplied through the fourth and fifth transistors T4 and T5 of the node control unit 113 and the high voltage The fourteenth and sixteenth transistors T14 and T16 of the first discharging circuit 150 are turned on by the second driving voltage Vdd2 of the level VH. Accordingly, the voltage of each of the first and second output nodes No1 and No2 is discharged to the low potential voltage line LVL through the respective turned-on fourteenth and sixteenth transistors T14 and T16, The voltage of each of the gate lines connected to each of the two output nodes No1 and No2 is set to the low potential voltage level Vss, that is, the gate off voltage level Voff.

At the same time, in the eighth period t8, the third node Q3 is connected to the second node Q2 of the second i-th stage ST [2i] in the second i-1 stage ST [2i-1] The fifteenth and seventeenth transistors T15 and T17 of the first discharging circuit 150 and the eighteenth transistor T18 of the second discharging circuit 170 are connected to the second i stage ST [2i] On by the second drive voltage Vdd2 of the high voltage level VH supplied through the second node Q2 of the second transistor Q2. Accordingly, the voltage of each of the first and second output nodes No1 and No2 is discharged to the low potential voltage line LVL through the turned-on fifteenth and seventeenth transistors T15 and T17, respectively, The voltage of each of the gate lines connected to each of the two output nodes No1 and No2 is set to the low potential voltage level Vss or the gate off voltage level Voff and the voltage of the first node Q1 is turned on Is discharged to the low potential voltage line LVL through the eighteenth transistor T18 and is set to the low potential voltage level Vss, that is, the gate off voltage level Voff.

Next, after the eighth period (t8), each of the second i-th stage ST [2i] and the second i-1st stage ST [2i-1] The operation state of the eighth period t8 is maintained as it is until an output signal from the output node is supplied.

The shift register according to this example sequentially outputs two gate signals in each of the first to m-th stages ST [1] to ST [m], thereby reducing the number of stages, Can be reduced. In particular, in the shift register according to this example, the second node Q2 of the second i-1 stage ST [2i-1] and the third node Q3 of the second i-th stage ST [2i] The third node Q3 of the second i-1 stage ST [2i-1] and the second node Q2 of the second i-th stage ST [2i] are connected to each other so that the first discharge circuit 150 The number of transistors constituting the transistor is reduced, and consequently the circuit area of each stage can be reduced. The shift register according to the present example is a full-shift register provided in each of the first signal output section 131 and the second signal output section 133 of each of the first to m-th stages ST [1] to ST [m] Up transistors T11 and T13 share the first node Q1 and are biased only in a part of the period during which the gate voltages of the pull-up transistors T11 and T13 output the gate signal, The threshold voltage shift of the pull-up thin film transistor can be minimized.

6 is a view schematically showing a display device according to an example of the present application.

6, a flat panel display device according to an exemplary embodiment of the present invention includes a display panel 200, a timing controller 300, a data driving circuit 400, a gate driving circuit 500, and a voltage generator 600, .

The display panel 200 includes first and second substrates bonded to each other.

The first substrate includes a display region AA having a plurality of pixels P formed in a pixel region defined by the intersection of a plurality of gate lines GL and a plurality of data lines DL, And a non-display area IA provided in the periphery of the display area IA.

Each of the plurality of pixels P includes a pixel cell for displaying an image according to a data voltage supplied from a data line DL adjacent to a gate signal supplied from an adjacent gate line GL. Here, the pixel cell includes at least one thin film transistor and at least one capacitor. The pixel cell may be a liquid crystal cell for displaying an image by controlling the light transmittance of liquid crystal according to a data voltage, May be an organic light emitting cell.

The second substrate covers the entire first substrate excluding a part of the non-display area IA. In this case, when each pixel P is a liquid crystal cell, a color filter layer may be formed on the second substrate to overlap each pixel P.

The timing control unit 300 generates pixel-by-pixel data Pdata by aligning the input image data Idata so as to be suitable for driving the display panel 200, and generates data Pdata based on the timing synchronization signal TSS And provides the control signal DCS to the data driving circuit 300.

The timing controller 300 includes a gate start signal Vst and first to fourth clock signals CLK1 to CLK4 based on the timing synchronization signal TSS as shown in FIG. 4 or FIG. And provides the generated gate control signal GCS to the gate driving circuit 500. [ The timing controller 300 generates a voltage control signal PCS including a scan direction control signal based on the drive voltage inversion signal and the rotation angle of the display device, and provides the voltage control signal PCS to the power generator 600.

The data driving circuit 400 is connected to a plurality of data lines DL provided in the display panel 200. The data driving circuit 300 receives the pixel data signal Pdata, the data control signal DCS, and the plurality of reference gamma voltages from the timing controller 300 to generate a pixel-by-pixel data signal Pdata in analog form Pixel data voltage, and supplies the converted data voltage for each pixel to the corresponding data line DL.

The gate driving circuit 500 is formed in the left and / or right non-display region of the first substrate together with the manufacturing process of the thin film transistor of the pixel. For example, the gate driving circuit 500 may include first and second gate driving circuits formed on both side non-display regions of the first substrate. In one example, each of the first and second gate driving circuits may supply the same gate signal to one gate line. In another example, the first gate driving circuit supplies gate signals to odd-numbered gate lines among the plurality of gate lines GL, and the second gate driving circuit supplies gate signals to the even- Signal.

The gate driving circuit 500 receives the gate start signal and the first to fourth clock signals provided from the timing controller 300 and generates a first driving voltage, A forward drive voltage, a reverse drive voltage, and a low-potential drive voltage, respectively. The gate driving circuit 500 generates gate signals according to the first to fourth clock signals using the received signals and voltages, and supplies the gate signals to corresponding gate lines GL in a predetermined order. Since the gate driving circuit 500 includes the shift registers shown in FIGS. 2 to 5, the description thereof will be omitted.

The power generator 600 generates a first driving voltage, a second driving voltage, a forward driving voltage, a backward driving voltage, and a backward driving voltage by using an input power source Vin based on a power control signal PCS provided from the timing controller 300. [ And a low-potential driving voltage to the gate driving circuit 500. Also, the power generator 600 may further generate and output various voltages required for displaying an image on the display panel 200.

Alternatively, the timing controller 300, the data driving circuit 400, and the gate driving circuit 500 may be formed of a single driving integrated circuit (IC) and mounted on the first substrate of the display panel 200. Further, the power generating unit 600 may be embedded in the driving integrated circuit (IC).

Such a display device according to the present embodiment includes a gate driving circuit composed of a shift register according to the present application, so that it can have a thin bezel width due to the size reduction of the shift register.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the scope of the present application is to be defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present application.

ST [1] to ST [m]: stage 111:
111a: first switching circuit 111b: second switching circuit
113: second node control section 113a: third switching circuit
113b: fourth switching circuit 130: signal output circuit
131: first signal output unit 133: second signal output unit
150: first discharge circuit 170: second discharge circuit
200: display panel 300: timing controller
400: Data driving circuit 500: Gate driving circuit
600:

Claims (19)

And a first to an m-th stages that are driven by a gate start signal and sequentially output two output signals,
Wherein each of the first through m-
A first node;
A second node and a third node having different voltage levels than the first node;
A node controller for controlling a first node voltage of the first node and a second node voltage of the second node;
A signal output circuit for sequentially outputting two clock signals to the first and second output nodes according to the first node voltage;
A first discharging circuit for sequentially discharging the voltages of the first output node and the second output node according to the second node voltage and the voltage of the third node; And
And a second discharging circuit for discharging the voltage of the first node according to a third node voltage of the third node. The method according to claim 1,
The second node of the stage 2i-1 (i is a natural number from 1 to m / 2) of the first through m-th stages is connected to the third node of the second i-
And a third node of the second i-1 stage and a second node of the second i-stage are connected to each other. 3. The method of claim 2,
The node control unit of each of the first to m-
A first node controller for controlling the first node voltage; And
And a second node control unit for controlling the second node voltage. The method of claim 3,
The first node controller of each of the first through m-
A first switching circuit for supplying a forward driving voltage to the first node in response to a gate start signal or an output signal of a first output node of a previous single stage; And
And a second switching circuit for controlling the first node voltage according to the second node voltage and the output signal of the second output node of the next stage. 5. The method of claim 4,
Wherein the first switching circuit of each of the first through m-th stages is turned on in response to the gate start signal or the output signal of the first output node of the previous single stage to supply the forward driving voltage to the first node A shift register having a transistor. 5. The method of claim 4,
And the second switching circuit of each of the first to m-
A second transistor that is turned on according to the second node voltage to connect the first node to a low potential voltage line; And
And a third transistor which is turned on according to an output signal of the second output node of the next stage and supplies a reverse driving voltage having a voltage level different from the forward driving voltage to the first node. The method of claim 3,
Wherein the second node controller of each of the first through m-th stages includes a third switching circuit and a fourth switching circuit for controlling the second node voltage,
The third switching circuit of the second i-1 stage controls the second node voltage according to the first node voltage and the first drive voltage,
The third switching circuit of the second i stage controls the second node voltage according to the first node voltage and the second drive voltage,
The fourth switching circuit of the second i-1 stage controls the second node voltage in accordance with the first node voltage and the second drive voltage of the next stage,
And the fourth switching circuit of the second i stage controls the second node voltage in accordance with the first node voltage and the first drive voltage of the previous single stage. 8. The method of claim 7,
And the third switching circuit of the (2i-1)
A fourth transistor that is turned on according to the first driving voltage and outputs the first driving voltage to an internal node;
A fifth transistor that is turned on according to the voltage of the internal node and supplies the first driving voltage to the second node;
A sixth transistor that is turned on according to the first node voltage to couple the internal node to a low potential voltage line; And
And a seventh transistor that is turned on according to the first node voltage to connect the second node to the low potential voltage line. 8. The method of claim 7,
And the third switching circuit of the second i-
A fourth transistor that is turned on according to the second driving voltage to output the second driving voltage to the internal node;
A fifth transistor that is turned on according to the voltage of the internal node and supplies the second driving voltage to the second node;
A sixth transistor that is turned on according to the first node voltage to couple the internal node to a low potential voltage line; And
And a seventh transistor that is turned on according to the first node voltage to connect the second node to the low potential voltage line. 8. The method of claim 7,
And the fourth switching circuit of the (2i-1)
An eighth transistor for turning on the first node according to a first node voltage of the next stage and connecting the second node to a low potential voltage line; And
And a ninth transistor for turning on according to the second driving voltage to connect the second node to the low potential voltage line. 8. The method of claim 7,
And the fourth switching circuit of the second i-
An eighth transistor for turning on according to a first node voltage of the previous single stage and connecting the second node to a low potential voltage line; And
And a ninth transistor that is turned on according to the first driving voltage to connect the second node to the low potential voltage line. 3. The method of claim 2,
The signal output circuit of each of the first through m-
A first output circuit for outputting one of the two clock signals to the first output node according to the first node voltage; And
And a second output circuit for outputting the remaining one of the two clock signals to the second output node in accordance with the first node voltage. 13. The method of claim 12,
The first output circuit of each of the first through m-
A tenth transistor outputting the first node voltage to a first gate node;
A first capacitor connected between the gate electrode of the tenth transistor and the first node; And
And an eleventh transistor that is turned on according to a voltage of the first gate node and outputs either one of the two clock signals to the first output node. 13. The method of claim 12,
And a second output circuit of each of the first through m-
A twelfth transistor for outputting the first node voltage to a second gate node;
A second capacitor connected between the gate electrode of the twelfth transistor and the first node; And
And a thirteenth transistor that is turned on according to the voltage of the second gate node and outputs the remaining one of the two clock signals to the second output node. 3. The method of claim 2,
The first discharge circuit of each of the first through m-
A fourth transistor (14) for turning on the second node voltage and connecting the first output node to the low potential voltage line;
A fifteenth transistor for turning on according to the third node voltage and connecting the first output node to the low potential voltage line;
A sixth transistor for turning on according to the second node voltage and connecting the second output node to the low potential voltage line; And
And a seventeenth transistor that is turned on according to the third node voltage to couple the second output node to the low potential voltage line. 3. The method of claim 2,
And the second discharge circuit of each of the first through m-th stages includes an eighteenth transistor that is turned on according to the third node voltage to connect the first node to the low potential voltage line. 17. The method according to any one of claims 1 to 16,
Each of the first through m-th stages sequentially receives two clock signals sequentially shifted out of four sequentially shifted clock signals,
Each of the four clock signals cyclically repeats the gate-on voltage level of one horizontal period and the gate-off voltage level of three horizontal periods,
Wherein the first clock signal among the four clock signals has a phase difference of one horizontal period from the gate start signal. A display panel including a plurality of gate lines and a plurality of data lines;
A data driving circuit for converting input pixel data into data signals and supplying the data signals to the plurality of data lines; And
And a gate driving circuit for supplying a gate signal to each of the plurality of gate lines,
Wherein the gate driving circuit comprises a shift register according to any one of claims 1 to 16. 19. The method of claim 18,
Each of the first through m-th stages sequentially receives two clock signals sequentially shifted out of four sequentially shifted clock signals,
Each of the four clock signals cyclically repeats the gate-on voltage level of one horizontal period and the gate-off voltage level of three horizontal periods,
Wherein the first clock signal among the four clock signals has a phase difference of one horizontal period from the gate start signal.

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