KR20160094475A - Gate shift register and display device using the same - Google Patents

Abstract

A gate shift register according to an embodiment of the present invention further comprises an anti-ripple thin film transistors (TFTs) applying a low potential voltage to Q1 and Q2 nodes in response to front or rear carry pulses rising from a gate low voltage to a gate high voltage when first and second gate shift clocks input to a kth stage first rise from a gate low voltage to a gate high voltage after the kth stage outputs first and second scan pulses. Since ripples of a Q node are reduced, charging characteristics of a QB node are able to be enhanced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate shift register,

The present invention relates to a gate shift register and a display using the gate shift register.

 Various flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes (Cathode Ray Tube). The scan driving circuit of the flat panel display generally supplies scan pulses to the scan lines sequentially using a gate shift register.

The gate shift register of the scan driving circuit has stages including a plurality of thin film transistors (hereinafter referred to as "TFTs "). Stages are connected in a cascade to generate output sequentially.

Each of the stages includes a Q-node for controlling a pull-up transistor, and a Q-bar (QB) node for controlling a pull-down transistor. In addition, each of the stages includes switch circuits that charge and discharge the Q node and the QB node voltage in response to a carry signal input from a previous stage, a carry signal input from the next stage, and a clock signal.

Such a conventional gate shift register generates a scan pulse only in a single direction, that is, in the stage direction located at the lowermost position from the highest positioned position. Such a gate shift register can not be applied to a display device of various models, for example, a display device that sequentially displays images in the direction of the uppermost scan line from the lowermost scan line of the display panel, it's difficult. Thus, a gate shift register capable of bi-directional shift operation has recently been proposed. The bidirectional gate shift register includes a bidirectional control circuit and operates in a forward shift mode or a reverse shift mode. However, the bidirectional gate shift register causes various problems due to the bidirectional control circuit added to the unidirectional gate shift register. The bidirectional control circuit floats the gate electrode of the discharge TFT by applying a shift direction switching signal to the discharge TFT connected between the QB node in each stage and the input terminal of the low potential voltage. In the floating gate electrode, the leakage charges are accumulated during the operation of the gate shift register. As a result, the discharge TFT, which is to be maintained in the turn-off state due to the gate-source voltage exceeding the threshold voltage, is turned on abnormally. In this case, during a period in which the output of the stage is to be held at a low level, the QB node can not be charged sufficiently to a level that can turn on the pull-down transistor, and as a result, the output signal can not be maintained at the gate low level, . Further, the deterioration of the discharge TFT is accelerated by the gate-bias stress caused by the leakage charges, and the lifetime of the gate shift register is shortened. In addition, both the scan signal and the carry signal are outputted from the output terminal of the stage, thereby causing a problem of signal delay due to the line resistance.

In addition, the TFT deterioration that charges the QB during long-term driving deteriorates the charging characteristics of the QB node and the charging time of the QB node is increased due to deterioration of the TFT characteristics, Charging time becomes longer. If a ripple occurs in the Q node at a point before the QB node is fully charged, the voltage of the QB node sharply shrinks and the internal waveform characteristics deteriorate. In some cases, the gate multi-output occurs, .

The shift register according to the embodiment of the present invention and the display device using the shift register prevent floating and deterioration of the discharge TFT connected between the QB node and the input terminal of the low potential voltage in each stage and operated in accordance with the shift direction switching signal, A gate shift register capable of stabilizing the output and a display device using the gate shift register can be provided.

The shift register according to the embodiment of the present invention and the display device using the shift register include a scan output unit for outputting a scan pulse and a carry output unit for outputting a carry pulse, And a display device using the same.

Also, a shift register according to an embodiment of the present invention and a display device using the shift register may provide a gate shift register capable of improving a charging characteristic of a QB node by reducing a ripple of a Q node, and a display device using the gate shift register.

The gate shift register according to an embodiment of the present invention includes a plurality of stages for receiving a plurality of gate shift clocks and sequentially outputting a scan pulse and a carry pulse, and the k < th > A scan direction controller for switching the shift direction of the scan pulse and the carry pulse in response to the previous carry pulses input through the second input terminal and the subsequent carry pulses input through the third and fourth input terminals, And a discharge TFT for controlling charge and discharge of the Q2 node, the QB1 node, and the QB2 node, and discharging the QB1 node or the QB2 node to a low potential voltage in accordance with the shift direction switching signal, a node controller including the QB1 node or the QB2 node A floating prevention unit for applying the low potential voltage to the gate electrode of the discharge TFT in accordance with the voltage and the first and second scan pulses, A scan output unit for outputting the first scan pulse through the 1-1th output node and outputting the second scan pulse through the 2-1 output node according to the voltage of the Q2 node, the QB1 node, and the QB2 node, A carry output unit for outputting a first carry pulse through a first 1-2 output node and a second carry pulse through a second 2-2 output node according to the voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node, A scan pulse is outputted from the scan output section 50 and a carry pulse is outputted from the carry output section 60. Thus, the line resistance can be reduced and the signal delay can be minimized.

In the gate shift register according to the embodiment of the present invention, the first and second gate shift clocks, which are input to the k-th stage after the first and second scan pulse outputs, Further comprising ripple prevention TFTs for applying the low potential voltage to the Q1 and Q2 nodes in response to the front stage or rear stage carry pulses rising from a gate low voltage to a gate high voltage when rising to a high voltage The present invention can provide a gate shift register and a display device using the gate shift register that can improve the charging characteristic of the QB node by reducing the ripple of the Q node.

The shift register according to the embodiment of the present invention and the display device using the shift register prevent floating and deterioration of the discharge TFT connected between the QB node and the input terminal of the low potential voltage in each stage and operated in accordance with the shift direction switching signal, A scan output unit for outputting a scan pulse and a carry output unit for outputting a carry pulse can be provided to solve the signal delay problem caused by the line resistance. As the ripple of the Q node is reduced, A gate shift register and a display device using the gate shift register can be provided.

1 is a block diagram of a gate shift register according to an embodiment of the present invention;
2 is a circuit configuration diagram of the k-th stage STG (k).
3 is a waveform diagram of input and output signals of a k-th stage during a forward shift operation; Figs. 4 to 11 are diagrams showing the operation relationship of the k-th stage in the forward shift operation. Fig.
12 is a graph showing voltage and ripple voltage on a Q node;
13 is a block diagram of a display device according to an embodiment of the present invention.

Hereinafter, a gate shift register according to an embodiment of the present invention and a display using the same will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the embodiments disclosed herein but may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The dimensions and relative sizes of the layers and regions in the figures may be exaggerated for clarity of illustration.

It will be understood that when an element or layer is referred to as being another element or "on" or "on ", it includes both intervening layers or other elements in the middle, do. On the other hand, when a device is referred to as "directly on" or "directly above ", it does not intervene another device or layer in the middle.

The terms spatially relative, "below," "lower," "above," "upper," and the like, And may be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprise "and / or" comprising ", as used in the specification, means that the presence of stated elements, Or additions.

≪ Configuration of gate shift register >

1 schematically shows a gate shift register configuration according to an embodiment of the present invention.

Referring to FIG. 1, a gate shift register according to an embodiment of the present invention includes a plurality of stages STG (1) to STG (n) connected in a dependent manner and at least two dummy stages DT (0), DT n + 1)).

Each of the stages STG (1) to STG (n) has two output channels to output two scan pulses and two carry signal output channels to output two carry pulses. Stage stage referenced to k (1 &lt; k &lt; n) stage STG (k) corresponds to the k- (k-1) to the first dummy stage DT (0). Stage STG (k) is located at the bottom of the reference stage. For example, the rear stage referenced to k (1 <k <n) +1) to the second dummy stage DT (n + 1). The first dummy stage DT (0) outputs the carry signal Vd1 to be inputted to the subsequent stage and the second dummy stage DT (n + 1) outputs the carry signal Vd2 to be inputted to the preceding stage do.

The stages STG (1) to STG (n) are scanned in the forward shift mode in the order of the first stage STG (1) to kth stage STG (k) to nth stage STG (n) And outputs a pulse (Vout11 ---> Voutn2). In the forward shift mode, each of the stages STG (1) to STG (n) includes carry signals Vc of two different front stage stages applied as start signals to the first and second input terminals VST1 and VST2, And the carry signals Vc of two different rear stage stages applied as reset signals to the third and fourth input terminals VNT1 and VNT2. In the forward shift mode, a forward gate start pulse may be applied to the first and second input terminals VST1 and VST2 of the first stage STG (1) from the outside (timing controller).

The stages STG (1) to STG (n) are scanned in the reverse shift mode in the order of the n-th stage STG (n) to the k-th stage STG (k) And outputs a pulse (Voutn2 ---> Vout11). In the backward shift mode, each of the stages STG (1) to STG (n) includes carry signals Vc of two different front stage stages applied as reset signals to the first and second input terminals VST1 and VST2 , And the carry signals Vc of two different rear stage stages applied as the start signal to the third and fourth input terminals VNT1 and VNT2. In the backward shift mode, a reverse gate start pulse is externally applied to the third and fourth input terminals VNT1 and VNT2 of the n-th stage STG (n).

The gate shift register outputs scan pulses Vout11 to Voutn2 overlapping each other by a predetermined time. To this end, two gate shift clocks are input to i (i is a positive even-numbered) gate shift clocks which are overlapped and sequentially delayed by a predetermined time in each of the stages STG (1) to STG (n). It is preferable that the gate shift clocks are implemented in 6 phases or more in order to secure a sufficient charge time in high-speed operation of 240 Hz or more. The six-phase gate shift clocks CLK1 to CLK6 to be described below are each shifted by one horizontal period with a pulse width of three horizontal periods, and neighboring clocks are overlapped with each other by two horizontal periods.

The six-phase gate shift clocks (CLK1 to CLK6) swing between the gate high voltage (VGH) and the gate low voltage (VGL). The AC driving voltages VDD_E and VDD_O having a phase difference of 180 degrees between the gate high voltage VGH and the gate low voltage VGL and swinging opposite to each other are periodically supplied to the stages STG1 to STGn as shown in FIG. And is supplied with a low potential voltage VSS at a low low voltage (GND) or a gate low voltage (VGL) level. In the forward shift mode, the forward driving voltage VDD_F of the gate high voltage (VGH) level and the backward driving voltage (VDD_R) of the gate low voltage (VGL) level are supplied to the stages STG1 to STGn. In the reverse shift mode, the backward driving voltage VDD_R of the gate high voltage (VGH) level and the forward driving voltage (VDD_F) of the gate low voltage (VGL) level are supplied to the stages STG1 to STGn. The gate high voltage VGH is set to a voltage equal to or higher than the threshold voltage of the TFTs formed in the TFT array of the display device and the gate low voltage VGL is set to a voltage lower than the threshold voltage of the TFTs formed in the TFT array of the display device. The gate high voltage VGH may be set to about 20V to 30V, and the gate low voltage VGL may be set to about -5V.

<Circuit Configuration of Stage>

2 is an example showing a circuit configuration of the k-th stage STG (k). The circuit configuration of each of the other stages is substantially similar to that of Fig.

Referring to FIG. 2, two gate shift clocks (CLK A and CLK B) generated adjacent to each other among 6-phase clocks are input to the clock terminal of the k-th stage STG (k).

The k-th stage STG (k) includes an initialization unit 10 for initializing the Q1 node and the Q2 node in response to the frame reset signal VRST, a preamplifier 10 for inputting the front end input through the first and second input terminals VST1 and VST2 A scan direction controller 20 for switching the scan direction in response to the carry signals Vc and the subsequent carry signals Vc input through the third and fourth input terminals VNT1 and VNT2, A floating control unit 40 for preventing floating of discharge TFTs controlled according to the voltage of the second node N2, a node control unit 30 for controlling the charging and discharging of the nodes Q1, Q2 and QB2, And QB2 according to the voltages of the scan electrodes Y1, Y2 and QB2 and the scan signals Vout1 and Vout2 according to the voltages of the nodes Q1, Q2, QB1 and QB2, a carry output unit 60 for outputting two carry pulses Vc at the same timing as the first and second carry pulses V1 and V2 and the ripple prevention unit 70 for removing the ripple of the nodes Q1 and Q2 The.

The initialization section 10 includes a first reset TFT Trt1 and a second reset TFT Trt2. The first reset TFT Trt1 initializes the node Q1 to the low potential voltage VSS in response to the frame reset signal VRST. The low potential voltage VSS may be set to the ground low voltage GND or the gate low voltage VGL. The gate electrode of the first reset TFT (Trt1) is connected to the input terminal of the frame reset signal (VRST), the drain electrode thereof to the node Q1, and the source electrode thereof to the input terminal of the low potential voltage (VSS). The second reset TFT Trt2 initializes the node Q2 to the low potential voltage VSS in response to the frame reset signal VRST. The gate electrode of the second reset TFT (Trt2) is connected to the input terminal of the frame reset signal (VRST), the drain electrode thereof is connected to the node Q2, and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS).

The scan direction controller 20 includes first through third forward TFTs TF1 through TF3 and first through third reverse TFTs TR1 through TR3. The first forward TFT TF1 is driven in the forward direction in response to the second carry signal Vc (k-2) 2 of the (k-2) th stage STG (k-2) inputted through the first input terminal VST1 And applies the driving voltage VDD_F to the node Q1. The gate electrode of the first forward TFT TF1 is connected to the first input terminal VST1, the drain electrode thereof is connected to the input terminal of the forward drive voltage VDD_F, and the source electrode thereof is connected to the node Q1. The first reverse TFT TR1 is turned on in the reverse direction in response to the second carry signal Vc (k + 1) 2 of the (k + 1) th stage STG (k + 1) input through the third input terminal VNT1 And applies the driving voltage VDD_R to the node Q1. The gate electrode of the first reverse TFT (TR1) is connected to the third input terminal (VNT1), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the node Q1. The second forward TFT TF2 is driven in the forward direction in response to the first carry signal Vc (k-1) 1 of the (k-1) th stage STG (k-1) input through the second input terminal VST2 And applies the driving voltage VDD_F to the node Q2. The gate electrode of the second forward TFT TF2 is connected to the second input terminal VST2, the drain electrode thereof is connected to the input terminal of the forward drive voltage VDD_F, and the source electrode thereof is connected to the node Q2. The second reverse TFT TR2 is turned on in response to the first carry signal Vc (k + 2) 1 of the (k + 2) th stage STG (k + 2) input through the fourth input terminal VNT2 And applies the driving voltage VDD_R to the node Q2. The gate electrode of the second reverse TFT (TR2) is connected to the fourth input terminal (VNT2), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the node Q2. The third forward TFT TF3 is driven in the forward direction in response to the second carry signal Vc (k-2) 2 of the (k-2) th stage STG (k-2) inputted through the first input terminal VST1 And applies the driving voltage VDD_F to the second node N2. The gate electrode of the third forward TFT TF3 is connected to the first input terminal VST1, the drain electrode thereof is connected to the input terminal of the forward drive voltage VDD_F and the source electrode thereof is connected to the second node N2. The third reverse TFT TR3 is turned on in response to the first carry signal Vc (k + 2) 1 of the (k + 2) th stage STG (k + 2) input through the fourth input terminal VNT2 And applies the driving voltage VDD_R to the second node N2. The gate electrode of the third reverse TFT (TR3) is connected to the fourth input terminal (VNT2), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the second node (N2).

The node control unit 30 includes first and second TFTs T1 and T2 for controlling the Q1 node, a ninth and tenth TFTs T9 and T10 for controlling the Q2 node, Third to eighth TFTs T3 to T8, and eleventh to sixteenth TFTs T11 to T16 for controlling the QB2 node. The seventh TFT (T7) and the fifteenth TFT (T15) function as a discharge TFT for discharging QB1 and QB2, respectively. The operation deterioration of the seventh TFT T7 and the fifteenth TFT T15 is reduced to less than half because the QB1 node and the QB2 node are alternately activated in a period of a predetermined period (e.g., a frame period).

The first TFT (T1) discharges the node Q1 to the low potential voltage (VSS) according to the voltage of the node QB2. The gate electrode of the first TFT T1 is connected to the node QB2, the drain electrode thereof is connected to the node Q1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The second TFT T2 discharges the node Q1 to the low potential voltage VSS according to the voltage of the node QB1. The gate electrode of the second TFT T2 is connected to the node QB1, the drain electrode thereof is connected to the node Q1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The ninth TFT (T9) discharges the node Q2 to the low potential voltage (VSS) according to the voltage of the node QB1. The gate electrode of the ninth TFT T9 is connected to the QB1 node, the drain electrode thereof is connected to the node Q2, and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The tenth TFT (T10) discharges the node Q2 to the low potential voltage (VSS) according to the voltage of the node QB2. The gate electrode of the tenth TFT (T10) is connected to the node QB2, the drain electrode to the node Q2, and the source electrode to the input terminal of the low potential voltage (VSS).

The third TFT T3 is diode-connected to apply the alternate driving voltage VDD_O to the first node N1. The gate electrode and the drain electrode of the third TFT T3 are connected to the input terminal of the odd AC drive voltage VDD_O and the source electrode thereof is connected to the first node N1. The fourth TFT T4 switches the current path between the input terminals of the first node N1 and the low potential voltage VSS according to the voltage of the node Q1. The gate electrode of the fourth TFT T4 is connected to the node Q1, the drain electrode thereof is connected to the first node N1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The fifth TFT (T5) discharges the node QB1 to the low potential voltage (VSS) according to the voltage of the node Q1. The gate electrode of the fifth TFT (T5) is connected to the node Q1, the drain electrode is connected to the node QB1, and the source electrode is connected to the input terminal of the low potential voltage (VSS). The sixth TFT T6 charges the QB1 node to the odd AC drive voltage VDD_O according to the voltage of the first node N1. The gate electrode of the sixth TFT T6 is connected to the first node N1, the drain electrode thereof is connected to the input terminal of the odd AC drive voltage VDD_O and the source electrode thereof is connected to the node QB1. The seventh TFT T7 discharges the node QB1 to the low potential voltage VSS according to the voltage of the second node N2. The gate electrode of the seventh TFT T7 is connected to the second node N2, the drain electrode thereof is connected to the node QB1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The eighth TFT T8 switches the current path between the input terminals of the first node N1 and the low potential voltage VSS according to the voltage of the node Q2. The gate electrode of the eighth TFT T8 is connected to the node Q2, the drain electrode thereof is connected to the first node N1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The eleventh TFT T11 is diode-connected to apply the even-numbered ac driving voltage VDD_E to the third node N3. The gate electrode and the drain electrode of the eleventh TFT T11 are connected to the input terminal of the even AC drive voltage VDD_E and the source electrode thereof is connected to the third node N3. The twelfth TFT T12 switches the current path between the input terminal of the third node N3 and the low potential voltage VSS according to the voltage of the node Q2. The gate electrode of the twelfth TFT (T12) is connected to the node Q2, the drain electrode to the third node (N3), and the source electrode to the input terminal of the low potential voltage (VSS). The thirteenth TFT (T13) discharges the node QB2 to the low potential voltage (VSS) according to the voltage of the node Q2. The gate electrode of the thirteenth TFT (T13) is connected to the node Q2, the drain electrode is connected to the node QB2, and the source electrode is connected to the input terminal of the low potential voltage (VSS). The fourteenth TFT T6 charges the QB2 node to the even AC drive voltage VDD_E according to the voltage of the third node N3. The gate electrode of the fourteenth TFT T14 is connected to the third node N3, the drain electrode thereof is connected to the input terminal of the even AC drive voltage VDD_E and the source electrode thereof is connected to the node QB2. The fifteenth TFT T15 discharges the node QB2 to the low potential voltage VSS according to the voltage of the second node N2. The gate electrode of the fifteenth TFT T15 is connected to the second node N2, the drain electrode thereof is connected to the node QB2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The sixteenth TFT T16 switches the current path between the input terminals of the third node N3 and the low potential voltage VSS according to the voltage of the node Q1. The gate electrode of the sixteenth TFT T16 is connected to the node Q1, the drain electrode thereof is connected to the third node N3, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The floating preventing portion 40 may include a first floating preventing TFT TH1, a second floating preventing TFT TH2, a third anti-fliting TFT TH3, and a fourth floating preventing TFT TH4.

The first floating prevention TFT TH1 switches the current path between the input terminal of the second node N2 and the low potential voltage VSS according to the voltage of the node QB1. The gate electrode of the first floating prevention TFT TH1 is connected to the node QB1, the drain electrode thereof is connected to the second node N2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The first floating prevention TFT TH1 turns on the leakage charges accumulated in the second node N2 by preventing the floating of the seventh TFT T7 in the period in which the QB1 node is maintained at the charge level, VSS). As a result, the deterioration of the seventh TFT (T7) is prevented, and the abnormal turn-on of the seventh TFT (T7) is prevented and the output is stabilized in a period in which the QB1 node is maintained at the charge level.

The third floating prevention TFT TH3 switches the current path between the input terminal of the second node N2 and the input terminal of the low potential voltage VSS according to the voltage of the 1-1th output node NO11. The gate electrode of the third floating prevention TFT TH3 is connected to the 1-1th output node NO11, the drain electrode thereof is connected to the second node N2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The third floating prevention TFT TH3 is turned on when the scan pulse Vout (k1) / Vout (k2) rises to the gate high voltage VGH before the period when the QB1 node is maintained at the gate high voltage VGH, And prevents the floating of the seventh TFT T7, thereby discharging the leaked charges accumulated in the second node N2 to the input terminal of the low potential voltage VSS.

The second floating prevention TFT (TH2) switches the current path between the input terminal of the second node (N2) and the low potential voltage (VSS) according to the voltage of the node QB2. The gate electrode of the second floating prevention TFT TH2 is connected to the node QB2, the drain electrode thereof is connected to the second node N2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The second floating prevention TFT TH2 turns on the leakage charges accumulated in the second node N2 by preventing the floating of the fifteenth TFT T15 in the period in which the QB2 node is maintained at the charge level, VSS). As a result, the deterioration of the fifteenth TFT (T15) is prevented, and the abnormal turn-on of the fifteenth TFT (T15) is prevented and the output is stabilized in a period in which the node QB2 is maintained at the charge level.

The fourth floating prevention TFT TH4 switches the current path between the input terminal of the second node N2 and the input terminal of the low potential voltage VSS according to the voltage of the second-1 output node NO21. The gate electrode of the fourth floating prevention TFT TH4 is connected to the second-first output node NO21, the drain electrode thereof is connected to the second node N2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS . The fourth floating prevention TFT TH4 is turned on from the time when the scan pulse Vout (k1) / Vout (k2) is increased to the gate high voltage VGH before the period when the QB2 node is maintained at the gate high voltage VGH The floating gate of the fifteenth TFT T15 is turned off to discharge the leakage charges accumulated in the second node N2 to the input terminal of the low potential voltage VSS.

And holds the potential of the second node N2 longer by the gate-low voltage VGL by the third and fourth anti-flooding TFTs TH3 and TH4. As a result, the discharge TFTs T7 and T15 connected to the second node N2 for discharging the QB1 node or the QB2 node receive less gate-bias stress, so that the deterioration rate is further reduced.

The scan output unit 50 includes a first scan output unit for generating a first scan pulse Vout (k1) and a second output unit for generating a second scan pulse Vout (k2).

The first scan output section includes a 1-1 pull-up TFT (TU11) that turns on according to the voltage of the node Q1 to charge the 1-1 output node NO11 with the gate shift clock (CLK A), the voltage of the node QB1 The first 1-1 pull-down TFT (TD11) that turns on the first output node (NO11) to the low potential voltage (VSS) and turns on according to the voltage of the node QB2, And a first-second pull-down TFT (TD12) for discharging the first pull-down transistor (NO11) to the low-potential voltage (VSS). The 1-1 pull-up TFT TU11 is turned on due to the bootstrapping of the Q1 node, thereby charging the 1-1th output node NO11 with the gate shift clock signal CLK A, Vout (k1). The gate electrode of the 1-1 pull-up TFT (TU11) is connected to the node Q1, the drain electrode is connected to the input terminal of the gate shift clock (CLK A), and the source electrode is connected to the 1-1 output node (NO11). The 1-1 and 1-2 pull-down TFTs TD11 and TD12 are connected to the 1-1 output node NO11 according to the voltages of the QB1 node and the QB2 node, respectively, so that the first scan pulse Vout (k1) To the low-potential voltage VSS. The gate electrode of the 1-1 pull-down TFT (TD11) is connected to the QB1 node, the drain electrode thereof is connected to the 1-1th output node (NO11), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The gate electrode of the first-second pull-down TFT (TD12) is connected to the QB2 node, the drain electrode thereof is connected to the 1-1th output node (NO11), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The first scan pulse Vout (k1) is supplied to the corresponding scan line through the first output channel CH1.

The second scan output section includes a 2-1 pull-up TFT (TU21) for turning on the second-1 output node (NO21) with the gate shift clock (CLK B) according to the voltage of the node Q2, 2-1 pull-down TFT (TD21) that is turned on and discharges the second-1 output node (NO21) to the low-potential voltage (VSS), and a second- And a second -2 pull down TFT (TD22) for discharging node NO21 to the low potential voltage VSS. The 2-1 pull-up TFT (TU21) is turned on due to the bootstrapping of the Q2 node, thereby charging the 2-1 output node (NO21) with the gate shift clock (CLK B) to generate the second scan pulse Vout ). The gate electrode of the 2-1 pull-up TFT (TU21) is connected to the node Q2, the drain electrode is connected to the input terminal of the gate shift clock (CLK B), and the source electrode is connected to the 2-1 output node (NO21). The 2-1 and 2-2 pull-down TFTs TD21 and TD22 are connected to the second-1 output node NO21 according to the voltages of the QB1 node and the QB2 node, respectively, so that the second scan pulse Vout (k2) . The gate electrode of the second -1 pull-down TFT (TD21) is connected to the QB1 node, the drain electrode thereof is connected to the second-1 output node (NO21), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The gate electrode of the second pull-down TFT (TD22) is connected to the QB2 node, the drain electrode thereof is connected to the second-1 output node (NO21), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The second scan pulse Vout (k2) is supplied to the corresponding scan line through the second output channel CH2.

The carry output unit 600 includes a first carry output unit for generating a first carry pulse Vc (k1) and a second carry output unit for generating a second carry pulse (Vc (k2)).

The first carry output section includes a first 1-2 pull-up TFT (TU12) that turns on according to the voltage of the node Q1 to charge the first and second output nodes NO12 to the gate shift clock signal CLKA, And is turned on according to the voltage of the node QB2 to turn off the first and second output nodes NO12 and NO12 to the low potential voltage VSS, And a first to fourth pull-down TFT (TD14) for discharging the first voltage (NO12) to the low potential voltage (VSS). The first and second pull-up TFTs TU12 are turned on due to the bootstrapping of the Q1 node, thereby charging the first and second output nodes NO12 and G12 with the gate shift clock signal CLK A, Vc (k1). The gate electrode of the 1-2 pull-up TFT (TU12) is connected to the node Q1, the drain electrode is connected to the input terminal of the gate shift clock (CLK A), and the source electrode is connected to the 1-2 output node (NO12). The 1-3th and 1-4 pull-down TFTs TD13 and TD14 are connected to the 1-2nd output node NO12 according to the voltages of the QB1 node and the QB2 node, respectively, so that the first carry pulse Vc (k1) To the low-potential voltage VSS. The gate electrode of the first-third pull-down TFT (TD13) is connected to the QB1 node, the drain electrode thereof is connected to the 1-2th output node (NO12), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The gate electrode of the first-fourth pull-down TFT (TD14) is connected to the QB2 node, the drain electrode thereof is connected to the 1-2th output node (NO12), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The first carry pulse Vc (k1) is supplied to the fourth input terminal VNT2 of the (k-1) th stage STG (k + 1) And is supplied to the input terminal VST2.

The second carry output section includes a second -2 pull-up TFT (TU22) for turning on the second-2 output node (NO22) according to the voltage of the node Q2 with the gate shift clock (CLK B) And a second 2-3 pull-down TFT (TD23) for turning on the second-2 output node (NO22) to the low-potential voltage (VSS) according to the voltage of the node QB2, And a second-fourth pull-down TFT (TD24) for discharging node NO22 to the low potential voltage VSS. The second-2 pull-up TFT (TU22) is turned on due to the bootstrapping of the Q2 node, thereby charging the second-2 output node (NO22) with the gate shift clock (CLK B) to generate the second carry pulse ). The gate electrode of the 2-2 pull-up TFT (TU22) is connected to the node Q2, the drain electrode is connected to the input end of the gate shift clock (CLK B), and the source electrode is connected to the 2-2 output node (NO22). The second and third pull-down TFTs TD23 and TD24 are connected to the second-second output node NO22 according to the voltages of the QB1 node and the QB2 node, respectively, so that the second carry pulse Vc (k2) . The gate electrode of the 2-3 pull-down TFT (TD23) is connected to the QB1 node, the drain electrode thereof is connected to the 2-2 output node (NO22), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The gate electrode of the 2-4 pull-down TFT (TD24) is connected to the QB2 node, the drain electrode thereof is connected to the 2-2 output node (NO22), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The second carry pulse Vc (k2) is applied to the third input terminal VNT1 of the (k + 1) th stage STG (k + 1) And is supplied to the input terminal VST1.

The ripple prevention portion 70 may include a first ripple prevention portion for removing ripple on the Q1 node and a second ripple prevention portion for removing ripple on the Q2 node.

The first and second ripple prevention units are arranged in the k-th stage STG (k) after the k-th stage STG (k) outputs the first and second scan pulses Vout (k1) and Vout When the first and second gate shift clocks CLK A and CLK B input from the gate low voltage VGL to the gate high voltage VGL are first rising from the gate low voltage VGL to the gate high voltage VGH, ) To the Q1 and Q2 nodes in response to the previous or subsequent carry pulses.

The first ripple prevention portion includes a first ripple prevention TFT TC1 and the gate electrode of the first ripple prevention TFT TC1 is connected to the first carry pulse of the (k + 3) th stage STG (k + 3) The first carry pulse Vc (k + 3) 1 is input from the 1-2 output node NO12 of the (k + 3) th stage STG (k + 3) The drain terminal is connected to the node Q1, and the source terminal is connected to the input terminal of the low potential voltage VSS, respectively. The first ripple prevention TFT TC1 is turned on by the first carry pulse Vc (k + 3) 1 of the (k + 3) th stage STG (k + 3) ). &Lt; / RTI &gt; In this case, since the (k + 3) th stage STG (k + 3) outputs the first carry pulse Vc (k + 3) 1 at the time when CLK A becomes high level, Gt; (k) &lt; / RTI &gt; of the k-th stage STG (k).

The second ripple prevention portion is formed of a second ripple prevention TFT TC2 and the gate electrode of the second ripple prevention TFT TC2 is connected to the second carry pulse of the (k + 3) th stage STG (k + 3) The second carry pulse Vc (k + 3) 2 is output from the (2 + 2) th output node NO22 of the (k + 3) th stage STG The drain terminal is connected to the node Q2, and the source terminal is connected to the input terminal of the low potential voltage VSS, respectively. In this case, since the (k + 3) th stage STG (k + 3) outputs the second carry pulse Vc (k + 3) 2 at the time when CLK B becomes a high level, Gt; (k) &lt; / RTI &gt; of the k-th stage STG (k).

<Forward shift mode>

Fig. 3 shows the input and output signals of the k-th stage in a forward shift operation. And Figs. 4 to 11 show the operation relationship of the k-th stage in the forward shift operation. 12 is a graph showing the voltage on the Q node and the ripple voltage. The forward shift operation of the k-th stage STG (k) will be described step by step with reference to FIGS. 2 and 3. FIG.

2 and 3, a forward gate start pulse (not shown) is generated in the forward shift mode, and the six-phase gate shift clocks CLK1 to CLK6 are generated from the first gate shift clock CLK1 to the sixth gate shift And is generated as a circulating clock that is sequentially delayed to the clock (CLK6). In the forward shift mode, the forward drive voltage VDD_F is input to the gate high voltage (VGH) level, and the reverse drive voltage (VDD_R) is input to the gate low voltage (VGL) level. In the forward shift mode, "CLK A" input to the k-th stage STG (k) is assumed to be "CLK 1" and "CLK A" is assumed to be "CLK 2".

First, it is explained that the k-th stage STG (k) operates in odd frame in this forward shift mode. Here, the odd frame may include a group of odd-numbered frames including a single odd-numbered frame and a plurality of adjacent frames. In the odd frame, the odd AC drive voltage VDD_O is input to the gate high voltage (VGH) level and the even AC drive voltage VDD_E is input to the gate low voltage (VGL) level.

In addition, the QB2 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs (T1, T10, T14, T24, TD12, and TD22) to which the gate electrode is connected to the QB2 node are kept in the turn-off state (that is, kept in the idle driving state). In Fig. 3, "VQ1" represents the potential of the Q1 node, "VQ2" represents the potential of the Q2 node, and "VQB1" represents the potential of the QB1 node.

The second carry signal Vc (k-2) 2 of the (k-2) th stage STG (k-2) through the first input terminal VST1 at the times T1 and T2 as a start signal . The first and third forward TFTs TF1 and TF3 are turned on in response to the start signal. As a result, the Q1 node is charged to the gate high voltage (VGH), and the QB1 node is discharged to the gate low voltage (VGL).

The first carry signal Vc (k-1) 1 of the (k-1) th stage STG (k-1) through the second input terminal VST2 as the start signal at time T2 and T3 . The second forward TFT TF2 is turned on in response to the start signal. As a result, the node Q2 is charged to the gate high voltage VGH.

At times T3 and T4, as shown in FIG. 6, the first gate shift clock CLK1 is applied to the drain electrode of the 1-1 pull-up TFT TU11. The voltage of the node Q1 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the 1-1 pull-up TFT TU11, 1 pull-up TFT (TU11). Therefore, at time T3 and T4, the voltage of the 1-1th output node NO11 rises to the gate high voltage VGH to rise the first scan pulse Vout (k1).

In the same manner, at the times T3 and T4, the first gate shift clock CLK1 is applied to the drain electrode of the first and second pull-up TFTs TU12. The voltage of the node Q1 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the first and second pull-up TFTs TU12, 2 pull-up TFT (TU12) is turned on. Therefore, at time T3 and T4, the voltage of the 1-2th output node NO12 rises to the gate high voltage VGH to raise the first carry pulse Vc (k1).

At times T4 and T5, the second gate shift clock CLK2 is applied to the drain electrode of the second -1 pull-up TFT (TU21) as shown in FIG. The voltage of the node Q2 is raised to a voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the 2-1 pull-up TFT TU21, 1 pull-up TFT (TU21) is turned on. Therefore, at time T4 and T5, the voltage of the second-1 output node NO21 rises to the gate high voltage VGH to rise the second scan pulse Vout (k2).

In the same manner, at the times T4 and T5, the second gate shift clock CLK2 is applied to the drain electrode of the second-second pull-up TFT (TU22). The voltage of the node Q2 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the second-2 pull-up TFT TU22, 2 pull-up TFT (TU22) is turned on. Thus, at time T4 and T5, the voltage of the second-2 output node NO22 rises to the gate high voltage VGH to rise the second carry pulse Vc (k2).

In this manner, by outputting the scan pulse from the scan output section 50 and outputting the carry pulse from the carry output section 60, the line resistance can be reduced to minimize the signal delay.

At time T5, the second carry signal Vc (k + 1) 2 of the (k + 1) th stage STG (k + 1) is input as a reset signal through the third input terminal VNT1 as shown in Fig. 8 . In response to this reset signal, the first reverse TFT (TR1) is turned on. As a result, the node Q1 is discharged to the gate-low voltage VGL. The 1-1 and the 1-2 pull-up TFTs TU11 and TU12 are turned off due to the discharge of the node Q1. On the other hand, even if the fourth TFT (T4) is turned off due to the discharge of the node Q1, the node QB1 maintains the gate low voltage (VGL) by the turn-on of the eighth TFT (T8). At time T5, the first scan pulse Vout (k1) is polled to the gate low voltage VGL.

At time T6, the first carry signal Vc (k + 2) 1 of the (k + 2) th stage STG (k + 2) is inputted as a reset signal through the fourth input terminal VNT2 as shown in Fig. 9 . In response to this reset signal, the second reverse TFT (TR2) is turned on. As a result, the Q2 node is discharged to the gate low voltage (VGL). And the 2-1 and 2-2 pull-up TFTs (TU21 and TU22) are turned off due to the discharge of the Q2 node. Then, since the eighth TFT T8 is turned off due to the discharge of the node Q2, the node QB1 is turned to the odd alternating driving voltage VDD_O at the gate high voltage (VGH) level applied through the sixth TFT T6 Is charged. The pull-down TFTs TD11, TD12, TD21 and TD22 are turned on due to the charging of the QB1 node. Accordingly, the voltage of the 1-1 and 1-2 output nodes NO11 and NO12 falls to the gate low voltage VGL and the first scan pulse Vout (k1) and the first carry pulse Vc (k1 ), And the voltage of the second-first and second-2 output nodes NO21 and NO22 falls to the gate low voltage VGL and the second scan pulse Vout (k2) (Vc (k1)). The first floating prevention TFT TH1 is turned on due to the charging of the node QB1 and continuously applies the gate low voltage VGL to the second node N2 to prevent the deterioration and the abnormal state of the seventh TFT T7 Prevent operation.

At time T7, the first carry pulse Vc (k + 3) from the (k + 3) th stage STG (k + 3) is applied to the gate electrode of the first ripple prevention TFT (TC1) at the time when CLK A becomes high level, (k + 3) 1) is applied, and the node Q1 is discharged to the low potential voltage (VSS). Therefore, the ripple on the Q1 node can be reduced as shown in FIG.

At the time T8, the second carry pulse Vc (k + 3) from the (k + 3) th stage STG (k + 3) is applied to the gate electrode of the second ripple prevention TFT (TC2) (k + 3) 2) is applied, and the node Q2 is discharged to the low potential voltage (VSS). Therefore, the ripple on the Q2 node can be reduced as shown in FIG.

In particular, the operation timings of the first and second anti-ripple TFTs TC1 and TC2 are matched to the second pulse of CLK A and CLK B because the first and second anti-ripple TFTs Q1 and Q2 Since the first and second ripple prevention TFTs TC1 and TC2 are driven only when the ripple of the highest level is removed and the first and second ripple prevention TFTs TC1 and TC2 are not driven during the remaining period, 2 degradation of the ripple prevention TFTs (TC1, TC2) can be minimized.

Next, it is explained that the k-th stage STG (k) operates in an even frame in the forward shift mode. Here, an even frame may include a frame group arranged at the even-numbered frame including a single frame and a plurality of adjacent frames arranged at the odd-numbered frame. The odd AC drive voltage VDD_E is input to the gate high voltage VGH level and the odd AC drive voltage VDD_O is input to the gate low voltage VGL level. In addition, the QB1 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T2, T9, TD11, TD13, TD21 and TD24 to which the gate electrode is connected to the QB1 node are kept in the turn-off state (that is, kept in the idle driving state). The operation in the even frame is such that the voltage of the output nodes NO11, NO12, NO21 and NO22 is controlled by the QB2 node and the second and fourth floating prevention TFTs TH2 and TH4 are operated, (K1) and the second carry pulse (Vc (k2)), the first carry pulse (Vc (k1)) and the second carry pulse (Vc ) Is substantially the same as that in the radix frame. Therefore, detailed description of the operation in the even frame will be omitted.

<Reverse shift mode>

The backward shift operation of the k-th stage STG (k) will be described step by step with reference to FIG.

Referring to FIG. 2, a reverse gate start pulse (not shown) is generated in the reverse shift mode, and the 6-phase gate shift clocks CLK1 to CLK6 are shifted from the sixth gate shift clock CLK1 to the first gate shift clock CLK1 ), Which are sequentially delayed. In the reverse shift mode, the reverse drive voltage VDD_R is input to the gate high voltage VGH level, and the forward drive voltage VDD_F is input to the gate low voltage VGL level. In the backward shift mode, "CLK A" input to the k-th stage STG (k) is assumed to be "CLK 5" and "CLK A" is assumed to be "CLK 6".

First, it is explained that the k-th stage STG (k) operates in an odd frame in this backward shift mode. Here, the odd frame may include a single frame arranged at odd-numbered positions and a group of frames arranged at odd-numbered positions including a plurality of adjacent frames. In the odd frame, the odd AC drive voltage VDD_O is input to the gate high voltage (VGH) level and the even AC drive voltage VDD_E is input to the gate low voltage (VGL) level. In addition, the QB2 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs (T1, T10, T14, T24, TD12, and TD22) to which the gate electrode is connected to the QB2 node are kept in the turn-off state (that is, kept in the idle driving state).

The first carry signal Vc (k + 2) 1 of the (k + 2) th stage STG (k + 2) is input as the start signal through the fourth input terminal VNT2 at times T1 and T2. The second and third reverse TFTs TR2 and TR3 are turned on in response to the start signal. As a result, the Q2 node is charged to the gate high voltage (VGH), and the QB1 node is discharged to the gate low voltage (VGL).

The second carry signal Vc (k + 1) 2 of the (k + 1) th stage STG (k + 1) is input as the start signal through the third input terminal VNT1 in the times T2 and T3. The first reverse TFT (TR1) is turned on in response to the start signal. As a result, the node Q1 is charged to the gate high voltage VGH.

At times T3 and T4, a sixth gate shift clock (CLK6) is applied to the drain electrode of the second -1 pull-up TFT (TU21). The voltage of the node Q2 is raised to a voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the 2-1 pull-up TFT TU21, 1 pull-up TFT (TU21) is turned on. Therefore, the voltage of the second-1 output node NO21 rises to the gate high voltage VGH at time T3 and T4 to rise the second scan pulse Vout (k2). A sixth gate shift clock (CLK6) is applied to the drain electrode of the second -2 pull-up TFT (TU22). The voltage of the node Q2 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the second-2 pull-up TFT TU22, 2 pull-up TFT (TU22) is turned on. Thus, at time T3 and T4, the voltage of the second-2 output node NO22 rises to the gate high voltage VGH to rise the second carry pulse Vc (k2).

At times T4 and T5, a fifth gate shift clock (CLK5) is applied to the drain electrode of the 1-1 pull-up TFT (TU11). The voltage of the node Q1 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the 1-1 pull-up TFT TU11, 1 pull-up TFT (TU11). Therefore, at time T4 and T5, the voltage of the 1-1th output node NO11 rises to the gate high voltage VGH to rise the first scan pulse Vout (k1). A fifth gate shift clock (CLK5) is applied to the drain electrode of the first pull-up TFT (TU12). The voltage of the node Q1 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the first and second pull-up TFTs TU12, 2 pull-up TFT (TU12) is turned on. Thus, at time T4 and T5, the voltage of the 1-2th output node NO12 rises to the gate high voltage VGH to raise the first carry pulse Vc (k1).

At time T5, the first carry signal Vc (k-1) 1 of the (k-1) th stage STG (k-1) is inputted as a reset signal through the second input terminal VST2. In response to this reset signal, the second forward TFT TF2 is turned on. As a result, the Q2 node is discharged to the gate low voltage (VGL). The second pull-up TFT (TU2) is turned off due to the discharge of the node Q2. On the other hand, at time T5, the QB1 node holds the gate low voltage VGL by turning on the fourth TFT T4 and the second scan pulse Vout (k2) is polled to the gate low voltage VGL do.

At time T6, the second carry signal Vc (k-2) 2 of the (k-2) th stage STG (k-2) is inputted as a reset signal through the first input terminal VST1. In response to this reset signal, the first forward TFT TF1 is turned on. As a result, the node Q1 is discharged to the gate-low voltage VGL. The 1-1 pull-up TFT (TU11) is turned off due to the discharge of the node Q1. Since the fourth TFT T4 is turned off due to the discharge of the node Q1, the node QB1 is turned to the odd alternating drive voltage VDD_O at the gate high voltage (VGH) level applied through the sixth TFT T6 Is charged. The first, third, second, and second pull-down TFTs TD11, TD13, TD21, and TD24 are turned on due to the charging of the QB1 node. Thus, the voltages of the second and first-second output nodes NO21 and NO22 fall to the gate low voltage VGL to generate the second scan pulse Vout (k2) and the second carry pulse Vc (k2 ) And the voltages of the 1-1 and 1-2 output nodes NO11 and NO12 are lowered to the gate low voltage VGL so that the first scan pulse Vout (k1) and the first carry pulse Vout (Vc (k1)). The first floating prevention TFT TH1 is turned on due to the charging of the node QB1 and continuously applies the gate low voltage VGL to the second node N2 to prevent the deterioration and the abnormal state of the seventh TFT T7 Prevent operation.

At time T7, the second carry pulse Vc (k + 3) from the (k + 3) th stage STG (k + 3) is applied to the gate electrode of the second ripple prevention TFT (TC2) ) 2 is applied, and the node Q2 is discharged to the low potential voltage VSS. Thus, the ripple on the Q2 node can be reduced.

At time T8, the first carry pulse Vc (k + 3) from the (k + 3) th stage STG (k + 3) is applied to the gate electrode of the first ripple prevention TFT (TC1) ) 1 is applied, and the node Q1 is discharged to the low potential voltage VSS. Thus, the ripple on the Q1 node can be reduced.

Next, it is described that the k-th stage STG (k) operates in the even frame in the backward shift mode. Here, an even frame may include a single frame arranged at the even-numbered frame and a frame group arranged at the even-numbered frame including a plurality of adjacent frames. The odd AC drive voltage VDD_E is input to the gate high voltage VGH level and the odd AC drive voltage VDD_O is input to the gate low voltage VGL level. In addition, the QB1 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T2, T9, TD11, TD13, TD21 and TD24 to which the gate electrode is connected to the QB1 node are kept in the turn-off state (that is, kept in the idle driving state). The operation in the even frame is different from the operation in the odd frame in that the voltages of the output nodes NO11, NO12, NO21 and NO22 are controlled by the QB2 node and the second floating prevention TFT TH2 is operated The timing of generation of the first scan pulse Vout (k1) and the second scan pulse Vout (k2), the first carry pulse Vc (k1) and the second carry pulse Vc (k2) As in the radix frame. Therefore, detailed description of the operation in the even frame will be omitted.

<Display device>

13 schematically shows a display device according to an embodiment of the present invention.

Referring to FIG. 13, the display device of the present invention includes a display panel 100, a data driving circuit, a scan driving circuit, and a timing controller 110.

The display panel 100 includes data lines and scan lines which intersect with each other, and pixels arranged in a matrix form.

The display panel 100 may be implemented as a display panel of any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

The data driving circuit includes a plurality of source drive ICs 120. [ The source drive ICs 120 receive the digital video data RGB from the timing controller 110. The source driver ICs 120 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, To the data lines of the display panel 100 as shown in FIG. The source drive ICs may be connected to the data lines of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The scan driver circuit includes a timing controller 110 and a level shifter 150 connected between the scan lines of the display panel 100 and a gate shift register 130. The level shifter 150 outputs a TTL (Transistor-Transistor-Logic) logic level voltage of the six-phase gate shift clocks CLK1 to CLK6 input from the timing controller 110 to the gate high voltage VGH and the gate low voltage VGL ).

The gate shift register 130 is composed of stages for shifting the gate start pulse VST to the gate shift clocks CLK1 to CLK6 and sequentially outputting the carry signal Cout and the scan pulse Vout as described above do.

The scan driver circuit may be formed directly on the lower substrate of the display panel 100 using a GIP (Gate In Panel) method or may be connected between the gate lines of the display panel 100 and the timing controller 110 in a TAB manner. In the GIP scheme, the level shifter 150 is mounted on the PCB 140, and the gate shift register 130 may be formed on the lower substrate of the display panel 100.

The timing controller 110 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 110 transmits digital video data (RGB) input from the host computer to the source drive ICs 120.

The timing controller 110 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 110 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage.

The scan timing control signal includes gate start pulses, gate shift clocks (CLK1 to CLK6), gate output enable (GOE) signals (not shown), and the like. The gate start pulse includes a forward gate start pulse and a reverse gate start pulse. The gate start pulse is input to the gate shift register 130 to control the shift start timing. The gate shift clocks CLK1 to CLK6 are level shifted through the level shifter 150 and then input to the gate shift register 130 and used as a clock signal for shifting the gate start pulse VST. The gate output enable signal GOE controls the output timing of the gate shift register 130.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 110 and the source drive ICs 120 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the gate shift register according to the present invention and the display device using the gate shift register are connected between the QB1 / QB2 node and the input terminal of the low potential voltage in each stage of the gate shift register, and the discharge TFT It is possible to prevent floating and deterioration of the discharge TFT, and further stabilize the stage output. The reliability of the scan driver circuit can be improved by reducing the ripple of the nodes Q1 and Q2.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10 initialization unit
20 scan direction control section
30 node control section
40 Floating prevention part
50 Scan output section
60 carry output
70 Ripple prevention part
100 display panel
110 timing controller
120 Source drive IC
130 gate shift register
140 PCB
150 Level Shifter

Claims (10)

And a plurality of stages for receiving a plurality of gate shift clocks and sequentially outputting a scan pulse and a carry pulse,
The k-th stage of the plurality of stages includes:
A scan direction controller for switching the shift direction of the scan pulse and the carry pulse in response to the preceding carry pulse input through the first and second input terminals and the subsequent carry pulses input through the third and fourth input terminals, ;
And a discharge TFT (Thin Film Transistor) for controlling charging and discharging of the Q1 node, the Q2 node, the QB1 node, and the QB2 node and discharging the QB1 node or the QB2 node to a low potential voltage in accordance with the shift direction switching signal, ;
A floating prevention unit for applying the low potential voltage to the gate electrode of the discharge TFT in accordance with the voltage of the QB1 node or the QB2 node and the first and second scan pulses;
A scan output circuit for outputting the first scan pulse through the first output node according to the voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node and outputting the second scan pulse through the second output node; part; And
A carry output unit for outputting a first carry pulse through a first 1-2 output node and a second carry pulse through a second 2-2 output node according to voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node; And a gate shift register. The method according to claim 1,
When the first and second gate shift clocks, which are input to the k-th stage after the first and second scan pulse outputs, first rise from a gate low voltage to a gate high voltage, Further comprising: ripple prevention TFTs for applying the low potential voltage to the Q1 and Q2 nodes in response to a front stage or rear stage carry pulses rising at a gate high voltage. 3. The method of claim 2,
The discharge TFT includes a first discharge TFT connected between the QB1 node and the input terminal of the low potential voltage, and a second discharge TFT connected between the QB2 node and the input terminal of the low potential voltage;
The floating-
A first floating prevention TFT for switching a current path between a gate electrode of the first discharge TFT and an input end of the low potential voltage according to a voltage of the QB1 node;
A second floating prevention TFT for switching a current path between a gate electrode of the second discharge TFT and an input end of the low potential voltage in accordance with the voltage of the QB2 node;
A third floating prevention TFT for switching a current path between a gate electrode of the first discharge TFT and an input end of the low potential voltage according to the voltage of the 1-1th output node; And
And a fourth floating-prevention TFT for switching the current path between the gate electrode of the second discharge TFT and the input end of the low potential voltage in accordance with the voltage of the first-second output node. The method according to claim 1,
The first scan pulse and the first carry pulse are output at the same timing,
And the second scan pulse and the second carry pulse are output at the same timing. 5. The method of claim 4,
A first ripple prevention TFT for applying the low potential voltage to the node Q1; And a second ripple prevention TFT for applying the low potential voltage to the Q2 node,
The first anti-reflection TFT is connected to the 1-2 output node of the (k + 3) -th stage,
And the second anti-ripple TFT is connected to a (2-2) output node of the (k + 3) -th stage. The method according to claim 1,
Wherein the carry output unit comprises:
A first 1-2 pull-up TFT controlled by a voltage on the Q1 node and connected between a first gate shift clock input terminal and the 1-2 output node;
A third pull-down TFT controlled by the voltage on the QB1 node and connected between the first and second output nodes and the input of the low potential voltage;
A first pull-down TFT controlled by a voltage on the QB2 node and connected between the first and second output nodes and an input terminal of the low potential voltage;
A second-2 pull-up TFT controlled by the voltage on the Q2 node and connected between the second gate shift clock input terminal and the second-2 output node;
A second &lt; RTI ID = 0.0 &gt; 2-3 &lt; / RTI &gt; pull down TFT controlled by the voltage on the QB2 node and connected between the 2-2 output node and the input of the low potential voltage; And
And a second-fourth pull-down TFT controlled by a voltage on the QB1 node and connected between the second-second output node and an input terminal of the low potential voltage. A display panel including a plurality of pixels intersecting the data lines and the scan lines and arranged in a matrix form;
A data driving circuit for supplying a data voltage to the data lines; And
And a scan driving circuit for sequentially supplying scan pulses to the scan lines,
Wherein the scan driving circuit sequentially receives a plurality of gate shift clocks whose phases are shifted, sequentially outputs a scan pulse and a carry pulse, and has a plurality of stages connected in a dependent manner;
The k-th stage of the plurality of stages includes:
A scan direction controller for switching the shift direction of the scan pulse and the carry pulse in response to the preceding carry pulse input through the first and second input terminals and the subsequent carry pulses input through the third and fourth input terminals, ;
A node controller including a discharge TFT for controlling charging and discharging of the Q1 node, the Q2 node, the QB1 node and the QB2 node, and discharging the QB1 node or the QB2 node to a low potential voltage in accordance with the shift direction switching signal;
A floating prevention unit for applying the low potential voltage to the gate electrode of the discharge TFT in accordance with the voltage of the QB1 node or the QB2 node and the first and second scan pulses;
A scan output circuit for outputting the first scan pulse through the first output node according to the voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node and outputting the second scan pulse through the second output node; part; And
A carry output unit for outputting a first carry pulse through a first 1-2 output node and a second carry pulse through a second 2-2 output node according to voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node; . 8. The method of claim 7,
When the first and second gate shift clocks, which are input to the k-th stage after the first and second scan pulse outputs, first rise from a gate low voltage to a gate high voltage, And ripple prevention TFTs for applying the low potential voltage to the Q1 and Q2 nodes in response to the front stage or rear stage carry pulses rising at a gate high voltage. 8. The method of claim 7,
The first scan pulse and the first carry pulse are output at the same timing,
And the second scan pulse and the second carry pulse are outputted at the same timing. 10. The method of claim 9,
A first ripple prevention TFT for applying the low potential voltage to the node Q1; And a second ripple prevention TFT for applying the low potential voltage to the Q2 node,
The first anti-reflection TFT is connected to the 1-2 output node of the (k + 3) -th stage,
And the second anti-ripple TFT is connected to the (2-2) output node of the (k + 3) -th stage.

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