KR20130017281A - Shift register and display device using the same - Google Patents

Abstract

PURPOSE: A shift register and a display device using the same are provided to prevent the breakdown of a gate insulation layer in thin film transistors by supplying a gate low voltage to a gate electrode in voltage blocking transistors. CONSTITUTION: A Q node discharging unit discharges a Q node(Q) to a gate low voltage. A QB node charging unit charges a QB node(QB) with a gate high voltage. A Q node charging unit implements a Q node with a gate high voltage. A QB node discharging unit discharges the QB node with the gate low voltage. A Q node voltage blocking unit blocks connection between the Q node discharge unit, the Q node charging unit, and the Q node. An output unit outputs a pulse synchronized with a clock inputted through a clock terminal.

Description

SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a shift register and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, a variety of flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes. For example, various flat panel displays such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) display are utilized.

The display device displays an image by using a gate driving circuit which supplies a scan signal to gate lines of the display panel and a data driving circuit which supplies a data voltage to the data lines. Recently, the gate driving circuit mounts a plurality of gate drive integrated circuits on a printed circuit board (PCB) and directly attaches the GIP (Gate Drive) to the bottom of the display panel rather than attaching the tape automated bonding (TAB) method. IC in Panel). When the gate driving circuit is formed by the GIP method, the organic light emitting diode display device can be made slimmer than the gate driving circuit is formed by the conventional TAB method, thereby increasing the external aesthetics and reducing the cost. The display panel maker may directly design a plurality of scan signals for compensating the threshold voltage of the driving transistor of the pixel of the panel.

The shift register of the gate driving circuit includes stages including a plurality of thin film transistors. Stages are cascaded to generate output sequentially. However, as a result of aging the pixel circuit using the shift register of the gate driving circuit formed by the GIP method, a sudden voltage change of a specific node controlling the output of the shift register (for example, a boot generated when a signal is outputted) Due to the bootstrapping, the potential difference between the gate electrode and the source or drain electrode of the thin film transistors connected to the specific node is found to be large. As a result, the gate insulator of the thin film transistors connected to the specific node may be destroyed. In this case, since the potential of the specific node controlling the output of the shift register is shaken, the output of the shift register is abnormally generated. Abnormal output of the shift register results in a bad lighting of the horizontal line of the display panel.

The present invention provides a shift register and a display device using the same which can prevent the gate insulating layer breakdown of the thin film transistors connected to a specific node controlling the output.

The shift register of the present invention includes a plurality of stages that receive a start voltage, i.e. (i is a natural number of 4 or more) phases of which the phase is sequentially delayed, and sequentially generate outputs. Is a natural number satisfying 1 ≦ k ≦ n, and n is the number of stages). The stage may include: a Q node discharge unit configured to discharge the Q node to a gate low voltage in response to signals input through the first and second start terminals; A QB node charger configured to charge a QB node to a gate high voltage higher than the gate low voltage in response to a signal input through the first start terminal or in response to a gate low voltage of the Q node; A Q node charger configured to charge the Q node to the gate high voltage in response to the gate low voltage of the QB node; A QB node discharge unit configured to discharge the QB node to the gate low voltage in response to a signal input through a reset terminal; The Q node discharger, the Q node charger, when connected between the Q node discharger, the Q node charger, and the Q node, and when the Q node bootstrap and drops to a voltage level lower than the gate low voltage And a Q node voltage blocking unit to block a connection between the Q nodes. And an output unit configured to output a pulse synchronized with a clock input through a clock terminal according to the voltages of the Q node and the QB node.

According to an exemplary embodiment of the present invention, a display device includes: a display panel including data lines and scan lines intersecting the data lines; A data driving circuit for supplying a data voltage to the data lines; And a shift register configured to sequentially supply scan pulses to the scan lines in synchronization with the data voltage, wherein the shift register includes a start voltage and i whose phase is sequentially delayed (i equals 4). And a plurality of stages that sequentially receive output clocks of phase clocks, and sequentially generate outputs, wherein k is a natural number satisfying 1 ≦ k ≦ n, and n is the number of stages. A Q node discharge unit configured to discharge the Q node to a gate low voltage in response to a signal input through the first and second start terminals; A QB node charger configured to charge a QB node to a gate high voltage higher than the gate low voltage in response to a signal input through the first start terminal or in response to a gate low voltage of the Q node; A Q node charger configured to charge the Q node to the gate high voltage in response to the gate low voltage of the QB node; A QB node discharge unit configured to discharge the QB node to the gate low voltage in response to a signal input through a reset terminal; The Q node discharger, the Q node charger, when connected between the Q node discharger, the Q node charger, and the Q node, and when the Q node bootstrap and drops to a voltage level lower than the gate low voltage And a Q node voltage blocking unit to block a connection between the Q nodes. And an output unit configured to output a pulse synchronized with a clock input through a clock terminal according to the voltages of the Q node and the QB node.

The present invention further forms voltage blocking transistors for preventing the gate insulating film breakage of the thin film transistors connected to the Q node controlling the output of the shift register, and supplies a gate low voltage to the gate electrode of the voltage blocking transistors. As a result, the present invention can prevent destruction of the gate insulating film of the thin film transistors connected to the Q node. For this reason, the present invention can prevent abnormal output of the shift register, thereby preventing the horizontal line lighting failure of the display panel.

1 is a block diagram schematically illustrating a configuration of a shift register of a gate driving circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage of FIG. 1.
3 is a waveform diagram illustrating input and output signals of a k-th stage of FIG. 2.
4 is a block diagram schematically illustrating a configuration of a shift register of a gate driving circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage of FIG. 4.
6A and 6B are waveform diagrams showing input and output signals of the k-th stage of FIG. 5 in a forward or reverse mode.
FIG. 7 is a circuit diagram illustrating another example of a circuit configuration of a k-th stage of FIG. 4.
8 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.
9 is a waveform diagram illustrating input and output signals of the level shifter of FIG. 8.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. Component names used in the following description may be selected in consideration of ease of specification, and may be different from actual product part names.

1 is a block diagram schematically illustrating a configuration of a shift register of a gate driving circuit according to a first embodiment of the present invention. Referring to FIG. 1, the shift register according to the first embodiment of the present invention includes a plurality of stages (ST (1) to ST (n) where n is a natural number of stages) connected in a cascade manner. In FIG. 1, for convenience of description, only the first to third stages ST (1) to ST (3) are illustrated.

In the following description, the "shear stage" refers to being located on top of the stage to be a reference. For example, on the basis of kth (1 <k <n, k, k are two or more natural numbers) stages ST (k), the front end stages are the first stage ST (1) to the k-1st stage ST. (k-1)). The "back stage" refers to being located at the lower part of the stage used as a reference. For example, based on the k-th stage ST (k), the rear stage indicates any one of the k + 1th stage ST (k + 1) to the nth stage ST (n).

The start voltage VST is applied to the start voltage line VSTL, and the first clock CLK1 is applied to the first clock line CL1. In addition, a second clock CLK is applied to the second clock line CL2, a third clock CLK3 is applied to the third clock line CL3, and a fourth clock (CL4) is applied to the fourth clock line CL4. CLK4) is applied.

Each of the stages ST (1) to ST (n) includes first and second start terminals START1 and START2, a clock terminal CLK, a reset terminal RESET, and an output terminal OUT. The start voltage VST or the carry signal of the previous stage is input to the first start terminal START1 of each of the stages ST (1) to ST (n). For example, as shown in FIG. 1, a start voltage VST is applied to the first start terminal START1 of the first stage ST (1), and the second to nth stages ST (2) to ST ( n)) The carry signal of the preceding stage is input to each first start terminal START1.

Phase i (i is a natural number of 4 or more) whose phase is sequentially delayed in the second start terminal START2, the clock terminal CLK, and the reset terminal RESET of each of the stages ST (1) to ST (n). One of the clocks is input. In this case, a clock whose phase is delayed from a clock input to the second start terminal START2 is input to the clock terminal CLK of each of the stages ST (1) to ST (n), and to the reset terminal RESET. A clock whose phase is delayed from a clock input to the clock terminal CLK is input. In addition, the second start terminal START2 of each of the stages ST (1) to ST (n) has a pulse synchronized with a start signal VST input to the first start terminal START1 or a carry signal of a previous stage. The clock with is input.

I-phase clocks are preferably implemented in four or more phases to ensure sufficient charging time during high-speed operation of 120 Hz or more. For example, the four-phase clocks CLK1, CLK2, CLK3, and CLK4 have a pulse width of approximately 1 horizontal period 1H, as shown in FIG. 3, and the phases may be sequentially delayed by 1 horizontal period 1H. . The four-phase clocks CLK1, CLK2, CLK3, and CLK4 input to the shift register swing between the gate high voltage VGH and the gate low voltage VGL, and a pulse is generated at the gate low voltage VGL.

Each of the stages ST (1) to ST (n) has one output terminal OUT. The outputs Out (1) to Oout (n) of each of the stages ST (1) to ST (n) are output to the scan lines of the display panel 10, and at the same time, the first start terminal of the rear stage It is input as a carry signal to START1). The outputs Out (1) -Out (n) of each of the stages ST (1) -ST (n) have a pulse width of approximately 1 horizontal period 1H, and the first stage ST (1). To the nth stage ST (n) are sequentially output. The outputs Out (1) to Out (n) of each of the stages ST (1) to ST (n) serve as a carry signal input to the first start terminal START1 of the rear stage. Since each of the stages ST (1) to ST (n) is cascaded, only the stages ST (1) to ST (are applied when the start voltage VST is supplied to the first stage ST (1). n)) will generate output sequentially.

Each of the stages ST (1) to ST (n) is supplied with a gate high voltage VGH and a gate low voltage VGL. The gate low voltage VGL and the gate high voltage VGH are set in consideration of the threshold voltages of the thin film transistors of the stages ST (1) to ST (n). For example, the gate low voltage VGL may be set to approximately −7V, and the gate low voltage VGH may be set to approximately 30V. A detailed description of the circuit of each of the stages ST (1) to ST (n) will be described later with reference to FIG. 2.

FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage of FIG. 1. Referring to FIG. 2, the k-th stage ST (k) may include a Q node discharge unit 21 that discharges the Q node Q in response to signals input through the first and second start terminals START, The Q node charging unit 22 charging the Q node Q according to the voltage of the QB node QB, and the QB node discharge unit discharging the QB node QB in response to a signal input through the reset terminal RESET ( 23), the QB node charging unit 24 which charges the QB node QB in response to a signal input through the first start terminal START1 and the gate insulating layer of the thin film transistor connected to the Q node Q is prevented. And an output unit 26 for outputting a signal input through the clock terminal CLK according to the voltages of the Q node voltage blocking unit 25 and the Q and QB nodes Q and QB.

The Q node discharge part 21 includes first and second transistors T1 and T2. The gate electrode of the first transistor T1 is connected to the first start terminal START1, the source electrode is connected to the drain electrode of the second transistor T2, and the drain electrode is connected to the gate electrode. That is, the first transistor T1 is diode connected. The gate electrode of the second transistor T2 is connected to the second start terminal START2, the source electrode is connected to the first node N1, and the drain electrode is connected to the source electrode of the first transistor T1. The first transistor T1 is turned on in response to a signal input through the first start terminal START1, and the second transistor T2 is turned on in response to a signal input through the second start terminal START2. On, the first node N1 and the Q node Q are discharged to the gate low voltage VGL. The first node N1 is a contact point between the Q node discharge portion 21 and the Q node voltage cutoff portion 25. In more detail, the first node N1 is a contact point between the source electrode of the second transistor T2 and the drain electrode of the eighth transistor T8.

The Q node charger 22 includes third and fourth transistors T3 and T4. The gate electrode of the third transistor T3 is connected to the QB node QB, the source electrode is connected to the drain electrode of the fourth transistor T4, and the drain electrode is connected to the second node N2. The gate electrode of the fourth transistor T4 is connected to the QB node QB, the source electrode is connected to the gate high voltage VGH terminal, and the drain electrode is connected to the source electrode of the third transistor T3. The third and fourth transistors T3 and T4 are turned on in response to the QB node QB of the gate low voltage VGL to turn the second node N2 and the Q node Q into the gate high voltage VGH. To charge. The second node N2 is a contact point between the Q node charging unit 22 and the Q node voltage blocking unit 25. In more detail, the second node N2 is a contact point between the drain electrode of the third transistor T3 and the source electrode of the ninth transistor T9.

The QB node discharge part 23 includes a fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the reset terminal RESET, the source electrode is connected to the QB node QB, and the drain electrode is connected to the gate low voltage VGL terminal. The fifth transistor T5 is turned on in response to a signal input through the reset terminal RESET to discharge the QB node QB to the gate low voltage VGL.

The QB node charger 24 includes sixth and seventh transistors T6 and T7. The gate electrode of the sixth transistor T6 is connected to the first start terminal START1, the source electrode is connected to the drain electrode of the seventh transistor T7, and the drain electrode is connected to the QB node QB. The gate electrode of the seventh transistor T7 is connected to the first start terminal START1, the source electrode is connected to the gate high voltage VGH terminal, and the drain electrode is connected to the source electrode of the sixth transistor T6. . The sixth and seventh transistors T6 and T7 are turned on in response to a signal input through the first start terminal START1 to charge the QB node QB to the gate high voltage VGH.

The Q node voltage blocking unit 25 includes eighth and ninth transistors T8 and T9. The gate electrode of the eighth transistor T8 is connected to the gate low voltage VGL terminal, the source electrode is connected to the Q node Q, and the drain electrode is connected to the first node N1. The gate electrode of the ninth transistor T9 is connected to the gate low voltage VGL terminal, the source electrode is connected to the second node N2, and the drain electrode is connected to the Q node Q. The eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL to connect the first node N1, the second node N2, and the Q node Q.

However, when the voltage of the Q node Q drops to the voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the gate electrodes of the eighth and ninth transistors T8 and T9 are provided. The voltage difference Vgs between the source and the source electrode (or the drain electrode) becomes higher than the threshold voltage. As a result, the eighth and ninth transistors T8 and T9 are turned off. That is, when the voltage of the Q node Q falls to the voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the eighth and ninth transistors T8 and T9 are turned-on. Since it is turned off, the connection between the Q node Q and the first node N1 and the connection between the Q node Q and the second node N2 are blocked. As a result, the potentials of the first node N1 and the second node N2 do not fall to the voltage level VGL 'lower than the gate low voltage VGL, and thus, the second and third transistors T2 and T3 do not fall. Destruction of the gate insulating film can be prevented.

If the eighth and ninth transistors T8 and T9 are not present, the gate high voltage VGH is supplied to the gate electrodes of the second and third transistors T2 and T3, and the gate low voltage VGL is supplied to the source electrode. Since the lower voltage level VGL 'is supplied, the voltage difference Vgs between the gate and source electrodes (or drain electrodes) of the second and third transistors T2 and T3 becomes greater than 50V. In this case, the gate insulating film insulating between the gate electrode and the source electrode (or the drain electrode) may be destroyed. However, since the eighth and ninth transistors T8 and T9 block the connection between the Q node Q and the second and third transistors T2 and T3, it is possible to prevent the gate insulating film from being destroyed. Meanwhile, since only the gate low voltage VGL is applied to the gate electrodes of the eighth and ninth transistors T8 and T9, the voltage between the gate and source electrodes (or drain electrodes) of the eighth and ninth transistors T8 and T9 is applied. The difference Vgs is maintained at approximately 25V. That is, the voltage difference Vgs between the gate and source electrodes (or drain electrodes) of the eighth and ninth transistors T8 and T9 is not large enough to destroy the gate insulating film.

The output unit 26 includes a pull-up transistor TU and a pull-down transistor TD. The gate electrode of the pull-up transistor TU is connected to the Q node Q, the source electrode is connected to the clock terminal CLK, and the drain electrode is connected to the output terminal OUT. The pull-up transistor TU is turned on according to the voltage of the Q node Q to output a clock input through the clock terminal CLK to the output terminal OUT. The gate electrode of the pull-down transistor TD is connected to the QB node QB, the source electrode is connected to the gate high voltage VGH terminal, and the drain electrode is connected to the output terminal OUT. The pull-down transistor TD is turned on according to the voltage of the QB node QB to output the gate high voltage VGH to the output terminal OUT.

The first capacitor C1 is connected to the Q node Q and the gate high voltage VGH terminal, and serves to keep the voltage of the Q node Q constant. The second capacitor C2 is connected to the QB node QB and the gate high voltage VGH terminal, and serves to keep the voltage of the QB node QB constant. The third capacitor C3 is connected to the Q node Q and the output terminal OUT, and serves to maintain a constant voltage of the signal output through the output terminal OUT. However, when the clock input through the clock terminal CLK is output, the third capacitor C3 further lowers the voltage of the Q node Q by bootstrapping.

The first through ninth transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, the pull-up transistor TU, and the pull-down transistor TD are thin film transistors. It can be formed into). The semiconductor layers of the first through ninth transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, the pull-up transistor TU, and the pull-down transistor TD are a-Si. , Poly-Si, or oxide semiconductor. The first through ninth transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, the pull-up transistor TU, and the pull-down transistor TD are P-type MOS- Although described with reference to the implementation of the FET, but not limited to this, it can also be implemented as an N-type MOS-FET.

3 is a waveform diagram illustrating input and output signals of a k-th stage of FIG. 2. Referring to FIG. 3, the output signal OUT (k-1) of the k-1st stage ST (k-1), which is the start voltage VST or the previous carry signal, input to the kth stage ST (k). The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are shown, and the k-th output signal OUT (k) output from the k-th stage ST (k) is shown. In addition, the voltage VQ of the Q node Q of the k-th stage ST (k) and the voltage VQB of the QB node QB are shown.

The start voltage VST may occur once at the beginning of one frame period. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are generated so that the phases are sequentially delayed by one horizontal period 1H. The output signal OUT (k-1) and the four-phase clocks CLK1, CLK2, CLK3, and CLK4 of the k-1 stage ST (k-1), which are the start voltage VST or the front carry signal, are gated. A pulse is generated at the low voltage VGL, and a pulse is generated at a pulse width of approximately one horizontal period 1H. One horizontal period 1H means a one-line scanning time in which data is written in pixels of one line of the display panel. The kth output signal OUT (k) is pulsed with the gate low voltage VGL, and the pulse is generated with a pulse width of approximately one horizontal period 1H.

Hereinafter, the operation of the k-th stage ST (k) during the t1 to t4 periods will be described in detail with reference to FIGS. 2 and 3. The first start terminal START1 of the kth stage ST (k) has an output signal OUT (k−) of the k-1st stage ST (k-1), which is a start voltage VST or a front carry signal. 1)) is input, the fourth clock CLK4 is input to the second start terminal START2, the first clock CLK is input to the clock terminal CLK, and the third clock is input to the reset terminal RESET. Explanation was made centering on input of (CLK3).

During the t1 period, the first start terminal START1 has an output signal OUT (k−) of the k-1 stage ST (k-1), which is a start voltage VST of the gate low voltage VGL or a front carry signal. 1)) is input, and the fourth clock CLK4 of the gate low voltage VGL is input to the second start terminal START2. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK, and the third clock CLK3 of the gate high voltage VGL is input to the reset terminal RESET.

The first transistor T1 responds to the output voltage OUT (k-1) of the k-1 stage ST (k-1), which is the start voltage VST of the gate low voltage VGL or the front carry signal. Is turned on. The second transistor T2 is turned on in response to the fourth clock CLK4 of the gate low voltage VGL. The sixth and seventh transistors T6 and T7 output the output signal OUT (k−) of the k-1 stage ST (k−1), which is a start voltage VST of the gate low voltage VGL or a front carry signal. It is turned on in response to 1)). In addition, the eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL. The third, fourth, and fifth transistors T3, T4, and T5 are turned off by the gate high voltage VGH.

Due to the turn-on of the first, second, eighth, and ninth transistors T1, T2, T8, and T9, the first node N1, the second node N2, and the Q node Q may be Discharged to the gate low voltage VGL. The pull-up transistor TU is turned on in response to the gate low voltage VGL of the Q node Q to output the first clock CLK1 of the gate high voltage VGH to the output terminal OUT. Due to the turn-on of the sixth and seventh transistors T6 and T7, the QB node QB is charged to the gate high voltage VGH. The pull-down transistor TD is turned off by the gate high voltage VGH of the QB node QB.

During the t2 period, the first start terminal START1 has an output signal OUT (k−) of the k-1 stage ST (k-1), which is a start voltage VST of the gate high voltage VGH or a front carry signal. 1)) is input, and the fourth clock CLK4 of the gate high voltage VGH is input to the second start terminal START2. The first clock CLK1 of the gate low voltage VGL is input to the clock terminal CLK. The third clock CLK3 of the gate high voltage VGH is input to the reset terminal RESET.

The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are turned off by the gate high voltage VGH. The eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL. Since the pull-up transistor TU remains turned on in response to the gate low voltage VGL of the Q node Q, the pull-up transistor TU outputs the first clock CLK1 of the gate low voltage VGL to the output terminal OUT. Will output At this time, the Q node Q is bootstrapping by the third capacitor C3 and falls to a voltage level VGL 'lower than the gate low voltage VGL. The QB node QB maintains the gate high voltage VGH by the second capacitor C2. The pull-down transistor TD is turned off by the gate high voltage VGH of the QB node QB.

On the other hand, since the Q node Q falls to a voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the gate and source electrodes of the eighth and ninth transistors T8 and T9 are reduced. (Or the voltage difference Vgs between the drain electrodes) becomes higher than the threshold voltage. Thus, the eighth and ninth transistors T8 and T9 are turned off. That is, when the voltage of the Q node Q falls to the voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the eighth and ninth transistors T8 and T9 are turned-on. Since it is turned off, the connection between the Q node Q and the first node N1 and the connection between the Q node Q and the second node N2 are blocked. As a result, the potentials of the first node N1 and the second node N2 do not fall to the voltage level VGL 'lower than the gate low voltage VGL, and thus, the second and third transistors T2 and T3 do not fall. Destruction of the gate insulating film can be prevented.

If the eighth and ninth transistors T8 and T9 are not present, the gate high voltage VGH is supplied to the gate electrodes of the second and third transistors T2 and T3, and the gate low voltage VGL is supplied to the source electrode. Since the lower voltage level VGL 'is supplied, the voltage difference Vgs between the gate and source electrodes (or drain electrodes) of the second and third transistors T2 and T3 becomes greater than 50V. In this case, the gate insulating film insulating between the gate electrode and the source electrode (or the drain electrode) may be destroyed. However, since the eighth and ninth transistors T8 and T9 block the connection between the Q node Q and the second and third transistors T2 and T3, it is possible to prevent the gate insulating film from being destroyed. Meanwhile, since only the gate low voltage VGL is applied to the gate electrodes of the eighth and ninth transistors T8 and T9, the voltage between the gate and source electrodes (or drain electrodes) of the eighth and ninth transistors T8 and T9 is applied. The difference Vgs is maintained at approximately 25V. That is, the voltage difference Vgs between the gate and source electrodes (or drain electrodes) of the eighth and ninth transistors T8 and T9 is not large enough to destroy the gate insulating film.

During the t3 period, the first start terminal START1 has an output signal OUT (k−) of the k-1 stage ST (k-1), which is the start voltage VST of the gate high voltage VGH or the front carry signal. 1)) is input, and the fourth clock CLK4 of the gate high voltage VGH is input to the second start terminal START2. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK. The third clock CLK3 of the gate high voltage VGH is input to the reset terminal RESET.

The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are turned off by the gate high voltage VGH. Since the pull-up transistor TU is turned on in response to the gate low voltage VGL of the Q node Q, the first clock CLK1 of the gate high voltage VGH is output to the output terminal OUT. Will output Since the gate node high voltage VGH is reflected by the third capacitor C3, the Q node Q rises to the gate low voltage VGL. The QB node QB maintains the gate high voltage VGH by the second capacitor C2. The pull-down transistor TD is turned off by the gate high voltage VGH of the QB node QB.

The eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL. This is because the voltage difference Vgs between the gate-source electrode (or the drain electrode) of the eighth and ninth transistors T8 and T9 becomes lower than the threshold voltage because the Q node Q rises to the gate low voltage VGL. .

During the t4 period, the first start terminal START1 has an output signal OUT (k−) of the k-1 stage ST (k-1), which is a start voltage VST of the gate high voltage VGH or a front carry signal. 1)) is input, and the fourth clock CLK4 of the gate high voltage VGH is input to the second start terminal START2. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK. The third clock CLK3 of the gate low voltage VGL is input to the reset terminal RESET.

Since the fifth transistor T5 is turned on in response to the third clock CLK3 of the gate low voltage VGL, the QB node QB is discharged to the gate low voltage VGL. Since the third and fourth transistors T3 and T4 are turned on in response to the gate low voltage VGL of the QB node QB, the Q node Q is charged to the gate high voltage VGH. As a result, the pull-up transistor TU is turned off by the gate high voltage VGH of the Q node Q. Since the pull-down transistor TD is turned on by the gate low voltage VGL of the QB node QB, the pull-down transistor TD outputs the gate high voltage VGH to the output terminal OUT.

4 is a block diagram schematically illustrating a configuration of a shift register of a gate driving circuit according to a second embodiment of the present invention. Referring to FIG. 4, the shift register according to the second embodiment of the present invention includes a plurality of stages (ST (1) to ST (n) where n is a natural number of stages) connected in cascade. In FIG. 1, for convenience of description, only the first to third stages ST (1) to ST (3) and the n-th and n-th stages ST (n-1) and ST (n) are illustrated.

In the following description, the "shear stage" refers to being located on top of the stage to be a reference. For example, on the basis of kth (1 <k <n, k, k are two or more natural numbers) stages ST (k), the front end stages are the first stage ST (1) to the k-1st stage ST. (k-1)). The "back stage" refers to being located at the lower part of the stage used as a reference. For example, based on the k-th stage ST (k), the rear stage indicates any one of the k + 1th stage ST (k + 1) to the nth stage ST (n).

The shift register according to the second embodiment of the present invention may be implemented in the forward mode or the reverse mode. In the forward mode, the stages ST (1) to ST (n) sequentially generate outputs from the first stage ST (1) to the nth stage ST (n). In the reverse mode, the stages ST (1) to ST (n) sequentially generate outputs from the nth stage ST (n) to the first stage ST (1).

The start voltage VST is applied to the start voltage line VSTL, and the start reverse voltage VST_R is applied to the start reverse voltage line VST_RL. In addition, a first clock CLK1 is applied to the first clock line CL1, a second clock CLK is applied to the second clock line CL2, and a third clock (CL3) is applied to the third clock line CL3. CLK3 is applied, and a fourth clock CLK4 is applied to the fourth clock line CL4.

Each of the stages ST (1) to ST (n) includes first and second start terminals START1 and START2, first and second start reverse terminals START_R1 and START_R2, a clock terminal CLK, and a reset terminal. (RESET) and an output terminal (OUT). The start voltage VST or the carry signal of the previous stage is input to the first start terminal START1 of each of the stages ST (1) to ST (n). For example, as shown in FIG. 4, the start voltage VST is applied to the first start terminal START1 of the first stage ST (1), and the second to nth stages ST (2) to ST ( n)) The carry signal of the preceding stage is input to each first start terminal START1. The start reverse voltage VST_R or the carry signal of the rear stage is input to the first start reverse terminal START_R1 of each of the stages ST (1) to ST (n). For example, as shown in FIG. 4, the start reverse voltage VST_R is applied to the first start reverse terminal START_R1 of the nth stage ST (n), and the second through nth stages ST (2) through n. The carry signal of the rear stage is input to each of the first start reverse terminals START_R1).

The phase delay is sequentially delayed to the second start terminal START2, the second start reverse terminal START_R2, the clock terminal CLK, and the reset terminal RESET of each of the stages ST (1) to ST (n). The clock of any one of the i-phase clocks is input. In the forward mode, a clock whose phase is delayed from a clock input to the second start terminal START2 is input to the clock terminal CLK of each of the stages ST (1) to ST (n), and the reset terminal RESET. A clock whose phase is delayed from a clock input to the clock terminal CLK is input to the clock. In addition, the second start terminal START2 of each of the stages ST (1) to ST (n) has a pulse synchronized with a start signal VST input to the first start terminal START1 or a carry signal of a previous stage. The clock with is input. In the reverse mode, a clock whose phase is delayed from a clock input to the second start reverse terminal START_R2 is input to the clock terminal CLK of each of the stages ST (1) to ST (n), and the reset terminal RESET. ) Is input to a clock whose phase is delayed from the clock input to the clock terminal CLK. In addition, the second start reverse terminal START_R2 of each of the stages ST (1) to ST (n) has a carry signal of the start reverse voltage VSTR input to the first start reverse terminal START_R1 or the rear stage. A clock with a synchronized pulse is input.

I-phase clocks are preferably implemented in four or more phases to ensure sufficient charging time during high-speed operation of 120 Hz or more. For example, the four-phase clocks CLK1, CLK2, CLK3, and CLK4 have a pulse width of approximately 1 horizontal period 1H, as shown in FIG. 3, and the phases may be sequentially delayed by 1 horizontal period 1H. . The four-phase clocks CLK1, CLK2, CLK3, and CLK4 input to the shift register swing between the gate high voltage VGH and the gate low voltage VGL, and a pulse is generated at the gate low voltage VGL.

Each of the stages ST (1) to ST (n) has one output terminal OUT. In the forward mode, the outputs (Out (1) to Oout (n) of each of the stages ST (1) to ST (n) are output to the scan lines of the display panel 10, and at the same time, Input to one start terminal START1 as a carry signal. The outputs Out (1) -Out (n) of each of the stages ST (1) -ST (n) have a pulse width of approximately 1 horizontal period 1H, and the first stage ST (1). To the nth stage ST (n) are sequentially output. The outputs Out (1) to Out (n) of each of the stages ST (1) to ST (n) serve as a carry signal input to the first start terminal START1 of the rear stage. Since each of the stages ST (1) to ST (n) is cascaded, only the stages ST (1) to ST (are applied when the start voltage VST is supplied to the first stage ST (1). n)) will generate output sequentially.

In the reverse mode, the outputs (Out (1) to Oout (n) of each of the stages ST (1) to ST (n) are output to the scan lines of the display panel 10, and at the same time, It is input as a carry signal to one start reverse terminal START_R1. The outputs Out (1) -Out (n) of each of the stages ST (1) -ST (n) have a pulse width of approximately 1 horizontal period 1H, and the nth stage ST (n) Are sequentially output from the first stage ST (1). The outputs Out (1) to Out (n) of each of the stages ST (1) to ST (n) serve as a carry signal input to the first start reverse terminal START_R1 of the preceding stage. Since each of the stages ST (1) to ST (n) is cascaded, only the stages ST (1) to ST are supplied when the start reverse voltage VSTR is supplied to the nth stage ST (n). (n)) generates output sequentially.

Each of the stages ST (1) to ST (n) is supplied with a gate high voltage VGH and a gate low voltage VGL. The gate low voltage VGL and the gate high voltage VGH are set in consideration of the threshold voltages of the thin film transistors of the stages ST (1) to ST (n). For example, the gate low voltage VGL may be set to approximately −7V, and the gate low voltage VGH may be set to approximately 30V. A detailed description of the circuit of each of the stages ST (1) to ST (n) will be described later with reference to FIGS. 5 and 7.

FIG. 5 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage of FIG. 4. Referring to FIG. 5, the k-th stage ST (k) may include a forward Q node discharge unit configured to discharge the Q node Q in response to signals input through the first and second start terminals START1 and START2. 21), the Q node charging unit 22 that charges the Q node Q according to the voltage of the QB node QB, and the QB node that discharges the QB node QB in response to a signal input through the reset terminal RESET. Q node voltage for preventing the gate insulating film breakdown of the thin film transistor connected to the QB node charging section 24 and the Q node Q, which charges the QB node QB according to the discharge section 23, the voltage of the Q node Q. An output unit 26 for outputting a signal input through the clock terminal CLK according to the voltages of the blocking unit 25, the Q and QB nodes Q and QB, and the first and second start reverse terminals START_R1 and START_R2. And a reverse Q node discharge unit 27 for discharging the Q node Q in response to a signal input through the signal C1).

The Q node charging unit 22, the QB node discharge unit 23, the QB node charging unit 24, and the output unit 26 shown in FIG. 5 are substantially the same as those described with reference to FIG. The forward Q node discharge unit 21 shown in FIG. 5 is substantially the same as described in the Q node discharge unit 21 of FIG. 2. However, the QB node charger 24 shown in FIG. 5 charges the QB node QB according to the voltage of the Q node Q, whereas the QB node charger 24 shown in FIG. 2 has a first start terminal. The QB node QB is charged in response to the signal input through START1. That is, the gate electrodes of the sixth and seventh transistors T6 and T7 illustrated in FIG. 5 are connected to the third node N3 instead of the first start terminal START. The third node N3 is a contact point between the QB node charging section 24 and the Q node voltage blocking section 25. In more detail, the third node N3 is a contact point between the gate electrodes of the sixth and seventh transistors T6 and T7 and the source electrode of the tenth transistor T10.

The Q node voltage blocking unit 25 includes eighth to tenth transistors T8, T9, and T10. The eighth and ninth transistors T8 and T9 are substantially the same as those described with reference to FIG. 2. The gate electrode of the tenth transistor T10 is connected to the gate low voltage VGL terminal, the source electrode is connected to the third node N3, and the drain electrode is connected to the Q node Q. The tenth transistor T10 is turned on in response to the gate low voltage VGL to connect the third node N3 and the Q node Q.

However, when the voltage of the Q node Q falls to the voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the gate electrode and the source electrode (or The voltage difference Vgs between the drain electrodes is higher than the threshold voltage. As a result, the eighth and ninth transistors T8 and T9 are turned off. That is, when the voltage of the Q node Q drops to the voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the tenth transistor T10 is turned off, so that the Q node The connection between Q and the third node N3 is blocked. For this reason, destruction of the gate insulating film of the 6th and 7th transistors T6 and T7 connected with the Q node Q can be prevented.

If the tenth transistor T10 is not present, a gate high voltage VGH is supplied to the gate electrodes of the sixth and seventh transistors T6 and T7, and a voltage level lower than the gate low voltage VGL is supplied to the source electrode. Since VGL 'is supplied, the voltage difference Vgs between the gate and source electrodes (or drain electrodes) of the sixth and seventh transistors T6 and T7 becomes greater than 50V. In this case, the gate insulating film insulating between the gate electrode and the source electrode (or the drain electrode) may be destroyed. However, since the tenth transistor T10 blocks the connection between the Q node Q and the sixth and seventh transistors T6 and T7, it is possible to prevent the gate insulating layer from being destroyed. Meanwhile, since only the gate low voltage VGL is applied to the gate electrode of the tenth transistor T10, the voltage difference Vgs between the gate and the source electrode (or the drain electrode) of the tenth transistor T10 is maintained at about 25V. . That is, the voltage difference Vgs between the gate and the source electrode (or the drain electrode) of the tenth transistor T10 is not large enough to destroy the gate insulating film.

The reverse Q node discharge part 27 includes eleventh and twelfth transistors T11 and T12. The gate electrode of the eleventh transistor T11 is connected to the first start reverse terminal START_R1, the source electrode is connected to the drain electrode of the twelfth transistor T12, and the drain electrode is connected to the gate electrode. That is, the eleventh transistor T11 is diode connected. The gate electrode of the twelfth transistor T12 is connected to the second start reverse terminal START_R2, the source electrode is connected to the first node N1, and the drain electrode is connected to the source electrode of the eleventh transistor T11. . The eleventh transistor T11 is turned on in response to a signal input through the first start reverse terminal START_R1, and the twelfth transistor T12 is in response to a signal input through the second start reverse terminal START_R2. The first node N1 and the Q node Q are discharged to the gate low voltage VGL.

The first through twelfth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and T12, the pull-up transistor TU, and the pull-down transistor TD It may be formed of a thin film transistor. The first through twelfth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, pull-up transistors TU, and pull-down transistors TD The semiconductor layer may be formed of any one of a-Si, Poly-Si, and oxide semiconductor. The first through twelfth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and T12, pull-up transistors TU, and pull-down transistors TD. ) Is described as being implemented as a P-type MOS-FET, but is not limited thereto, and may also be implemented as an N-type MOS-FET.

6A and 6B are waveform diagrams showing input and output signals of the k-th stage of FIG. 5 in a forward or reverse mode. 6A and 6B, the output signal OUT (of the start voltage VST input to the kth stage ST (k) or the k-1th stage ST (k-1), which is a front carry signal, may be used. k-1)), the output signal OUT (k +) of the k + 1th stage ST (k + 1), which is the start reverse voltage VST_R inputted to the kth stage ST (k), or a subsequent carry signal. 1)), four-phase clocks CLK1, CLK2, CLK3, CLK4 are shown, and the output signal OUT (k) output from the k-th stage ST (k) is shown. In addition, the voltage VQ of the Q node Q of the k-th stage ST (k) and the voltage VQB of the QB node QB are shown.

In the forward mode as shown in FIG. 6A, the start voltage VST may occur once at the start of one frame period. In the forward mode, the start reverse voltage VST_R is generated as the gate high voltage VGH. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are generated such that the phases are sequentially delayed in the forward direction by one horizontal period 1H. The output signal OUT (k-1) and the four-phase clocks CLK1, CLK2, CLK3, and CLK4 of the k-1 stage ST (k-1), which are the start voltage VST or the front carry signal, are gated. A pulse is generated at the low voltage VGL, and a pulse is generated at a pulse width of approximately one horizontal period 1H. One horizontal period 1H means a one-line scanning time in which data is written in pixels of one line of the display panel. The kth output signal OUT (k) is pulsed with the gate low voltage VGL, and the pulse is generated with a pulse width of approximately one horizontal period 1H. In the forward mode, the k th output signal to the k + 3 th output signals OUT (k) to OUT (k + 3) are sequentially generated in the forward direction.

Hereinafter, the operation of the k-th stage ST (k) during the t1 to t4 periods in the forward mode will be described in detail with reference to FIGS. 5 and 6A. The first start terminal START1 of the kth stage ST (k) has an output signal OUT (k−) of the k-1st stage ST (k-1), which is a start voltage VST or a front carry signal. 1)) is input, the fourth clock CLK4 is input to the second start terminal START2, and the first reverse reverse terminal START_R1 is the start reverse voltage VST_R or the k + 1 of the subsequent carry signal. The output signal OUT (k + 1) of the stage ST (k + 1) is input, the second clock CLK2 is input to the second start reverse terminal START_R2, and the clock terminal CLK is input to the output signal OUT (k + 1). The first clock CLK is input, and the third clock CLK3 is input to the reset terminal RESET.

Meanwhile, in the forward mode, when the k-th stage ST (k) is substantially the same as the operation of the k-th stage ST (k) described with reference to FIGS. 2 and 3, the description thereof is for convenience of description. Omitted for. That is, the sixth, seventh, tenth, eleventh, and twelfth transistors T6, T7, T10, T11, and T12 will be described below.

During the t1 period, the first start reverse terminal START_R1 has an output signal OUT (of the k-1 stage ST (k-1), which is a start reverse voltage VST_R of the gate high voltage VGH or a subsequent carry signal. k-1)) is input, and the second clock CLK2 of the gate high voltage VGH is input to the second start reverse terminal START_R2.

The tenth transistor T10 is turned on in response to the gate low voltage VGL. The eleventh and twelfth transistors T11 and T12 are turned off by the gate high voltage VGH. Due to the turn-on of the tenth transistor T10, the third node N3 is discharged to the gate low voltage VGL. The sixth and seventh transistors T6 and T7 are turned on in response to the gate low voltage VGL of the third node N3 to charge the QB node QB to the gate high voltage VGH.

In addition, the description of the period t1 of FIG. 5 is substantially the same as that described during the period t1 of FIG. 2.

During the t2 period, the first start reverse terminal START_R1 has an output signal OUT (of the k-1 stage ST (k-1), which is a start reverse voltage VST_R of the gate high voltage VGH or a rear carry signal. k-1)) is input, and the second clock CLK2 of the gate high voltage VGH is input to the second start reverse terminal START_R2.

The eleventh and twelfth transistors T11 and T12 are turned off by the gate high voltage VGH. On the other hand, since the Q node Q drops to a voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the gate electrode and the source electrode (or the drain electrode) of the tenth transistor T10. The voltage difference Vgs between them becomes higher than the threshold voltage. Thus, the tenth transistor T10 is turned off. That is, when the voltage of the Q node Q drops to the voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the tenth transistor T10 is turned off, so that the Q node The connection between Q and the third node N3 is blocked. As a result, since the potential of the third node N3 does not fall to the voltage level VGL 'lower than the gate low voltage VGL, the gate insulating film of the sixth and seventh transistors T6 and T7 can be prevented from being destroyed. have.

If there is no tenth transistor T10, the gate high voltage VGH is supplied to the gate electrodes of the sixth and seventh transistors T6 and T7, and the voltage level VGL is lower than the gate low voltage VGL to the source electrode. Since ') is supplied, the voltage difference Vgs between the gate and source electrodes (or drain electrodes) of the sixth and seventh transistors T6 and T7 becomes greater than 50V. In this case, the gate insulating film insulating between the gate electrode and the source electrode (or the drain electrode) may be destroyed. However, since the tenth transistor T10 blocks the connection between the Q node Q and the sixth and seventh transistors T6 and T7, it is possible to prevent the gate insulating layer from being destroyed. Meanwhile, since only the gate low voltage VGL is applied to the gate electrode of the tenth transistor T10, the voltage difference Vgs between the gate and the source electrode (or the drain electrode) of the tenth transistor T10 is maintained at about 25V. . That is, the voltage difference Vgs between the gate and the source electrode (or the drain electrode) of the tenth transistor T10 is not large enough to destroy the gate insulating film.

In addition, the description of the period t2 of FIG. 5 is substantially the same as that of the period t2 of FIG. 2.

During the t3 period, the first start reverse terminal START_R1 has an output signal OUT (of the k-1 stage ST (k-1) which is a start reverse voltage VST_R of the gate high voltage VGH or a subsequent carry signal). k-1)) is input, and the second clock CLK2 of the gate low voltage VGL is input to the second start reverse terminal START_R2.

The eleventh transistor T12 is turned off by the gate high voltage VGH, but the twelfth transistor T12 is turned on by the second clock CLK2 of the gate high voltage VGH. The turn-on of the twelfth transistor T12 does not affect the driving of the k th stage ST (k). The tenth transistor T10 is turned on in response to the gate low voltage VGL. This is because the voltage difference Vgs between the gate-source electrode (or the drain electrode) of the eighth and ninth transistors T8 and T9 becomes lower than the threshold voltage because the Q node Q rises to the gate low voltage VGL. .

In addition, the description of the period t3 of FIG. 5 is substantially the same as that of the period t3 of FIG. 2.

During the t4 period, the first start reverse terminal START_R1 has an output signal OUT of the k-1 stage ST (k-1) which is a start reverse voltage VST_R of the gate high voltage VGH or a rear carry signal. k-1)) is input, and the second clock CLK2 of the gate high voltage VGH is input to the second start reverse terminal START_R2.

The eleventh and twelfth transistors T11 and T12 are turned off by the gate high voltage VGH. The tenth transistor T10 is turned on in response to the gate low voltage VGL.

In addition, the description of the period t4 of FIG. 5 is substantially the same as that of the period t4 of FIG. 2.

In reverse mode as shown in FIG. 6B, the start reverse voltage VST_R may occur once at the start of one frame period. In the reverse mode, the start voltage VST is generated with the gate high voltage VGH. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are generated such that the phases are sequentially delayed in the reverse direction by one horizontal period (1H). The output signal OUT (k-1) and the four-phase clocks CLK1, CLK2, CLK3, and CLK4 of the k-1 stage ST (k-1), which are the start voltage VST or the front carry signal, are gated. A pulse is generated at the low voltage VGL, and a pulse is generated at a pulse width of approximately one horizontal period 1H. One horizontal period 1H means a one-line scanning time in which data is written in pixels of one line of the display panel. The kth output signal OUT (k) is pulsed with the gate low voltage VGL, and the pulse is generated with a pulse width of approximately one horizontal period 1H. In the reverse mode, the k th output signal to the k + 3 th output signals OUT (k) to OUT (k + 3) are sequentially generated in the reverse direction.

Hereinafter, the operation of the k-th stage ST (k) during the t1 to t4 periods in the reverse mode will be described in detail with reference to FIGS. 5 and 6B. The first start terminal START1 of the kth stage ST (k) has an output signal OUT (k−) of the k-1st stage ST (k-1), which is a start voltage VST or a front carry signal. 1)) is input, the third clock CLK3 is input to the second start terminal START2, and the first reverse reverse terminal START_R1 is the start reverse voltage VST_R or the k + 1 of the subsequent carry signal. The output signal OUT (k + 1) of the stage ST (k + 1) is input, the first clock CLK1 is input to the second start reverse terminal START_R2, and the clock terminal CLK is input to the output signal OUT (k + 1). The description has been made mainly on the fact that four clocks CLK4 are input and a second clock CLK2 is input to the reset terminal RESET.

Meanwhile, in the reverse mode, the operation of the kth stage ST (k) is performed by the first start terminal START1, the second start terminal START2, the first start reverse terminal START_R1, and the second start reverse terminal START_R2. The signals input to the clock terminal CLK and the reset terminal RESET are different, and are substantially the same as the operation of the k-th stage ST (k) in the forward mode described with reference to FIGS. 5 and 6A. Therefore, a detailed description of the operation of the k-th stage ST (k) in the reverse mode will be omitted. However, the first and second transistors T1 and T2 connected to the first and second start terminals START1 and START2 in the reverse mode are connected to the first and second start reverse terminals START_R1 and START_R2 in the forward mode. It operates substantially the same as the 11th and 12th transistors T11 and T12. In addition, the eleventh and twelfth transistors T11 and T12 connected to the first and second start reverse terminals START_R1 and START_R2 in the reverse mode are connected to the first and second start terminals START1 and START2 in the forward mode. It operates substantially the same as the first and second transistors T1 and T2.

FIG. 7 is a circuit diagram illustrating another example of a circuit configuration of a k-th stage of FIG. 4. Referring to FIG. 7, the k th stage ST (k) may include a forward Q node discharge unit configured to discharge the Q node Q in response to signals input through the first and second start terminals START1 and START2. 21), the Q node charging unit 22 that charges the Q node Q according to the voltage of the QB node QB, and the QB node that discharges the QB node QB in response to a signal input through the reset terminal RESET. The QB node is charged in response to a signal input through the discharge unit 23, the first start terminal START1, and the first start reverse terminal START_R1, and the QB node QB is charged according to the voltage of the Q node Q. The clock terminal according to the voltage of the QB node charging section 24 to charge, the Q node voltage blocking section 25 to prevent the gate insulating film destruction of the thin film transistor connected to the Q node Q, and the Q and QB nodes Q and QB. In response to a signal input through an output unit 26 for outputting a signal input through CLK, and first and second start reverse terminals START_R1 and START_R2. The reverse Q node discharge part 27 which discharges a Q node Q is provided.

The Q node charging unit 22, the QB node discharge unit 23, and the output unit 26 shown in FIG. 7 are substantially the same as those described with reference to FIG. The forward Q node discharge section 21, the Q node voltage blocking section 25, and the reverse Q node discharge section 27 shown in FIG. 7 are substantially the same as described with reference to FIG. However, the drain electrode of the first transistor T1 of the forward Q node discharge part 21 shown in FIG. 7 is connected to the gate low voltage VGL terminal, and the eleventh transistor of the reverse Q node discharge part 21 is applied. The drain electrode of T11 is connected to the gate low voltage VGL terminal.

The sixth and seventh transistors T6 and T7 of the QB node charger 24 illustrated in FIG. 7 are substantially the same as those described with reference to FIG. 5. The QB node charger 24 illustrated in FIG. 7 further includes thirteenth and fourteenth transistors T13 and T14. The gate electrode of the thirteenth transistor T13 is connected to the first start terminal START1, the source electrode is connected to the gate high voltage VGH terminal, and the drain electrode is connected to the QB node QB. The gate electrode of the fourteenth transistor T14 is connected to the first start reverse terminal START_R1, the source electrode is connected to the gate high voltage VGH terminal, and the drain electrode is connected to the QB node QB. The thirteenth transistor T13 is turned on in response to a signal input through the first start terminal START1 to charge the QB node QB to the gate high voltage VGH. The fourteenth transistor T14 is turned on in response to a signal input through the first start reverse terminal START_R1 to charge the QB node QB to the gate high voltage VGH.

The first capacitor C1 illustrated in FIG. 7 is connected to the Q node Q and the output terminal OUT, and serves to maintain a constant voltage of a signal output through the output terminal OUT. However, when the clock input through the clock terminal CLK is output, the third capacitor C3 further lowers the voltage of the Q node Q by bootstrapping. In addition, FIG. 7 includes a capacitor connected to the Q node Q and the gate high voltage VGH terminal to maintain a constant voltage of the Q node Q, and a QB node QB and the gate high voltage VGH terminal. The capacitors that are connected to keep the voltage of the QB node QB constant are deleted. According to the present invention, since the thirteenth and fourteenth transistors T13 and T14 are added to the QB node charging unit 24 to ensure the control of the QB node QB, the capacitors are omitted.

First through Fourteenth transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14), pull-up transistors (TU), pull-down transistors The TD may be formed of a thin film transistor. First through Fourteenth transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14), pull-up transistors (TU), pull-down transistors The semiconductor layer of (TD) may be formed of any one of a-Si, Poly-Si, and oxide semiconductor. The first through fourteenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, and T14, pull-up transistors (TU), and pull- Although the down transistor TD has been described based on the P type MOS-FET, the present invention is not limited thereto, and the down transistor TD may also be implemented as an N type MOS-FET.

Meanwhile, the input and output signals of the k-th stage ST (k) of FIG. 7 are substantially the same as the waveform diagrams shown in FIGS. 6A and 6B. First, an operation of the k-th stage ST (k) during the t1 to t4 periods in the forward mode will be described in detail with reference to FIGS. 6A and 7. Meanwhile, in the forward mode, when the k-th stage ST (k) is substantially the same as the operation of the k-th stage ST (k) described with reference to FIGS. 5 and 6A, the description thereof is for convenience of description. Omitted for. That is, the following description will focus on the thirteenth and fourteenth transistors T13 and T14.

During the t1 period, the thirteenth transistor T13 carries the carry signal OUT (k-1) of the k-1 stage ST (k-1) which is the start voltage VST of the gate low voltage VGL or the front carry signal. It is turned on in response to)) to charge the QB node QB to the gate high voltage VGH. The fourteenth transistor T14 is connected to the start reverse voltage VST_R of the gate high voltage VGH or the carry signal OUT (k + 1) of the k + 1th stage ST (k + 1) which is a subsequent carry signal. By turning it off.

In addition, the description of the period t1 of FIG. 7 is substantially the same as that described during the period t1 of FIG. 5.

During the t2 to t4 periods, the thirteenth transistor T13 carries the start signal VST of the gate high voltage VGH or the carry signal OUT (k) of the k-1 stage ST (k-1), which is a front carry signal. -14) is turned off. The fourteenth transistor T14 is the start reverse voltage VST_R of the gate high voltage VGH or the k + 1th stage ST (k + 1) which is a rear carry signal. It is turned off by the carry signal OUT (k + 1).

In addition, the descriptions for the period t2 to t4 of FIG. 7 are substantially the same as those described for the period t2 to t4 of FIG. 5.

Hereinafter, an operation of the k-th stage ST (k) during the t1 to t4 periods in the reverse mode will be described in detail with reference to FIGS. 7 and 6B. Meanwhile, in the reverse mode, the operation of the kth stage ST (k) is performed by the first start terminal START1, the second start terminal START2, the first start reverse terminal START_R1, and the second start reverse terminal START_R2. The signals input to the clock terminal CLK and the reset terminal RESET are different, and are substantially the same as the operation of the k-th stage ST (k) in the forward mode described with reference to FIGS. 7 and 6A. Therefore, a detailed description of the operation of the k-th stage ST (k) in the reverse mode will be omitted. However, the first and second transistors T1 and T2 connected to the first and second start terminals START1 and START2 in the reverse mode are connected to the first and second start reverse terminals START_R1 and START_R2 in the forward mode. It operates substantially the same as the 11th and 12th transistors T11 and T12. In addition, the eleventh and twelfth transistors T11 and T12 connected to the first and second start reverse terminals START_R1 and START_R2 in the reverse mode are connected to the first and second start terminals START1 and START2 in the forward mode. It operates substantially the same as the first and second transistors T1 and T2.

8 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 8, the display device according to the exemplary embodiment includes a display panel 10, a data driving circuit, a gate driving circuit, a timing controller 11, and the like.

The display panel 10 is formed such that the data lines DL and the scan lines SL cross each other. The display panel 10 includes a pixel array PIXEL ARRAY in which pixels are arranged in a matrix in cell regions defined by data lines DL and scan lines SL.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive the digital video data RGB from the timing controller 11. [ The source driver ICs 12 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, To the data lines (DL) of the display panel 10 so as to be synchronized with each other. The source drive ICs 12 may be connected to the data lines DL of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit includes a level shifter 13 and a shift register 14. The level shifter 13 converts a TTL (Transistor-Transistor-Logic) logic level voltage of the clocks CLKs input from the timing controller 11 into the gate high voltage VGH and the gate low voltage VGL as shown in FIG. 9. Level shift. The level shifted clocks CLKs are input to the shift register 14. The shift register 14 is connected to the scan lines GL of the display panel 10 and sequentially outputs the scan pulse SP to the scan lines SL. The shift register 14 sequentially outputs the scan pulse SP in the forward direction in the forward mode, and sequentially outputs the scan pulse SP in the reverse direction in the reverse mode. The shift register 14 is directly formed on the lower substrate of the display panel 10 by a gate drive-IC in panel (GIP) method. In the GIP method, the level shifter 13 is mounted on a printed circuit board 15.

The timing controller 11 receives digital video data RGB from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits digital video data (RGB) input from the host system to the source drive ICs 12.

The timing controller 11 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock, and the like from a host system through an LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage VST and clocks CLKs sequentially generated in three phases. The start voltage VST is input to the shift register 14 to control the shift start timing of the shift register 14. The clocks CLKs are input to the level shifter 13, level shifted, and then input to the shift register 14, and are used as clock signals for shifting the start voltage VST.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 12. [ The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the present invention further forms voltage blocking transistors for preventing the gate insulating layer destruction of the thin film transistors connected to the Q node controlling the output of the shift register, and applying a gate low voltage to the gate electrode of the voltage blocking transistors. Supply. As a result, the present invention can prevent destruction of the gate insulating film of the thin film transistors connected to the Q node. For this reason, the present invention can prevent abnormal output of the shift register, thereby preventing the horizontal line lighting failure of the display panel.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board

Claims (20)

A start voltage and a plurality of stages that sequentially receive outputs of i (i is a natural number of 4 or more) phases of which phase is sequentially delayed, and sequentially generate outputs,
K of the stages (k is a natural number satisfying 1≤k≤n, n is the number of stages)
A Q node discharge unit configured to discharge the Q node to a gate low voltage in response to a signal input through the first and second start terminals;
A QB node charger configured to charge a QB node to a gate high voltage higher than the gate low voltage in response to a signal input through the first start terminal or in response to a gate low voltage of the Q node;
A Q node charger configured to charge the Q node to the gate high voltage in response to the gate low voltage of the QB node;
A QB node discharge unit configured to discharge the QB node to the gate low voltage in response to a signal input through a reset terminal;
The Q node discharger, the Q node charger, when connected between the Q node discharger, the Q node charger, and the Q node, and when the Q node bootstrap and drops to a voltage level lower than the gate low voltage And a Q node voltage blocking unit to block a connection between the Q nodes. And
And an output unit configured to output a pulse synchronized with a clock input through a clock terminal according to the voltages of the Q node and the QB node. The method of claim 1,
The Q node voltage blocking unit,
A first node connected between the Q node discharge unit and the Q node and turned on in response to the gate low voltage to connect the first node and the Q node between the Q node discharge unit and the Q node voltage blocking unit; 8 transistors; And
A ninth transistor connected between the Q node charging unit and the Q node and turned on in response to the gate low voltage to connect a second node between the Q node charging unit and the Q node voltage blocking unit and the Q node; And a shift register. The method of claim 2,
A gate electrode of the eighth transistor is connected to a gate low voltage terminal, a source electrode is connected to the Q node, a drain electrode is connected to the first node,
And a gate electrode of the ninth transistor is connected to the gate low voltage terminal, a source electrode is connected to the second node, and a drain electrode is connected to the Q node. The method of claim 2,
The Q node voltage blocking unit,
A tenth transistor connected between the QB node charging unit and the Q node and turned on in response to the gate low voltage to connect a third node between the QB node charging unit and the Q node voltage blocking unit and the Q node; The shift register further comprises. The method of claim 4, wherein
And a gate electrode of the tenth transistor is connected to a gate low voltage terminal, a source electrode is connected to the third node, and a drain electrode is connected to the Q node. The method of claim 1,
A start voltage or a carry signal of a previous stage is input to the first start terminal, and one of the i-phase clocks is input to each of the second start terminal, the clock terminal, and the reset terminal;
The clock inputted to the clock terminal is a clock whose phase is delayed from the clock inputted to the second start terminal, and the clock input to the reset terminal is a clock whose phase is delayed from the clock inputted to the clock terminal. register. The method of claim 1,
The Q node discharge unit,
And the Q node is discharged to the gate low voltage in response to a signal input through the first and second start reverse terminals. The method of claim 7, wherein
A start voltage or a carry signal of a previous stage is input to the first start terminal, and a start reverse voltage or a carry signal of a rear stage is input to the first start reverse terminal, and the second start terminal and the second start reverse terminal are input. And one of the i-phase clocks is input to each of the clock terminal and the reset terminal. The method of claim 8,
In the forward mode in which the output of the output is sequentially generated in the forward direction,
The clock inputted to the clock terminal is a clock whose phase is delayed from the clock inputted to the second start terminal, and the clock input to the reset terminal is a clock whose phase is delayed from the clock inputted to the clock terminal. register. The method of claim 8,
In the reverse mode in which the output of the output is sequentially generated in the reverse direction,
The clock input to the clock terminal is a clock whose phase is delayed from the clock input to the second start reverse terminal, and the clock input to the reset terminal is a clock whose phase is delayed than the clock input to the clock terminal. Shift register. The method of claim 7, wherein
The Q node discharge unit,
And first and second transistors turned on in response to signals input through the first and second start terminals to discharge the Q node to the gate low voltage. The method of claim 11,
A gate electrode of the first transistor is connected to the first start terminal, a source electrode is connected to a drain electrode of the second transistor, a drain electrode is connected to the first start terminal or a gate low voltage terminal,
A gate electrode of the second transistor is connected to the second start terminal, a source electrode is connected to a first node between the Q node discharge portion and the Q node voltage blocking portion, and a drain electrode is a source of the first transistor A shift register connected to the electrode. The method of claim 11,
The Q node discharge unit,
And eleventh and twelfth transistors that are turned on in response to signals input through the first and second start reverse terminals to discharge the Q node to the gate low voltage. The method of claim 13,
A gate electrode of the eleventh transistor is connected to the first start reverse terminal, a source electrode is connected to a drain electrode of the twelfth transistor, a drain electrode is connected to the first start reverse terminal or a gate low voltage terminal,
A gate electrode of the twelfth transistor is connected to the second start reverse terminal, a source electrode is connected to a first node between the Q node discharge portion and the Q node voltage blocking portion, and a drain electrode of the eleventh transistor A shift register connected to the source electrode. The method of claim 7, wherein
The QB node charging unit,
And sixth and seventh transistors which are turned on in response to a signal input through the first start terminal or a gate low voltage of the Q node to charge the QB node to the gate high voltage. register. The method of claim 15,
The gate electrode of the sixth transistor is connected to the first start terminal or the third node between the Q node voltage blocking part and the QB node charging part, the source electrode is connected to the drain electrode of the seventh transistor, and the drain electrode is Connected to the QB node,
The gate electrode of the seventh transistor is connected to the third node between the first start terminal or the Q node voltage blocking part and the QB node charging part, the source electrode is connected to the gate high voltage terminal, and the drain electrode is connected to the sixth node. A shift register connected to the source electrode of the transistor. The method of claim 15,
The QB node charging unit,
A thirteenth transistor that is turned on in response to a signal input through the first start terminal to charge the QB node to a gate high voltage; And
And a fourteenth transistor that is turned on in response to a signal input through the first start reverse terminal to charge the QB node to a gate high voltage. The method of claim 17,
A gate electrode of the thirteenth transistor is connected to the first start terminal, a source electrode is connected to a gate high voltage terminal, a drain electrode is connected to the QB node,
And the gate electrode of the fourteenth transistor is connected to the first start reverse terminal, the source electrode is connected to a gate high voltage terminal, and the drain electrode is connected to the QB node. The method of claim 1,
And the output of the output unit is supplied to the scan line of the display panel and functions as a carry signal of the front or rear stage stage. A display panel including data lines and scan lines crossing the data lines;
A data driving circuit for supplying a data voltage to the data lines; And
A gate driving circuit including a shift register configured to sequentially supply scan pulses to the scan lines in synchronization with the data voltage,
The shift register,
A start voltage and a plurality of stages that sequentially receive outputs of i (i is a natural number of 4 or more) phases of which phase is sequentially delayed, and sequentially generate outputs,
K of the stages (k is a natural number satisfying 1≤k≤n, n is the number of stages)
A Q node discharge unit configured to discharge the Q node to a gate low voltage in response to a signal input through the first and second start terminals;
A QB node charger configured to charge a QB node to a gate high voltage higher than the gate low voltage in response to a signal input through the first start terminal or in response to a gate low voltage of the Q node;
A Q node charger configured to charge the Q node to the gate high voltage in response to the gate low voltage of the QB node;
A QB node discharge unit configured to discharge the QB node to the gate low voltage in response to a signal input through a reset terminal;
The Q node discharger, the Q node charger, when connected between the Q node discharger, the Q node charger, and the Q node, and when the Q node bootstrap and drops to a voltage level lower than the gate low voltage And a Q node voltage blocking unit to block a connection between the Q nodes. And
And an output unit configured to output a pulse synchronized with a clock input through a clock terminal according to the voltages of the Q node and the QB node.

Images