KR101977247B1 - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register and a display device using the shift register. The shift register of the present invention includes: a start terminal to which a start signal or a carry signal is input; A first clock terminal and a second clock terminal receiving a clock signal and an inverted clock signal inverting the clock signal; An output terminal for outputting the start signal inputted to the start terminal or a signal having the same waveform as the previous carry signal; A Q node charging unit charging / discharging the Q node with the start signal or the front carry signal input through the start terminal in response to the clock signal or the inverted clock signal input through the first clock terminal; A QB node discharging unit discharging the QB node to a low potential voltage in response to the clock signal input through the first clock terminal or the inverted clock signal and the start signal input through the start terminal or the front carry signal; A QB node charging unit charging the QB node with a high potential voltage; And an output unit for outputting the high potential voltage to the output terminal in response to the voltage of the Q node and outputting the low potential voltage to the output terminal in response to the voltage of the QB node.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register for sequentially outputting signals having the same waveform as a start voltage and a display using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, a variety of flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes. For example, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) . The flat panel display uses a shift register to display an image using a gate driving circuit for sequentially supplying gate signals to the gate lines of the display panel and a data driving circuit for supplying data voltages to the data lines.

In recent years, in the case of an organic light emitting diode display device, each pixel of the display panel includes a plurality of switching TFTs (thin film transistors) for the purpose of improving image quality and the like. In this case, the gate driving circuit requires shift registers by the number of switching control signals for controlling the plurality of switching TFTs. Since the shift register generates an output depending on the clock, the number of clocks input to the shift register and the phase of the clock depend on the waveform of the switching control signal. Therefore, when the waveforms of the plurality of switching control signals are different from each other, the number of clocks input to each of the shift registers and the phase of the clock may be different from each other. As a result, the number of clock lines increases, which increases the circuit design area of the shift register. Particularly, in the case of a GIP (gate drive IC in panel) method in which a shift register is directly formed in a bezel region of a display panel, a bezel region of the organic light emitting diode display device is widened due to an increase in the circuit design area of the shift register .

The present invention provides a shift register capable of reducing a bezel area of a display device and a display device using the shift register.

The shift register of the present invention includes: a start terminal to which a start signal or a carry signal is input; A first clock terminal and a second clock terminal receiving a clock signal and an inverted clock signal inverting the clock signal; An output terminal for outputting the start signal inputted to the start terminal or a signal having the same waveform as the previous carry signal; A Q node charging unit charging / discharging the Q node with the start signal or the front carry signal input through the start terminal in response to the clock signal or the inverted clock signal input through the first clock terminal; A QB node discharging unit discharging the QB node to a low potential voltage in response to the clock signal input through the first clock terminal or the inverted clock signal and the start signal input through the start terminal or the front carry signal; A QB node charging unit charging the QB node with a high potential voltage; And an output unit for outputting the high potential voltage to the output terminal in response to the voltage of the Q node and outputting the low potential voltage to the output terminal in response to the voltage of the QB node.

A display device of the present invention includes: a display panel including data lines and at least one group of switching signal lines; A data driving circuit for converting input digital video data into analog data voltages and supplying the analog data voltages to the data lines; And a gate driving circuit including at least one shift register for sequentially outputting a switching control signal to the at least one switching signal line group using the shift register.

The shift register of the present invention sequentially outputs signals having the same waveform as the start signal using two clock signals. As a result, in the present invention, when only the waveform of the start signal input to each of the plurality of shift registers is made different, the plurality of shift registers can output a plurality of switching control signals of different waveforms. As a result, the present invention can greatly reduce the circuit design area, thereby reducing the bezel area of the display device.

1 is a block diagram showing a shift register according to an embodiment of the present invention;
2 is a circuit diagram showing an example of a circuit configuration of a k-th stage according to the first embodiment of the present invention;
3 is a waveform diagram showing an example of input signals and output signals of a first stage;
4A to 4J are exemplary diagrams showing circuit operations of the first stage during the first to tenth periods.
5 is a waveform diagram showing an example of input signals and output signals of a second stage;
6A to 6K are exemplary diagrams showing the circuit operation of the second stage during the first to eleventh periods.
7 is a waveform diagram showing an example of input signals and output signals of a third stage;
8 is a circuit diagram showing an example of a circuit configuration of a k-th stage according to a second embodiment of the present invention;
9 is a block diagram schematically showing a display device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 is a block diagram showing a shift register according to an embodiment of the present invention. Referring to FIG. 1, a shift register according to an embodiment of the present invention includes a plurality of stages (ST (1) to ST (n), n being the number of stages connected). In FIG. 1, only the first to third stages ST (1) to ST (3) are illustrated for convenience of explanation.

In the following description, the term " front stage " means that the stage is located above the reference stage. For example, with respect to the stage k (1? K? N, where k is a natural number equal to or greater than 2) stage ST (k), the front stage is a stage from the first stage ST (1) -1)). Quot; rear stage " refers to a stage located at the bottom of the reference stage. For example, on the basis of the k-th stage ST (k), the trailing stage indicates any one of the (k + 1) th stages ST (k + 1) to k (n).

The shift register includes a start signal line STL to which the start signal VST is supplied, a clock line CL to which the clock signal CLK is supplied, an inverted clock line CBL to which the inverted clock signal CLKB is supplied, A high-potential voltage line VDDL to which a voltage is applied, and a low-potential voltage line VSSL to which a low-potential voltage is applied.

Each of the stages ST (1) to ST (n) includes a start terminal START, a first clock terminal CLK1, a second clock terminal CLK2, an output terminal OUT, a high potential voltage input terminal VDDT QB node voltage output terminal QB_OUT, rear Q node voltage input terminal Q_NEXT, and rear end QB node voltage input terminal QB_NEXT, Respectively. The start terminal START of each of the stages ST (1) to ST (n) is connected to the start signal line STL or the output terminal OUT of the front stage. A start signal VST or a previous carry signal is input to the start terminal START of each of the stages ST (1) to ST (n). The start signal VST is input to the start terminal START of the first stage ST 1 but the start terminal START of each of the second to nth stages ST 2 to ST A carry signal is inputted. The carry signal at the front end means a signal input to the start terminal (START) of the k-th stage ST (k) as the output signal of the output terminal OUT of the front stage. For example, the first output signal GOUT (1) of the output terminal OUT of the first stage ST (1) is connected to the start terminal (START) of the second stage ST (2) As shown in FIG.

The first clock terminal CLK1 of each of the stages ST (1) to ST (n) is connected to the clock line CL or the inverted clock line CBL. When the first clock terminal CLK1 of the k-th stage ST (k) is connected to the clock line CL, the clock signal CLK is input to the first clock terminal CLK1. When the first clock terminal CLK1 of the k-th stage ST (k) is connected to the inverted clock line CBL, the inverted clock signal CLBK is input to the first clock terminal CLK1. The inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK. The second clock terminal CLK2 of each of the stages ST (1) to ST (n) is also connected to the clock line CL or the inverted clock line CBL. When the second clock terminal CLK2 of the k-th stage ST (k) is connected to the clock line CL, the clock signal CLK is input to the second clock terminal CLK2. When the second clock terminal CLK2 of the k-th stage ST (k) is connected to the inverted clock line CBL, the inverted clock signal CLKB is input to the second clock terminal CLK2. However, the signal input to the first clock terminal CLK1 of the k-th stage ST (k) differs from the signal input to the second clock terminal CLK2. For example, when the first clock terminal CLK1 of the k-th stage ST (k) is connected to the clock line CL and the clock signal CLK is input to the first clock terminal CLK1, The clock terminal CLK2 is connected to the inverted clock line CBL and the inverted clock signal CLKB is input to the second clock terminal CLK2. When the first clock terminal CLK1 of the k-th stage ST (k) is connected to the inverted clock line CBL and the inverted clock signal CLKB is input to the first clock terminal CLK1, The clock signal CLK2 is connected to the clock line CL and the clock signal CLK is input to the second clock terminal CLK2. The first clock terminal CLK1 and the second clock terminal CLK2 of each of the stages ST (1) to ST (n) are alternately connected to the clock line CL and the inverted clock line CBL do. For example, when the clock signal CLK is input to the first clock terminal CLK1 of the k-th stage ST (k) and the inverted clock signal CLKB is input to the second clock terminal CLK2, the inverted clock signal CLKB is input to the first clock terminal CLK1 of the (k + 1) th stage ST (k + 1) and the clock signal CLK is input to the second clock terminal CLK2. When the inverted clock signal CLKB is input to the first clock terminal CLK1 of the k-th stage ST (k) and the clock signal CLK is input to the second clock terminal CLK2, the (k + 1) The clock signal CLK is input to the first clock terminal CLK1 of the first clock terminal ST (k + 1) and the inverted clock signal CLKB is input to the second clock terminal CLK2.

Since the high-potential voltage input terminal VDDT is connected to the high-potential voltage supply line VDDL, a high-potential voltage is supplied to the high-potential voltage input terminal VDDT. Since the low potential voltage input terminal VSST is connected to the low potential voltage supply line VSSL, a low potential voltage is supplied to the low potential voltage input terminal VSST. The high potential voltage can be set to the gate high voltage VGH and the low potential voltage can be set to the gate low voltage VGL. The gate high voltage VGH may be set to a voltage capable of turning on thin film transistors (TFTs) present in the internal circuits of each of the stages ST (1) to ST (n).

The Q-node voltage output terminal Q_OUT of the k-th stage ST (k) is connected to the rear-end Q-node voltage input terminal Q_NEXT of the front stage. The Q-node voltage output terminal Q_OUT of the k-th stage ST (k) outputs the voltage of the Q-node of the k-th stage ST (k) to the rear-end Q-node voltage input terminal Q_NEXT of the preceding stage. The QB node voltage output terminal QB_OUT of the k-th stage ST (k) is connected to the rear end QB node voltage input terminal QB_NEXT of the front stage. The QB node voltage output terminal QB_OUT of the k-th stage ST (k) outputs the voltage of the QB node of the k-th stage ST (k) to the rear-end QB node voltage input terminal QB_NEXT of the preceding stage. For example, the Q-node voltage output terminal Q_OUT of the second stage ST (2) is connected to the rear-end Q-node voltage input terminal Q_NEXT of the first stage ST (1). The QB node voltage output terminal QB_OUT of the second stage ST 2 is connected to the rear stage QB node voltage input terminal QB_NEXT of the first stage ST 1.

The rear stage Q-node voltage input terminal Q_NEXT of the k-th stage ST (k) is connected to the Q-node voltage output terminal Q_OUT of the rear stage. The rear-end Q-node voltage input terminal Q_NEXT of the k-th stage ST (k) receives the Q-node voltage of the rear stage. The rear stage QB node voltage input terminal QB_NEXT of the k-th stage ST (k) is connected to the QB node voltage output terminal QB_OUT of the rear stage. The rear stage QB node voltage input terminal QB_NEXT of the k-th stage ST (k) receives the QB node voltage of the rear stage. For example, the rear-end Q-node voltage input terminal Q_NEXT of the second stage ST 2 is connected to the Q-node voltage output terminal Q_OUT of the third stage ST 3. The rear stage QB node voltage input terminal QB_NEXT of the second stage ST2 is connected to the QB node voltage output terminal QB_OUT of the third stage ST3.

The output terminal OUT of the k-th stage ST (k) is connected to the k-th output line. The output terminal OUT of the k-th stage ST (k) outputs the k-th output signal GOUT (k) to the k-th output line. The output terminal OUT of the k-th stage ST (k) is connected to the start terminal (START) of the subsequent stage. The k-th output signal GOUT (k) of the output terminal OUT of the k-th stage ST (k) is input as the preceding carry signal to the start terminal (START) of the subsequent stage. For example, the output terminal OUT of the second stage ST (2) outputs the second output signal GOUT (2) to the second output line, and the output terminal OUT of the third stage ST (3) And outputs it to the start terminal (START) in FIG.

2 is a circuit diagram showing an example of a circuit configuration of a k-th stage according to the first embodiment of the present invention. 2, a Q-node charging unit 10 for controlling charging and discharging of a Q-node Q of a k-th stage ST (k) according to the first embodiment of the present invention, a Q- A QB node charging unit 30 for controlling the charging of the QB node QB and a Q node boosting controller 40 for controlling the voltage boost of the Q node Q. The QB node discharging unit 20 controls the discharging of the QB node QB, And an output section 50 for charging the output node NO connected to the output terminal OUT according to the voltage of the Q node Q and the QB node QB at a high potential or for discharging to a low potential voltage do.

The Q node charging unit 10 includes a start signal VST inputted through a start terminal START in response to a clock signal CLK input through the first clock terminal CLK1 or an inverted clock signal CLKB, Charge and discharge with carry signal. To this end, the Q-node charging section 10 includes a first TFT (not shown) for connecting the Q-node Q to the start terminal START in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB T1. The first TFT T1 is a transistor that is responsive to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB to convert the Q node Q into a start signal VST or a first logic level voltage Or discharges the Q node Q to the start signal VST or the second logic level voltage of the previous carry signal. The gate electrode of the first TFT T1 is connected to the first clock terminal CLK1, the source electrode thereof is connected to the Q node Q, and the drain electrode thereof is connected to the start terminal START.

On the other hand, the first logic level voltage and the high potential voltage can be set to the same level voltage, and the second logic level voltage and the low potential voltage can be set to the same level voltage. For example, the first logic level voltage and the high potential voltage may be set to the gate high voltage (VGH), and the second logic level voltage and the low potential voltage may be set to the gate low voltage (VGL).

The QB node discharging unit 20 outputs a clock signal CLK or an inverted clock signal CLKB input via the first clock terminal CLK1 and a start signal VST input via the start terminal START, And discharges the QB node QB to a low potential voltage in response to the low voltage. To this end, the QB node discharging unit 20 includes a second TFT (not shown) for connecting the first node N1 to the start terminal (START) in response to the first logic level voltage of the clock signal (CLK) or the inverted clock signal (T2). The QB node discharging unit 20 further includes a third TFT T3 for connecting the QB node QB to the low potential input terminal VSST in response to the first logic level voltage of the first node N1 . The second TFT T2 is turned on in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB so that the first node N1 is turned on by the start signal VST or the first logic level Or discharges the first node N1 to the start signal VST or the second logic level voltage of the previous carry signal. The third TFT T3, in response to the first logic level voltage of the first node N1, discharges the QB node QB to a low potential voltage. The gate electrode of the second TFT T2 is connected to the first clock terminal CLK1, the source electrode thereof is connected to the first node N1, and the drain electrode thereof is connected to the start terminal START. The gate electrode of the third TFT T3 is connected to the first node N1, the source electrode thereof is connected to the low potential voltage input terminal VSST, and the drain electrode thereof is connected to the QB node QB.

In addition, the QB node discharger 20 discharges the QB node QB to a low potential voltage in response to the first logic level voltage of the Q node (Q). To this end, the QB node discharging unit 20 further includes a fourth TFT (T4) for connecting the QB node (QB) to the low voltage input terminal (VSST) in response to the first logic level voltage of the Q node . The fourth TFT T4 discharges the QB node QB to the low potential voltage in response to the first logic level voltage of the Q node Q. [ The gate electrode of the fourth TFT T4 is connected to the Q node Q, the source electrode thereof is connected to the low potential voltage input terminal VSST, and the drain electrode thereof is connected to the QB node QB.

The QB node charging unit 30 charges the QB node QB to the high potential voltage VDD in response to the high potential voltage VDD input through the high potential input terminal VDDT. To this end, the QB node charging unit 30 includes a fifth TFT T5 for connecting the second node N2 to the high voltage input terminal VDDT in response to the high potential voltage VDD, a second node N2, A sixth TFT T6 for connecting the QB node QB to the low potential input terminal VSST in response to the high potential voltage VDD of the Q node Q, And a seventh TFT (T7) for connecting the second node (N2) to the low potential voltage input terminal (VSST). The fifth TFT T5 charges the second node N2 to the high-potential voltage in response to the high-potential voltage VDD. The sixth TFT T6 charges the QB node QB to the high potential voltage in response to the high potential voltage of the second node N2. The seventh TFT T7 discharges the second node N2 to the low potential voltage in response to the first logic level voltage of the Q node (Q). The gate electrode and the drain electrode of the fifth TFT T5 are connected to the high potential voltage input terminal VDDT, and the source electrode thereof is connected to the second node N2. The gate electrode of the sixth TFT T6 is connected to the second node N2, the source electrode thereof is connected to the QB node QB, and the drain electrode thereof is connected to the high potential voltage input terminal VDDT. The gate electrode of the seventh TFT T7 is connected to the Q node Q, the source electrode thereof is connected to the low potential voltage input terminal VSST, and the drain electrode thereof is connected to the second node N2.

The Q node boost controller 40 receives the clock signal CLK or the inverted clock signal CLKB inputted through the second clock terminal CLK2 and the Q node Q2 of the subsequent stage input through the subsequent Q node voltage input terminal Q_NEXT, The third node N3 is charged to the first logic level voltage in response to the voltage of the third node N3 and the voltage variation of the third node N3 is reflected to the Q node Q. To this end, the Q-node boost controller 40 controls the Q-node boost controller 40 in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB and the first logic level voltage of the Q- And an eighth TFT T8 and a ninth TFT T9 for connecting the third clock terminal N3 to the second clock terminal CLK2. The eighth TFT T8 supplies the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB to the n- To the drain electrode of the transistor T9. The ninth TFT T9 supplies the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB to the third node N3 in response to the first logic level voltage of the Q node Q of the subsequent stage Supply.

The Q node boost controller 40 discharges the third node N3 to the low potential voltage in response to the voltage of the QB node QB of the subsequent stage inputted through the QB node voltage input terminal QB_NEXT. To this end, the Q-node boost controller 40 further includes a tenth TFT (T10) for connecting the third node N3 to the low-potential-voltage input terminal VSST in response to the voltage of the QB node (QB) . The tenth TFT (T10) discharges the third node N3 to a low potential voltage in response to the voltage of the QB node (QB) of the subsequent stage.

The Q node boost controller 40 further includes a first capacitor Cp connected between the third node N3 and the Q node Q. [ One electrode of the first capacitor Cp is connected to the third node N3, and the other electrode thereof is connected to the Q node Q. [ The first capacitor Cp reflects the voltage variation of the third node N3 to the Q node Q when a change occurs in the voltage of the third node N3.

The output unit 50 charges the output node NO to the high potential voltage in response to the voltage of the Q node Q and discharges the output node NO to the low potential voltage in response to the voltage of the QB node QB. do. The output section 50 includes a pull-up TFT TU that connects the output node NO to the high potential input terminal VDDT in response to the first logic level voltage of the Q node Q, And a pull-down TFT (TD) which connects the output node (NO) to the low potential input terminal (VSST) in response to the first logic level voltage of the low level voltage input terminal (VSST). The gate electrode of the pull-up TFT (TU) is connected to the Q node (Q), the source electrode thereof is connected to the high potential input terminal (VDDT), and the drain electrode thereof is connected to the output node (NO). The gate electrode of the pull-down TFT (TD) is connected to the QB node (QB), the source electrode is connected to the output node (NO), and the drain electrode is connected to the low potential voltage input terminal (VSST). Since the output terminal OUT is connected to the output node NO, the voltage of the output node NO is output as an output signal.

2, the first through tenth TFTs T1 through T10, the pull-up TFT TU, and the pull-down TFT TD are formed of an N type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) .

3 is a waveform diagram showing an example of input signals and output signals of the first stage. 3 shows the start signal VST input to the start terminal START as the input signals of the first stage ST 1, the clock signal CLK input to the first clock terminal CLK1, And an inverted clock signal CLKB input to the terminal CLK2. 3, the Q-node voltage Q (2) of the second stage ST (2) input to the rear-end Q-node voltage input terminal Q_NEXT and the Q-node voltage Q And the QB node voltage QB (2) of the two stage ST (2). 3 shows the Q-node voltage Q (1) of the first stage ST (1) outputted as the output signals of the first stage ST (1) to the Q-node voltage output terminal Q_OUT, QB The QB node voltage QB (1) of the first stage ST (1) output to the node voltage output terminal QB_OUT and the QB node voltage QB (1) output to the output terminal OUT of the first stage ST 1 output signal (GOUT (1)) is shown.

Each of the stages ST (1) to ST (n) outputs an output signal having the same waveform and phase as the start signal VST or the preceding carry signal inputted through the start terminal START, through the output terminal OUT Output. The first stage ST 1 outputs a first output signal GOUT (1) having the same waveform as the start signal VST input via the start terminal START through the output terminal OUT. The start signal VST shown in Fig. 3 is generated at the first logic level voltage during the first period t1, the second period t2, and the fifth to eighth periods t5 to t8, 2 logic level voltage. However, the start signal VST shown in FIG. 3 is only one embodiment, and the start signal VST can be predetermined through a preliminary experiment in consideration of the waveform of the first output signal GOUT (1) .

3, each of the first to tenth periods t1 to t10 is one horizontal period (1H), but it should be noted that the present invention is not limited thereto. One horizontal period (1H) denotes a one-line scanning period for supplying a data voltage to all the pixels existing in one horizontal line of the display panel.

The clock signal CLK is generated in a period of a predetermined period and the inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK and therefore occurs at the same cycle as the clock signal CLK. Therefore, when the clock signal CLK is generated as the first logic level voltage as shown in FIG. 3, the inverted clock signal CLKB is generated as the second logic level voltage. Further, when the clock signal CLK is generated at the second logic level voltage, the inverted clock signal CLKB is generated at the first logic level voltage. In FIG. 3, the first logic level voltage is the gate high voltage (VGH) and the second logic level voltage is the gate low voltage (VGL).

The Q node voltage Q (2) of the second stage ST (2) is generated with a phase delay from the Q node voltage Q (1) of the first stage ST (1) by a predetermined period . The QB node voltage QB (2) of the second stage ST (2) is generated by delaying the phase of the QB node voltage QB (1) of the first stage ST (1) by a predetermined period . In FIG. 3, the predetermined period is mainly described as being implemented in one horizontal period.

The Q-node voltage QB (1) of the first stage ST (1) and the QB node voltage QB (1) of the first stage ST (1) The QB node voltage QB (2) of the second stage ST (2) and the first output signal GOUT (1) of the first stage ST (1) ) Will be described in detail with reference to Figs. 4A to 4I.

4A to 4I are exemplary diagrams showing the circuit operation of the first stage during the first to tenth periods. Each of Figs. 4A to 4I shows the turn-on and turn-off states of the TFTs present in the first stage ST (1) in each of the first to tenth periods t1 to t10. In each of Figs. 4A to 4I, the turn-on TFTs are indicated by circles. In the following description, the first logic level voltage and the high potential voltage are the gate high voltage (VGH), and the second logic level voltage and the low potential voltage are the gate low voltage (VGL).

First, the operation of the first stage ST (1) during the first period t1 will be described in detail with reference to FIG. 3 and FIG. 4A. The start signal VST of the first logic level voltage VGH is input to the start terminal START during the first period t1 and the start signal VST of the first logic level voltage VGH is input to the first clock terminal CLK1, And an inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the first period t1, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the second stage ST 2 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The Q-node charging unit 10 charges the Q-node Q to the first logic level voltage VGH during the first period t1. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the first period t1. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the start signal VST.

The QB node discharging unit 20 discharges the QB node QB to the low potential voltage VGL during the first period t1. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the first period t1. Due to the turn-on of the second TFT T2, the first node N1 is charged with the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the first period t1. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the first period t1. Due to the turn-on of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is discharged to the low potential voltage (VGL).

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the first period t1. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the first period t1. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the first period t1, Is turned off by the second logic level voltage (VGL). The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-on of the tenth TFT (T10), the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the first period t1. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the low potential voltage VGL of the QB node QB. Lt; / RTI > The output node OUT of the first stage ST 1 is turned off at the high potential voltage VHH due to the turn-on of the pull-up TFT TU, And outputs the first output signal GOUT (1) of the VGH.

Secondly, the operation of the first stage ST (1) during the second period t2 will be described in detail with reference to FIG. 3 and FIG. 4B. The start signal VST of the first logic level voltage VGH is input to the start terminal START during the second period t2 and the start signal VST of the second logic level voltage VGL is input to the first clock terminal CLK1, And the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, since the Q node Q of the second stage ST (2) has the first logic level voltage VGH during the second period t2, the subsequent Q node voltage input terminal Q_NEXT has the first logic level The QB node QB of the second stage ST 2 has the second logic level voltage VGL so that the second QB node voltage input terminal QB_NEXT receives the second logic level voltage VGL, (VGL) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the second period t2.

The QB node discharger 20 maintains the QB node QB at the low potential voltage VGL during the second period t2. The second TFT T2 is turned off by the clock signal CLK of the second logic level voltage VGL during the second period t2. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the second period t2. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the second period t2. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The Q node boost controller 40 boosts the voltage of the Q node Q during the second period t2. The eighth TFT T8 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged with the first logic level voltage of the inverted clock signal CLKB. That is, the voltage of the third node N3 rises from the low potential voltage VGL to the first logic level voltage VGH during the second period t2, and the voltage variation of the third node N3 rises from the low- (Q) by the node Cp. Thus, during the second period t2, the Q node Q rises to a voltage VGH 'that is higher than the first logic level voltage VGH. The pull-up TFT (TU) has an advantage that it can be stably turned on due to the voltage rise of the Q node (Q).

The output section 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the second period t2. The pull-down TFT TU is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the QB node QB, And is turned off by a second logic level voltage (VGL) The output node OUT of the first stage ST 1 is maintained at the high potential voltage VHH because the output node NO maintains the high potential voltage VGH due to the turn- And outputs the first output signal GOUT (1) of the VGH.

Third, the operation of the first stage ST (1) during the third period t3 will be described in detail with reference to Figs. 3 and 4C. The start signal VST of the second logic level voltage VGL is input to the start terminal START during the third period t3 and the start signal VST of the first logic level voltage VGH is input to the first clock terminal CLK1, And an inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. Also, during the third period t3, the Q node Q of the second stage ST (2) has a voltage VGH 'higher than the first logic level voltage VGH, The voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and the QB node QB of the second stage ST 2 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q node charging unit 10 discharges the Q node Q to the second logic level voltage VGL during the third period t3. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the third period t3. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the start signal VST.

The second TFT T2 of the QB node discharging portion 20 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the third period t3. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the start signal VST. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the third period t3. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the third period t3. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the third period t3. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the third period t3. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the third period t3. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the third period t3. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-off of the eighth TFT (T8) and the tenth TFT (T10), the third node (N3) floats.

The output section 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the third period t3. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > Because the output node NO is discharged to the low potential voltage VGL due to the turn-on of the pull-down TFT (TD), the output terminal OUT of the first stage ST (1) VGL of the first output signal GOUT (1).

Fourth, the operation of the first stage ST (1) during the fourth period t4 will be described in detail with reference to FIG. 3 and FIG. 4D. The start signal VST of the second logic level voltage VGL is input to the start terminal START during the fourth period t4 and the start signal VST of the second logic level voltage VGL is input to the first clock terminal CLK1, And the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the fourth period t4, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the second stage ST 2 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the fourth period t4.

The second TFT T2 of the QB node discharging portion 20 is turned off by the clock signal CLK of the second logic level voltage VGL during the fourth period t4. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the fourth period t4. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the fourth period t4. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the fourth period t4. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control section 40 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the fourth period t4. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the fourth period t4. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > Because the output node NO is discharged to the low potential voltage VGL due to the turn-on of the pull-down TFT (TD), the output terminal OUT of the first stage ST (1) VGL of the first output signal GOUT (1).

Fifth, the operation of the first stage ST (1) during the fifth period t5 will be described in detail with reference to FIG. 3 and FIG. 4E. The start signal VST of the first logic level voltage VGH is input to the start terminal START during the fifth period t5 and the start signal VST of the first logic level voltage VGH is input to the first clock terminal CLK1, And an inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the fifth period t5, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the second stage ST 2 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The Q node charging section 10 charges the Q node Q to the first logic level voltage VGH during the fifth period t5. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the fifth period t5. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the start signal VST.

The QB node discharging unit 20 discharges the QB node QB to the low potential voltage VGL during the fifth period t5. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the fifth period t5. Due to the turn-on of the second TFT T2, the first node N1 is charged with the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the fifth period t5. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the fifth period t5. Due to the turn-on of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is discharged to the low potential voltage (VGL).

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the fifth period t5. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the fifth period t5. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the fifth period t5. The ninth TFT T9 is turned off by the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-on of the tenth TFT (T10), the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the fifth period t5. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the low potential voltage VGL of the QB node QB. Lt; / RTI > The output node OUT of the first stage ST 1 is turned off at the high potential voltage VHH due to the turn-on of the pull-up TFT TU, And outputs the first output signal GOUT (1) of the VGH.

Sixth, the operation of the first stage ST (1) during the sixth period t6 will be described in detail with reference to FIG. 3 and FIG. 4f. The start signal VST of the first logic level voltage VGH is input to the start terminal START during the sixth period t6 and the start signal VST of the second logic level voltage VGL is input to the first clock terminal CLK1, And the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, during the sixth period t6, the Q node Q of the second stage ST (2) has the first logic level voltage VGH, so that the subsequent Q node voltage input terminal Q_NEXT has the first logic level The QB node QB of the second stage ST 2 has the second logic level voltage VGL so that the second QB node voltage input terminal QB_NEXT receives the second logic level voltage VGL, (VGL) is input.

The first TFT T1 of the Q-node charging portion 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the sixth period t6.

The QB node discharging unit 20 maintains the QB node QB at the low potential voltage VGL during the sixth period t6. The second TFT T2 is turned off by the clock signal CLK of the second logic level voltage VGL during the sixth period t6. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the sixth period t6. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the sixth period t6. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The Q node boost controller 40 boosts the voltage of the Q node Q during the sixth period t6. The eighth TFT T8 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged with the first logic level voltage of the inverted clock signal CLKB. That is, the voltage of the third node N3 rises from the low potential voltage VGL to the first logic level voltage VGH during the sixth period t6, and the voltage variation of the third node N3 rises from the low- (Q) by the node Cp. Thus, during the sixth period t6, the Q node Q rises to a voltage VGH 'that is higher than the first logic level voltage VGH. The pull-up TFT (TU) has an advantage that it can be stably turned on due to the voltage rise of the Q node (Q).

The output section 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the sixth period t6. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the second logic level voltage < RTI ID = 0.0 > VGL). ≪ / RTI > The output node OUT of the first stage ST 1 is maintained at the high potential voltage VHH because the output node NO maintains the high potential voltage VGH due to the turn- And outputs the first output signal GOUT (1) of the VGH.

Seventh, the operation of the first stage ST (1) during the seventh period t7 will be described in detail with reference to Figs. 3 and 4G. The start signal VST of the first logic level voltage VGH is input to the start terminal START during the seventh period t7 and the start signal VST of the first logic level voltage VGH is input to the first clock terminal CLK1, And an inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. Also, during the seventh period t7, the Q node Q of the second stage ST (2) has a voltage VGH 'higher than the first logic level voltage VGH, The voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and the QB node QB of the second stage ST 2 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The inverted clock signal CLKB of the first logic level voltage VGH which is a turn-on voltage is input to the gate electrode of the first TFT T1 of the Q-node charging portion 10 during the seventh period t7. However, since the voltage of the Q node Q connected to the source electrode of the first TFT T1 is higher than the first logic level voltage VGH, the Q node Q is higher than the first logic level voltage VGH And maintains the voltage VGH '.

The QB node discharging unit 20 maintains the QB node QB at the low potential voltage VGL during the seventh period t7. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the seventh period t7. Due to the turn-on of the second TFT T2, the first node N1 is charged with the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the seventh period t7. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is discharged to the low potential voltage (VGL).

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the seventh period t7. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the seventh period t7. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-off of the eighth TFT (T8) and the tenth TFT (T10), the third node (N3) maintains the first logic level voltage (VGH).

The output section 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the seventh period t7. The pull-down TFT TU is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the QB node QB, Off by the low potential voltage (VGL) The output node OUT of the first stage ST 1 is turned off at the high potential voltage VHH due to the turn-on of the pull-up TFT TU, And outputs the first output signal GOUT (1) of the VGH.

Eighthly, the operation of the first stage ST (1) during the eighth period t8 will be described in detail with reference to Figs. 3 and 4H. During the eighth period t8, the start signal VST of the first logic level voltage VGH is input to the start terminal START and the clock signal VST of the second logic level voltage VGL is input to the first clock terminal CLK1. And the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, during the eighth period t8, the Q node Q of the second stage ST (2) has the voltage VGH 'higher than the first logic level voltage VGH, The voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and the QB node QB of the second stage ST 2 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The first TFT T1 of the Q-node charging portion 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the eighth period t8.

The QB node discharging unit 20 maintains the QB node QB at the low potential voltage VGL during the eighth period t8. The second TFT T2 is turned off by the clock signal CLK of the second logic level voltage VGL during the eighth period t8. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the eighth period t8. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the eighth period t8. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q-node boost control section 40 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged with the first logic level voltage of the inverted clock signal CLKB.

The output section 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the eighth period t8. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the second logic level voltage < RTI ID = 0.0 > VGL). ≪ / RTI > The output node OUT of the first stage ST 1 is maintained at the high potential voltage VHH because the output node NO maintains the high potential voltage VGH due to the turn- And outputs the first output signal GOUT (1) of the VGH.

The operation of the first stage ST (1) during the ninth period t9 will be described in detail with reference to Figs. 3 and 4i. The start signal VST of the second logic level voltage VGL is input to the start terminal START during the ninth period t9 and the start signal VST of the first logic level voltage VGH is input to the first clock terminal CLK1, And an inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. Also, during the ninth period t9, the Q node Q of the second stage ST (2) has a voltage VGH 'higher than the first logic level voltage VGH, The voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and the QB node QB of the second stage ST 2 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q-node charging unit 10 discharges the Q-node Q to the second logic level voltage VGL during the ninth period t9. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the ninth period t9. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the start signal VST.

The second TFT T2 of the QB node discharging portion 20 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the ninth period t9. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the start signal VST. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the ninth period t9. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the ninth period t9. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the ninth period t9. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the ninth period t9. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the ninth period t9. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control unit 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the ninth period t9. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-off of the eighth TFT (T8) and the tenth TFT (T10), the third node (N3) floats.

The output section 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the ninth period t9. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > Because the output node NO is discharged to the low potential voltage VGL due to the turn-on of the pull-down TFT (TD), the output terminal OUT of the first stage ST (1) VGL of the first output signal GOUT (1).

The operation of the first stage ST (1) during the tenth period t10 will be described in detail with reference to FIG. 3 and FIG. 4J. The start signal VST of the second logic level voltage VGL is input to the start terminal START during the tenth period t10 and the start signal VST of the second logic level voltage VGL is input to the first clock terminal CLK1, And the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the tenth period t10, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the second stage ST 2 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the tenth period t10.

The second TFT T2 of the QB node discharging portion 20 is turned off by the clock signal CLK of the second logic level voltage VGL during the tenth period t10. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the tenth period t10. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the tenth period t10. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the tenth period t10. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control section 40 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the tenth period t10. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the tenth period t10. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > Because the output node NO is discharged to the low potential voltage VGL due to the turn-on of the pull-down TFT (TD), the output terminal OUT of the first stage ST (1) VGL of the first output signal GOUT (1).

The first stage ST (1) repeats the operations of the ninth period t9 and the tenth period t10 from the tenth period t10 to the first period t1 of the next frame period will be.

As described above, the first stage ST (1) outputs the output signal GOUT (1) having the same waveform and phase as the start signal VST. However, each of the second to n-th stages ST (2) to ST (n) has the same waveform as that of the previous carry signal input through the start terminal (START), and the phase is an output signal delayed by a predetermined period Output. Hereinafter, the input signals, the output signals, and the operation method of each of the second to n-th stages ST (2) to ST (n) will be described in detail with reference to FIG. 5 and FIGS. 6A to 6K .

5 is a waveform diagram showing an example of input signals and output signals of the second stage. 5 shows the output signal GOUT (1) of the first stage ST (1), which is a front carry signal input to the start terminal (START) as input signals of the second stage ST (2) An inverted clock signal CLKB input to the terminal CLK1, and a clock signal CLK input to the second clock terminal CLK2. That is, the clock signal CLK is input to the first clock terminal CLK1 of the first stage ST (1) and the inverted clock signal CLKB is input to the second clock terminal CLK2, It should be noted that the inverted clock signal CLKB is input to the first clock terminal CLK1 of the first clock terminal ST2 and the clock signal CLK is input to the second clock terminal CLK2.

5, the Q-node voltage Q (3) of the third stage ST (3) input to the rear-end Q-node voltage input terminal Q_NEXT and the Q-node voltage Q And the QB node voltage (QB (3)) of the third stage (ST (3)). 5 shows a second stage ST (2) Q node voltage Q (2) output to the Q node voltage output terminal Q_OUT as output signals of the second stage ST (2) The QB node voltage QB (2) of the second stage ST (2) output to the voltage output terminal QB_OUT and the QB node voltage QB (2) of the second stage ST (2) output to the output terminal OUT of the second stage ST The output signal GOUT (2) is shown.

Each of the stages ST (1) to ST (n) outputs an output signal whose waveform is the same as the start signal VST input through the start terminal START or the previous carry signal but whose phase is delayed by a predetermined period Through the terminal OUT. The second stage ST 2 has the same waveform as that of the first output signal GOUT (1) which is the front carry signal inputted through the start terminal START, but the phase of the second stage ST 2 is delayed by one horizontal period And outputs the output signal GOUT (2) through the output terminal OUT. 5, each of the first to eleventh periods t1 to t11 is one horizontal period (1H), but it should be noted that the present invention is not limited to this. The first output signal GOUT (1) shown in FIG. 5 has the same waveform and phase as the start signal VST input to the start terminal of the first stage ST (1) .

The clock signal CLK is generated in a period of a predetermined period and the inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK and therefore occurs at the same cycle as the clock signal CLK. Therefore, when the clock signal CLK is generated as the first logic level voltage as shown in FIG. 5, the inverted clock signal CLKB is generated as the second logic level voltage. Further, when the clock signal CLK is generated at the second logic level voltage, the inverted clock signal CLKB is generated at the first logic level voltage. In FIG. 5, the first logic level voltage is the gate high voltage (VGH) and the second logic level voltage is the gate low voltage (VGL).

The Q node voltage Q (3) of the third stage ST (3) is generated by a delay of a predetermined period from the Q node voltage Q (2) of the second stage ST (2) . The QB node voltage QB (3) of the third stage ST (3) is generated by delaying the phase of the QB node voltage QB (2) of the second stage ST (2) by a predetermined period . In FIG. 5, the predetermined period is mainly described as being implemented in one horizontal period.

The Q-node voltage Q (2) of the second stage ST (2), the Q-node voltage QB (2) of the second stage ST (2) The QB node voltage QB (3) of the third stage ST (3) and the output signal GOUT (2) of the second stage ST (2) 6A to 6K will be described in detail.

6A to 6K are exemplary diagrams showing the circuit operation of the second stage during the first to eleventh periods. Each of Figs. 6A to 6K shows the turn-on and turn-off states of the TFTs present in the second stage ST (2) in each of the first to eleventh periods t1 to t11. In each of Figs. 6A to 6K, the turn-on TFTs are indicated by circles. In the following description, the first logic level voltage and the high potential voltage are the gate high voltage (VGH), and the second logic level voltage and the low potential voltage are the gate low voltage (VGL).

First, the operation of the second stage ST (2) during the first period t1 will be described in detail with reference to Figs. 5 and 6A. During the first period t1, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START and the second logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. Since the Q node Q of the third stage ST 3 during the first period t1 has the second logic level voltage VGL, the second logic level input terminal Q_NEXT receives the second logic level voltage VGL, The QB node QB of the third stage ST 3 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the first period t1.

The second TFT T2 of the QB node discharging portion 20 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the first period t1. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the first period t1. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the first period t1. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the first period t1. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the first period t1. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the first period t1. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control section 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the first period t1. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the first period t1. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > The output node OUT of the second stage ST 2 is turned off at the low potential voltage VGL because the output node NO is discharged to the low potential voltage VGL due to the turn- VGL of the second output signal GOUT (2).

Secondly, the operation of the second stage ST (2) during the second period t2 will be described in detail with reference to Figs. 5 and 6B. The first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START during the second period t2 and the first logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. Since the Q node Q of the third stage ST 3 during the second period t2 has the second logic level voltage VGL, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the third stage ST 3 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The Q node charging section 10 charges the Q node Q to the first logic level voltage VGH during the second period t2. The first TFT T1 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the second period t2. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the first output signal GOUT (1).

The QB node discharger 20 discharges the QB node QB to the low potential voltage VGL during the second period t2. The second TFT T2 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the second period t2. Due to the turn-on of the second TFT T2, the first node N1 is charged with the first logic level voltage VGH of the first output signal GOUT (1). The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the second period t2. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is discharged to the low potential voltage (VGL).

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the second period t2. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the second period t2 and the ninth TFT T9 And is turned off by the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the second period t2. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the low potential voltage VGL of the QB node QB. Lt; / RTI > The output node OUT of the second stage ST 2 is turned off at the high potential voltage VHH due to the turn-on of the pull-up TFT TU, And outputs the second output signal GOUT (2) of the VGH.

Third, the operation of the second stage ST (2) during the third period t3 will be described in detail with reference to Figs. 5 and 6C. During the third period t3, the first output signal GOUT (1) of the second logic level voltage VGH is input to the start terminal START and the second logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, during the third period t3, the Q node Q of the third stage ST 3 has the first logic level voltage VGH, so that the subsequent Q node voltage input terminal Q_NEXT has the first logic level The QB node QB of the third stage ST 3 has the second logic level voltage VGL so that the second QB node voltage input terminal QB_NEXT receives the second logic level voltage VGL, (VGL) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the third period t3.

The QB node discharging unit 20 maintains the QB node QB at the low potential voltage VGL during the third period t3. The second TFT T2 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the third period t3. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the third period t3. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the third period t3. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the third period t3. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the third period t3. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The Q node boost controller 40 boosts the voltage of the Q node Q during the third period t3. The eighth TFT T8 is turned on in response to the clock signal CLK of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged with the first logic level voltage VGH of the clock signal CLK. That is, the voltage of the third node N3 rises from the low potential voltage VGL to the first logic level voltage VGH during the third period t3, and the voltage variation of the third node N3 rises from the low- (Q) by the node Cp. Thus, during the third period t3, the Q node Q rises to a voltage VGH 'that is higher than the first logic level voltage VGH. The pull-up TFT (TU) has an advantage that it can be stably turned on due to the voltage rise of the Q node (Q).

The output section 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the third period t3. The pull-down TFT TU is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the QB node QB, And is turned off by a second logic level voltage (VGL) The output node OUT of the second stage ST 2 is maintained at the high potential voltage VHH because the output node NO maintains the high potential voltage VGH due to the turn-on of the pull-up TFT TU And outputs the second output signal GOUT (2) of the VGH.

Fourth, the operation of the second stage ST (2) during the fourth period t4 will be described in detail with reference to Figs. 5 and 6D. The first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START during the fourth period t4 and the first logic level voltage VGL is input to the first clock terminal CLK1 The clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. Also, during the fourth period t4, the Q node Q of the third stage ST 3 has the voltage VGH 'higher than the first logic level voltage VGH, A voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and a QB node QB of the third stage ST 3 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q node charging unit 10 discharges the Q node Q to the second logic level voltage VGL during the fourth period t4. The first TFT T1 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the fourth period t4. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the first output signal GOUT (1)).

The second TFT T2 of the QB node discharging portion 20 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the fourth period t4. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the first output signal GOUT (1). The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the fourth period t4. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the fourth period t4. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the fourth period t4. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control unit 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the fourth period t4. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-off of the eighth TFT (T8) and the tenth TFT (T10), the third node (N3) floats.

The output section 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the fourth period t4. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > The output node OUT of the second stage ST 2 is turned off at the low potential voltage VGL because the output node NO is discharged to the low potential voltage VGL due to the turn- VGL of the second output signal GOUT (2).

Fifth, the operation of the second stage ST (2) during the fifth period t5 will be described in detail with reference to FIG. 5 and FIG. 6E. The first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START during the fifth period t5 and the second logic level voltage VGL is input to the first clock terminal CLK1 The clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. Since the Q node Q of the third stage ST 3 has the second logic level voltage VGL during the fifth period t5, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the third stage ST 3 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the fifth period t5.

The second TFT T2 of the QB node discharging portion 20 is turned off by the inverted clock signal CLK of the second logic level voltage VGL during the fifth period t5. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the fifth period t5. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the fifth period t5. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the fifth period t5. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the fifth period t5. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the fifth period t5. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control section 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the fifth period t5. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the fifth period t5. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > The output node OUT of the second stage ST 2 is turned off at the low potential voltage VGL because the output node NO is discharged to the low potential voltage VGL due to the turn- VGL of the second output signal GOUT (2).

Sixth, the operation of the second stage ST (2) during the sixth period t6 will be described in detail with reference to Figs. 5 and 6F. During the sixth period t6, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START and the first logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. Since the Q node Q of the third stage ST 3 during the sixth period t6 has the second logic level voltage VGL, the second logic level input terminal Q_NEXT receives the second logic level voltage VGL, The QB node QB of the third stage ST 3 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The Q node charging section 10 charges the Q node Q to the first logic level voltage VGH during the sixth period t6. The first TFT T1 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the sixth period t6. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the first output signal GOUT (1).

The QB node discharging unit 20 discharges the QB node QB to the low potential voltage VGL during the sixth period t6. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the sixth period t6. Due to the turn-on of the second TFT T2, the first node N1 is charged with the first logic level voltage VGH of the first output signal GOUT (1). The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the sixth period t6. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is discharged to the low potential voltage (VGL).

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the sixth period t6. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the sixth period t6. The ninth TFT T9 is turned off by the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-on of the tenth TFT (T10), the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the sixth period t6. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the low potential voltage VGL of the QB node QB. Lt; / RTI > The output node OUT of the second stage ST 2 is turned off at the high potential voltage VHH due to the turn-on of the pull-up TFT TU, And outputs the second output signal GOUT (2) of the VGH.

Seventh, the operation of the second stage ST (2) during the seventh period t7 will be described in detail with reference to Figs. 5 and 6G. During the seventh period t7, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START and the second logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. Further, during the seventh period t7, the Q node Q of the third stage ST (3) has the first logic level voltage VGH, so that the subsequent Q node voltage input terminal Q_NEXT has the first logic level The QB node QB of the third stage ST 3 has the second logic level voltage VGL so that the second QB node voltage input terminal QB_NEXT receives the second logic level voltage VGL, (VGL) is input.

The first TFT T1 of the Q-node charging portion 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the seventh period t7.

The QB node discharging unit 20 maintains the QB node QB at the low potential voltage VGL during the seventh period t7. The second TFT T2 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the seventh period t7. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the seventh period t7. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the seventh period t7. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The Q node boost controller 40 boosts the voltage of the Q node Q during the seventh period t7. The eighth TFT T8 is turned on in response to the clock signal CLK of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged with the first logic level voltage VGH of the clock signal CLKB. That is, the voltage of the third node N3 rises from the low potential voltage VGL to the first logic level voltage VGH during the seventh period t7, and the voltage variation of the third node N3 rises from the low- (Q) by the node Cp. Thus, during the seventh period t7, the Q node Q rises to a voltage VGH 'that is higher than the first logic level voltage VGH.

The output section 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the seventh period t7. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the second logic level voltage < RTI ID = 0.0 > VGL). ≪ / RTI > The output node OUT of the second stage ST 2 is maintained at the high potential voltage VHH because the output node NO maintains the high potential voltage VGH due to the turn-on of the pull-up TFT TU And outputs the second output signal GOUT (2) of the VGH.

Eighthly, the operation of the second stage ST (2) during the eighth period t8 will be described in detail with reference to Figs. 5 and 6H. During the eighth period t8, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START and the first logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. Also, during the eighth period t8, the Q node Q of the third stage ST 3 has the voltage VGH 'higher than the first logic level voltage VGH, A voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and a QB node QB of the third stage ST 3 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The inverted clock signal CLKB of the first logic level voltage VGH which is a turn-on voltage is input to the gate electrode of the first TFT T1 of the Q-node charging portion 10 during the eighth period t8. However, since the voltage of the Q node Q connected to the source electrode of the first TFT T1 is higher than the first logic level voltage VGH, the Q node Q is higher than the first logic level voltage VGH And maintains the voltage VGH '.

The QB node discharging unit 20 maintains the QB node QB at the low potential voltage VGL during the eighth period t8. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the eighth period t8. Due to the turn-on of the second TFT T2, the first node N1 is charged with the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the eighth period t8. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is discharged to the low potential voltage (VGL).

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Thus, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the eighth period t8. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the eighth period t8. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-off of the eighth TFT (T8) and the tenth TFT (T10), the third node (N3) maintains the first logic level voltage (VGH).

The output section 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the eighth period t8. The pull-down TFT TU is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the QB node QB, Off by the low potential voltage (VGL) The output node OUT of the second stage ST 2 is turned off at the high potential voltage VHH due to the turn-on of the pull-up TFT TU, And outputs the second output signal GOUT (2) of the VGH.

The operation of the second stage ST (2) during the ninth period t9 will be described in detail with reference to Figs. 5 and 6i. During the ninth time period t9, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START and the second logic level voltage VGH is input to the first clock terminal CLK1 The clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. Also, during the ninth period t9, the Q node Q of the third stage ST (3) has the voltage VGH 'higher than the first logic level voltage VGH, A voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and a QB node QB of the third stage ST 3 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The first TFT T1 of the Q node charging portion 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the ninth period t9.

The QB node discharging section 20 maintains the QB node QB at the low potential voltage VGL during the ninth period t9. The second TFT T2 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the ninth period t9. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the ninth period t9. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the ninth period t9. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging section 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the ninth period t9. Due to the turn-on of the seventh TFT (T7), the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the ninth period t9. Due to the turn-off of the sixth TFT (T6), the high-potential voltage (VGH) is not supplied to the QB node (QB).

The eighth TFT T8 of the Q node boost control section 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged with the first logic level voltage of the clock signal CLK.

The output section 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the ninth period t9. The pull-down TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q and the pull-down TFT TD is turned on in response to the second logic level voltage < RTI ID = 0.0 > VGL). ≪ / RTI > The output node OUT of the second stage ST 2 is maintained at the high potential voltage VHH because the output node NO maintains the high potential voltage VGH due to the turn-on of the pull-up TFT TU And outputs the second output signal GOUT (2) of the VGH.

The operation of the second stage ST (2) during the tenth period t10 will be described in detail with reference to FIG. 5 and FIG. 6J. During the tenth period t10, the first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START and the first logic level voltage VGL is input to the first clock terminal CLK1 The clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. The Q node Q of the third stage ST 3 during the tenth period t10 has the voltage VGH 'higher than the first logic level voltage VGH, A voltage VGH 'higher than the first logic level voltage VGH is input to the QB node Q_NEXT and a QB node QB of the third stage ST 3 has the second logic level voltage VGL, The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q-node charging unit 10 discharges the Q-node Q to the second logic level voltage VGL during the tenth period t10. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the tenth period t10. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the first output signal GOUT (1).

The second TFT T2 of the QB node discharging portion 20 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the tenth period t10. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the first output signal GOUT (1). The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the tenth period t10. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the tenth period t10. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the tenth period t10. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control unit 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the tenth period t10. The ninth TFT T9 is turned on in response to a voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT (T10) is turned off by the second logic level voltage (VGL). Due to the turn-off of the eighth TFT (T8) and the tenth TFT (T10), the third node (N3) floats.

The output section 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the tenth period t10. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > The output node OUT of the second stage ST 2 is turned off at the low potential voltage VGL because the output node NO is discharged to the low potential voltage VGL due to the turn- VGL of the second output signal GOUT (2).

Eleventh, the operation of the second stage ST (2) during the eleventh period t11 will be described in detail with reference to FIG. 5 and FIG. 6k. The first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START during the eleventh period t11 and the second logic level voltage VGL is input to the first clock terminal CLK1 The clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. Since the Q node Q of the third stage ST 3 has the second logic level voltage VGL during the eleventh period t11, the subsequent Q node voltage input terminal Q_NEXT has the second logic level The QB node QB of the third stage ST 3 has the first logic level voltage VGH so that the subsequent QB node voltage input terminal QB_NEXT receives the first logic level voltage VGH, (VGH) is input.

The first TFT T1 of the Q node charging portion 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the eleventh period t11.

The second TFT T2 of the QB node discharging portion 20 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the eleventh period t11. Due to the turn-off of the second TFT T2, the first node N1 floats. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the eleventh period t11. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the eleventh period t11. Due to the turn-off of the third TFT (T3) and the fourth TFT (T4), the QB node (QB) is not discharged to the low potential voltage (VGL).

The QB node charging unit 30 charges the QB node QB to the high potential voltage VGH during the eleventh period t11. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the eleventh period t11. Due to the turn-off of the seventh TFT (T7), the second node N2 is charged to the high-potential voltage VGH. Thus, the sixth TFT T6 is turned on in response to the high-potential voltage VGH of the second node N2 during the eleventh period t11. Due to the turn-on of the sixth TFT (T6), the QB node (QB) is charged to the high-potential voltage (VGH).

The eighth TFT T8 of the Q node boost control section 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the eleventh period t11. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT (T10) is turned on in response to the first logic level voltage (VGH). Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output section 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the eleventh period t11. The pull-down TFT TU is turned off by the second logic level voltage VGL of the Q node Q and the pull-down TFT TD is turned off by the first logic level voltage VGH of the QB node QB ). ≪ / RTI > The output node OUT of the second stage ST 2 is turned off at the low potential voltage VGL because the output node NO is discharged to the low potential voltage VGL due to the turn- VGL of the second output signal GOUT (2).

The second stage ST (2) repeats the operations of the tenth period t11 and the eleventh period t11 from the eleventh period t11 to the first period t1 of the next frame period will be.

As described above, the second stage ST (2) outputs the second output signal GOUT (2) having the same waveform as the preceding carry signal and having a phase delayed by a predetermined period. Note that the operation method of the second stage ST (2) described with reference to Figs. 6A to 6K is one embodiment. That is, the first clock terminal CLK1 receives the inverted clock signal CLKB, the second clock terminal CLK2 receives the clock signal CLK, and the start terminal START receives the previous carry signal. The operation method of the k stage ST (k) is the same as that of the second stage ST (2) described with reference to Figs. 6A to 6K. Accordingly, the clock signal CLK is input to the first clock terminal CLK1, the clock signal CLK is input to the second clock terminal CLK2, and the previous carry signal is input to the start terminal START The k stage ST (k) outputs the k-th output signal GOUT (k), which has the same waveform as the preceding carry signal and whose phase is delayed by a predetermined period.

7 is a waveform diagram showing an example of input signals and output signals of the third stage. 7 shows the output signal GOUT (2) of the second stage ST (2), which is the previous carry signal input to the start terminal (START) as the input signals of the third stage ST (3) A clock signal CLK input to the terminal CLK1 and an inverted clock signal CLKB input to the second clock terminal CLK2 are shown. That is, the clock signal CLK is input to the first clock terminal CLK1 of the first stage ST (1) and the third clock signal CLK2 of the third stage ST (3) The inverted clock signal CLKB is input to the first clock terminal CLK1 of the second stage ST 2 and the clock signal CLK is input to the second clock terminal CLK2 .

7, the Q-node voltage (Q (4)) of the fourth stage ST (4) input to the rear-end Q-node voltage input terminal Q_NEXT and the Q- And the QB node voltage (QB (4)) of the fourth stage (ST (4)). 7 shows a third stage ST (3) Q node voltage Q (3) output to the Q node voltage output terminal Q_OUT as output signals of the third stage ST (3) The QB node voltage QB (3) of the third stage ST (3) output to the voltage output terminal QB_OUT and the QB node voltage QB (3) of the third stage ST The output signal GOUT (3) is shown.

Each of the stages ST (1) to ST (n) outputs an output signal whose waveform is the same as the start signal VST input through the start terminal START or the previous carry signal but whose phase is delayed by a predetermined period Through the terminal OUT. The third stage ST 3 has the same waveform as the second output signal GOUT 2 that is the front carry signal input through the start terminal START but has a phase that is delayed by one horizontal period And outputs the output signal GOUT (3) through the output terminal OUT. In FIG. 7, each of the second to twelfth periods (t2 to t12) is one horizontal period (1H), but it is not limited thereto.

The clock signal CLK is generated in a period of a predetermined period and the inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK and therefore occurs at the same cycle as the clock signal CLK. Therefore, when the clock signal CLK is generated at the first logic level voltage as shown in FIG. 7, the inverted clock signal CLKB is generated at the second logic level voltage. Further, when the clock signal CLK is generated at the second logic level voltage, the inverted clock signal CLKB is generated at the first logic level voltage. In FIG. 7, the first logic level voltage is the gate high voltage (VGH) and the second logic level voltage is the gate low voltage (VGL).

The Q node voltage Q (4) of the fourth stage ST (4) is generated by delaying the phase of the Q node voltage Q (3) of the third stage ST (3) by a predetermined period . The QB node voltage QB (4) of the fourth stage ST (4) is generated by delaying the phase of the QB node voltage QB (3) of the third stage ST (3) by a predetermined period . In FIG. 7, the predetermined period is mainly described as being implemented in one horizontal period.

On the other hand, the operation method of the third stage ST (3) during the second to twelfth periods t2 to t12 is the same as the first to the eleventh periods t1 to t11 described with reference to Figs. 6A to 6K, Is the same as the operation method of the stage ST (2). Therefore, the Q node voltage Q (3) of the third stage ST (3), the QB node voltage QB (3) of the third stage ST (3) The QB node voltage QB (4) of the fourth stage ST (4), and the third output signal GOUT (4) of the third stage ST (3) 3) are also described with reference to Figs. 6A to 6K. However, the first output signal GOUT (1) is input to the start terminal START of the second stage ST (2), the inverted clock signal CLKB is input to the first clock terminal CLK1, The clock signal CLK is input to the second clock terminal CLK2 and the Q node voltage Q (3) of the third stage ST (3) is input to the subsequent Q node voltage input terminal Q_NEXT, The QB node voltage Q (3) of the third stage ST (3) is input to the rear stage QB node voltage input terminal QB_NEXT. However, the second output signal GOUT2 is input to the start terminal START of the third stage ST (3), the clock signal CLK is input to the first clock terminal CLK1, The Q node voltage Q (4) of the fourth stage ST (4) is inputted to the rear stage Q node voltage input terminal Q_NEXT and the inverted clock signal CLKB is inputted to the rear stage QB node CLK2, It should be noted that the QB node voltage Q (4) of the fourth stage ST (4) is input to the voltage input terminal QB_NEXT.

As a result, the third stage ST (3) outputs the third output signal GOUT (3), which has the same waveform as the preceding carry signal and whose phase is delayed by a predetermined period. A kth stage in which a clock signal CLK is input to the first clock terminal CLK1 and an inverted clock signal CLKB is input to the second clock terminal CLK2 and a previous carry signal is input to the start terminal START, (ST (k)) is the same as the operation method of the third stage (ST (3)) described with reference to FIG. Therefore, when the clock signal CLK is input to the first clock terminal CLK1, the inverted clock signal CLKB is input to the second clock terminal CLK2, and the previous carry signal is input to the start terminal START The k stage ST (k) outputs the k-th output signal GOUT (k), which has the same waveform as the preceding carry signal and whose phase is delayed by a predetermined period.

As described above, the shift register according to the embodiment of the present invention includes the first to n-th stages ST (1) to ST (n), and the first clock terminal CLK1 is supplied with the clock signal CLK The first stage ST (1), to which the inverted clock signal CLKB is input to the second clock terminal CLK2 and the start signal VST is input to the start terminal START, To 4j. A k-th stage ST (ST) in which an inverted clock signal CLKB is input to the first clock terminal CLK1, a clock signal CLK is input to the second clock terminal CLK2, and a previous carry signal is input to the start terminal START (k) operates as described in connection with Fig. 5 and Figs. 6A to 6K. The clock signal CLK is input to the first clock terminal CLK1 and the inverted clock signal CLKB is input to the second clock terminal CLK2 and the previous carry signal is input to the start terminal START The stage ST (k) operates as described with reference to Fig.

8 is a circuit diagram showing an example of a circuit configuration of a k-th stage according to the second embodiment of the present invention. 8, a Q-node charging unit 10 for controlling charging and discharging of a Q-node Q of a k-th stage ST (k) according to the second embodiment of the present invention, a Q- A QB node charging unit 30 for controlling the charging of the QB node QB and a Q node boosting controller 40 for controlling the voltage boost of the Q node Q. The QB node discharging unit 20 controls the discharging of the QB node QB, And an output section 50 for charging the output node NO connected to the output terminal OUT according to the voltage of the Q node Q and the QB node QB at a high potential or for discharging to a low potential voltage do.

The Q-node charging unit 10, QB node discharging unit 20, Q-node boost control unit 40 and output unit 50 of the k-th stage ST (k) according to the second embodiment of the present invention The present invention can be implemented in substantially the same manner as the first embodiment of the present invention described with reference to FIG. 2, so that a description thereof will be omitted. However, the QB node charging unit 30 of the k-th stage ST (k) according to the second embodiment of the present invention is implemented differently from the first embodiment of the present invention, and will be described in detail below.

Referring to FIG. 8, the QB node charging unit 30 charges the QB node QB to the high-potential voltage VDD in response to the high-potential voltage VDD input through the high-potential voltage input terminal VDDT. To this end, the QB node charging section 30 includes a fifth TFT T5 for connecting the QB node QB to the high potential input terminal VDDT in response to the high potential voltage VDD. The fifth TFT T5 charges the QB node QB to the high-potential voltage in response to the high-potential voltage VDD. The gate electrode and the drain electrode of the fifth TFT T5 are connected to the high potential voltage input terminal VDDT and the source electrode thereof is connected to the QB node QB.

Since the k-th stage ST (k) according to the second embodiment of the present invention operates substantially the same as the k-th stage ST (k) according to the first embodiment of the present invention, A description thereof will be omitted.

9 is a block diagram schematically showing a display device according to an embodiment of the present invention. Referring to FIG. 9, a display device according to an embodiment of the present invention includes a display panel 10, a data driving circuit, a gate driving circuit, and a timing controller 11.

A display device according to an embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write digital video data to pixels by line sequential scanning have. For example, a display device according to an embodiment of the present invention may include a liquid crystal display (LCD), an organic light emitting diode (OLED), a field emission display (FED) , And an electrophoresis display (EPD). Although the present invention has been described in the following embodiments mainly on the display device being implemented as an organic light emitting diode display device, it should be noted that the display device of the present invention is not limited to the organic light emitting diode display device.

In the display panel 10, data lines and at least one group of switching signal lines are formed. One switching signal line group includes first to nth switching signal lines. In the display panel 10, a pixel array in which pixels are arranged in a matrix form is formed. Each of the pixels of the display panel 10 includes at least one of a thin film transistor, a driving TFT, an organic light emitting diode, and at least one capacitor. Each of the pixels controls an electric current flowing in the organic light emitting diode element using a switching TFT and a driving TFT to display an image. The display panel 10 may display an image in the form of bottom emission and top emission depending on the pixel structure.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive digital video data (DATA) from the timing controller 11. [ Each of the source drive ICs 12 converts the digital video data DATA into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, To the data lines of the display panel 10. The source drive ICs 12 may be connected to the data lines of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate drive circuit includes a level shifter (13) and at least one shift register (14). The level shifter 13 level-shifts the TTL (Transistor-Transistor-Logic) logic level voltage of the clock signals (CLK, CLKB) input from the timing controller 11 to the first logic level voltage and the second logic level voltage . Level shifted clocks (CLK, CLKB) are input to at least one shift register (14). The shift register 14 is connected to one switching signal line group of the display panel 10 and sequentially outputs a switching control signal. That is, the shift register 14 sequentially outputs switching control signals to the first to nth signal lines. Further, for example, when each of the pixels of the organic light emitting diode display includes the first to third switching TFTs, the gate driving circuit supplies the first switching control signal to the first switching TFT A second shift register for supplying a second switching control signal to the second switching signal line group for controlling the second switching TFT, and a third shift register for controlling the third switching TFT, And a third shift register for supplying a control signal to the third switching signal line group.

The shift register 14 according to the embodiment of the present invention sequentially outputs the switching control signals having the same waveform as the start signal by using the two clock signals so that only the waveform of the start signal input to each of the plurality of shift registers is different The plurality of shift registers can output a plurality of switching control signals of different waveforms. As a result, since the circuit design area of the shift register can be greatly reduced, the bezel area of the display device can be reduced.

The shift register 14 is formed directly on the lower substrate of the display panel 10 by a GIP (Gate Drive-IC In Panel) method. In the GIP scheme, the level shifter 13 is mounted on a printed circuit board 15. The shift register 14 has already been described in detail with reference to Figs. 1 to 7.

The timing controller 11 receives digital video data (DATA) from an external host system through an interface such as an LVDS (Low Voltage Differential Signaling) interface and a TMDS (Transition Minimized Differential Signaling) interface. The timing controller 11 transmits the digital video data (DATA) input from the host system to the source drive ICs 12. The timing controller 11 receives a timing signal such as a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, and a main clock from the host system through the LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage VST and clock signals CLK and CLKB. The start voltage VST is input to the shift register 14 to control the shift start timing of the shift register 14. The clock signals CLK and CLKB are input to the level shifter 13 and level-shifted, and then input to the shift register 14 to control each of the stages of the shift register 14.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a polarity control signal, and a source output enable signal. The source start pulse controls the shift start timing of the source drive ICs 12. [ The source sampling clock is a clock signal that controls the sampling timing of data within the source drive ICs 12 based on the rising or falling edge. The polarity control signals control the polarity of the data voltages output from the source drive ICs 12. [ If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the shift register of the present invention sequentially outputs signals having the same waveform as the start signal using two clock signals. As a result, in the present invention, when only the waveform of the start signal input to each of the plurality of shift registers is made different, the plurality of shift registers can output a plurality of switching control signals of different waveforms. As a result, the present invention can greatly reduce the circuit design area, thereby reducing the bezel area of the display device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board
10: Q node voltage charging part 20: QB node voltage discharging part
30: QB node voltage charging unit 40: Q node boost control unit
50: Output section

Claims (20)

And a plurality of stages that sequentially generate outputs,
Each of the stages includes:
A start terminal to which a start signal or a previous carry signal is input;
A first clock terminal and a second clock terminal receiving a clock signal and an inverted clock signal inverting the clock signal;
An output terminal for outputting the start signal inputted to the start terminal or a signal having the same waveform as the previous carry signal;
A Q node charging unit charging / discharging the Q node with the start signal or the front carry signal input through the start terminal in response to the clock signal or the inverted clock signal input through the first clock terminal;
A QB node discharging unit discharging the QB node to a low potential voltage in response to the clock signal input through the first clock terminal or the inverted clock signal and the start signal input through the start terminal or the front carry signal;
A QB node charging unit charging the QB node with a high potential voltage; And
And an output unit for outputting the high potential voltage to the output terminal in response to the voltage of the Q node and outputting the low potential voltage to the output terminal in response to the voltage of the QB node. delete The method according to claim 1,
The Q node charge /
And a first TFT for connecting the Q node to the start terminal in response to a first logic level voltage of the clock signal or the inverted clock signal. The method of claim 3,
The QB node discharger includes:
A second TFT for connecting a first node to the start terminal in response to the clock signal or the first logic level voltage of the inverted clock signal; And
And a third TFT for discharging the QB node to the low potential voltage in response to a first logic level voltage of the first node. 5. The method of claim 4,
The QB node discharger includes:
And a fourth TFT for discharging the QB node to the low potential voltage in response to a first logic level voltage of the Q node. 6. The method of claim 5,
The QB node charging unit,
And a fifth TFT for supplying the high potential voltage to the QB node in response to the high potential voltage. 6. The method of claim 5,
The QB node charging unit,
A fifth TFT for supplying the high potential voltage to a second node in response to the high potential voltage;
A sixth TFT for charging the QB node to the high potential voltage in response to a high potential voltage of the second node; And
And a seventh TFT for discharging the second node to the low potential voltage in response to the first logic level voltage of the Q node. 8. The method of claim 7,
The output unit includes:
A pull-up TFT which charges an output node connected to the output terminal in response to a first logic level voltage of the Q node to the high potential voltage; And
And a pull-down TFT for discharging the output node to the low potential voltage in response to a high potential voltage of the QB node. 9. The method of claim 8,
The output unit includes:
And a first capacitor connected between the Q node and the output node. The method according to claim 1,
Each of the stages includes:
The third node is charged with the first logic level voltage in response to the voltage of the clock signal or the inverted clock signal input through the second clock terminal and the Q node of the subsequent stage input through the Q input terminal of the subsequent stage And a Q-node boost controller for discharging the third node to the low-potential voltage in response to a voltage of a QB node of the rear stage inputted through a rear-stage QB node voltage input terminal. 11. The method of claim 10,
Wherein the Q-node boost controller comprises:
An eighth TFT for connecting the third node to the second clock terminal in response to a first logic level voltage of the clock signal or the inverted clock signal and a first logic level voltage of a Q node of the subsequent stage, ;
A tenth TFT for discharging the third node to the low potential voltage in response to a high potential voltage of a QB node of the subsequent stage; And
And a second capacitor connected between the Q node and the third node. 11. The method of claim 10,
When the clock signal is input to the first clock terminal, the inverted clock signal is input to the second clock terminal,
Wherein when the inverted clock signal is input to the first clock terminal, the clock signal is input to the second clock terminal. 11. The method of claim 10,
When the clock signal is input to the first clock terminal of the k stage (1? K? N, k is a natural number of 2 or more and n is the number of stages) and the inverted clock signal is input to the second clock terminal, Wherein the inverted clock signal is input to the first clock terminal of the (k + 1) th stage and the clock signal is input to the second clock terminal. The method according to claim 1,
Wherein the output terminal outputs a signal having the same phase as the start signal when the start signal is input to the start terminal of the k stage (1? K? N, k is a natural number of 2 or more and n is the number of stages)
Wherein the output terminal outputs a signal whose phase is delayed from that of the previous carry signal when the previous carry signal is input to the start terminal of the k-th stage. A display panel including data lines and at least one switching signal line group;
A data driving circuit for converting input digital video data into analog data voltages and supplying the analog data voltages to the data lines; And
And a gate driving circuit including at least one shift register for sequentially outputting a switching control signal to the at least one switching signal line group,
Wherein the shift register comprises a plurality of stages that sequentially generate outputs,
Each of the stages
A start terminal to which a start signal or a previous carry signal is input;
A first clock terminal and a second clock terminal receiving a clock signal and an inverted clock signal inverting the clock signal;
An output terminal for outputting the start signal inputted to the start terminal or a signal having the same waveform as the previous carry signal;
A Q node charging unit charging / discharging the Q node with the start signal or the front carry signal input through the start terminal in response to the clock signal or the inverted clock signal input through the first clock terminal;
A QB node discharging unit discharging the QB node to a low potential voltage in response to the clock signal input through the first clock terminal or the inverted clock signal and the start signal input through the start terminal or the front carry signal;
A QB node charging unit charging the QB node with a high potential voltage; And
And an output unit for outputting the high potential voltage to the output terminal in response to the voltage of the Q node and outputting the low potential voltage to the output terminal in response to the voltage of the QB node. 16. The method of claim 15,
Each of the stages includes:
The third node is charged with the first logic level voltage in response to the voltage of the clock signal or the inverted clock signal input through the second clock terminal and the Q node of the subsequent stage input through the Q input terminal of the subsequent stage And a Q node boost controller for discharging the third node to the low potential voltage in response to a voltage of a QB node of the rear stage inputted through a rear stage QB node voltage input terminal.
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