KR101232171B1 - A shift register - Google Patents

Abstract

The present invention relates to a shift register capable of preventing multiple outputs due to a coupling phenomenon, comprising a plurality of stages for outputting output pulses in turn; Each stage includes: a charging switching element for supplying a charging voltage source to the node in response to a start pulse from an outside or an output pulse from a front end stage; A discharge switching element for supplying a discharge voltage source to the node in response to the start pulse or an output pulse from a next stage; A first pull-up switching element controlled according to the voltage source supplied to the node and outputting an output pulse; And at least two noise removing switching elements operating in different periods and shorting an output terminal between the node and the charging switching element during operation.

LCD, Shift Register, Stage, Coupling

Description

A shift register

1 is a view showing a circuit configuration provided in a conventional stage

2 illustrates a shift register according to a first embodiment of the present invention.

3A and 3B illustrate timing diagrams of various signals supplied to the shift register of FIG. 2 and output pulses output from the shift register.

4 is a diagram for comparing and comparing A and P clock pulses.

5 is a diagram illustrating a circuit configuration of the third stage of FIG. 2.

FIG. 6 shows the first to third stages having the circuit configuration of FIG.

7 illustrates a shift register according to a second embodiment of the present invention.

8A and 8B illustrate timing diagrams of various signals supplied to the shift register of FIG. 7 and output pulses output from the shift register.

FIG. 9 is a diagram illustrating a circuit configuration of the third stage of FIG. 7.

10 is a view showing first to third stages having the circuit configuration of FIG.

* Explanation of symbols on the main parts of the drawings

ST: Stage clk: Clock Pulse

Aclk: A clock pulse Bclk: B clock pulse

VDD: Voltage source for charging VSS: Voltage source for discharge

Vst: Start pulse Vout: Output pulse

STn + 1: dummy stage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of preventing multiple outputs due to coupling phenomenon.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by an output pulse applied to the gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for controlling the gate driver and the data driver, and a liquid crystal display. It is provided with a power supply for supplying various drive voltages used in the device.

The timing controller controls the driving timings of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or decompresses input power to generate driving voltages such as a common voltage, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display. The gate driver sequentially supplies output pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever an output pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the output pulses as described above.

Conventional shift registers are composed of a plurality of stages connected dependently to each other. Here, each stage outputs one output pulse. These output pulses are sequentially supplied to the gate lines of the liquid crystal panel (not shown) to sequentially scan the gate lines.

1 is a view showing a circuit configuration provided in a conventional stage.

Each stage includes a node control unit 101 for controlling the charging and discharging states of the first node n1 and the second node n2, and an output pulse Vout according to the signal state of the first node n1. And a pull-down switching device Trdw for outputting a discharge voltage source VSS in accordance with the signal state of the second node n2.

Here, the first node n1 and the second node n2 are alternately charged and discharged. Specifically, when the first node n1 is charged, the second node n2 is discharged. The first node n1 is discharged when the second node n2 is in a charged state.

At this time, an output pulse Vout is output from the pull-up switching device Trup when the first node n1 is in a charged state, and a pull-down switching device of the output unit when the second node n2 is in a charged state. The discharge voltage source VSS is output from Trdw.

The output pulse Vout output from the pull-up switching device Trup and the discharge voltage source VSS output from the pull-down switching device Trdw are supplied to the corresponding gate line.

Here, the gate terminal of the pull-up switching device Trup is connected to the first node n1, the drain terminal is connected to a clock transmission line to which a clock pulse clk is applied, and the source terminal is connected to the gate line. do. The clock pulse clk has a high state and a low state periodically and is supplied to the drain terminal of the pull-up switching device Trup. In this case, the pull-up switching device Trup outputs any one of the clock pulses clk in the high state input every cycle. The clock pulse clk output at this particular time point is an output pulse Vout for driving the gate line.

This specific time point means a time point after the first node n1 is charged. That is, the pull-up switching device Trup is at the specific time point (ie, the time point at which the first node n1 is charged) among the clock pulses clk that are continuously input to its drain terminal periodically. The input high clock pulse clk is output as an output pulse Vout. After the output of the output pulse Vout, the first node n1 is maintained in a discharge state until the next frame period starts, so that the pull-up switching device Trup outputs one output pulse Vout per frame. Will print). However, since the clock pulse clk is output several times in one frame period, the clock pulse even when the pull-up switching device Trup is turned off, that is, even when the first node n1 is discharged. Clk is continuously input to the drain terminal of the pull-up switching element Trup.

In other words, the pull-up switching device Trup is turned on only once for one frame, and outputs the clock pulse clk input to its drain terminal as an output pulse Vout during this turn-on period. .

Thereafter, the pull-up switching device Trup is turned off until the start of the next frame period, so that the pull-up switching device Trup is clock pulse clk at its drain terminal no matter how long it is turned off. ) Can not be output as output pulse (Vout). However, as the clock pulse clk is periodically applied to the drain terminal of the pull-up switching device Trup, the first node n1 and the pull-up connected to the gate terminal of the pull-up switching device Trup are connected. Coupling phenomenon occurs between the drain terminals of the switching element Trup. Due to such a coupling phenomenon, the first node n1 is continuously charged with a predetermined voltage corresponding to the clock pulse clk.

Then, the first node n1 may be maintained in a charged state at any moment. That is, the first node n1 may be maintained in a charged state at an unwanted timing. In this case, the first node n1 may be maintained in the charging state more than once in one frame period, whereby the pull-up switching device Trup may be turned on more than once in one frame period. As a result, a multi-output phenomenon in which one stage outputs two or more output pulses Vout during one frame period may occur due to the above coupling phenomenon.

As such, when one stage outputs two or more output pulses Vout during one frame period, the quality of an image displayed on the liquid crystal panel is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a shift register capable of preventing multiple outputs by including a switching device for noise removal capable of periodically discharging a node.

The shift register according to the present invention for achieving the above object comprises a plurality of stages in order to output an output pulse; Each stage includes: a charging switching element for supplying a charging voltage source to the node in response to a start pulse from an outside or an output pulse from a front end stage; A discharge switching element for supplying a discharge voltage source to the node in response to an output pulse from a next stage; A first pull-up switching element controlled according to the voltage source supplied to the node and outputting an output pulse; And at least two noise removing switching elements operating in different periods and shorting an output terminal between the node and the charging switching element during operation.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to a first embodiment of the present invention, and FIGS. 3A and 3B are diagrams illustrating timing signals of various signals supplied to the shift register of FIG. 2 and output pulses output from the shift register. to be.

As shown in FIG. 2, the shift register according to the first embodiment of the present invention includes n stages ST1 to STn and a dummy stage STn + 1 connected to each other.

Here, the stages ST1 to STn and the dummy stage STn + 1 sequentially output output pulses Vout1 to Voutn + 1 for one frame period. That is, output pulses Vout1 to Voutn + 1 are sequentially output from the first stage ST1 to the dummy stage STn + 1.

Here, output pulses Vout1 to Voutn output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

The output pulse Voutn + 1 output from the dummy stage STn + 1 is not applied to the gate line but is supplied only to the nth stage STn. That is, the n + 1th output pulse Voutn + 1 output from the dummy stage STn + 1 is a signal for disabling the nth stage STn.

Each stage ST1 to ST201n + 1 includes a charging voltage source VDD, a discharge voltage source VSS, a first clock pulse clk1, a second clock pulse clk2, a first A clock pulse Aclk1, 2 A clock pulse Aclk2, a first B clock pulse Bclk1, and a second B clock pulse Bclk2 are supplied.

In addition to the above-described signals, the first stage ST1 is further supplied with a start pulse Vst.

The charging voltage source VDD and the discharge voltage source VSS are voltage sources having different sizes, and the charging voltage source VDD has a larger voltage size than the discharge voltage source VSS.

In general, the charging voltage source VDD represents a positive polarity, and the discharge voltage source VSS represents a negative polarity. In addition, the discharge voltage source VSS may be a ground voltage.

The first and second clock pulses clk1 and clk2 are output with phase differences from each other. That is, the second clock pulse clk2 is output by being delayed by one pulse width than the first clock pulse clk1.

The start pulse Vst may be output in synchronization with the second clock pulse clk4. The first and second clock pulses clk1 and clk2 are output several times during one frame period, but the start pulse Vst is output only once during one frame period.

Specifically, the one frame period includes an initial period during which the start pulse Vst is output, and a first through n + 1 period during which the first to dummy stages output an output pulse. Each of the clock pulses clk1 to clk4 periodically shows a high state (high state) for a plurality of periods of one frame period, but the start pulse Vst is high only for one period of one frame period, that is, the initial period. Stays in the state.

The A clock pulses Aclk1 and Aclk2 and the B clock pulses Bclk1 and Bclk2 are alternately outputted with at least one frame period.

That is, in the first frame period as shown in FIG. 3A, the A clock pulses Aclk1 and Aclk2 periodically show a high state, and the B clock pulses Bclk1 and Bclk2 remain low. In the second frame period as shown in FIG. 3B, the B clock pulses Bclk1 and Bclk2 periodically show a high state, and the A clock pulses Aclk1 and Aclk2 remain low.

4 is a view for comparing and comparing the A clock pulse and the B clock pulse.

That is, as shown in FIG. 4, the A clock pulses Aclk1 and Aclk2 are periodically maintained in a high state and a low state during the odd frame period Fm, and during the even-numbered frame period Fm + 1. It remains low.

On the other hand, the B clock pulses Bclk1 and Bclk2 are kept low during the odd frame period Fm and periodically maintained high and low during the even-numbered frame period Fm + 1.

Further, if the A clock pulses Aclk1 and Aclk2 are periodically held high and low for a plurality of consecutive first frame periods, and remain low for a plurality of consecutive second frame periods, the B The clock pulses Bclk1 and Bclk2 remain low for a plurality of first frame periods, and are periodically held high and low for the plurality of second frame periods.

Meanwhile, the A clock pulses Aclk1 and Aclk2 include a first A clock pulse Aclk1 and a second A clock pulse Aclk2 having a phase difference from each other. The first A clock pulse Aclk1 is a signal synchronized with the first clock pulse clk1, and the second A clock pulse Aclk2 is a signal synchronized with the second clock pulse clk2.

That is, as shown in FIG. 3A, the waveform of the first A clock pulse Aclk1 is the first clock pulse clk1 during the period in which the first A clock pulse Aclk1 is periodically maintained high and low. Is the same as the waveform. The waveform of the second A clock pulse Aclk2 is the same as the waveform of the second clock pulse clk2 during the period in which the second A clock pulse Aclk2 is periodically maintained high and low.

Each stage ST1 to STn + 1 is enabled in response to an output pulse from the preceding stage. This enabled stage outputs the clock pulse (clk1 or clk2) supplied to it as an output pulse.

That is, the k-th stage paper is enabled in response to the k-th output pulse from the k-th stage.

Each stage ST1 to STn is disabled in response to an output pulse from the next stage. The disabled stage discharges the gate line by supplying a discharge voltage source VSS to the corresponding gate line.

That is, the kth stage paper is disabled in response to the k + 1th output pulse from the k + 1th stage.

However, since the stage does not exist in front of the uppermost first stage ST1, the first stage ST1 is enabled by receiving the start pulse Vst from the level shifter controlled by the timing controller. .

In addition, since there is no stage behind the dummy stage STn + 1, the dummy stage STn + 1 is disabled by receiving the start pulse Vst.

Here, a circuit configuration of each stage ST1 to STn + 1 will be described.

FIG. 5 is a diagram illustrating a circuit configuration of the third stage of FIG. 2.

Each stage ST1 to STn + 1 includes a node n, a charging switching element Trc, a discharge switching element Trd, a pull-up switching element Trup, a first pull-down switching element Trdw1, and a second pull-down. A switching element Trdw2, a first noise preventing switching element Trn1, and a second noise removing preventing switching element Trn2.

The charging switching element Trc provided in the k-th stage supplies the charging voltage source VDD to the node n of the k-th stage in response to the k-1 output pulse from the k-1st stage. To this end, the gate terminal of the charging switching element (Trc) provided in the k-th stage is connected to the output terminal of the k-1st stage, the drain terminal is connected to the power line for transmitting the charging voltage source (VDD) And the source terminal is connected to the node n of the kth stage.

For example, the charging switching device Trc included in the third stage ST3 of FIG. 5 may respond to the charging voltage source VDD in response to the second output pulse Vout2 from the second stage ST2. It supplies to the node n of 3rd stage ST3.

The discharge switching element Trd included in the k-th stage supplies the discharge voltage source VSS to the node n of the k-th stage in response to the k + 1th output pulse from the k + 1th stage. For this purpose, the gate terminal of the discharge switching element Trd provided in the kth stage is connected to the output terminal of the k + 1th stage, the drain terminal is connected to the node n of the kth stage, and The source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the discharge switching element Trd included in the third stage ST3 of FIG. 5 may generate the discharge voltage source VSS in response to the fourth output pulse Vout4 from the fourth stage ST4. It supplies to the node n of 3rd stage ST3.

The pull-up switching device Trup included in the k-th stage outputs a clock pulse as an output pulse in response to the charging voltage source VDD supplied to the node n of the k-th stage, and outputs the output pulse k. Supply to the gate line, the k-th stage, and the k + 1th stage.

To this end, the gate terminal of the pull-up switching element provided in the k-th stage is connected to the node n of the k-th stage, the drain terminal is connected to the clock transmission line for transmitting the clock pulse, and the source terminal It is connected to the k-th gate line, the input terminal of the k-1st stage, and the input terminal of the k + 1th stage.

For example, the pull-up switching device provided in the third stage ST3 of FIG. 5 is supplied to itself in response to the charging voltage source VDD supplied to the node n of the third stage ST3. One clock pulse is output as the third output pulse Vout3, and the third output pulse Vout3 is supplied to the first gate line, the second stage ST2, and the fourth stage ST4.

The first pull-down switching device Trdw1 included in the k-th stage supplies the discharge voltage source VSS to the k-th gate line in response to the A clock pulse Aclk1 or Aclk2. The A clock pulse Aclk1 or Aclk2 supplied to the first pull-down switching device Trdw1 is a clock pulse having the same phase as the clock pulse supplied to the pull-up switching device Trup provided in the k + 1 stage. To this end, the gate terminal of the first pull-down switching device Trdw1 provided in the k-th stage is connected to a clock transmission line for transmitting the A clock pulse Aclk1 or Aclk2, and the drain terminal is connected to the k-th gate line. The source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the first pull-down switching element Trdw1 included in the third stage ST3 of FIG. 5 supplies the discharge voltage source VSS to the third gate line in response to the second A clock pulse Aclk2. do.

The second pull-down switching device Trdw2 provided in the k-th stage supplies the discharge voltage source VSS to the k-th gate line in response to the B clock pulse Bclk1 or Bclk2. The B clock pulse Bclk1 or Bclk2 supplied to the second pull-down switching device Trdw2 is a clock pulse having the same phase as the clock pulse supplied to the pull-up switching device Trup provided in the k + 1th stage. To this end, a gate terminal of the second pull-down switching device Trdw2 provided in the k-th stage is connected to a clock transmission line for transmitting the B clock pulse Bclk1 or Bclk2, and a drain terminal of the second pull-down switching device Trdw2 is connected to the k-th gate line. The source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the second pull-down switching device Trdw2 included in the third stage ST3 of FIG. 5 supplies the discharge voltage source VSS to the third gate line in response to the second B clock pulse Bclk2. .

The first noise removing switching element Trn1 included in the k-th stage is an output terminal (source terminal) of the node n of the k-th stage and the pull-up switching element Trup in response to the A clock pulse Aclk1 or Aclk2. Short circuit between To this end, the gate terminal of the first noise removing switching element Trn1 provided in the k-th stage is connected to a clock transmission line for transmitting the A clock pulse Aclk1 or Aclk2, and the drain terminal of the k-th stage Is connected to the node n, and the source terminal is connected to the source terminal of the pull-up switching device Trup provided in the k-th stage.

For example, the first noise removing switching element Trn1 included in the third stage ST3 of FIG. 5 may correspond to the node n of the third stage ST3 in response to the first A clock pulse Aclk1. The output terminal (source terminal) of the pull-up switching device Trup included in the third stage ST3 is short-circuited.

The second noise removing switching element Trn2 provided in the k-th stage is an output terminal (source terminal) of the node n of the k-th stage and the pull-up switching element Trup in response to the B clock pulse Bclk1 or Bclk2. Short circuit between To this end, the gate terminal of the second noise removing switching element Trn2 provided in the kth stage is connected to a clock transmission line for transmitting the B clock pulse Bclk1 or Bclk2, and the drain terminal of the kth stage. Is connected to the node n, and the source terminal is connected to the source terminal of the pull-up switching device Trup provided in the k-th stage.

For example, the first noise removing switching element Trn1 included in the third stage ST3 of FIG. 5 may correspond to the node n of the third stage ST3 in response to the first B clock pulse Bclk1. The output terminal (source terminal) of the pull-up switching device Trup included in the third stage ST3 is short-circuited.

As described above, the operation of the shift register having the circuit configuration will be described in detail.

FIG. 6 is a diagram illustrating first to third stages having the circuit configuration of FIG. 5.

First, the operation during the initial period T0 in the first frame period will be described.

Here, as shown in FIG. 3A, the A clock pulses Aclk1 and Aclk2 periodically show high and low states during the first frame period, and the B clock pulses Bclk1 and Bclk2 remain low. 3B, the B clock pulses Bclk1 and Bclk2 periodically show high and low states during the second frame period, and the A clock pulses Aclk1 and Aclk2 remain low. Each frame period includes the initial period T0 to the i th period (i is a natural number).

Accordingly, the second noise removing switching element Trn2 receives the first B clock pulse Bclk1 through the gate terminal and the second B clock pulse Bclk2 through the gate terminal during the first frame period. The second pull-down switching device Trdw2 remains turned off for the first frame period.

During the initial period T0, only the start pulse Vst remains high and the remaining clock pulses clk1, clk2, Aclk1, Aclk2, Bclk1, and Bclk2 remain low, as shown in FIG. do.

The start pulse Vst is input to the first stage ST1. Specifically, as shown in FIG. 6, the start pulse Vst is supplied to the gate terminal of the charging switching element Trc provided in the first stage ST1.

Then, the charging switching device Trc of the first stage ST1 is turned on.

The charging voltage source VDD is supplied to the node n of the first stage ST1 through the turned-on charging switching element Trc. Accordingly, the node n of the first stage ST1 is charged by the charging voltage source VDD, and the pull-up switching device Trup having a gate terminal connected to the charged node n is turned on. -On.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 3A, only the first clock pulse clk1 and the first A clock pulse Aclk1 are kept high and the remaining clock pulses including the start pulse Vst. The fields clk2, Aclk2, Bclk1, and Bclk2 remain low.

Therefore, the charging switching element Trc of the first stage ST1 is turned off in response to the start pulse Vst in the low state.

At this time, as the charging switching device Trc is turned off, the node n of the first stage ST1 is maintained in a floating state.

 As the node n of the first stage ST1 is kept charged by the charging voltage source VDD applied during the initial period T0, a gate terminal connected to the node n is connected. The pull-up switching device Trup of the first stage ST1 is turned on.

In this case, the first clock pulse clk1 is supplied to the drain terminal of the turned-on pull-up switching device Trup. Then, the charging voltage source VDD charged in the node n of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping). This amplification occurs because the node n is in a floating state.

Therefore, the first clock pulse clk1 supplied to the drain terminal of the pull-up switching device Trup included in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trup. The first clock pulse clk1 output from the pull-up switching device Trup is the first output pulse Vout1.

On the other hand, the first A clock pulse Aclk1 output in the first period T1 is supplied to the gate terminal of the first noise removing switching element Trn1 provided in the first stage ST1. Then, the first noise removing switching element Trn1 is turned on, and thus, a short circuit between the node n of the first stage ST1 and the source terminal of the pull-up switching element Trup.

In the first period T1, since the first output pulse Vout1 having a high state is output from the pull-up switching device Trup, the node n of the first stage ST1 and the pull-up switching device Trup. ), Both the drain terminal and the source terminal are kept high.

The first noise removing switching element Trn1 has no influence on the output of the pull-up switching element Trup when the node n is in a charged state. However, the first noise removing switching element Trn1 periodically supplies the discharge voltage source VSS to the node n when the node n is floated in the discharge state, thereby providing It stabilizes the signal state. This will be described in more detail later.

Meanwhile, the first output pulse Vout1 output from the first stage ST1 is supplied to the first gate line and serves as a scan pulse for driving the first gate line.

In addition, the first output pulse Vout1 output from the first stage ST1 in the first period T1 is supplied to the second stage ST2 to provide the node n of the second stage ST2. It acts as a start pulse to charge.

Accordingly, the second stage ST2 is enabled in the same manner as the first stage ST1 is enabled during the above-described initial period T0.

That is, the first output pulse Vout1 output from the first stage ST1 in the first period T1 is supplied to the gate terminal of the charging switching element Trc provided in the second stage ST2. . Accordingly, the node n of the second stage ST2 is charged in the first period T1, and the pull-up switching device Trup connected to the charged node n is turned on.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3A, only the second clock pulse clk2 and the second A clock pulse Aclk2 remain high. On the other hand, the clock pulses clk1, Aclk1, Bclk1, and Bclk2 including the start pulse Vst and the first output pulse Vout1 remain low.

Therefore, the charging switching element Trc of the second stage ST2 is turned off in response to the first output pulse Vout1 in the low state.

At this time, as the charging switching device Trc is turned off, the node n of the second stage ST2 is maintained in a floating state.

 As the node n of the second stage ST2 is kept charged by the charging voltage source VDD which has been applied during the first period T1, a gate terminal is connected to the node n. The pull-up switching device Trup of the second stage ST2 is turned on.

At this time, the second clock pulse clk2 is supplied to the drain terminal of the turned-on pull-up switching device Trup. Then, the charging voltage source VDD charged in the node n of the second stage ST2 is amplified.

Therefore, the second clock pulse clk2 supplied to the drain terminal of the pull-up switching device Trup included in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trup. The second clock pulse clk2 output from the pull-up switching device Trup is the second output pulse Vout2.

The output second output pulse Vout2 is supplied to the second gate line and serves as a scan pulse for driving the second gate line.

In addition, the second output pulse Vout2 output from the second stage ST2 is supplied to the third stage ST3 to enable the third stage ST3 in the manner described above.

In addition, the second output pulse Vout2 output from the second stage ST2 is supplied to the first stage ST1 to discharge the first node n of the first stage ST1. That is, the first stage ST1 is disabled in response to the second output pulse Vout2 from the second stage ST2. If this is explained in more detail as follows.

That is, the second output pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the discharge switching element Trd provided in the first stage ST1. do.

Then, the discharge switching element Trd is turned on, and at this time, the discharge voltage source VSS is connected to the node n of the first stage ST1 through the turned-on discharge switching element Trd. Supplied. Then, the node n is discharged, and the pull-up switching device Trup having the gate terminal connected to the node n of the discharged first stage ST1 is turned off.

The second A clock pulse Aclk2 is supplied to the gate terminal of the first pull-down switching device Trdw1 provided in the first stage ST1. Accordingly, the first pull-down switching device Trdw1 is turned on. Then, the discharge voltage source VSS is supplied to the first gate line through the turned-on first pull-down switching device Trdw1. As a result, the first gate line is discharged.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 3A, only the first clock pulse clk1 and the first A clock pulse Aclk1 remain high. The remaining clock pulses clk2, Aclk2, Bclk1, and Bclk2 including the start pulse Vst and the first and second output pulses Vout1 and Vout2 remain low.

The enabled third stage ST3 receives the first clock pulse clk1 to output a third output pulse Vout3, and outputs the third output pulse Vout3 to a third gate line and a second stage. It supplies to ST2 and 4th stage ST4.

Meanwhile, the first clock pulse clk1 and the first A clock pulse Aclk1 output in the third period T3 are also supplied to the first stage ST1.

That is, the first clock pulse clk1 is supplied to the drain terminal of the pull-up switching device Trup provided in the first stage ST1, and the first A clock pulse Aclk1 is the first noise removing switching device. It is supplied to the gate terminal of (Trn1).

In this third period T3, the node n of the first stage ST1 is in a discharge state, and thus the pull-up switching device Trup is in a turn-off state. Therefore, in the third period T3, the pull-up switching device Trup of the first stage ST1 does not generate an output.

On the other hand, the first noise removing switching element Trn1 is turned on by the first A clock pulse clk1. Then, the discharge voltage source VSS of the first gate line is supplied to the node n of the first stage ST1 through the turned-on first noise removing switching element Trn1.

The voltage source VSS for discharge generated by the first pull-down switching device Trdw1 of the first stage ST1 is periodically supplied to the first gate line.

The first pull-down switching device Trdw1 of the first stage ST1 is periodically turned on from the second period T2 until the end of one frame period including this period. This is because the second A clock pulse Aclk2 is periodically supplied to the gate terminal of the first pull-down switching device Trdw1.

Accordingly, the discharge voltage source VSS is supplied to the first gate line whenever the second A clock pulse Ac2 is in a high state after the second period T2.

Meanwhile, the first noise removing switching element Trn1 of the first stage ST1 is periodically turned on every time the first A clock pulse Aclk1 is output, and the turned-on first noise removing element Trn1 is periodically turned on. The discharge voltage source VSS from the first gate line is periodically supplied to the node n of the first stage ST1 through the switching element Trn1.

Therefore, after the first stage ST1 outputs the first output pulse Vout1, the node n of the first stage ST1 is stably maintained in the discharge state.

As a result, even if the first clock pulse clk1 is supplied to the drain terminal of the pull-up switching device Trup after the output period of the first stage ST1, the node n is charged by the coupling phenomenon. You can prevent it.

In the next second frame period, as shown in FIG. 3B, the B clock pulses Bclk1 and Bclk2 periodically show high and low states, and the A clock pulses Aclk1 and Aclk2 remain low. Therefore, the first noise canceling switching device Trn1 receiving the first A clock pulse Aclk1 and the first pull-down switching device Trdw1 receiving the second A clock pulse Aclk2 during the second frame period. ) Is turned off during the first frame period.

On the other hand, the second noise removing switching element Trn2 receiving the first B clock pulse Bclk1 and the second pull-down switching element Trdw2 receiving the second B clock pulse Bclk2 during the second frame period. Is periodically turned on during the first frame period.

As described above, the first pull-down switching device Trdw1 and the first noise removing switching device Trn1 operate in the odd frame period, and the second pull-down switching device Trdw2 and the second noise removing switching device operate. (Trn2) does not work. That is, during the odd frame period, the second pull-down switching device Trdw2 and the second noise removing switching device Trn2 have a dormant state.

On the other hand, the second pull-down switching device Trdw2 and the second noise removing switching device Trn2 operate in the even-numbered frame period, and the first pull-down switching device Trdw1 and the first noise removing switching device Trn1 operate. ) Does not work. In other words, the first pull-down switching device Trdw1 and the first noise removing switching device Trn1 have a dormant state during the even-numbered frame period.

Therefore, deterioration of each of the pull-down switching devices Trdw1 and Trdw2 and the noise removing switching devices Trn1 and Trn2 can be prevented.

Hereinafter, the shift register according to the second embodiment of the present invention will be described.

7 is a diagram illustrating a shift register according to a second embodiment of the present invention, and FIGS. 8A and 8B are diagrams illustrating timing signals of various signals supplied to the shift register of FIG. 7 and output pulses output from the shift register. to be.

As illustrated in FIG. 7, the shift register according to the second embodiment of the present invention includes n stages ST1 to STn and dummy stages STn + 1 connected to each other.

Since the connection relationship between the stages ST1 to STn + 1 is the same as that of the stages of the first embodiment described above, description thereof will be omitted.

Each stage ST1 to STn + 1 includes a charging voltage source VDD, a discharge voltage source VSS, a first A clock pulse Aclk1, a second A clock pulse Aclk2, and a first B clock pulse Bclk1. The second B clock pulse Bclk2 is supplied.

In addition to the above-described signals, the first stage ST1 is further supplied with a start pulse Vst.

Each of the power supplies VDD and VSS and the clock pulses Aclk1, Aclk2, Bclk1, and Bclk2 are the same as those described above in the first embodiment, and a description thereof will be omitted.

Here, a circuit configuration of each stage ST1 to STn + 1 will be described.

9 is a diagram illustrating a circuit configuration of the third stage of FIG. 7.

Each stage includes a node n, a charging switching element Trc, a discharge switching element Trd, a first pull-up switching element Trup1, a second pull-up switching element Trup2, and a first pull-down switching element Trdw1. And a second pull-down switching element Trdw2, a first noise removing switching element Trn1, and a second noise removing switching element Trn2.

Here, the node n shown in FIG. 9, the charging switching element Trc, the discharge switching element Trd, the first pull-down switching element Trdw1, the second pull-down switching element Trdw2, and the first noise The removal switching element Trn1 and the second noise removal switching element Trn2 are the same as those in the first embodiment, and thus description thereof will be omitted.

The first and second pull-up switching devices Trup1 and Trup2 will be described below.

The first pull-up switching device Trup1 included in the k-th stage outputs the A clock pulse Aclk1 or Aclk2 as an output pulse in response to the charging voltage source VDD supplied to the node n of the k-th stage. This output pulse is supplied to the k-th gate line, the k-1st stage, and the k + 1th stage.

To this end, the gate terminal of the first pull-up switching device Trup1 provided in the kth stage is connected to the node n of the kth stage, and the drain terminal transmits the A clock pulse Aclk1 or Aclk2. The source terminal is connected to the k-th gate line, the input terminal of the k-th stage, and the input terminal of the k-th stage.

For example, in response to the charging voltage source VDD supplied to the node n of the third stage ST3, the first pull-up switching device Trup1 included in the third stage ST3 of FIG. 9 is provided. The first A clock pulse Aclk1 supplied thereto is output as the third output pulse Vout3, and the third output pulse Vout3 is output to the first gate line, the second stage ST2, and the fourth stage ( To ST4).

The second pull-up switching device Trup2 provided in the k-th stage outputs the B clock pulse Bclk1 or Bclk2 as an output pulse in response to the charging voltage source VDD supplied to the node n of the k-th stage. This output pulse is supplied to the k-th gate line, the k-1st stage, and the k + 1th stage.

To this end, the gate terminal of the second pull-up switching device Trup2 provided in the kth stage is connected to the node n of the kth stage, and the drain terminal transmits the B clock pulse Bclk1 or Bclk2. And a source terminal are connected to a k-th gate line, an input terminal of a k-1st stage, and an input terminal of a k + 1th stage.

For example, in response to the charging voltage source VDD supplied to the node n of the third stage ST3, the second pull-up switching device Trup2 provided in the third stage ST3 of FIG. 9 is provided. The first B clock pulse Bclk1 supplied to it is output as the third output pulse Vout3, and the third output pulse Vout3 is output to the first gate line, the second stage ST2, and the fourth stage ( To ST4).

As described above, the operation of the shift register having the circuit configuration will be described in detail.

FIG. 10 is a diagram illustrating first to third stages having the circuit configuration of FIG. 9.

First, the operation during the initial period T0 in the first frame period will be described.

Here, as illustrated in FIG. 8A, the A clock pulses Aclk1 and Aclk2 periodically show high and low states during the first frame period, and the B clock pulses Bclk1 and Bclk2 remain low. As shown in FIG. 8B, the B clock pulses Bclk1 and Bclk2 periodically show high and low states during the second frame period, and the A clock pulses Aclk1 and Aclk2 remain low. Each frame period includes the initial period T0 to the i th period (i is a natural number).

Accordingly, the second noise removing switching element Trn2 receives the first B clock pulse Bclk1 through the gate terminal and the second B clock pulse Bclk2 through the gate terminal during the first frame period. The second pull-down switching device Trdw2 remains turned off for the first frame period.

During the initial period T0, only the start pulse Vst remains high and the remaining clock pulses Aclk1, Aclk2, Bclk1, and Bclk2 remain low, as shown in FIG. 8A.

The start pulse Vst is input to the first stage ST1. Specifically, as shown in FIG. 10, the start pulse Vst is supplied to the gate terminal of the charging switching element Trc provided in the first stage ST1.

Then, the charging switching device Trc of the first stage ST1 is turned on.

The charging voltage source VDD is supplied to the node n of the first stage ST1 through the turned-on charging switching element Trc. Accordingly, the node n of the first stage ST1 is charged by the charging voltage source VDD, and the pull-up switching device Trup having a gate terminal connected to the charged node n is turned on. Is on.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 8A, only the first A clock pulse Aclk1 remains high and the remaining clock pulses Aclk2, Bclk1, and Bclk2 including the start pulse Vst are maintained. Remains low.

Accordingly, the charging switching element Trc of the first stage ST1 is turned off in response to the start pulse Vst in the low state.

At this time, as the charging switching device Trc is turned off, the node n of the first stage ST1 is maintained in a floating state.

 As the node n of the first stage ST1 is kept charged by the charging voltage source VDD applied during the initial period T0, a gate terminal connected to the node n is connected. The pull-up switching device Trup of the first stage ST1 is turned on.

In this case, the first A clock pulse Aclk1 is supplied to the drain terminal of the turned-on pull-up switching device Trup. Then, the charging voltage source VDD charged in the node n of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping). This amplification occurs because the node n is in a floating state.

Therefore, the first A clock pulse Aclk1 supplied to the drain terminal of the pull-up switching device Trup included in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trup. The first A clock pulse Aclk1 output from the pull-up switching device Trup is the first output pulse Vout1.

On the other hand, the first A clock pulse Aclk1 output in the first period T1 is supplied to the gate terminal of the first noise removing switching element Trn1 provided in the first stage ST1. Then, the first noise removing switching element Trn1 is turned on, and thus, a short circuit between the node n of the first stage ST1 and the source terminal of the pull-up switching element Trup.

In the first period T1, since the first output pulse Vout1 having a high state is output from the pull-up switching device Trup, the node n of the first stage ST1 and the pull-up switching device Trup. ), Both the drain terminal and the source terminal are kept high.

The first noise removing switching element Trn1 has no influence on the output of the pull-up switching element Trup when the node n is in a charged state. However, the first noise removing switching element Trn1 periodically supplies the discharge voltage source VSS to the node n when the node n is floated in the discharge state, thereby providing It stabilizes the signal state. Since this is the same as the noise removing switching element described in the first embodiment, a detailed description thereof will be omitted.

Meanwhile, the first output pulse Vout1 output from the first stage ST1 is supplied to the first gate line and serves as a scan pulse for driving the first gate line.

In addition, the first output pulse Vout1 output from the first stage ST1 in the first period T1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse to charge.

Accordingly, the second stage ST2 is enabled in the same manner as the first stage ST1 is enabled during the above-described initial period T0.

That is, the first output pulse Vout1 output from the first stage ST1 in the first period T1 is supplied to the gate terminal of the charging switching element Trc provided in the second stage ST2. . Accordingly, in the first period T1, the node n of the second stage ST2 is charged, and the pull-up switching device Trup connected to the charged node n is turned on.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 8A, only the second A clock pulse Aclk2 remains high. On the other hand, the clock pulses Aclk1, Bclk1, and Bclk2 including the start pulse Vst and the first output pulse Vout1 remain low.

Therefore, the charging switching element Trc of the second stage ST2 is turned off in response to the first output pulse Vout1 in the low state.

At this time, as the charging switching device Trc is turned off, the node n of the second stage ST2 is maintained in a floating state.

 As the node n of the second stage ST2 remains charged by the charging voltage source VDD applied during the first period T1, a gate terminal is connected to the node n. The pull-up switching device Trup of the second stage ST2 is turned on.

At this time, the second A clock pulse Aclk2 is supplied to the drain terminal of the turned-on pull-up switching device Trup. Then, the charging voltage source VDD charged in the node n of the second stage ST2 is amplified.

Therefore, the second A clock pulse Aclk2 supplied to the drain terminal of the pull-up switching device Trup included in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trup. The second A clock pulse Aclk2 output from the pull-up switching device Trup is the second output pulse Vout2.

The output second output pulse Vout2 is supplied to the second gate line and serves as a scan pulse for driving the second gate line.

In addition, the second output pulse Vout2 output from the second stage ST2 is supplied to the third stage ST3 to enable the third stage ST3 in the manner described above.

In addition, the second output pulse Vout2 output from the second stage ST2 is supplied to the first stage ST1 to discharge the node n of the first stage ST1. That is, the first stage ST1 is disabled in response to the second output pulse Vout2 from the second stage ST2. If this is explained in more detail as follows.

That is, the second output pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the discharge switching element Trd provided in the first stage ST1. do.

Then, the discharge switching element Trd is turned on, and at this time, the discharge voltage source VSS is connected to the node n of the first stage ST1 through the turned-on discharge switching element Trd. Supplied. Then, the pull-up switching device Trup having the gate terminal connected to the node n of the discharged first stage ST1 is turned off.

The second A clock pulse Aclk2 is supplied to the gate terminal of the first pull-down switching device Trdw1 provided in the first stage ST1. Accordingly, the first pull-down switching device Trdw1 is turned on. Then, the discharge voltage source VSS is supplied to the first gate line through the turned-on first pull-down switching device Trdw1. As a result, the first gate line is discharged.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in Fig. 8A, only the first A clock pulse Aclk1 remains high. The remaining clock pulses Aclk2, Bclk1, and Bclk2 including the start pulse Vst and the first and second output pulses Vout1 and Vout2 are kept low.

The enabled third stage ST3 receives the first A clock pulse Aclk1 to output a third output pulse Vout3, and outputs the third output pulse Vout3 to a third gate line and a second gate line. It supplies to stage ST2 and 4th stage ST4.

On the other hand, the first A clock pulse Aclk1 output in the third period T3 is also supplied to the first stage ST1.

That is, the first A clock pulse Aclk1 is supplied to the drain terminal of the pull-up switching device Trup provided in the first stage ST1 and the gate terminal of the first noise removing switching device Trn1.

In this third period T3, the node n of the first stage ST1 is in a discharge state, and thus the pull-up switching device Trup is in a turn-off state. Therefore, in the third period T3, the pull-up switching device Trup of the first stage ST1 does not generate an output.

On the other hand, the first noise removing switching element Trn1 is turned on by the first A clock pulse Aclk1. Then, the discharge voltage source VSS of the first gate line is supplied to the node n of the first stage ST1 through the turned-on first noise removing switching element Trn1.

The voltage source VSS for discharge generated by the first pull-down switching device Trdw1 of the first stage ST1 is periodically supplied to the first gate line.

The first pull-down switching device Trdw1 of the first stage ST1 is periodically turned on from the second period T2 until the end of one frame period including this period. This is because the second A clock pulse Aclk2 is periodically supplied to the gate terminal of the first pull-down switching device Trdw1.

Accordingly, the discharge voltage source VSS is supplied to the first gate line whenever the second A clock pulse Ac2 is in a high state after the second period T2.

Meanwhile, the first noise removing switching element Trn1 of the first stage ST1 is periodically turned on every time the first A clock pulse Aclk1 is output, and the turned-on first noise removing element Trn1 is periodically turned on. The discharge voltage source VSS from the first gate line is periodically supplied to the node n of the first stage ST1 through the switching element Trn1.

Therefore, after the first stage ST1 outputs the first output pulse Vout1, the node n of the first stage ST1 is stably maintained in the discharge state.

As a result, even if the first A clock pulse Aclk1 is supplied to the drain terminal of the first pull-up switching device Trup1 after the output period of the first stage ST1, the node n is coupled by a coupling phenomenon. The charging can be prevented.

In the next second frame period, as shown in Fig. 8B, the B clock pulses Bclk1 and Bclk2 periodically show high and low states, and the A clock pulses Aclk1 and Aclk2 remain low. Therefore, the first noise canceling switching device Trn1 receiving the first A clock pulse Aclk1 and the first pull-down switching device Trdw1 receiving the second A clock pulse Aclk2 during the second frame period. ) Is turned off during the first frame period.

On the other hand, the second noise removing switching element Trn2 receiving the first B clock pulse Bclk1 and the second pull-down switching element Trdw2 receiving the second B clock pulse Bclk2 during the second frame period. ) Is periodically turned on during the second frame period.

As described above, the first pull-down switching device Trdw1 and the first noise removing switching device Trn1 operate in the odd frame period, and the second pull-down switching device Trdw2 and the second noise removing switching device ( Trn2) does not work. That is, during the odd frame period, the second pull-down switching device Trdw2 and the second noise removing switching device Trn2 have a dormant state.

On the other hand, the second pull-down switching device Trdw2 and the second noise removing switching device Trn2 operate in the even-numbered frame period, and the first pull-down switching device Trdw1 and the first noise removing switching device Trn1 operate. ) Does not work. That is, the first pull-down switching device Trdw1 and the first noise canceling switching device Trn1 have a dormant state during the even-numbered frame period.

Therefore, deterioration of each of the pull-down switching devices Trdw1 and Trdw2 and the noise removing switching devices Trn1 and Trn2 can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The shift register of the present invention can prevent the generation of multiple outputs due to the coupling phenomenon by periodically supplying a discharge voltage source of the gate line to the node through the noise removing switching element.

Claims (6)

A plurality of stages which in turn output pulses; Each stage, A charging switching element for supplying a charging voltage source to the node in response to a start pulse from the outside or an output pulse from the front end stage; A discharge switching element for supplying a discharge voltage source to the node in response to an output pulse from a next stage; A first pull-up switching element controlled according to the voltage source supplied to the node and outputting an output pulse; And And at least two noise removing switching elements operating in different periods and shorting an output terminal between the node and the charging switching element during operation. The method of claim 1, The noise removing switching element, A high and low state periodically during a first period, and turned on or off according to a first clock pulse maintained in the low state for a second period, and at the turn-on, an output terminal of the node and the pull-up switching element A first noise removing switching element for shorting the trunk; And It is maintained in the low state for the first period, and is turned on or off in accordance with a second clock pulse that periodically indicates a high and low state during the second period, the turn-on of the node and the pull-up switching device And a second noise canceling switching element for shorting between output terminals. The method of claim 1, A high and low state periodically during a first period, and are turned on or off according to a first clock pulse maintained in the low state for a second period, and a discharge voltage source for turning-on And a first pull-down switching element for supplying the output terminal. The method of claim 3, wherein The pull-up switching device which is periodically turned on or off during the second period, and is turned on or turned off according to a second clock pulse maintained in the low state during the first period. And a second pull-down switching element for supplying to an output terminal of the shift register. The method of claim 1, And a second pull-up switching element controlled according to a voltage source supplied to the node, the second pull-up switching element outputting an output pulse in a period different from the output period of the first pull-up switching element. 6. The method of claim 5, The first pull-up switching element outputs a first clock pulse which is in a high state and a low state periodically for a first period, and which remains in the low state for a second period, as an output pulse; And, And the second pull-up switching element is maintained in a low state for the first period and outputs a second clock pulse which indicates a high and low state periodically during the second period as an output pulse.

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