KR20090061527A - Shift register - Google Patents

Abstract

A shift register is provided, which can prevent the threshold voltage of the switching element from increasing to one side by periodically setting up the negative bias condition and positive bias condition by the switching element. A plurality of stages successively outputs the scan pulse. Each stage comprises the node control part, the output unit, and the power selector. The node control part(NC) controls the signal state of the reset node and set note. The output unit(OP) is controlled by the signal state of the reset node and set note and outputs the scan pulse through the output terminal. According to the signal state of the set note, the power selector(777) selects one out of the high potential voltage and low level voltage and outputs the selected voltage by the power output terminal. The node control part comprises the switching element.

Description

Shift register {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register that can prevent deterioration of the switching element.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. Here, the gate driver includes a shift register to sequentially output the scan pulses as described above.

The conventional shift register includes a plurality of stages which in turn output a scan signal.

Each stage includes a plurality of switching elements for outputting the scan signal.

Several switching elements of each switching element are connected to a reset node of the stage through a gate terminal, since the reset node is maintained at a high voltage for almost 100% of one frame period. The switching elements connected to the reset node remain almost positively biased. As a result, deterioration of the switching devices connected to the reset node through the gate terminal is accelerated, thereby causing a problem that the threshold voltage of the switching devices continues to increase in either direction. Such deterioration of the switching element reduces the driving ability of the shift register, which in turn causes a poor image quality in the display device displaying an image.

The present invention has been made to solve the above problems, it is possible to prevent the degradation by switching the switching elements connected to the reset node to have a negative bias (positive bias) state and positive bias (positive bias) state periodically The purpose is to provide a shift register.

The shift register according to the present invention has the following effects.

In the present invention, the threshold voltage of the switching device is increased by periodically supplying a high potential voltage and a low potential voltage to a source terminal of the switching device connected to the reset node so that the switching device has a negative bias state and a positive bias state periodically. We can prevent increase to any Han Chinese.

The shift register according to the present invention for achieving the above object comprises a plurality of stages for sequentially outputting a scan pulse; Each stage includes: a node controller for controlling signal states of the set node and the reset node; An output unit controlled by the signal states of the set node and the reset node to output a scan pulse through an output terminal; A power selector for selecting one of a high potential voltage and a low potential voltage according to the signal state of the set node and outputting the same through a power output terminal; In addition, the node control unit is controlled by the signal state of the reset node, characterized in that it comprises a switching element connected between the set node and the power output terminal of the power selector.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages for sequentially outputting a scan pulse; Each stage includes: a node controller for controlling signal states of the set node, the first reset node, and the second reset node; An output unit controlled by signal states of the set node, the first reset node, and the second reset node to output a scan pulse through an output terminal; A power selector for selecting one of a high potential voltage and a low potential voltage according to the signal state of the set node and outputting the same through a power output terminal; The node controller may include a first switching device controlled by the signal state of the first reset node and connected between the set node and a power output terminal of the power selector.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages for sequentially outputting the scan pulse through its output terminal; Each stage includes: a node controller for controlling signal states of the set node, the first reset node, and the second reset node; An output unit controlled by the signal states of the set node, the first reset node, and the second reset node to output a scan pulse through an output terminal; The node control unit includes: a first switching element controlled by a first AC voltage supplied to the first reset node and connected between the set node and a second AC power line for transmitting a second AC voltage; A second switching element controlled by a second AC voltage supplied to said second reset node and connected between said set node and a first AC power line for transmitting said first AC voltage; The first AC voltage and the second AC voltage have opposite phases to each other.

First Example

1 is a diagram illustrating a shift register according to a first embodiment of the present invention, and FIG. 2 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 1.

The shift register according to the first embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in FIG. 1. Here, each of the stages ST1 to STn including the dummy stage STn + 1 outputs one scan pulse Vout1 to Voutn + 1 for one frame period through each output terminal, and the front end and its front end and It is supplied to the stage located at the rear stage to control its operation.

The stages ST1 to STn + 1 output scan pulses Vout1 to Voutn + 1 in order from the first stage ST1 to the dummy stage STn + 1. That is, the first stage ST1 outputs the first scan pulse Vout1, the second stage ST2 outputs the second scan pulse Vout2, and then the third stage ST3 receives the third stage. The scan pulse Vout3 is output, the n-th stage STn outputs the n-th scan pulse Voutn, and the dummy stage STn + 1 finally outputs the n + 1 scan pulse. Outputs Voutn + 1.

Scan pulses output from the stages ST1 to STn except the dummy stage STn + 1 are sequentially supplied to gate lines of a liquid crystal panel (not shown) to sequentially scan the gate lines. .

Such a shift register may be embedded in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

The entire stages ST1 to STn + 1 of the shift register configured as described above are any one of the charging voltage VDD, the discharging voltage VSS, and the clock pulses CLK1 to CLK4 circulating with sequential phase differences. Is authorized. Meanwhile, the first stage ST1 of the stages ST1 to STn + 1 is further supplied with a start pulse Vst.

The charging voltage VDD is provided from a charging power line DDL, the discharge voltage VSS is provided from a discharge power line SSL, and the first clock pulse CLK1 is a first clock. The second clock pulse CLK2 is provided from the transmission line CL1, the second clock pulse CLK2 is provided from the second clock transmission line CL2, and the third clock pulse CLK3 is provided from the third clock transmission line CL3. The fourth clock pulse CLK4 is provided from the fourth clock transmission line CL4, and the start pulse Vst is provided from the start transmission line STL.

The charging voltage VDD is used to charge the nodes of each stage ST1 to STn + 1, and the discharge voltage VSS discharges the nodes and output terminals of each stage ST1 to STn + 1. It is used to

The charging voltage VDD and the discharging voltage VSS are both DC voltages, and the charging voltage VDD has a potential higher than that of the discharging voltage VSS. For example, the charging voltage VDD may indicate positive polarity, and the discharge voltage VSS may indicate negative polarity. The discharge voltage VSS may be a ground voltage. The discharge voltage VSS is equal to the voltage value in the low state of each of the clock pulses CLK1 to CLK4.

Each of the clock pulses CLK1 to CLK4 is a signal used to generate scan pulses Vout1 to Voutn + 1 of each stage ST1 to STn + 1, and each stage ST1 to STn + 1 is a clock pulse. The scan pulses Vout1 to Voutn + 1 are generated and output by receiving any one of the CLK1 to CLK4. For example, the 4k + 1 stage outputs the scan pulse using the first clock pulse CLK1, and the 4k + 2 stage outputs the scan pulse using the second clock pulse CLK1, and the 4k + 1 stage outputs the scan pulse. The +3 stage outputs the scan pulse using the third clock pulse CLK1, and the 4k + 4 stage outputs the scan pulse using the fourth clock pulse CLK1. K is a natural number including zero.

In the present invention, an example of using four types of clock pulses having different phase differences is shown, but any number of clock pulses can be used.

The first to fourth clock pulses CLK1 to CLK4 are output with phase differences from each other. The second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse width longer than the second clock pulse CLK2. The fourth clock pulse (CLK4) is phase-delayed and output by one pulse width than the third clock pulse (CLK3), and the first clock pulse (CLK1) is output by the fourth clock pulse ( Phase delayed by CLK4) and outputted.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output in a circular manner. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse Vst may be synchronized with each other and output. As such, when the fourth clock pulse CLK4 and the start pulse Vst are synchronized with each other, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Each of the clock pulses CLK1 to CLK4 is output several times during one frame period, but the start pulse Vst is output only once during one frame period. In other words, each clock pulse CLK1 to CLK4 periodically shows several active states (high states) during one frame period, but the start pulse Vst shows only one active state during one frame period.

In order for each stage ST1 to STn + 1 to output scan pulses Vout1 to Voutn + 1, an enable operation of each stage ST1 to STn + 1 must be preceded. The stage being enabled means that the stage is set to a state capable of outputting, that is, a state capable of outputting a clock pulse supplied thereto as a scan pulse. To this end, each stage ST1 to STn + 1 is enabled by receiving scan pulses from the stage located at the front end thereof.

For example, the k th stage is enabled in response to the scan pulse from the k-1 st stage. On the other hand, since there is no stage immediately in front of the first stage ST1 located at the uppermost side, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

In addition, each stage ST1 to STn + 1 is disabled in response to the scan pulse from the next stage. When the stage is disabled, it means that the stage is reset to a state in which the output is impossible, that is, the clock pulse supplied to the stage cannot be output as a scan pulse.

For example, the kth stage is disabled in response to the scan pulse from the k + 1th stage.

Here, since the stage does not exist at the rear end of the dummy stage STn + 1 located at the bottom, the dummy stage STn + 1 is disabled in response to the start pulse Vst from the timing controller.

The configuration of each stage ST1 to STn + 1 in the shift register configured as described above will be described in more detail as follows.

3 is a diagram illustrating a configuration of an arbitrary stage shown in FIG. 1.

As illustrated in FIG. 3, each stage ST1 to STn + 1 includes a set node Q, a reset node QB, a node control unit NC, an output unit OP, and a power selection unit 777. ).

The node control unit NC controls the signal states of the set node Q and the reset node QB.

The set node Q and the reset node QB always remain opposite to each other. That is, the reset node QB is maintained in the discharge state when the set node Q is in the charged state, and the reset node QB is maintained in the charged state when the set node Q is in the discharge state. do.

The node controller NC of the k-th stage includes first to sixth switching elements Tr1 to Tr6.

The first switching element Tr1 provided in the k-th stage is controlled by the signal state of the reset node QB, and is between the set node Q and the power output terminal of the power selector 777 (444 in FIG. 5). Is connected to. In other words, the gate terminal of the first switching element Tr1 provided in the k-th stage is connected to the reset node QB, the drain terminal is connected to the set node Q, and the source terminal is connected to the power supply. It is connected to the output terminal.

The second switching element Tr2 provided in the kth stage is controlled by the scan pulse Vout (k-1) from the k-1st stage, and the reset node Q and the discharge power line SSL ) Is connected. In other words, the gate terminal of the second switching element Tr2 provided in the k-th stage is connected to the output terminal 333 of the k-th stage, and the drain terminal is connected to the reset node QB. The source terminal is connected to the discharge power supply line SSL.

However, the gate terminal of the second switching element Tr2 provided in the first stage ST1 is connected to the start transmission line STL.

The third switching device Tr3 provided in the kth stage is controlled by the scan pulse Vout (k + 1) from the k + 1th stage, and the charging power line DDL and the reset node QB ) Is connected. In other words, the gate terminal of the third switching element Tr3 provided in the kth stage is connected to the output terminal 333 of the k + 1th stage, and the drain terminal is connected to the charging power supply line DDL. And a source terminal are connected to the reset node QB.

However, the gate terminal of the third switching element Tr3 provided in the dummy stage STn + 1 is connected to the start transfer line STL.

The fourth switching device Tr4 provided in the kth stage is controlled by the scan pulse Vout (k-1) from the k-1st stage, and the charging power line DDL and the set node Q It is connected between. In other words, the gate terminal of the fourth switching device Tr4 provided in the kth stage is connected to the output terminal 333 of the k-1st stage, and the drain terminal is connected to the charging power supply line DDL. And a source terminal is connected to the set node Q.

However, the gate terminal of the fourth switching element Tr4 provided in the first stage ST1 is connected to the start transmission line STL.

The fifth switching element Tr5 provided in the k-th stage is controlled by the signal state of the set node Q, and is connected between the reset node QB and the discharge power supply line SSL. In other words, the gate terminal of the fifth switching element Tr5 provided in the k-th stage is connected to the set node Q, the drain terminal is connected to the reset node QB, and the source terminal is connected to the reset node QB. It is connected to the said discharge power supply line SSL.

The sixth switching device Tr6 provided in the kth stage is controlled by the scan pulse Vout (k + 1) from the k + 1th stage, and the set node Q and the discharge power line SSL are provided. It is connected between. In other words, the gate terminal of the sixth switching element Tr6 provided in the kth stage is connected to the output terminal 333 of the k + 1th stage, the drain terminal is connected to the set node Q, and The source terminal is connected to the discharge power supply line SSL.

However, the gate terminal of the sixth switching element Tr6 provided in the dummy stage STn + 1 is connected to the start transfer line STL.

The output unit OP of each stage ST1 to STn + 1 includes a pull-up switching device Trpu and a pull-down switching device Trpd.

The pull-up switching device Trpu provided in the k-th stage is controlled by the signal state of the set node Q, and outputs 333 of any one of the clock transmission lines CL1 to CL4 and the k-th stage. ) Is connected. In other words, a gate terminal of the pull-up switching device Trpu provided in the k-th stage is connected to the set node Q, a drain terminal is connected to any one of the clock transmission lines CL1 to CL4, and a source The terminal is connected to the output terminal 333 of the k-th stage.

The pull-down switching device Trpd provided in the k-th stage is controlled by the signal state of the reset node QB, and is connected between the output terminal 333 of the k-th stage and the power output terminal of the power selector 777. do. In other words, the gate terminal of the pull-down switching device Trpd provided in the k-th stage is connected to the reset node QB, the drain terminal is connected to the output terminal 333 of the k-th stage, and the source The terminal is connected to the power output terminal of the power selector 777.

The power selector 777 is provided for each stage ST1 to STn + 1 to prevent deterioration of the first switching element Tr1 and the pull-down switching element Trpd.

The power selector 777 selects one of a high potential voltage and a low potential voltage according to the signal state of the set node Q, and selects the selected voltage from the first switching element Tr1 and the pull-down switching element. Supply to each source terminal of Trpd).

Specifically, when the charging voltage VDD is supplied to the set node Q and the set node Q is maintained in the charged state, the power selector 777 and the first switching element Tr1 and A high potential voltage is supplied to each source terminal of the pull-down switching device Trpd. On the other hand, when the discharge voltage VSS is supplied to the set node Q and the set node Q is maintained in the discharge state, the power selector 777 and the first switching element Tr1 and pull-down are performed. The low potential voltage is supplied to each source terminal of the switching element Trpd.

The high potential voltage is a voltage at the same level as the charging voltage VDD, and the low potential voltage is a voltage at the same level as the discharge voltage VSS, and the power selector 777 is configured to supply the high potential voltage. Instead, the charging voltage VDD may be output, and the discharge voltage VSS may be output instead of the low potential voltage.

As described above, the set node Q and the reset node QB always remain in the opposite state, so that the reset node QB is in a discharge state if the set node Q is in a charged state. Accordingly, the first switching device Tr1 and the pull-down switching device Trpd having the gate terminal connected to the discharged reset node QB remain turned off.

As such, the discharge voltage VSS is applied to each gate terminal of the first switching element Tr1 and the pull-down switching element Trpd so that the first switching element Tr1 and the pull-down switching element Trpd are turned off. When maintained in the state, the power selector 777 supplies a high potential voltage to each of the source terminals of the first switching element Tr1 and the pull-down switching element Trpd to gate the first switching element Tr1. The voltage between the terminal and the source terminal and the voltage between the gate terminal and the source terminal of the rule-down switching element Trpd are respectively maintained in a negative bias state.

On the other hand, if the set node Q is in a discharged state, the reset node QB is in a charged state, and accordingly, the first switching element Tr1 and pull-down having a gate terminal connected to the charged reset node QB The switching element Trpd is kept turned on.

As described above, when the charging voltage VDD is applied to each gate terminal of the first switching element Tr1 and the pull-down switching element Trpd, the power selector 777 is configured to include the first switching element Tr1 and The low potential voltage is supplied to each source terminal of the pull-down switching device Trpd. Then, the first switching device Tr1 in the turn-on state supplies the low potential voltage to the set node Q, and the pull-down switching device Trpd in the turn-on state supplies the low potential voltage to the stage. Supply to the output terminal 333.

FIG. 4 is a diagram for describing a change in polarity of the gate-source voltage Vgs of the first switching device Tr1 according to the output from the power selector 777.

The power selector 777 is connected to the first switching element Tr1 and the pull-down switching element Trpd during an enable period and an output period during which the set node Q is charged and the reset node QB is discharged. By supplying the high potential voltage (charge voltage VDD) to each of the source terminals of the first switching element Tr1 and the pull-down switching element Trpd so that negative bias can be applied, during the enable period and the output period. The deterioration of the turned-off first switching device Tr1 and the pull-down switching device Trpd is restored.

That is, as shown in FIG. 4A, a discharge voltage VSS is supplied to a gate terminal of the first switching element Tr1 in the enable period and an output period, and a discharge voltage is supplied to a source terminal. Since a high potential voltage having a potential higher than that of the voltage VSS is supplied, the voltage Vgs between the gate and source terminals of the first switching element Tr1 becomes negative, causing the voltage to be generated during the enable period and the output period. One switching device Tr1 maintains a negative bias state. The pull-down switching device Trpd is also maintained in the negative bias state during the enable period and the output period in the same manner as the first switching device Tr1.

On the other hand, the power selector 777 normally operates the first switching element Tr1 and the pull-down switching element Trpd during the non-output period during which the set node Q is discharged and the reset node QB is charged. The low potential voltage is supplied to each source terminal of the first switching element Tr1 and the pull-down switching element Trpd so as to output a low potential voltage (discharge voltage VSS).

As shown in FIG. 4B, a charging voltage VDD is supplied to a gate terminal of the first switching element Tr1 in the non-output period, and a charging voltage (VDD) is supplied to a source terminal. Since a low potential voltage having a lower potential than that of VDD is supplied, the voltage Vgs between the gate and source terminals of the first switching element Tr1 becomes positive, and the first switching element is positive during the non-output period. A positive bias state is maintained.

As described above, in the present invention, the first switching element Tr1 and the pull-down switching element Trpd periodically have a negative bias and a positive bias, so that the threshold voltages of the switching elements Tr1 and Trpd increase to either side. By preventing the degradation of the switching elements (Tr1, Trpd) can be minimized.

The power selector 777 may determine the signal state from the reset node Q instead of the set node Q, and select one of the high potential voltage and the low potential voltage. In this case, the power selector 777 outputs a low potential voltage when the reset node Q is in a charged state, and outputs a high potential voltage when the reset node QB is in a discharged state. .

The power selector 777 may have a configuration as follows.

5 is a detailed configuration diagram of the power source selection unit 777.

As shown in FIG. 5, the power selector 777 includes a high potential switching element Tr_A and a low potential switching element Tr_B. The high potential switching element Tr_A and the low potential switching element Tr_B are opposite types of switching elements. For example, when the high potential switching element Tr_A is an N type switching element, the low potential switching element Tr_B Is a P-type switching element.

The high potential switching element Tr_A is controlled by the signal state of the set node Q and is connected between the charging power supply line DDL and the power output terminal 444. In other words, the gate terminal of the high potential switching element Tr_A is connected to the set node Q, the drain terminal is connected to the charging power line DDL, and the source terminal is connected to the power output terminal 444. Connected.

The low potential switching element Tr_B is controlled by the signal state of the set node Q, and is connected between the power output terminal 444 and the discharge power line SSL. In other words, the gate terminal of the low potential switching device Tr_B is connected to the set node Q, the drain terminal is connected to the power output terminal 444, and the source terminal is the discharge power line SSL. ) Is connected.

The operation of the shift register according to the first embodiment of the present invention configured as described above will be described in detail with reference to FIGS. 2 and 6.

FIG. 6 is a diagram illustrating first to third stages ST1 to ST3 having the circuit structure shown in FIG. 3.

First, the operation during the initial period T0 will be described.

The initial period T0 corresponds to the enable period of the first stage. During this initial period T0, only the start pulse Vst is kept high as shown in FIG. The pulses CLK1 to CLK4 are all kept low.

The start pulse Vst is input to the first stage ST1. Specifically, as shown in FIG. 5, the start pulse Vst is a gate terminal of the fourth switching device Tr1 provided in the first stage ST1, and a gate terminal of the second switching device Tr2. Is entered.

Then, the fourth and second switching devices Tr4 and Tr2 are turned on, and the charging voltage VDD is applied to the set node Q through the turned-on fourth switching device Tr4. do. Accordingly, the set node Q is charged, and the pull-up switching device Trpu and the fifth switching device Tr5 having the gate terminal connected to the charged set node Q are turned on.

Then, the discharge voltage VSS is applied to the reset node QB through the turned-on second and fifth switching devices Tr2 and Tr5. Accordingly, the reset node QB of the first stage ST1 is discharged by the discharge voltage VSS, and the pull-down switching element Trpd and the gate terminal connected to the reset node QB are formed. 1 switching element Tr1 is turned off.

On the other hand, since the second scan pulse Vout2 from the second stage ST2 is in the low state during this initial period T0, the third and sixth switching elements Tr3 and Tr6 of the first stage ST1 that receive the second scan pulse Vout2 are low. ) Is turned off.

In this manner, during the initial period T0, the set node Q of the first stage ST1 is charged to the charging voltage VDD, and the reset node QB to the discharge voltage VSS. By discharging, the first stage ST1 is enabled.

The operation of the power selector 777 provided in the first stage ST1 during this initial period T0 will be described below.

In this initial period T0, the set node Q of the first stage is charged by the charging voltage VDD, and as shown in FIG. 5, the charging voltage VSS is set through the set node Q. ), The high potential switching element Tr_A is turned on and the low potential switching element Tr_B is turned off. Then, the charging voltage VDD is applied to the power output terminal 444 through the turned-on high potential switching element Tr_A. The charging voltage VDD applied to the power output terminal 444 is supplied to the source terminal of the first switching element and the source terminal of the pull-down switching element, respectively. Accordingly, the voltage between the gate and source terminals of the first switching device and the voltage between the gate and source terminals of the pull-down switching device exhibit negative polarity. In other words, during this initial period, the first switching element and the pull-down switching element remain in a negative bias state.

Next, the operation during the first period T1 will be described.

The first period T1 is an output period of the first stage ST1. During this first period T1, only the first clock pulse CLK1 is kept high, as shown in FIG. (Vst) and the remaining clock pulses remain low.

Therefore, as the start pulse Vst applied in the initial period T0 changes to low in the first period T1, the first stage receiving the start pulse Vst of the low state through the gate terminal ( The fourth and second switching elements Tr4 and Tr2 of ST1 are turned off. At this time, since the first and sixth switching elements Tr1 and Tr6 including the fourth switching element Tr4 are turned off, the set node Q of the first stage ST1 is maintained in a floating state.

Meanwhile, as the set node Q of the first stage ST1 is maintained at the charging voltage VDD applied during the initial period T0, the pull-up switching device Trpu of the first stage ST1 is maintained. ) Is turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu, the charging voltage VDD charged in the set node Q of the first stage ST1. ) Is amplified by bootstrapping. Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST1 is stable through the source terminal (output terminal 333) of the pull-up switching device Trpu. Is output. In this case, as illustrated in FIG. 2, the output first clock pulse CLK1 is the first scan pulse Vout1.

The first scan pulse Vout1 output from the first stage ST1 is supplied to the first gate line and input to the second stage ST2. In detail, as illustrated in FIG. 6, the first scan pulse Vout1 may include the gate terminal of the fourth switching device Tr4 and the second switching device Tr2 provided in the second stage ST2. It is input to the gate terminal.

Here, the first scan pulse Vout1 supplied to the second stage ST2 plays the same role as the start pulse Vst supplied to the first stage BST1 and the first scan pulse Vout1. In response to), the second stage ST2 is enabled. That is, the set node Q of the second stage ST2 is charged by the charging voltage VDD by the first scan pulse Vout1, and the reset node QB is charged by the discharge voltage VSS. Discharged. In other words, the first scan pulse Vout1 output from the first stage ST1 during the first period T1 drives the first gate line and, as shown in FIG. 6, the second stage. The second stage ST2 is enabled by charging the set node Q of ST2 and discharging the reset node QB.

In the first period T1, since the set nodes Q of the first and second stages ST1 and ST2 are both in a charged state, each power selector included in the first and second stages ST1 and ST2 is in a charged state. 777 outputs the charging voltage VDD.

Next, the operation during the second period T2 will be described.

The second period T2 is an output period of the second stage ST2. During this second period T2, only the second clock pulse CLK2 is kept high and is started, as shown in FIG. The pulse Vst and the remaining clock pulses remain low.

In the second period T2, the second stage ST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2, and the second stage ST2 outputs the second clock pulse CLK2. It supplies to stage ST1.

The second scan pulse Vout2 output from the second stage ST2 is supplied to the second gate line to drive the second gate line, and is also supplied to the third stage St3 to supply the third stage ST3. ) Is enabled and supplied to the first stage ST1 to disable the first stage ST1.

In this second period T2, since the set nodes Q of the second and third stages ST2 and ST3 are both in a charged state, each power selector provided in the second and third stages ST2 and ST3 777 outputs the charging voltage VDD. On the other hand, since the first stage ST1 is disabled in the second period T2, the power selector 777 provided in the first stage ST1 outputs the discharge voltage VSS. If this is explained in more detail as follows.

The second scan pulse Vout2 output from the second stage ST2 in the second period T2 is the gate terminal of the third and sixth switching elements Tr3 and Tr6 provided in the first stage ST1. Is applied to. Accordingly, the third and sixth switching elements Tr3 and Tr6 of the first stage ST1 are turned on. At this time, the discharge voltage VSS is supplied to the set node Q of the first stage ST1 through the turned-on sixth switching element Tr6, and the set node Q is discharged. Accordingly, the pull-up switching device Trpu and the fifth switching device Tr5 having the gate terminal connected to the set node Q are turned off. On the other hand, since the start pulse Vst is in the low state during the second period T2, the fourth and second switching devices Tr4 and Tr2 of the first stage ST1 that receive the start pulse Vst are turned off.

As the third switching device Tr3 of the first stage ST1 is turned on, the charging voltage VDD of the first stage ST1 is turned on through the turned-on third switching device Tr3. The reset node Q is supplied. Accordingly, the pull-down switching device Trpd and the first switching device Tr1 having the gate terminal connected to the reset node QB are turned on.

As described above, since the set node Q of the first stage ST1 is discharged in the second period T2, the high potential switching element provided in the power selector 777 of the first stage ST1 is discharged. Tr_A is turned off and the low potential switching element Tr_B is turned on. Then, the discharge voltage VSS is supplied to the source terminal of the first switching element Tr1 and the source terminal of the pull-down switching element Trpd through the turned-on low potential switching element Tr_B.

Accordingly, the discharge voltage VSS is supplied to the set node Q of the first stage ST1 through the turned-on first switching device Tr1, so that the set node Q is more stable. It is kept in a discharged state. In addition, the discharge voltage VSS is supplied to the first gate line through the turned-on pull-down switching element Trpd to maintain the first gate line in the discharge state.

In this manner, the remaining stages are sequentially enabled or disabled, and the power selector 777 provided in the enabled stage or the stage for outputting the scan pulse outputs the charging voltage VDD, and The power selector 777 provided in the enabled stage outputs a discharge voltage VSS.

Meanwhile, the charging voltage VDD or the discharge voltage VSS from the power selector 777 may be supplied only to the source terminal of the first switching element Tr1 or the source of the pull-down switching element Trpd. It may be supplied only to the terminal.

2nd Example

FIG. 7 is a diagram illustrating a shift register according to a second exemplary embodiment of the present invention, and FIG. 8 is a timing diagram of various signals supplied or output to each stage of FIG. 7.

The shift register according to the second embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in FIG. 7. Here, each of the stages ST1 to STn including the dummy stage STn + 1 outputs one scan pulse Vout1 to Voutn + 2 for one frame period through each output terminal 333, and this is itself. It is fed to stages located at the front and rear of the to control its operation.

The entire stages ST1 to STn + 1 of the shift register configured as described above are sequentially charged with the charging voltage VDD, the discharging voltage VSS, the first AC voltage Vac1, the second AC voltage Vac2, and Any one of the clock pulses CLK1 to CLK4 having a phase difference is applied thereto. Meanwhile, the first stage ST1 of the stages ST1 to STn + 1 is further supplied with a start pulse Vst.

The charge voltage VDD, the discharge voltage VSS, the clock pulses CLK1 to CLK34, and the start pulse Vst are the same as those described in the first embodiment, and thus description thereof will be omitted.

The first and second AC voltages Vac1 and Vac2 are signals for controlling the charging and discharging of the reset nodes among the nodes of the stages ST1 to STn + 1. The first and second AC voltages Vac1 and Vac2 are supplied. The AC precondition 1 and the second AC voltage Vac1 and Vac2 are both AC voltages, and the first AC voltage Vac1 has a phase inverted 180 degrees with respect to the second AC voltage Vac2. The voltage value in the high state of the first and second AC voltages Vac1 and Vac2 may be the same as the voltage value of the charging voltage VDD, and the first and second AC voltages Vac1 and Vac2 The voltage value in the low state may be equal to the voltage value of the discharge voltage VSS. The first and second alternating voltages Vac1 and Vac2 are inverted in their p-cycle periods. Where p is a natural number.

The first AC voltage Vac1 is provided from the first AC power line ACL1, and the second AC voltage Vac2 is provided from the second AC power line ACL2.

The configuration of each stage ST1 to STn + 1 in the shift register configured as described above will be described in more detail as follows.

9 is a diagram illustrating a configuration of an arbitrary stage shown in FIG. 7.

Each stage ST1 to STn + 1 has a set node Q, a first reset node QB1, a second reset node QB2, a node control unit NC, and an output as shown in FIG. And a power supply selector 777.

The node control unit NC controls the signal states of the set node Q, the first reset node QB1, and the second reset node QB2. That is, the node controller NC maintains both the first and second reset nodes QB1 and QB2 in a discharge state when the set node Q is in a charged state, and the set node Q discharges. In the state, one of the first and second reset nodes QB1 and QB2 is kept in a charged state and the other is kept in a discharged state.

The node controller NC of the k-th stage includes first to fourteenth switching elements Tr1 to Tr14.

The first switching element Tr1 provided in the k-th stage is controlled by the signal state of the first reset node QB1 and is connected between the set node Q and the power output terminal 444 of the power selector 777. Connected. In other words, the gate terminal of the first switching element Tr1 provided in the k-th stage is connected to the first reset node QB1, the drain terminal is connected to the set node Q, and the source terminal is It is connected to the power output terminal 444.

The second switching element Tr2 provided in the k-th stage is controlled by the signal state of the second reset node QB2 and is connected between the set node Q and the power output terminal 444 of the power selector 777. Connected. In other words, the gate terminal of the second switching element Tr2 provided in the kth stage is connected to the second reset node QB2, the drain terminal is connected to the set node Q, and the source terminal is It is connected to the power output terminal 444.

The third switching element Tr3 provided in the kth stage is controlled by the scan pulse from the k-1st stage and is connected between the charging power supply line DDL and the discharge power supply line SSL. In other words, the gate terminal of the third switching element Tr3 provided in the k-th stage is connected to the output terminal 333 of the k-th stage, and the drain terminal is connected to the charging power supply line DDL. And a source terminal is connected to the discharge power supply line SSL.

However, the gate terminal of the third switching element Tr3 provided in the first stage ST1 is connected to the start transmission line STL.

The fourth switching element Tr4 provided in the kth stage is controlled by the scan pulse from the k + 1th stage, and is connected between the set node Q and the discharge power supply line SSL. In other words, the gate terminal of the fourth switching element Tr4 provided in the kth stage is connected to the output terminal 333 of the k + 1th stage, the drain terminal is connected to the set node Q, and The source terminal is connected to the discharge power supply line SSL.

However, the gate terminal of the fourth switching element Tr4 provided in the dummy stage STn + 1 is connected to the start transfer line STL.

The fifth switching element Tr5 provided in the kth stage is controlled by the scan pulse from the k + 1th stage and is connected between the first AC power line ACL1 and the first reset node QB1. . In other words, the gate terminal of the fifth switching element Tr5 provided in the kth stage is connected to the output terminal 333 of the k + 1th stage, and the drain terminal of the fifth switching element Tr5 is connected to the first AC power line ACL1. The source terminal is connected to the first reset node QB1.

However, the gate terminal of the fifth switching device Tr5 provided in the dummy stage STn + 1 is connected to the start transfer line STL.

The sixth switching element Tr6 included in the k-th stage is controlled by the first AC voltage Vac1 from the first AC power line ACL1, and the first AC power line ACL1 and the first AC power line VL1 are provided. It is connected between reset nodes QB1. In other words, the gate terminal of the sixth switching element Tr6 provided in the k-th stage is connected to the first AC power line ACL1, the drain terminal is connected to the first AC power line ACL1, and The source terminal is connected to the first reset node QB1.

The seventh switching element Tr7 included in the kth stage is controlled by the scan pulse from the k + 1th stage, and is connected between the second AC power line ACL2 and the second reset node QB2. In other words, the gate terminal of the seventh switching element Tr7 provided in the kth stage is connected to the output terminal 333 of the k + 1th stage, and the drain terminal is connected to the second AC power line ACL2. The source terminal is connected to the second reset node QB2.

However, the gate terminal of the seventh switching element Tr7 provided in the dummy stage STn + 1 is connected to the start transfer line STL.

The eighth switching device Tr8 provided in the k-th stage is controlled by the second AC voltage Vac2 from the second AC power line ACL2, and the second AC power line ACL2 and the second re- It is connected between set nodes QB2. In other words, the gate terminal of the eighth switching element Tr8 provided in the k-th stage is connected to the second AC power line ACL2, the drain terminal is connected to the second AC power line ACL2, and The source terminal is connected to the second reset node QB2.

The ninth switching element Tr9 provided in the k-th stage is controlled by the second alternating voltage Vac2 from the second alternating current power line ACL2, and the first reset node QB1 and the discharge power source. It is connected between lines SSL. In other words, the gate terminal of the ninth switching element Tr9 provided in the k-th stage is connected to the second AC power line ACL2, the drain terminal is connected to the first reset node QB1, and The source terminal is connected to the discharge power supply line SSL.

The tenth switching element Tr10 provided in the k-th stage is controlled by the signal state of the set node Q, and is connected between the first reset node QB1 and the discharge power supply line SSL. In other words, the gate terminal of the tenth switching element Tr10 provided in the k-th stage is connected to the set node Q, the drain terminal is connected to the first reset node QB1, and the source terminal is It is connected to the said discharge power supply line SSL.

 The eleventh switching element Tr11 provided in the kth stage is controlled by the scan pulse from the k-1st stage and is connected between the first reset node QB1 and the discharge power supply line SSL. In other words, the gate terminal of the eleventh switching element Tr11 included in the kth stage is connected to the output terminal 333 of the k-1st stage, and the drain terminal is connected to the first reset node QB1. And a source terminal is connected to the discharge power supply line SSL.

However, the gate terminal of the eleventh switching element Tr11 provided in the first stage ST1 is connected to the start transmission line STL.

 The twelfth switching element Tr12 provided in the k-th stage is controlled by the first alternating voltage Vac1 from the first alternating current power line ACL1, and the second reset node QB2 and the discharge power supply. It is connected between lines SSL. In other words, the gate terminal of the twelfth switching element Tr12 provided in the k-th stage is connected to the first AC power line ACL1, the drain terminal is connected to the second reset node QB2, and The source terminal is connected to the discharge power supply line SSL.

The thirteenth switching element Tr13 included in the k-th stage is controlled by the signal state of the set node Q and is connected between the second reset node QB2 and the discharge power supply line SSL. In other words, the gate terminal of the thirteenth switching element Tr13 provided in the k-th stage is connected to the set node Q, the drain terminal is connected to the second reset node QB2, and the source terminal is It is connected to the said discharge power supply line SSL.

The fourteenth switching element Tr14 included in the k-th stage is controlled by the scan pulse from the k-th stage, and is connected between the second reset node QB2 and the discharge power supply line SSL. In other words, the gate terminal of the fourteenth switching element Tr14 included in the k-th stage is connected to the output terminal 333 of the k-th stage, and the drain terminal is connected to the second reset node QB2. And a source terminal is connected to the discharge power supply line SSL.

However, the gate terminal of the fourteenth switching element Tr14 provided in the first stage ST1 is connected to the start transmission line STL.

The output unit OP of each stage ST1 to STn + 1 includes a pull-up switching device Trpu, a first pull-down switching device Trpd1, and a second pull-down switching device Trpd2.

The pull-up switching device Trpu provided in the k-th stage is controlled by the signal state of the set node Q, and outputs 333 of any one of the clock transmission lines CL1 to CL4 and the k-th stage. ) Is connected. In other words, a gate terminal of the pull-up switching device Trpu provided in the k-th stage is connected to the set node Q, a drain terminal is connected to any one of the clock transmission lines CL1 to CL4, and a source The terminal is connected to the output terminal 333 of the k-th stage.

The first pull-down switching device Trpd1 provided in the k-th stage is controlled by the signal state of the first reset node QB1, and the power supply of the output terminal 333 of the k-th stage and the power selector 777 is provided. It is connected between the output terminals 444. In other words, the gate terminal of the first pull-down switching device Trpd1 provided in the k-th stage is connected to the first reset node QB1, and the drain terminal is connected to the output terminal 333 of the k-th stage. The source terminal is connected to the power output terminal 444 of the power selector 777.

The second pull-down switching device Trpd2 provided in the k-th stage is controlled by the signal state of the second reset node QB2, and the power supply of the output terminal 333 of the k-th stage and the power selector 777 is provided. It is connected between the output terminals 444. In other words, the gate terminal of the second pull-down switching device Trpd2 provided in the kth stage is connected to the second reset node QB2, and the drain terminal is connected to the output terminal 333 of the kth stage. The source terminal is connected to the power output terminal 444 of the power selector 777.

The power selector 777 is configured to prevent deterioration of the first switching device Tr1, the second switching device Tr2, the first pull-down switching device Trpd1, and the second pull-down switching device Trpd2. It is provided for every (ST1 to STn + 1).

The power selector 777 selects one of a high potential voltage and a low potential voltage according to the signal state of the set node Q, and selects the selected voltage from the first and second switching devices Tr1 and Tr2. Are supplied to each source terminal of and to each source terminal of the first and second pull-down switching devices Trpd1 and Trpd2.

Specifically, when the charging node VDD is supplied to the set node Q so that the set node Q is maintained in the charged state, the power selector 777 may include the first and second switching devices. A high potential voltage is supplied to each source terminal of Tr1 and Tr2 and each source terminal of the first and second pull-down switching devices Trpd1 and Trpd2. On the other hand, when the discharge voltage VSS is supplied to the set node Q and the set node Q is maintained in the discharged state, the power selector 777 may provide the first and second switching devices Tr1. , A low potential voltage is supplied to each source terminal of Tr2 and each source terminal of the first and second pull-down switching devices Trpd1 and Trpd2.

The high potential voltage is a voltage at the same level as the charging voltage VDD, and the low potential voltage is a voltage at the same level as the discharge voltage VSS, and the power selector 777 is configured to supply the high potential voltage. Instead, the charging voltage VDD may be output, and the discharge voltage VSS may be output instead of the low potential voltage.

The power selector 777 may have a configuration as shown in FIG. 5.

The operation of the shift register according to the second embodiment of the present invention configured as described above will be described in detail with reference to FIGS. 8 and 10.

FIG. 10 is a diagram illustrating first to third stages ST1 to ST3 having the circuit structure shown in FIG. 9.

First, the operation of the initial period T0 in the first frame period will be described.

During the first frame period, the first AC voltage Vac1 represents the positive polarity and the second AC voltage Vac2 represents the negative polarity.

The initial period T0 corresponds to the enable period of the first stage ST1. During this initial period T0, only the start pulse Vst output from the timing controller is high, as shown in FIG. The state is maintained and the remaining first to fourth clock pulses CLK1 to CLK4 remain low.

The start pulse Vst output from the timing controller is input to the first stage ST1.

That is, the start pulse Vst is applied to the gate terminal of the third switching element Tr3, the gate terminal of the eleventh switching element Tr11, and the fourteenth switching element Tr14 that are provided in the first stage ST1. Supplied.

Then, the third, eleventh, and fourteenth switching elements Tr3, Tr11, and Tr14 are turned on, and the charging voltage VDD is set through the turned-on third switching element Tr3. Is applied to node Q. Accordingly, the set node Q is charged, the pull-up switching device Trpu, the tenth switching device Tr10 of the first stage ST1 having a gate terminal connected to the charged set node Q, and The thirteenth switching element Tr13 is turned on.

The discharge voltage VSS is supplied to the first reset node QB1 of the first stage ST1 through the turned-on tenth switching element Tr10 to discharge the first reset node QB1. . Accordingly, the first pull-down switching device Trpd1 and the first switching device Tr1 of the first stage ST1 having the gate terminal connected to the first reset node QB1 are turned off.

The discharge voltage VSS is supplied to the second reset node QB2 of the first stage ST1 through the turned-on thirteenth switching element Tr13 to discharge the second reset node QB2. . Accordingly, the second pull-down switching device Trpd2 and the second switching device Tr2 of the first stage ST1 having the gate terminal connected to the second reset node QB2 are turned off.

Meanwhile, since the first AC voltage Vac1 remains positive during the first frame period, the sixth switching element Tr6 and the sixth switching element of the first stage ST1 that are supplied with the first AC voltage Vac1. The twelve switching elements Tr12 remain turned on for the first frame period. The second reset node QB2 maintains a discharge state by the turned-on twelfth switching element Tr12, and a second pull-down switching element having a gate terminal connected to the discharged second reset node QB2. Trpd2 and the second switching device Tr2 are maintained in a turn-off state.

Meanwhile, a first AC voltage Vac1 is supplied to the first reset node QB1 of the first stage ST1 through the turned-on sixth switching device Tr6. In this case, the discharge voltage VSS output through the turned-on tenth and eleventh switching elements Tr10 and Tr11 is also supplied to the first reset node QB1 of the first stage ST1. Accordingly, the first reset node QB1 of the first stage ST1 is simultaneously supplied with the first AC voltage Vac1 having the positive polarity and the voltage VSS for the negative polarity.

However, the size of the tenth and eleventh switching elements Tr10 and Tr11 for supplying the discharge voltage VSS is larger than the size of the sixth switching element Tr6 for supplying the first AC voltage Vac1. Since it is set, the first reset node QB1 of the first stage ST1 is maintained at the discharge voltage VSS. Accordingly, the first reset node QB1 is discharged, and the first pull-down switching device Trpd1 and the first of the first stage ST1 having the gate terminal connected to the discharged first reset node QB1. The switching element Tr1 maintains a turn-off state.

Meanwhile, since the second AC voltage Vac2 remains negative during the first frame period, the eighth and ninth switching elements Tr8 of the first stage ST1 that receive the second AC voltage Vac2. , Tr9) remains turned on for the first frame period.

As described above, the set node Q of the first stage ST1 is charged and the first and second reset nodes QB1 and QB2 are discharged during the initial period T0. Is enabled.

The operation of the power selector 777 provided in the first stage ST1 during this initial period T0 will be described below.

In this initial period T0, the set node Q of the first stage ST1 is charged by the charging voltage VDD, and as shown in FIG. 5, the charging is performed through the set node Q. The high potential switching element Tr_A supplied with the voltage VSS is turned on and the low potential switching element Tr_B is turned off. Then, the charging voltage VDD is applied to the power output terminal 444 through the turned-on high potential switching element Tr_A. The charging voltage VDD applied to the power output terminal 444 is applied to the source terminals of the first and second switching elements Tr1 and Tr2 and the first and second pull-down switching elements Trpd1 and Trpd2. It is supplied to each source terminal. Accordingly, the voltage between each gate-source terminal of the first and second switching devices Tr1 and Tr2 and the voltage between each gate-source terminal of the first and second pull-down switching devices Trpd1 and Trpd2 are negative. Indicates. In other words, the first switching device Tr1, the second switching device Tr2, the first pull-down switching device Trpd1, and the second pull-down switching device Trpd2 remain in a negative bias state during this initial period T0. do.

Next, the operation during the first period T1 will be described.

The first period T1 corresponds to an output period of the first stage ST1. In this first period T1, only the first clock pulse CLK1 is high as shown in FIG. 8. Is maintained, and the second to fourth clock pulses CLK2 to CLK4 and the start pulse Vst are kept low.

Here, as the set node Q of the first stage ST1 is kept in the charged state by the charging voltage VDD applied during the initial period T0, the pull-up of the first stage ST1 is performed. The switching element Trpu, the tenth switching element Tr10, and the thirteenth switching element Tr13 maintain a turn-on state. At this time, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu, the charging voltage VDD charged to the set node Q in the floating state is bootstraped. Is amplified by

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST1 is stable through the source terminal (output terminal 333) of the pull-up switching device Trpu. Is output. Here, the first clock pulse CLK1 output through the pull-up switching device Trpu is the first scan pulse Vout1. The first scan pulse Vout1 is supplied to the third stage ST3 to enable the third stage ST3. The first scan pulse Vout1 is supplied to a first gate line to drive the first gate line.

The first scan pulse Vout1 output from the first stage ST1 is applied to the gate terminals of the third, eleventh, and fourteenth switching elements Tr3, Tr11, and Tr14 provided in the second stage ST2. Supplied. Accordingly, the second stage ST2 is enabled in the first period T1. The enabling operation of the second stage ST2 in this first period T1 is the same as the enabling operation of the first stage ST1 in the initial period T0 described above.

In the first period T1, since the set nodes Q of the first and second stages ST1 and ST2 are both in a charged state, each power selector included in the first and second stages ST1 and ST2 is in a charged state. 777 outputs the charging voltage VDD.

Next, the operation during the second period T2 will be described.

The second period T2 corresponds to the output period of the second stage ST2. In this second period T2, only the second clock pulse CLK2 is in a high state as shown in FIG. The first, third, and fourth clock pulses CLK1, CLK3, CLK4, and the start pulse Vst are held low.

Here, as the set node Q of the second stage ST2 is kept in the charged state by the charging voltage VDD applied during the initial period T0, the pull-up of the second stage ST2 is performed. The switching element Trpu, the tenth switching element Tr10, and the thirteenth switching element Tr13 maintain a turn-on state. In this case, as the second clock pulse CLK2 is applied to the drain terminal of the turned-on pull-up switching device Trpu, the charging voltage VDD charged to the set node Q in the floating state is bootstraped. Is amplified by

Therefore, the second clock pulse CLK2 applied to the drain terminal of the pull-up switching device Trpu of the second stage ST2 is stable through the source terminal (output terminal 333) of the pull-up switching device Trpu. Is output. Here, the second clock pulse CLK2 output through the pull-up switching device Trpu is the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the third stage ST3 to enable the third stage ST3. The second scan pulse Vout2 is supplied to a second gate line to drive the second gate line.

In this second period T2, since the set nodes Q of the second and third stages ST2 and ST3 are both in a charged state, each power selector provided in the second and third stages ST2 and ST3 777 outputs the charging voltage VDD. On the other hand, since the first stage ST1 is disabled in the second period T2, the power selector 777 provided in the first stage ST1 outputs the discharge voltage VSS. If this is explained in more detail as follows.

That is, the second scan pulse Vout2 output from the second stage ST2 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first stage ST1. Then, the fourth switching device Tr4 of the first stage ST1 is turned on, and the discharge voltage VSS of the first stage ST1 is turned on by the fourth switching device Tr4. It is supplied to the set node Q. Accordingly, the set node Q is discharged, and the pull-up switching device Trpu, the tenth switching device Tr10, and the thirteenth switching device Tr13 having gate terminals connected to the set node Q are discharged. Is turned off.

As the ninth and tenth switching elements Tr9 and Tr10 of the first stage ST1 are turned off, the sixth switching element Tr6 is connected to the first reset node QB1 of the first stage ST1. The first AC voltage Vac1 of the high state outputted through) is supplied. Accordingly, the first reset node QB1 of the first stage ST1 is charged, and the first stage ST1 of the first stage ST1 having a gate terminal connected to the charged first reset node QB1. The pull-down switching device Trpd1 and the first switching device Tr1 are turned on.

On the other hand, since the first AC voltage Vac1 remains positive during the first frame period, the twelfth switching device Tr12 of the first stage ST1 supplied with the first AC voltage Vac1 is formed in the first frame period. It remains turned on for one frame period. The second reset node QB2 maintains a discharge state by the turned-on twelfth switching element Tr12, and a second pull-down switching element having a gate terminal connected to the discharged second reset node QB2. Trpd2 and the second switching device Tr2 maintain a turn-off state.

As described above, since the set node Q of the first stage ST1 is discharged in the second period T2, the high potential switching element provided in the power selector 777 of the first stage ST1 is discharged. Tr_A is turned off and the low potential switching element Tr_B is turned on. Then, each source terminal of the first and second switching devices Tr1 and Tr2 and the first and second pull-down switching devices Trpd1 have a discharge voltage VSS through the turned-on low potential switching device Tr_B. , Trpd2) is supplied to the source terminal.

Accordingly, the discharge voltage VSS is supplied to the set node Q of the first stage ST1 through the turned-on first switching device Tr1, so that the set node Q is more stable. It is kept in a discharged state. In addition, the discharge voltage VSS is supplied to the first gate line through the turned-on first pull-down switching device Trpd1 to maintain the first gate line in the discharge state.

In this manner, the remaining stages are sequentially enabled or disabled, and the power selector 777 provided in the enabled stage and the stage for outputting the scan pulse outputs the charging voltage VDD, and The power selector 777 provided in the disabled stage outputs the discharge voltage VSS.

On the other hand, since the first AC voltage Vac1 is kept low and the second AC voltage Vac2 is kept high in the second frame period, in the period when the stages ST1 to STn + 1 are disabled, As the first reset node QB1 of each stage ST1 to STn + 1 is discharged and the second reset node QB2 is charged, the first pull-up switching device Trpd1 is turned off and the second pull-up switching is performed. Element Trpd2 is turned on.

On the other hand, the charging voltage VDD or the discharge voltage VSS from the power selector 777 may include a first switching element Tr1, a second switching element Tr2, a first pull-down switching element Trpd1, And only one source terminal of the second pull-down switching device Trpd2.

3rd Example

Meanwhile, in the shift register according to the second embodiment of the present invention, each stage may be driven without a separate power selector 777.

FIG. 11 is a diagram illustrating another configuration of any stage shown in FIG. 7.

The third to fourteenth switching elements Tr3 to Tr14 and the pull-up switching element Trpu shown in FIG. 11 are the same as those described in the second embodiment.

The first and second pull-down switching devices Trpd1 and Trpd2 and the first and second switching devices Tr1 and Tr2 shown in FIG. 11 will be described below.

The first pull-down switching device Trpd1 provided in the k-th stage is controlled by the signal state of the first reset node QB1 and is connected between the output terminal 333 of the k-th stage and the power supply line SSL for discharge. do. In other words, the gate terminal of the first pull-down switching device Trpd1 provided in the k-th stage is connected to the first reset node QB1, and the drain terminal is connected to the output terminal 333 of the k-th stage. The source terminal is connected to the discharge power supply line SSL.

The second pull-down switching device Trpd2 provided in the k-th stage is controlled by the signal state of the second reset node QB2 and is connected between the output terminal 333 of the k-th stage and the power supply line SSL for discharge. do. In other words, the gate terminal of the second pull-down switching device Trpd2 provided in the kth stage is connected to the second reset node QB2, and the drain terminal is connected to the output terminal 333 of the kth stage. The source terminal is connected to the discharge power supply line SSL.

The first switching element Tr1 provided in the k-th stage is controlled by the signal state of the first reset node QB1 and is connected between the set node Q and the second AC power line ACL2. In other words, the gate terminal of the first switching element Tr1 provided in the k-th stage is connected to the first reset node QB1, the drain terminal is connected to the set node Q, and the source terminal. Is connected to the second AC power line ACL2.

The second switching element Tr2 provided in the k-th stage is controlled by the signal state of the second reset node QB2, and is connected between the set node Q and the first AC power line ACL1. In other words, the gate terminal of the second switching element Tr2 provided in the kth stage is connected to the second reset node QB2, the drain terminal is connected to the set node Q, and the source terminal Is connected to the first AC power line ACL1.

As described above, when the set node Q is in the charged state, both the first and second reset nodes QB1 and QB2 are in a discharged state. Therefore, when the set node Q is in the charged state, the first and second switching devices Tr1 and Tr2 are both turned off.

Since the first AC voltage Vac1 and the second AC voltage Vac2 have different polarities in the same frame period, the source terminal of the first switching element Tr1 and the source terminal of the second switching element have different polarities. Voltage is supplied.

For example, if the first AC voltage Vac1 is maintained at the positive high voltage and the second AC voltage Vac2 is maintained at the negative low voltage during the first frame period, the source terminal The second switching device Tr2, which is supplied with the first AC voltage Vac1 in the high state, is maintained in the negative bias state in the enable period.

If the first AC voltage Vac1 is maintained at a negative low voltage during the second frame period and the second AC voltage Vac2 is maintained at a positive high voltage, The first switching device Tr1 receiving the second AC voltage Vac2 in the high state is maintained in the negative bias state in the enable period.

Meanwhile, in the disable period, the set node Q is discharged, one of the first reset node QB1 and the second reset node QB2 is charged, and the other is discharged.

For example, in the first frame period, the first reset node QB is charged by the first AC voltage Vac1 in the high state, and the second reset node QB2 is charged with the discharge voltage VSS ( Alternatively, when discharged by the second AC voltage Vac2 in the low state, the first switching device to which the gate terminal of the first reset node QB1 is connected is turned on and the second reset node QB2 is turned off. The second switching element connected to the gate terminal is turned off, at this time, the second AC voltage Vac2 in a low state is supplied to the source terminal of the first switching element Tr1 and the second switching element Tr2 is turned on. Since the first AC voltage Vac1 of the high state is supplied to the drain terminal of, the turned-on first switching device Tr1 turns on the second AC voltage Vac2 of the low state during the disable period of the first frame period. Is supplied to the first reset node QB1 to discharge the first reset node QB1, Group are turned off the second switching element (Tr2) is maintained by the first AC voltage (Vac1) of the high state supplied to its source terminal to the negative bias condition.

In the second frame period, the first reset node QB is discharged by the discharge voltage VSS (or the first AC voltage Vac1 in the low state) and the second reset node QB2 is discharged. When charged by the second AC voltage Vac2 in the high state, the first switching device Tr1 to which the gate terminal of the first reset node QB1 is connected is turned off, and the second reset node ( The second switching element Tr2 connected to the gate terminal of QB2 is turned on. In this case, the second AC voltage Vac2 of the high state is supplied to the source terminal of the first switching element Tr1, and the first AC voltage Vac1 of the low state is supplied to the drain terminal of the second switching element Tr2. Since the first switching device Tr1 is turned off during the disable period in the second frame period, the first switching element Tr1 is supplied to the negative bias state by the high second AC voltage Vac2 supplied to its source terminal. The second switching device Tr2 maintained and turned on supplies the first AC voltage Vac1 in a low state to the second reset node QB2 to discharge the second reset node QB2.

4th Example

FIG. 12 is a diagram showing another configuration of any stage shown in FIG. 7.

The first to fourteenth switching elements Tr1 to Tr14 and the pull-up switching element Trpu shown in FIG. 12 are the same as those shown in FIG. 11.

The first pull-down switching device Trpd1 provided in the k-th stage is controlled by the signal state of the first reset node QB1 and is connected between the output terminal 333 of the k-th stage and the second AC power line ACL2. Connected. In other words, the gate terminal of the first pull-down switching device Trpd1 provided in the k-th stage is connected to the first reset node QB1, and the drain terminal is connected to the output terminal 333 of the k-th stage. And, the source terminal is connected to the second AC power line (ACL2).

The first pull-down switching device Trpd1 is equally maintained in the negative bias state when the first switching device Tr1 is maintained in the negative bias state, and corresponds to the second AC voltage Vac2 in the low state during the disable period. Supply to the gate line.

The second pull-down switching device Trpd2 provided in the k-th stage is controlled by the signal state of the second reset node QB2 and is connected between the output terminal 333 of the k-th stage and the first AC power line ACL1. Connected. In other words, the gate terminal of the second pull-down switching device Trpd2 provided in the kth stage is connected to the second reset node QB2, and the drain terminal is connected to the output terminal 333 of the kth stage. And, the source terminal is connected to the first AC power line (ACL1).

The second pull-down switching device Trpd2 is maintained in the same negative bias state when the second switching device Tr2 is maintained in the negative bias state, and corresponds to the first AC voltage Vac1 in the low state during the disable period. Supply to the gate line.

Meanwhile, the stages ST1 to STn + 1 may be supplied with clock pulses CLK1 to CLK4 as shown in FIG. 13 instead of the above-described clock pulses CLK1 to CLK4.

FIG. 13 is a diagram illustrating a timing diagram of first to fourth clock pulses CLK1 to CLK4 in which output periods overlap.

In the present invention, as shown in FIG. 13, the first to fourth clock pulses CLK1 to CLK4 in which the pulse width sections are overlapped may be used. That is, as shown in FIG. 13, the second half of the pulse width section of the m th clock pulse overlaps the first half of the pulse width section of the m + 1 th clock pulse. Where m is a natural number.

The length of the section of the pulse width to be filled is not limited to the length corresponding to the 1/2 section and can be adjusted as much as possible.

When the overlapped clock pulses CLK1 to CLK4 are used, the pulse widths of the scan pulses Vout1 to Voutn + 1 output from each stage also overlap each other.

In addition, when the superimposed clock pulses CLK1 to CLK4 shown in FIG. 13 are used, the k th stage is enabled by the scan pulse from the k-2 stage, not the scan pulse from the k-1 st stage. It is disabled by the scan pulse from the k + 2 stage, not the scan pulse from the k + 1 stage.

According to the number of the clock pulses and the length of the overlapping pulse width between the clock pulses, the positions of the front stage and the rear stage connected to the k-th stage can be varied.

Each of the switching elements described above (first to fourteenth switching elements Tr1 to Tr14), pull-up switching element Trpu, pull-down switching element Trpd, first and second pull-down switching elements Trpd1 and Trpd2, and high potential switching. The device Tr_A and the low potential switching device Tr_B may be a metal oxide semi-conductor (MOS), and each of the semiconductor layers may be formed of amorphous silicon.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a diagram showing a shift register according to a first embodiment of the present invention.

FIG. 2 is a timing diagram of various signals supplied or output to each stage of FIG. 1. FIG.

FIG. 3 is a diagram showing the configuration of any stage shown in FIG.

4 is a view for explaining a change in polarity of a gate-source voltage of a first switching device in response to an output from a power supply selection unit;

5 is a detailed configuration diagram of the power selection unit;

FIG. 6 shows first to third stages having the circuit structure shown in FIG.

7 illustrates a shift register according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 7.

FIG. 9 shows a configuration of an arbitrary stage shown in FIG. 7. FIG.

FIG. 10 is a view showing first to third stages having the circuit structure shown in FIG.

11 shows yet another configuration of any stage shown in FIG.

FIG. 12 shows yet another configuration of any stage shown in FIG.

FIG. 13 is a timing diagram of first to fourth clock pulses having overlapping output periods. FIG.

* Description of the main parts of the drawing:

Tr: switching element Trpu: pull-up switching element

Trpd: Pull-down switching element Q: Set node

QB: Reset Node 333: Output Terminal

CLK: Clock pulse CL: Clock transmission line

Vout: Scan pulse VDD: Voltage source for charging

VSS: Voltage source for discharge 777: Power selector

NC: node control unit OP: output unit

Claims (8)

A plurality of stages that sequentially output scan pulses; Each stage includes: a node controller for controlling signal states of the set node and the reset node; An output unit controlled by the signal states of the set node and the reset node to output a scan pulse through an output terminal; A power selector for selecting one of a high potential voltage and a low potential voltage according to the signal state of the set node and outputting the same through a power output terminal; And, And the node controller includes a switching element controlled by a signal state of the reset node and connected between the set node and a power output terminal of the power selector. The method of claim 1, The power selector, And selecting and outputting a high potential voltage when the set node is in a charged state and selecting and outputting a low potential voltage when the set node is in a discharged state. The method of claim 1, The output of each stage A pull-up switching element controlled by the signal state of the set node and connected between a clock transmission line for transmitting any one of at least two clock pulses having a phase difference and the output terminal; And, And a pull-down switching element controlled by the signal state of the reset node and connected between the output terminal and the power output terminal. A plurality of stages that sequentially output scan pulses; Each stage includes: a node controller for controlling signal states of the set node, the first reset node, and the second reset node; An output unit controlled by signal states of the set node, the first reset node, and the second reset node to output a scan pulse through an output terminal; A power selector for selecting one of a high potential voltage and a low potential voltage according to the signal state of the set node and outputting the same through a power output terminal; And, And the node controller includes a first switching element controlled by the signal state of the first reset node and connected between the set node and a power output terminal of the power selector. The method of claim 4, wherein The node control unit, And a second switching element controlled by the signal state of the second reset node and connected between the set node and the power output terminal. The method of claim 4, wherein The output of each stage is A pull-up switching element controlled by the signal state of the set node and connected between a clock transmission line for transmitting any one of at least two clock pulses having a phase difference and an output terminal of the stage; A first pull-down switching element controlled by the signal state of the first reset node and connected between the output terminal and the power output terminal; And, And a second pull-down switching element controlled by the signal state of the second reset node and connected between the output terminal and the power output terminal. It includes a plurality of stages to sequentially output the scan pulse through its output terminal; Each stage includes: a node controller for controlling signal states of the set node, the first reset node, and the second reset node; An output unit controlled by the signal states of the set node, the first reset node, and the second reset node to output a scan pulse through an output terminal; The node control unit includes: a first switching element controlled by a first AC voltage supplied to the first reset node and connected between the set node and a second AC power line for transmitting a second AC voltage; A second switching element controlled by a second AC voltage supplied to said second reset node and connected between said set node and a first AC power line for transmitting said first AC voltage; And, And the first AC voltage and the second AC voltage have opposite phases to each other. The method of claim 7, wherein The output of each stage is A pull-up switching element controlled by the signal state of the set node and connected between an output terminal and a clock transmission line for transmitting any one of at least two clock pulses having a phase difference; A first pull-down switching element controlled by the signal state of the first reset node and connected between the output terminal and the second AC power line; And, And a second pull-down switching element controlled by the signal state of the second reset node and connected between the output terminal and the first AC power line.

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