KR20140095209A

KR20140095209A - Shift register

Info

Publication number: KR20140095209A
Application number: KR1020130007837A
Authority: KR
Inventors: 김지하
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-01-24
Filing date: 2013-01-24
Publication date: 2014-08-01
Also published as: KR102034053B1

Abstract

The present invention relates to a shift register capable of improving the reliability of a circuit operation and minimizing an occupied area, and includes a plurality of stages for outputting a scan pulse through an output terminal; Each stage being controlled in accordance with a scan pulse from a front end stage and having a first switching element connected between a set power source line and a set node for transmitting a charging voltage; A second switching element connected between the set node and a discharge power supply line for transmitting a discharge voltage, the second switching element being controlled in accordance with a scan pulse from a rear stage; A third switching device controlled according to a first AC voltage from a first AC power supply line and connected between the first AC power supply line and a first reset node; A fourth switching device controlled according to a second AC voltage from a second AC power supply line and connected between the second AC power supply line and a second reset node; A fifth switching device controlled according to the second AC voltage, the fifth switching device being connected between the first reset node and the discharging power supply line; A sixth switching device controlled according to the first AC voltage, the sixth switching device being connected between the second reset node and the discharging power supply line; A seventh switching device controlled according to a voltage of the set node, the seventh switching device being connected between the first reset node and the discharging power supply line; An eighth switching device controlled according to a voltage of the set node, the eighth switching device being connected between the second reset node and the discharging power supply line; And a ninth switching element controlled in accordance with at least one of the voltage of the first reset node and the voltages of the second reset node and connected between the set node and the discharge power supply line .

Description

SHIFT REGISTER {SHIFT REGISTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, and more particularly, to a shift register capable of improving the reliability of a circuit operation and minimizing an occupied area.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

This driver circuit includes a shift register for driving the gate lines, and this shift register includes a plurality of stages.

Each stage includes a plurality of switching elements. As the driving time of the shift register increases, a threshold voltage of the switching elements increases in one direction, and deterioration phenomenon that is not recovered to the original state occurs. In such a case, the switching element is not turned on by the target voltage, which causes a problem that the circuit does not operate normally. Particularly, the degree of deterioration of the pull-down switching device supplied with the bias voltage in one direction for a relatively long time is much higher than that of the other switching devices.

Conventionally, a deterioration preventing structure for alternately driving two reset nodes is adopted to prevent deterioration of such a pull-down switching device. However, conventionally, since one pull-down switching element and one set discharge switching element are required per one reset node, at least four switching elements are required to use the deterioration preventing structure having two reset nodes. As a result, the area occupied by the shift register in the substrate is increased.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a dual gate switching device which can prevent the deterioration of a switching element by a relatively small number of switching elements, It is another object of the present invention to provide a shift register capable of reducing the occupied area of a shift register.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages for outputting a scan pulse through an output terminal; Each stage being controlled in accordance with a scan pulse from a front end stage and having a first switching element connected between a set power source line and a set node for transmitting a charging voltage; A second switching element connected between the set node and a discharge power supply line for transmitting a discharge voltage, the second switching element being controlled in accordance with a scan pulse from a rear stage; A third switching device controlled according to a first AC voltage from a first AC power supply line and connected between the first AC power supply line and a first reset node; A fourth switching device controlled according to a second AC voltage from a second AC power supply line and connected between the second AC power supply line and a second reset node; A fifth switching device controlled according to the second AC voltage, the fifth switching device being connected between the first reset node and the discharging power supply line; A sixth switching device controlled according to the first AC voltage, the sixth switching device being connected between the second reset node and the discharging power supply line; A seventh switching device controlled according to a voltage of the set node, the seventh switching device being connected between the first reset node and the discharging power supply line; An eighth switching device controlled according to a voltage of the set node, the eighth switching device being connected between the second reset node and the discharging power supply line; And a ninth switching element controlled in accordance with at least one of the voltage of the first reset node and the voltages of the second reset node and connected between the set node and the discharge power supply line .

Each of the stages further includes a pulldown switching element controlled between at least one of the voltage of the first reset node and the voltages of the second reset node and connected between the output terminal and the discharge power supply line .

The ninth switching element and the pull-down switching element are dual gate switching elements having a top-gate electrode and a bottom-gate electrode.

A top-gate electrode of the ninth switching element is connected to the first reset node, and a bottom-gate electrode thereof is connected to the second reset node; A top-gate electrode of the pull-down switching element is connected to the first reset node, and a bottom-gate electrode thereof is connected to the second reset node.

Each stage is controlled according to the voltage of the set node, and further includes a clock transmission line for transmitting a clock pulse and a pull-up switching element connected between the output terminal and the clock transmission line.

The shift register according to the present invention has the following effects.

According to the present invention, only two switching elements are required in using the deterioration preventing structure having two reset nodes. That is, in the present invention, the pull-down switching element and the set discharge switching element are constituted by a dual gate switching element, and each of the gate electrodes is connected to the first and second reset nodes, . Therefore, deterioration of the switching element can be prevented with a relatively small number of switching elements, and the area occupied by the shift register can be reduced.

1 is a view showing a shift register according to the present invention;
Fig. 2 is a timing chart of various signals supplied to and output from each stage of Fig. 1
3 is a view showing a configuration of a stage according to an embodiment of the present invention
4 is a view showing a dual gate switching device according to the first embodiment;
5 is a view showing a dual gate switching device according to a second embodiment;

FIG. 1 shows a shift register according to the present invention. FIG. 2 is a timing diagram of various signals supplied to and output from the stage of FIG. On the other hand, only the input / output lines of the n-th stage STn are shown in Fig. 1, and the input / output lines of the remaining stages are not shown. The input / output lines of the remaining stages have a connection relationship in the same manner as the n-th stage STn.

The shift register according to the embodiment of the present invention includes a plurality of stages. In Fig. 1, only some of the entire stages, i.e., the (n-4) th stage to (n + 5) th stages STn-4 to STn + Is shown. ..., SPn-4 to SPn + 5) for one frame period through each output terminal OT, and each stage (..., STn-4 to STn + 5, 5, ...).

At this time, odd-numbered stages (..., STn-4, STn-2, STn, STn + 2, STn + 4, ..., STn-1, STn + 1, STn + 3, STn + 1, ...) constitute one shift register SR1 (hereinafter referred to as a first shift register) 5, ... constitute another shift register SR2 (hereinafter, referred to as a second shift register). The stages (i.e., even-numbered stages) included in the first shift register SR1 drive odd-numbered gate lines while the stages (i.e., even-numbered stages) Numbered gate lines.

Each of the stages (..., STn-4 to STn + 5, ...) drives the gate line connected thereto by using the scan pulse, and also controls the operation of the stage located at the rear end from itself, And controls the stage.

The stages (..., STn-4 to STn + 5, ...) output scan pulses in order from the stage to which the quick number is given. For example, the n-4th stage STn-4 outputs the n-4th scan pulse SPn-4 and the n-3th stage STn-3 outputs the n-3th scan pulse SPn- 2, the n-2th stage STn-2 outputs the (n-2) th scan pulse SPn-2, Pulse, and finally, the (a + 1) th stage outputs a + 1 scan pulse. Where a is a natural number greater than n-2.

On the other hand, when the a-stage is the last one of the odd-numbered stages provided in the first shift register SR1, the (a + 2) th stage outputs a scan pulse for resetting the a- 4 stage and the (a + 2) stage. Further, when the (a + 1) -th stage is the last one of the even-numbered stages provided in the second shift register SR2, the scan pulse for resetting the (a + 1) And the (a + 5) th stage and the (a + 3) th stage. Here, the (a + 4) th stage, the (a + 2) th stage, the (a + 5) th stage and the (a + 3) stage are dummy stages not connected to the gate line. That is, the scan pulse from these dummy stages is not supplied to the gate line.

Such a shift register can be incorporated in the liquid crystal panel. That is, this liquid crystal panel has a display portion for displaying an image and a non-display portion enclosed by the display portion, and such a shift register can be embedded in the non-display portion.

Each of the stages (..., STn-4 to STn + 5, ...) of the shift register having such a structure is provided with a charging voltage VDD, a discharging voltage VSS, a first AC voltage Vac1, And receives the AC voltage (Vac2). Further, each stage (..., STn-4 to STn + 5, ...) receives any one of the first to eighth clock pulses CLK1 to CLK8 having a sequential phase difference with each other. The odd-numbered clock pulses CLK1, CLK3, CLK5 and CLK7 are provided to the first shift register SR1 and the even-numbered clock pulses CLK2, CLK4, CLK6 and CLK8 are provided to the second shift register SR2 ). Thus, the stages (..., STn-4, STn-2, STn, ...) provided in the first shift register SR1 are controlled by the first, third, fifth and seventh clock pulses CLK1, ..., STn-3, STn-1, STn + 1, ...) provided in the second shift register SR2 are supplied with one of the stages CLK1, CLK3, CLK5, Second, fourth, sixth and eighth clock pulses CLK2, CLK4, CLK6 and CLK8.

On the other hand, the first stage, the third stage, the second stage and the fourth stage among the stages (..., STn-4 to STn + 5, ...) are further supplied with start pulses S1 and S2. Specifically, the first and third stages are further supplied with the first start pulse, and the second and fourth stages are further supplied with the second start pulse. On the other hand, the first, third, second, and fourth stages may be supplied with the start pulse independently of each other. For example, if the first stage is supplied with the first start pulse, then the second stage is supplied with the second start pulse, then the third stage is supplied with the third start pulse, 4 start pulse can be supplied. The first to fourth start pulses are sequentially output from the first start pulse.

Here, the first stage and the third stage are stages provided in the first shift register SR1, and the first stage outputs the first scan pulse among the stages in the first shift register SR1. The second stage and the fourth stage are provided in the second shift register SR2, and the second stage outputs the first scan pulse among the stages in the second shift register SR2.

The charging voltage VDD is mainly used to charge the nodes of each stage, and the discharging voltage VSS is mainly used to discharge the nodes of each stage and the output terminal OT. The charging voltage VDD is a direct current voltage, which indicates a positive polarity, and a discharging voltage VSS indicates a negative polarity. On the other hand, the discharge voltage VSS can be ground (0 [V]).

The first AC voltage Vac1 has a high voltage and a low voltage in units of i frames (i is a natural number), and the high voltage can have the same level as the charging voltage VDD described above, And may have the same level as the voltage VSS. ]

The second AC voltage Vac2 also has a high voltage and a low voltage in units of i frames (i is a natural number), and the high voltage can have the same level as the charging voltage VDD described above, And may have the same level as the voltage VSS. However, the second AC voltage (Vac2) has a phase inverted by 180 degrees with respect to the first AC voltage (Vac1). Therefore, when the second AC voltage (Vac2) is maintained at a high voltage in a specific frame period, the first AC voltage (Vac1) is held at the low voltage in the specific frame period. That is, in the same frame period, the first AC voltage (Vac1) and the second AC voltage (Vac2) always have opposite levels.

The first to eighth clock pulses CLK1 to CLK4 are sequentially output, and are output while being circulated. That is, the signals are sequentially output from the first clock pulse CLK1 to the eighth clock pulse CLK8, and sequentially output from the first clock pulse CLK1 to the eighth clock pulse CLK8. Therefore, the first clock pulse CLK1 is output in a period corresponding to the eighth clock pulse CLK8 and the second clock pulse CLK2. The seventh clock pulse CLK7 and the first start pulse S1 may be synchronized with each other and the eighth clock pulse CLK8 and the second start pulse S2 may be synchronized with each other. In this case, the seventh clock pulse CLK8 of the first to eighth clock pulses CLK1 to CLK4 is output first, followed by the eighth clock pulse CLK8.

Clock pulses adjacent to each other among the first to eighth clock pulses CLK1 to CLK8 are superposed for a certain period of their pulse widths. For example, when the pulse width of each clock pulse is divided into four periods as shown in FIG. 2, the second to fourth periods of the pulse width of the first clock pulse CLK1 and the second clock pulse CLK2 are overlapped with each other. Accordingly, the first clock pulse CLK1 and the fifth clock pulse CLK5 do not overlap each other, the second clock pulse and the sixth clock pulse do not overlap, and the third clock pulse and the seventh clock pulse overlap each other And the fourth clock pulse and the eighth clock pulse do not overlap.

The first start pulse S1 and the second start pulse S2 may overlap each other for a certain period of time. On the other hand, although not shown, when four start pulses are used, they can also be superimposed in the manner as described above.

The first to eighth clock pulses CLK1 to CLK8 are used to generate scan pulses of each stage (..., STn-4 to STn + 5, ...). For example, the n-4th stage STn-4 generates the scan pulse SPn-4 using the first clock pulse CLK1 and the n-3th stage STn- 2 generates the scan pulse SPn-2 using the third clock pulse CLK2 and generates the scan pulse SPn-3 using the pulse CLK2, the n-2th stage STn-2 generates the scan pulse SPn- The n-1 stage STn-1 generates the scan pulse SPn-1 using the fourth clock pulse CLK4 and the n-th stage STn generates the scan pulse SPn-1 using the fifth clock pulse CLK5. Th stage STn + 1 generates a scan pulse SPn + 1 using the sixth clock pulse CLK6, and generates the scan pulse SPn + 1 using the sixth clock pulse CLK6 in the (n + 1) 3 generates the scan pulse SPn + 3 using the seventh clock pulse CLK7 and the nth + 3 stage STn + 3 generates the scan pulse SPn + 2 using the eighth clock pulse CLK8. .

In the present invention, eight clock pulses having different phase differences are used. However, the number of clock pulses may be two or more.

Each of the clock pulses CLK1 to CLK8 is output several times during one frame period, but the first and second start pulses S1 and S2 are output only once during one frame period. In other words, although each of the clock pulses CLK1 to CLK8 represents a plurality of active states (high state) periodically for one frame period, the first and second start pulses S1 and S2 can be applied only once Indicates an active state. The third and fourth start pulses not shown are also output in this manner.

The enable operation of each stage (..., STn-4 to STn + 5, ...) in order to output the scan pulses (..., STn-4 to STn + Should be preceded. The fact that the stage is enabled means that the stage is set in a state in which it can output, that is, a state in which a clock pulse supplied thereto can be outputted as a scan pulse. To this end, each stage (..., STn-4 to STn + 5, ...) is supplied with a scan pulse from the stage located at the previous stage thereof and is enabled. That is, the stage s is enabled by receiving a clock pulse and a scan pulse from the s-p stage synchronized with the clock pulse. Where s is a natural number and p is a natural number less than s, which can be four.

For example, the n-th stage STn is enabled in response to the scan pulse SPn-4 from the n-4th stage STn-4, and the (n + 1) and is enabled in response to the scan pulse SPn-3 from the (n-3) th stage STn-3. However, the first stage and the third stage of the first shift register SR1 are enabled in response to the first start pulse S1 from the timing controller (not shown). Similarly, the second stage and the fourth stage of the second shift register SR2 are enabled in response to the second start pulse S2 from the timing controller.

Further, each stage (..., STn-4 to STn + 5, ...) is supplied with a scan pulse from the stage located at the rear end from itself and is disabled. The fact that the stage is disabled means that the stage is reset to a state in which output is impossible, i.e., a state in which a clock pulse supplied thereto can not be output as a scan pulse. That is, the stage s is disabled in response to the carry pulse from the s + q stage. Here, q is a natural number, and q and p may be set to the same number. Here, q may be four.

For example, the n-th stage STn is disabled in response to the scan pulse SPn + 4 from the (n + 2) th stage STn + 4, and is enabled in response to the scan pulse (SPn + 5) from the (n + 5) th stage STn + 5. However, the dummy stages described above are disabled by the corresponding start pulse.

The configuration of each stage (..., STn-4 to STn + 5, ...) in the shift register constructed as described above will be described in more detail as follows.

3 is a diagram showing a configuration of a stage according to an embodiment of the present invention, and Fig. 3 is a diagram showing the configuration of any stage in Fig.

As shown in Fig. 3, one n-th stage STn includes a node controller NC for controlling the voltages of the set node Q and the reset node Qb, And an output unit OU for outputting a scan pulse and a discharge voltage VSS in accordance with the voltage of the reset node Qb. Here, the node control unit NC includes the first to ninth switching elements Tr1 to Tr9. The output unit OU includes a pull-up switching device Us and a pull-down switching device Ds.

The switching elements will be described in detail as follows.

The first switching device Tr1 provided in the n-th stage STn is controlled in accordance with the scan pulse SPn-4 from the n-4th stage STn-4, (Q). The first switching element Tr1 is turned on or off according to the (n-4) th scan pulse and applies the turn-on charging voltage VDD to the set node Q. The charging voltage VDD is applied to the charging power supply line VDL described above.

The second switching device Tr2 provided in the nth stage STn is controlled in accordance with the scan pulse SPn + 4 from the (n + 4) th stage STn + 4, Line VSL. The second switching device Tr2 turns on or off according to the (n + 4) th scan pulse SPn + 4 and applies the turn-on discharge voltage VSS to the set node Q . The discharging voltage VSS is applied to the discharging power supply line VSL.

The third switching device Tr3 provided in the nth stage STn is controlled according to the first AC voltage Vac1 and is connected between the first AC power supply line VAL1 and the first reset node Qb1 . The third switching device Tr1 is turned on or off according to the first AC voltage Vac1 and applies the first AC voltage Vac1 to the first reset node Qb1 when the first switching device Tr1 turns on. The first AC voltage (Vac1) is applied to the first AC power supply line (VAL1).

The fourth switching device Tr4 provided in the nth stage STn is controlled according to the second AC voltage Vac2 and is connected between the second AC power supply line VAL2 and the second reset node Qb2 . The fourth switching device Tr4 is turned on or off according to the second AC voltage Vac2 and applies the second AC voltage Vac2 to the second reset node Qb2 at the turn-on time. The second AC voltage (Vac2) is applied to the second AC power supply line (VAL2).

The fifth switching element Tr5 provided in the nth stage STn is controlled according to the second AC voltage Vac2 and is connected between the first reset node Qb1 and the discharge power supply line VSL. The fifth switching element Tr5 is turned on or off according to the second AC voltage Vac2 and applies the turn-on discharge voltage VSS to the first reset node Qb1.

The sixth switching element Tr6 provided in the nth stage STn is controlled according to the first AC voltage Vac1 and is connected between the second reset node Qb2 and the discharge power supply line VSL. The sixth switching element Tr6 is turned on or off according to the first AC voltage Vac1 and applies the turn-on discharge voltage VSS to the second reset node Qb2.

The seventh switching device Tr7 provided in the nth stage STn is controlled according to the voltage from the set node Q and is connected between the first reset node Qb1 and the discharge power supply line VSL . This seventh switching device Tr7 is turned on or off according to the voltage of the set node Q and applies the turn-on discharge voltage VSS to the set node Q. [

The eighth switching element Tr8 provided in the nth stage STn is controlled according to the voltage of the set node Q and is connected between the second reset node Qb2 and the discharge power supply line VSL. The eighth switch Tr8 is turned on or off according to the voltage of the set node Q and applies the turn-on discharge voltage VSS to the second reset node Qb2.

The ninth switching element Tr9 provided in the nth stage STn is controlled according to at least one of the voltage of the first reset node Qb1 and the voltages of the second reset node Qb2, Q) and a discharge power supply line (VSL). The ninth switching element Tr9 is turned on or off according to one of the voltages of the first reset node Qb1 and the second reset node Qb2 and the turn- (VSS) to the set node (Q). The ninth switching element Tr9 is a dual gate switching element having a top-gate electrode and a bottom-gate electrode. The top-gate electrode of the ninth switching element Tr9 is connected to the first reset node Qb1 And its bottom-gate electrode is connected to the second reset node Qb2.

The pull-up switching device Us included in the n-th stage STn is controlled in accordance with the voltage of the set node Q. The fifth clock transmission line CL5 for transmitting the fifth clock pulse CLK5, Is connected between the output terminal OT of the output terminal STn. This pull-up switching device Us turns on or off according to the voltage applied to the set node Q and outputs the fifth clock pulse CLK5 as the n th scan pulse SPn at turn-on . The nth scan pulse SPn output from the pull-up switching device Us is supplied to the n-th gate line, the n-4th stage STn-4 and the (n + 4) th stage STn + ).

The pulldown switching element Ds provided in the nth stage STn is controlled according to at least one of the voltage of the first reset node Qb1 and the voltages of the second reset node Qb2, ) And a discharge power supply line (VSL). This pulldown switching element Ds is turned on or off according to the voltage of the first reset node Qb1 and the voltage of the second reset node Qb2 and is turned on at the turn- VSS to the output terminal OT. The pull-down switching device Ds is a dual gate switching device having a top-gate electrode and a bottom-gate electrode. The top-gate electrode of the pull-down switching device Ds is connected to the first reset node Qb1 , And its bottom-gate electrode is connected to the second reset node Qb2.

On the other hand, all of the switching elements described above may be composed of transistors including an oxide semiconductor layer. At this time, since the ninth switching element Tr9 and the pull-down switching element Ds are constituted by a dual gate switching element, a deterioration preventing structure can be realized by using a smaller number of switching elements compared to the related art. That is, conventionally, since one pull-down switching element and one set discharge switching element Tr9 are required per one reset node, in order to use the deterioration preventing structure having two reset nodes Qb1 and Qb2 A total of four switching elements were required. However, according to the present invention, only two switching elements Tr9 and Ds are needed in using the deterioration preventing structure having two reset nodes. That is, in the present invention, the pull-down switching device Ds and the set-discharging switching device Tr9 are constituted by a dual gate switching device, and each of these gate electrodes is connected to the first and second reset nodes Qb1 and Qb2 The deterioration preventing structure can be constituted by only two switching elements (one pull-up switching element Ds and one set discharging switching element Tr9).

For example, when the first AC voltage (Vac1) is maintained at a high voltage and the second AC voltage (Vac2) is maintained at a low voltage, The set node Qb1 is charged to a high voltage and the second reset node Qb2 is discharged to the discharge voltage VSS. Each of the top-gate electrodes of the ninth switching device Tr9 and the pull-down switching device Ds is supplied with a bias voltage in the positive polarity direction, while the ninth switching device Tr9 and the pulldown switching device Ds Each bottom-gate electrode receives a negative bias voltage. On the other hand, considering another specific frame period in which the first AC voltage Vac1 is maintained at the low voltage and the second AC voltage Vac2 is maintained at the high voltage, in the reset period of the n-th stage STn, The set node Qb1 is discharged to the discharging voltage VSS and the second reset node Qb2 is charged to the high voltage. Each of the top-gate electrodes of the ninth switching element Tr9 and the pull-down switching element Ds is supplied with a bias voltage in the negative polarity direction while the ninth switching element Tr9 and the pulldown switching element Ds Each bottom-gate electrode receives a positive bias voltage. Since the gate electrodes of the ninth switching element Tr9 and the pull-down switching element Ds are biased alternately in positive and negative polarities on a frame-by-frame basis, the ninth switching element Tr9 and the pulldown switching element Ds are deteriorated Can be prevented.

Hereinafter, the operation of the n-th stage STn shown in FIG. 3 will be described with reference to FIGS. 2 and 3. FIG.

First, the operation of the n-th stage STn in the first period T1 included in the first frame period will be described. The first period T1 corresponds to the set period of the n-th stage STn. Here, it is assumed that during the first frame period, the first AC voltage Vac1 is maintained at a high voltage and the second AC voltage Vac2 is maintained at a low voltage.

1) the first period ( T1 )

In this first period T1, as shown in Fig. 2, a first clock pulse CLK1 is generated from the (n-4) th stage STn-4 based on the first clock pulse CLK1, And the n-4th scan pulse (SPn-4) becomes the high level. Thus, the first switching device Tr1 is turned on. Then, the charging voltage VDD is supplied to the set node Q through the turned-on first switching element Tr1. Therefore, the seventh switching element Tr7, the eighth switching element Tr8, and the pull-up switching element (hereinafter, referred to as " Us are all turned on.

The seventh switching element Tr7 is turned on so that the discharging voltage VSS is applied to the first reset node Qb and the eighth switching element Tr8 is turned on, The discharging voltage VSS is applied to the second reset node Qb through this. Meanwhile, as the first AC voltage is held at the high voltage during the first frame period, the third switching device Tr3 and the sixth switching device Tr6, which are supplied with the first AC voltage, maintain the turn-on state during the frame period, The fourth switching device Tr4 and the fifth switching device Tr5, which are supplied with the second alternating voltage maintained at the low voltage during the frame period, maintain the turn-off state during the frame period. Accordingly, a high voltage is applied to the first reset node Qb1 through the turned-on third switching element Tr3, and the discharge voltage VSS is applied to the first reset node Qb1 through the sixth switching element Tr6 turned on. 2 reset node Qb2.

Accordingly, the first reset node Qb1 is supplied with the voltages of different levels, that is, the discharge voltage VSS by the seventh switching device Tr7 turned on and the third switching device Tr3 turned on Is applied at the same time. However, since the seventh switching device Tr7 is designed to have a larger channel area than the third switching device Tr3, when the two switching devices are all turned on, the first reset node Qb1 The discharge voltage VSS provided from the seventh switching device Tr7 having a relatively larger area is applied. Therefore, the first and second reset nodes Qb1 and Qb2 are both discharged to the low state, and the ninth switching (Qb1 and Qb2) connected through the gate electrode to the discharged first and second reset nodes Qb1 and Qb2 The element Tr9 and the pull-down switching element Ds are turned off.

Meanwhile, since the scan pulse (SPn + 4) from the (n + 4) th stage STn + 4 is in the low state during the first period T1, the second switching element Tr2 supplied thereto is in the turn-off state .

As described above, in the first period T1, the set node Q of the n-th stage STn is charged and the first and second reset nodes Qb1 and Qb2 are discharged, whereby the n-th stage STn is set .

Next, the operation of the n-th stage STn in the second period T2 included in the first frame period will be described. The second period T2 corresponds to the output period of the n-th stage STn.

2) the second period ( T2 )

In the second period T2 of the first frame period, as shown in Fig. 2, the first clock pulse CLK1 and the n-4th scan pulse SPn-4 described above are all changed to the low state , While the fifth clock pulse CLK5 goes high.

As described above, as the n-4th scan pulse SPn-4 is changed to the low state, the first switching element Tr1 supplied thereto is turned off. As a result, the set node Q is brought into a floating state. Here, the set node Q in the floating state is charged with the charging voltage VDD supplied in the previous first period T1. Therefore, the seventh switching element Tr7, the eighth switching element Tr8, and the pull-up switching element Us, which are connected to the set node Q in the floating state through the gate electrode, remain in the turn-on state .

The aforementioned fifth clock pulse CLK6 in the high state is applied to the source electrode of the turn-on pull-up switching element Us. At this time, as the set node Q is kept in the floating state, when the fifth clock pulse CLK5 in the high state is applied to the source electrode of the pull-up switching device Us, The voltage of the set node Q is bootstrapped by the coupling phenomenon. That is, the voltage of the set node Q is raised by bootstrapping. As the voltage of the set node Q is bootstrapped, the pull-up switching device Us is almost completely turned on so that the nth scan pulse SPn can be stably generated. The nth scan pulse SPn is supplied to the n-th gate line through the output terminal OT of the n-th stage STn, the n-4th stage STn-4 and the (n + 4) th stage STn + .

Next, the operation of the n-th stage STn in the third period T3 included in the first frame period will be described. The third period T3 corresponds to the reset period of the n-th stage STn.

3) The third period ( T3 )

In this first period T1, as shown in Fig. 2, a first clock pulse CLK1 is generated from the (n + 4) th stage STn + 4 based on the first clock pulse CLK1, And the (n + 4) th scan pulse (SPn + 4) is in a high state. Meanwhile, the first clock pulse CLK1 generated in the third period T3 is also supplied to the n-4th stage STn-4, but the n-4th stage STn- The scan pulse can not be output even if the first clock pulse CLK1 is input.

The n + 4th scan pulse SPn + 4 in the high state is applied to the second switching element Tr2 of the n-th stage STn. Accordingly, the second switching device Tr2 is turned on, and the discharging voltage VSS is applied to the set node Q through the turned-on second switching device Tr2. Therefore, the seventh switching element Tr7, the eighth switching element Tr8, and the pull-up switching element (the first switching element Tr2) are connected to the set node Q by discharging the set node Q to a low state, Us are all turned off.

Here, when the seventh switching device Tr7 is turned off, the voltage of the first reset node Qb1 is set to the first AC voltage Vac1 from the third switching device Tr3 in the turn-on state . That is, the first reset node Qb1 is charged to a high voltage.

On the other hand, the eighth switching element Tr8 is turned off, but the sixth reset element Tr6 is still turned on, so that the second reset node Qb2 is maintained in the discharged state.

Therefore, the ninth switching element Tr9 and the pulldown switching element Ds connected to the charged first reset node Qb1 and the discharged second reset node Qb2 through the gate electrode are turned on. Then, the discharge voltage VSS is applied to the set node Q through the turned-on ninth switching element Tr9, and the discharge voltage VSS is discharged through the turn-on pull-down switching element Ds Is applied to the terminal OT. Therefore, both the set node Q and the output terminal OT are discharged.

As described above, in the third period T3, the set node Q and the second reset node Qb2 of the n-th stage STn are discharged and the first reset nodes Qb1 and Qb2 are charged, The stage STn is reset.

Therefore, in this third period T3, the top-gate electrodes of the ninth switching device Tr9 and the pull-down switching device Ds are supplied with the bias voltage in the positive polarity direction (high voltage Vac1) Each of the bottom-gate electrodes of the ninth switching element Tr9 and the pull-down switching element Ds receives a negative bias voltage (discharge voltage VSS).

On the other hand, assuming that the first AC voltage Vac1 is maintained at the low voltage and the second AC voltage Vac2 is maintained at the high voltage during the second frame period, in the third period T3, the nth stage STn, The ninth switching element Tr9 and the pull-down switching element Ds are supplied with a bias voltage (discharge voltage VSS) in the negative polarity direction, while the ninth switching element Tr9 and the pull- Each bottom-gate electrode of the pull-down switching device Ds receives a bias voltage (high voltage Vac2) in the positive direction.

The ninth switching element Tr9 and the pulldown switching element Ds are constituted by a dual gate switching element. The construction of the dual gate switching element will be described in detail as follows.

4 is a diagram illustrating a dual gate switching device according to the first embodiment.

The dual gate switching device includes a bottom-gate electrode GE_B formed on a substrate (lower substrate of the liquid crystal panel) and a bottom-gate electrode GE_B formed on the bottom-gate electrode GE_B as shown in FIGS. A drain electrode DE and a source electrode SE formed on both sides of the oxide semiconductor layer ACT and a drain electrode DE and a source electrode SE formed on both sides of the oxide semiconductor layer ACT, A top-gate electrode GE_T formed on the gate insulating film GI so as to overlap the oxide semiconductor layer ACT and a top-gate electrode GE_T formed on the front surface of the substrate including the top- (PAS) formed on the substrate.

4B is a view showing a state of the dual gate switching device when a positive bias voltage is applied to the top-gate electrode GE_T. As shown in FIG. 4B, the top-gate electrode GE_T, It can be seen that charge is generated in the front channel (CH_F) between the oxide semiconductor layers (ACT). 4C shows a state of the dual gate switching device when a positive bias voltage is applied to the bottom-gate electrode GE_B. As shown in FIG. 4C, the bottom-gate electrode GE_B and the bottom- It can be seen that charge is generated in the back channel (CH_B) between the oxide semiconductor layers (ACT).

5 is a view illustrating a dual gate switching device according to a second embodiment of the present invention.

5A and 5B, the dual gate switching device includes a bottom-gate electrode GE_B formed on a substrate (a lower substrate of a liquid crystal panel) and a bottom-gate electrode GE_B formed on the substrate A gate insulating film GI formed on the entire surface of the substrate including the bottom gate electrode GE_B and an oxide semiconductor layer ACT formed on the gate insulating film GI so as to overlap the bottom gate electrode GE_B, And a drain electrode DE and a source electrode SE formed on both sides of the oxide semiconductor layer ACT and a drain electrode DE and a source electrode SE, And a top-gate electrode GE_T formed on the passivation layer PAS to overlap the oxide semiconductor layer ACT.

5B shows a state of the dual gate switching device when a positive bias voltage is applied to the top-gate electrode GE_T. As shown in FIG. 5B, the top-gate electrode GE_T and the top- It can be seen that charge is generated in the front channel (CH_F) between the oxide semiconductor layers (ACT). 5C shows a state of the dual gate switching device when a positive bias voltage is applied to the bottom-gate electrode GE_B. As shown in FIG. 5C, the bottom-gate electrode GE_B and the bottom- It can be seen that charge is generated in the back channel (CH_B) between the oxide semiconductor layers (ACT).

The ninth switching element Tr9 and the pull-down switching element Ds described above may have the structure as shown in Fig. 4 or Fig. 5 described above.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Tr #: Tr # switching element Us: Pull-up switching element
Ds: Pulldown switching element SP #: 1st scan pulse
CLK #: Clock pulse # CL #: Clock pulse #
Q: Set node Qb #: Node #
OT; Output terminal NC: node control section
OU: Output section VDD: Charging voltage
VSS: discharge voltage VDL: charging power supply line
Vac #: No. AC Voltage VAL #: No. AC Power Line

Claims

A plurality of stages for outputting a scan pulse through an output terminal;
In each stage,
A first switching element controlled in accordance with a scan pulse from the front stage and connected between a set power supply line and a set node for transmitting a charging voltage;
A second switching element connected between the set node and a discharge power supply line for transmitting a discharge voltage, the second switching element being controlled in accordance with a scan pulse from a rear stage;
A third switching device controlled according to a first AC voltage from a first AC power supply line and connected between the first AC power supply line and a first reset node;
A fourth switching device controlled according to a second AC voltage from a second AC power supply line and connected between the second AC power supply line and a second reset node;
A fifth switching device controlled according to the second AC voltage, the fifth switching device being connected between the first reset node and the discharging power supply line;
A sixth switching device controlled according to the first AC voltage, the sixth switching device being connected between the second reset node and the discharging power supply line;
A seventh switching device controlled according to a voltage of the set node, the seventh switching device being connected between the first reset node and the discharging power supply line;
An eighth switching device controlled according to a voltage of the set node, the eighth switching device being connected between the second reset node and the discharging power supply line; And
And a ninth switching element controlled in accordance with at least one of the voltage of the first reset node and the voltages of the second reset node and connected between the set node and the discharge power supply line. .

The method according to claim 1,
Wherein each of the stages includes:
Further comprising a pulldown switching element controlled in accordance with at least one of a voltage of the first reset node and a voltage of the second reset node and connected between the output terminal and the discharge power supply line register.

3. The method of claim 2,
Wherein the ninth switching element and the pull-down switching element are dual gate switching elements having a top-gate electrode and a bottom-gate electrode.

The method of claim 3,
A top-gate electrode of the ninth switching element is connected to the first reset node, and a bottom-gate electrode thereof is connected to the second reset node; And,
A top-gate electrode of the pull-down switching element is connected to the first reset node, and a bottom-gate electrode thereof is connected to the second reset node.

The method according to claim 1,
In each stage,
And a pull-up switching element connected between the clock transmission line and the output terminal, the pull-up switching element being controlled according to the voltage of the set node and transmitting a clock pulse.