KR101201308B1 - A shift register - Google Patents

Abstract

The present invention relates to a shift register that can prevent deterioration of a pull-down transistor, and alternately charges / discharges a node connected to a gate terminal of a pull-down transistor every period so that the pull-down transistor is turned on or off every period. It is characterized by providing a shift register which can be prevented from deterioration of the pull-down transistor by being turned off.

LCD, Shift Register, Scan Pulse, Pull-Up Transistor, Pull-Down Transistor

Description

A shift register

1 is a view showing a conventional shift register

2 illustrates a shift register according to an embodiment of the present invention.

3 is a detailed configuration diagram of the second stage of FIG.

4 is a diagram illustrating a circuit configuration of a node controller and an output unit provided in the second stage of FIG. 3.

FIG. 5 is a diagram illustrating first to third stages having the circuit configuration of FIG. 4. FIG.

6 is a timing diagram of various signals supplied to each stage of FIG. 5 and scan pulses output from the stage.

7 is a timing diagram of a four-phase clock pulse and a voltage waveform of a second node.

* Explanation of symbols on the main parts of the drawings

BST1 to BSTn: first to nth stage BSTn + 1: first dummy stage

BSTn + 2: second dummy stage VDD: first voltage source VSS: second voltage source SP: start pulses Vout1 to Voutn + 2: first to n + 2 scan pulses

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display device, and more particularly, to a shift register that can prevent deterioration of a pull-down transistor by inverting a voltage polarity of a node every period.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The timing controller controls the driving timings of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or depressurizes the input power source to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display device. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a view showing a conventional shift register.

As shown in FIG. 1, the conventional shift register includes n stages AST1 to ASTn and one dummy stage ASTn + 1 connected dependently to each other. Here, each of the stages AST1 to ASTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 sequentially from the first stage AST1 to the dummy stage ASTn + 1. To Voutn + 1). In this case, scan pulses Vout1 to Voutn output from the stages AST1 to ASTn except for the dummy stage ASTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

The entire stages AST1 to ASTn + 1 of the shift register configured as described above are configured with the first voltage source VDD and the second voltage source VSS, and the first to fourth clock pulses CLK1 to CLK4 having sequential phase differences with each other. Two clock pulses are received. Here, the first voltage source VDD means a positive voltage source, and the second voltage source VSS means a ground voltage.

Meanwhile, the first stage AST1 positioned at the uppermost side of the stages AST1 to ASTn + 1 may include a start pulse (in addition to the first voltage source VDD, the second voltage source VSS, and the two clock pulses). SP).

The operation of the conventional shift register configured as described above will be described in detail as follows.

First, when a start pulse SP from a timing controller (not shown) is applied to the first stage AST1, the first stage AST1 is enabled in response to the start pulse SP.

Subsequently, the enabled first stage AST1 receives the first and second clock pulses CLK1 to CLK2 from the timing controller, and outputs the first scan pulse Vout1, and the first gate line and the first gate line. It is supplied together to the 2 stage AST2. Then, the second stage AST2 is enabled in response to the first scan pulse Vout1.

Subsequently, the enabled second stage AST2 receives the second and third clock pulses CLK2 and CLK3 from the timing controller and outputs a second scan pulse Vout2, and the second gate line, The third stage AST3 and the first stage AST1 are supplied together. Then, the third stage AST3 is enabled in response to the second scan pulse Vout2, and the first stage AST1 is disabled in response to the second scan pulse Vout2. A second voltage source VSS is supplied to the first gate line.

Subsequently, the enabled third stage AST3 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller, and outputs a third scan pulse Vout3, and the third gate line, The fourth stage AST4 and the second stage AST2 are supplied together. Then, the fourth stage AST4 is enabled in response to the third scan pulse Vout3, and the second stage AST2 is disabled in response to the third scan pulse Vout3. A second voltage source VSS is supplied to the second gate line.

In this manner, the fourth to nth scan pulses Voutn are sequentially output to the remaining fourth to nth stages AST4 to ASTn and sequentially applied to the fourth to nth gate lines. As a result, the first to nth gate lines are sequentially scanned by the sequentially output first to nth scan pulses Vout1 to Voutn.

Meanwhile, the dummy stage ASTn + 1 is enabled in response to the nth scan pulse Voutn from the nth stage ASTn, and then receives two clock pulses from the timing controller. One scan pulse Voutn + 1 is supplied to the nth stage ASTn so that the nth stage ASTn is disabled to provide the second voltage source VSS to the nth gate line. In other words, the dummy stage ASTn + 1 merely provides the n + 1 scan pulse Voutn + 1 so that the nth stage ASTn can output the second voltage source VSS. The n + 1th scan pulse Voutn + 1 is not supplied to the gate line. Therefore, the total number of stages including the dummy stage ASTn + 1 is always one more than the number of gate lines.

In general, the first to nth stages AST1 to ASTn and the dummy stage ASTn + 1 may include a node controller for controlling charge and discharge states of the first and second nodes, and the first and second nodes. According to the state of the node outputs a scan pulse or the second voltage source (VSS) and has an output for supplying it to the gate line of the liquid crystal panel.

The output section includes a pull-up transistor having a gate terminal connected to the first node and a pull-down transistor having a gate terminal connected to the second node.

Here, the first node and the second node are alternately charged and discharged. Specifically, when the first node is charged, the second node maintains a discharged state, and when the second node is charged The first node is maintained in a discharged state. In this case, each of the stages AST1 to ASTn + 1 outputs a scan pulse only in one horizontal period 1H of one frame, and outputs a second voltage source for the remaining period. Accordingly, the pull-up transistor of the output unit is turned on only one horizontal period, and the pull-down transistor remains turned on for the remaining period except the period. In other words, the pull-down transistor remains turned on for most of one frame. This accelerates deterioration of the pull-down transistor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and alternately charges / discharges a node connected to a gate terminal of a pull-down transistor every period so that the pull-down transistor is turned on or off every period. It is an object of the present invention to provide a shift register that can prevent deterioration of the pull-down transistor.

The shift registers according to the present invention for achieving the above object are at least two clocks having different phases in a shift register having a plurality of stages connected to each other and sequentially outputting scan pulses. Each stage receiving the pulse comprises: a first switching element for charging the first node with a high potential voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging the first node to a low potential voltage source in response to a scan pulse output from a next stage; A third switching device configured to charge the second node with the first clock pulse in response to the first clock pulse output delayed from the start pulse and the scan pulse from the previous stage; A fourth switching element for discharging the second node to the second voltage source in response to the second clock pulse synchronized with the scan pulse output from the next stage; A fifth switching device for discharging the second node to the second voltage source in response to the scan pulse output from the current stage; A pull-up switching device for outputting the first clock pulse as a scan pulse and supplying the first clock pulse to a gate line, a previous stage, and a next stage of the liquid crystal panel in response to a high potential voltage source charged in the first node; And a pull-down switching device for supplying a low potential voltage source to the gate line, the previous stage, and the next stage of the liquid crystal panel in response to the first clock pulse charged in the second node. do.

2 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the shift register according to the first embodiment of the present invention includes n stages BST1 to BSTn and a dummy stage BSTn + 1 connected to each other. Here, all the stages BST1 to BSTn + 1 output one scan pulse Vout1 to Voutn + 2, and in this case, the scan pulse Vout1 is sequentially performed from the first stage BST1 to the dummy stage BSTn + 1. To Voutn + 1). Here, scan pulses Vout1 to Voutn output from the stages BST1 to BSTn except for the dummy stage BSTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

On the other hand, the entire stages BST1 to BSTn + 1 of the shift registers configured as described above are circulated with the first voltage source VDD and the second voltage source VSS, and have a sequential phase difference to each other. CLK1, CLK2) are authorized. Here, the first voltage source VDD refers to a positive voltage source as a high potential voltage source, and the second voltage source VSS refers to a negative voltage source as a low potential voltage source.

Here, the first stage BST1 positioned on the uppermost side of the stages BST1 to BSTn + 1 may include the first voltage source VDD, the second voltage source VSS, and the first and second clock pulses. In addition to CLK1 and CLK2), a start pulse SP is supplied.

Meanwhile, as described above, the first and second clock pulses CLK1 and CLK2 are phase-delayed by one pulse width and output. That is, the second clock pulse CLK2 is phase-delayed by one pulse width than the first clock pulse CLK1 and output.

Meanwhile, the start pulse SP applied to the first stage BST1 among the stages BST1 to BSTn + 1 is output earlier than the clock pulses CLK1 to CLK4. That is, the start pulse SP is output by one clock pulse width ahead of the first clock pulse CLK1. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is outputted first in every frame, the first and second clock pulses CLK1 and CLK2 are sequentially output.

At this time, the first and second clock pulses CLK1 and CLK2 are sequentially output, and are also output while circulating. That is, after the first clock pulse CLK1 is output, the second clock pulse CLK2 is output, after which the first clock pulse CLK1 is output, and the second clock pulse CLK2 is output again.

Herein, the configuration of each stage BST1 to BSTn + 1 provided in the shift register according to the first embodiment of the present invention will be described in more detail. Here, since the configurations of the second to nth stages BST2 to BSTn and the dummy stages BSTn + 1 are the same, only the second stage BST2 will be representatively described.

FIG. 3 is a detailed configuration diagram of the second stage of FIG. 2.

That is, as illustrated in FIG. 3, the second stage BST2 may include a node controller 300a that controls charging and discharging of the first node Q and charging and discharging of the second node QB. And an output unit 300b that outputs a scan pulse or a second voltage source VSS according to the states of the first and second nodes QB and supplies them to the second gate line of the liquid crystal panel.

The output unit 300b may include a pull-up transistor Tru that scan pulses to a second gate line when the first node Q is in a charged state, and when the second node QB is in a charged state. And a pull-down transistor Trd for supplying a second voltage source VSS to the second gate line.

Here, the first node Q and the second node QB are alternately charged and discharged. Specifically, when the first node Q is in a charged state, the second node QB is discharged. The first node Q is discharged when the second node QB is in a charged state. The charging and discharging states of the first node Q and the second node QB are controlled by a plurality of switching elements (not shown) provided in the node controller 300a.

The remaining third to nth stages BST3 to BSTn and the dummy stage BSTn + 1 also have the same configuration as the second stage BST2.

Here, a circuit configuration of the node controller 300a and the output unit 300b included in the second stage BST2 will be described.

4 is a diagram illustrating a circuit configuration of a node controller and an output unit provided in the second stage of FIG. 3.

That is, as shown in FIG. 4, the node controller 400a of the second stage BST2 includes first to fifth NMOS transistors Tr1 to Tr5.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, the first NMOS transistor Tr1 of the second stage BST2 sets the first node Q to the first voltage source VDD in response to the first scan pulse Vout1 from the first stage BST1. Charge with. To this end, the gate terminal of the first NMOS transistor Tr1 is connected to the first stage BST1, the source terminal is connected to a power line for transmitting the first voltage source VDD, and the drain terminal is connected to the first node. It is connected to (Q).

The second NMOS transistor Tr2 discharges the first node Q to the second voltage source VSS in response to the scan pulse output from the next stage. That is, in response to the third scan pulse Vout3 from the third stage BST3, the second NMOS transistor Tr2 of the second stage BST2 connects the first node Q to the second voltage source ( VSS). To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to the third stage BST3, the source terminal is connected to the first node Q, and the drain terminal of the second voltage source VSS. It is connected to the transmitting power line.

The third NMOS transistor Tr3 charges the second node QB with the clock pulse in response to the clock pulse supplied to the source terminal of the pull-up transistor Tru. That is, the third NMOS transistor Tr3 charges the second node QB to the second clock pulse CLK2 in response to the second clock pulse CLK2. For this purpose, the gate terminal and the source terminal of the third NMOS transistor Tr3 are connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second node QB.

The fourth NMOS transistor Tr4 discharges the second node QB to the second voltage source VSS in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the fourth NMOS transistor Tr4 of the second stage BST2 is in response to the first clock pulse CLK1 synchronized with the third scan pulse Vout3 output from the third stage BST3. The second node QB is discharged to the second voltage source VSS.

The fifth NMOS transistor Tr5 discharges the second node QB to the second voltage source VSS in response to the scan pulse output from the stage to which the fifth NMOS transistor Tr5 belongs. That is, the fifth NMOS transistor Tr5 of the second stage BST2 responds to the second scan pulse Vout2 output from the second stage BST2, and thus, the fifth NMOS transistor Tr5 of the second stage BST2 receives the second NMOS transistor Tr5. The node QB is discharged to the second voltage source VSS. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to the second stage BST2, the source terminal is connected to the second node QB, and the drain terminal of the fifth voltage source VSS. It is connected to the power line to transmit.

The output unit 400b of the second stage BST2 includes the pull-up transistor Tru and the pull-down transistor Trd described above.

The pull-up transistor Tru is delayed by one clock pulse width than the scan pulse applied to the gate terminal of the first NMOS transistor Tr1 in response to the first voltage source VDD charged in the first node Q. The pulses are output as scan pulses. That is, the pull-up transistor Tru of the second stage BST2 outputs the second clock pulse CLK2 delayed by one pulse width from the first scan pulse Vout1 as the second scan pulse Vout2. The output second scan pulse Vout2 is supplied to the gate line connected to the stage to which it belongs, the stage at the previous stage, and the stage at the next stage. That is, the pull-up transistor Tru outputs the second clock pulse CLK2 as a second scan pulse Vout2 for driving a second gate line. The second scan pulse Vout2 is supplied to the second gate line, the first stage BST1, and the third stage BST3. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second gate. It is commonly connected to the line, the first stage BST1, and the third stage BST3. Here, the second scan pulse Vout2 supplied to the first stage BST1 disables the first stage BST1, and the second scan pulse Vout2 supplied to the third stage BST3 is The third stage BST3 is enabled.

The pull-down transistor Trd outputs the second voltage source VSS in response to the clock pulse charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage in the previous stage, and the stage in the next stage. That is, the pull-down transistor Trd of the second stage BST2 supplies the second voltage source VSS to the second gate line, the first stage BST1, and the third stage BST3. The second voltage source VSS supplied to the second gate line functions as a signal for deactivating the second gate line. To this end, the gate terminal of the pull-down transistor Trd is connected to the second node QB, and the source terminal is commonly connected to the second gate line, the first stage BST1, and the third stage BST3. The drain terminal is connected to a power line for transmitting the second voltage source VSS.

On the other hand, the first stage BST1, the third to nth stages BSTn, and the dummy stage BSTn + 1 also have the above configuration.

However, since the stage does not exist before the first stage BST1, the first NMOS transistor Tr1 included in the first stage BST1 receives the start pulse SP from the timing controller. That is, the first NMOS transistor Tr1 included in the first stage BST1 charges the first node Q to the first voltage source VDD in response to the start pulse SP from the timing controller. Let's do it.

In addition, for the same reason as described above, the drain terminal of the pull-up transistor Tru provided in the first stage BST1 is commonly connected to the first gate line and the second stage BST2, and the first stage BST1 is used. The source terminal of the pull-down transistor Trd included in the N-th transistor) is commonly connected to the first gate line and the second stage BST2.

There is no stage next to the dummy stage BSTn + 1. In addition, the dummy stage BSTn + 1 does not supply scan pulses to the gate lines, and the stage (i.e., the nth stage BSTn) does not supply the n + 1 scan pulse Voutn + 1 outputted from the dummy stage BSTn + 1. ) To disable the nth stage BSTn. Therefore, the drain terminal of the pull-up transistor Tru and the source terminal of the pull-down transistor Trd included in the dummy stage BSTn + 1 are commonly connected to the nth stage BSTn.

Meanwhile, the first to fifth NMOS transistors Tr1 to Tr5 and the pull-up and pull-down transistors Tru and Trd may use amorphous TFT (Tin Film Transistor). In addition, the stages BST1 to BSTn + 1 may be embedded in the liquid crystal panel.

Referring to the operation of the shift register according to an embodiment of the present invention configured as described above in detail.

FIG. 5 is a diagram illustrating first to third stages having the circuit configuration of FIG. 4. 6 is a timing diagram for various signals supplied to each stage of FIG. 5 and scan pulses output from the stage.

First, the operation during the enable period T0 will be described.

During the enable period TO, as shown in FIG. 6, only the start pulse SP output from the timing controller is kept high and the remaining start pulse SP is kept low.

The start pulse SP output from the timing controller is input to the first stage BST1. Specifically, as shown in FIG. 5, the start pulse SP is supplied to the gate terminal of the first NMOS transistor Tr1 provided in the first stage BST1. Then, the first NMOS transistor Tr1 is turned on, and a first voltage source VDD is applied to the first node Q through the turned-on first NMOS transistor Tr1.

During the enable period T0, as shown in FIG. 5, the first node Q of the first stage BST1 is charged to the first voltage source VDD.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 6, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Therefore, in response to the start pulse SP in the low state, the first NMOS transistor Tr1 of the first stage BST1 is turned off, and accordingly, the first node Q of the first stage BST1 is turned off. ) Remains floating.

Meanwhile, as the first node Q of the first stage BST1 is continuously maintained as the first voltage source VDD applied during the enable period T0, the pull-up transistor of the first stage BST1 Tru) remains turned on. In this case, as the first clock pulse CLK1 is applied to the source terminal of the turned-on pull-up transistor Tru, as shown in FIG. 6, the first node Q of the first stage BST1. The first voltage source VDD charged to is amplified by bootstrapping. Therefore, the first clock pulse CLK1 applied to the source terminal of the pull-up transistor Tru of the first stage BST1 is stably output through the drain terminal of the pull-up transistor Tru. In this case, as shown in FIG. 6, the output first clock pulse CLK1 is applied to a first gate line to serve as a first scan pulse Vout1 for driving the first gate line. The first scan pulse Vout1 is input to the gate terminal of the fifth NMOS transistor Tr5 provided in the first stage BST1 to turn on the tenth NMOS transistor Tr10. Then, the second voltage source VSS is supplied to the second node of the first stage BST1 through the turned-on fifth NMOS transistor Tr5.

On the other hand, the first clock pulse output in the first period is supplied to the gate terminal and the source terminal of the third NMOS transistor provided in the first stage, thereby turning on the third NMOS transistor. Through this turned-on third NMOS transistor, the first clock pulse is supplied to the second node of the first stage. As a result, in the first period, the second voltage source and the first clock pulse are supplied to the second node of the first stage. At this time, the channel width of the fifth NMOS transistor for supplying the second voltage source is set larger than the channel width of the third NMOS transistor for supplying the first clock pulse. The second node is maintained as a second voltage source. As a result, in the first period, the second node of the first stage maintains a discharge state.

On the other hand, the first scan pulse Vout1 output from the first stage BST1 in the first period T1 is also input to the second stage BST2. Specifically, as shown in FIG. 5, the first scan pulse Vout1 is input to the gate terminal of the first NMOS transistor Tr1 provided in the second stage BST2. Here, the first scan pulse Vout1 supplied to the second stage BST2 plays the same role as the start pulse SP supplied to the first stage BST1 and the first scan pulse Vout1. In response to the second stage BST2 is enabled. That is, the first node Q of the second stage BST2 is charged to the first voltage source VDD by the first scan pulse Vout1.

In summary, the first scan pulse Vout1 output from the first stage BST1 during the first period T1 drives the first gate line, and as shown in FIG. 6, the second stage. The first node Q of BST2 is charged.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 6, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

Accordingly, as the first scan pulse Vout1 from the first stage BST1 that has been applied in the first period T1 changes to a low state in the second period, the second stage that is applied through the gate terminal. The first NMOS transistor Tr1 of BST2 is turned off, so that the first node Q of the second stage BST2 remains in a floating state. Meanwhile, as the first node Q of the second stage BST2 is continuously maintained as the first voltage source VDD applied during the first period T1, the pull-up provided in the second stage BST2 is provided. The transistor Tru remains turned on. In this case, as the second clock pulse CLK2 is applied to the source terminal of the pull-up transistor Tru of the second stage BST2, the first node Q of the second stage BST2 is charged. One voltage source VDD is amplified by bootstrapping. Therefore, the second clock pulse CLK2 applied to the source terminal of the pull-up transistor Tru is stably output through the drain terminal of the pull-up transistor Tru. In this case, as shown in FIG. 6, the second clock pulse CLK2 output from the second stage BST2 is applied to a second gate line to drive the second gate pulse Vout2. Acts as).

Meanwhile, in the second period T2, the second stage BST2 uses its second node using the second scan pulse Vout2 output from itself, similarly to the above-described first stage BST1. Discharge.

The second scan pulse Vout2 output from the second stage BST2 is also input to the first stage BST1. Specifically, as shown in FIG. 5, the second scan pulse Vout2 is input to the gate terminal of the second NMOS transistor Tr6 provided in the first stage BST1. Here, as the second NMOS transistor Tr2 of the first stage BST1 is turned on by the second scan pulse Vout2, the second NMOS transistor whose turn-on of the second voltage source VSS is turned on. It is supplied to the first node Q of the first stage BST1 through Tr2. Therefore, as shown in FIG. 6, the first node Q of the first stage BST1 is discharged by the second voltage source VSS. As a result, the pull-up transistor Tru having the gate terminal connected to the first node Q of the first stage BST1 is turned off.

On the other hand, the second clock pulse CLK2 output in the second period T2 is also applied to the gate terminal of the fourth NMOS transistor Tr4 of the first stage BST1. The fourth NMOS transistor Tr4 of BST1 is turned on. At this time, the second voltage source VSS is supplied to the second node QB of the first stage BST1 through the turned-on fourth NMOS transistor Tr4. Therefore, as shown in FIG. 6, the second node QB of the first stage BST1 is discharged by the second voltage source VSS.

During the second period T2, the second scan pulse Vout2 is output from the second stage BST2. This second scan pulse Vout2 drives the second gate line. In addition, the second scan pulse Vout2 discharges the first node of the first stage BST1 and charges the first node of the third stage. The second clock pulse output in synchronization with the second scan pulse discharges the second node of the first stage.

Next, in the third period T3, the third stage BST3 outputs the first clock pulse CLK1 as the third scan pulse Vout3 to drive the third gate line. The third scan pulse Vout3 is also supplied to the second stage BST2 and the fourth stage BST4 to disable the second stage BST2 and to enable the fourth stage BST4.

The first clock pulse CLK1 output in the third period T3 is also supplied to the gate terminal and the source terminal of the third NMOS transistor Tr3 provided in the first stage BST1. Therefore, during the third period T3, the third NMOS transistor Tr3 of the first stage BST1 is turned on. The first clock pulse CLK1 is supplied to the second node QB of the first stage BST1 through the turned-on third NMOS transistor Tr3. Then, the second node QB of the first stage BST1 is charged, and the pull-down transistor Trd of the first stage BST1 connected to the charged second node QB is turned on. Through this turned on pull-down transistor Trd, the second voltage source VSS is supplied to the first gate line. As a result, during the third period T3, the first node Q of the first stage BST1 maintains a discharge state, and the second node QB is charged.

Thereafter, in the fourth period T4, the fourth stage BST4 outputs the second clock pulse CLK2 as the fourth scan pulse Vout4. The fourth scan pulse Vout4 disables the third stage BST3 and enables the fifth stage. On the other hand, the second clock pulse CLK2 output in the fourth period T4 is supplied to the second stage BST2. Thus, in the manner as described above, in response to the second clock pulse CLK2, the second stage BST2 charges its second node QB to the second clock pulse CLK2.

In the fourth period T4, as the first clock pulse CLK1 changes to low, the third NMOS transistor Tr3 of the first stage BST1 is turned off. The second clock pulse CLK2 output in the fourth period T4 is supplied to the gate terminal of the fourth NMOS transistor Tr4 of the first stage BST1. Then, the fourth NMOS transistor Tr4 of the first stage BST1 is turned on. Through the turned-on fourth NMOS transistor Tr4, the second voltage source VSS is supplied to the second node QB of the first stage BST1. Accordingly, the second node QB of the first stage BST1 is discharged. As a result, in the fourth period T4, the second node QB of the first stage BST1 maintains a discharge state. Of course, the first node Q of the first stage BST1 maintains a discharge state.

Next, in the fifth period T5, the fifth stage outputs the first clock pulse CLK1 as the fifth scan pulse. This fifth scan pulse disables the fourth stage BST4 and enables the sixth stage. On the other hand, the first clock pulse CLK1 output in the fifth period T5 is supplied to the first and third stages BST1 and BST3 again, and the second node QB of the first stage BST1 is provided. And charge the second node QB of the third stage BST3. In addition, the first clock pulse CLK1 output in the fifth period T5 is supplied to the second and fourth stages BST2 and BST4 to discharge the second node QB of the second stage BST2. In addition, the second node QB of the fourth stage BST4 is discharged.

In this manner, one scan pulse Vout1 to Voutn + 1 is output from the sixth stage to the dummy stage BSTn + 1 for one frame. At this time, as described above, the second node QB of each stage BST1 to BSTn + 1 is alternately charged and discharged every period. Therefore, it is possible to prevent deterioration of the switching element, that is, the pull-down transistor Trd, of the output unit 400b connected to the second node QB.

In other words, each stage BST1 to BSTn + 1 outputs the clock pulse input thereto to the scan pulses Vout1 to Voutn + 1, and after the scan pulses Vout1 to Voutn + 1 are outputted to itself. The supplied clock pulse CLK1 or CLK2 is continuously supplied to its second node QB. Therefore, the voltage waveform of the second node QB of each stage BST1 to BSTn + 1 is the same as the waveform of the clock pulse CLK1 or CLK2. As a result, as described above, the second node QB is charged every time the clock pulse CLK1 or CLK2 is output (ie, indicates a high state), and every time the clock pulse CLK1 or CLK2 is not output. Discharged (i.e., low state). Accordingly, since the pull-down transistor Trd having the gate terminal connected to the second node QB is alternately turned on and off every period, the pull-down transistor Trd configured in the shift register of the present invention is Deterioration is prevented. Of course, this clock pulse CLK1 or CLK2 means a clock pulse supplied to the source terminal of the pull-up transistor Tru of each stage.

7 is a diagram illustrating a timing diagram of a four-phase clock pulse and a voltage waveform of a second node. When four phases are used, the voltage waveform of the first node of the first stage has the same waveform as that of the first clock pulse. Indicates.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The shift register according to the present invention deteriorates the pull-down transistor by alternately charging / discharging the node to which the gate terminal of the pull-down transistor is connected in every period so that the pull-down transistor is turned on or off every period. Can be prevented.

Claims (6)

A shift register having a plurality of stages which are connected to each other dependently and sequentially output scan pulses, Each stage receives at least two clock pulses having different phases, A first switching element for charging the first node with a high potential voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging the first node to a low potential voltage source in response to a scan pulse output from a next stage; A third switching device configured to charge a second node with the first clock pulse in response to the first clock pulse output delayed from the start pulse and the scan pulse from the previous stage; A fourth switching element for discharging the second node to a low potential voltage source in response to the second clock pulse synchronized with the scan pulse output from the next stage; A fifth switching element for discharging the second node to a low potential voltage source in response to the scan pulse output from the current stage; A pull-up switching device for outputting the first clock pulse as a scan pulse and supplying the first clock pulse to a gate line, a previous stage, and a next stage of the liquid crystal panel in response to a high potential voltage source charged in the first node; And And a pull-down switching element for supplying a low potential voltage source to the gate line, the previous stage, and the next stage of the liquid crystal panel in response to the first clock pulse charged in the second node. . The method of claim 1, And the first to fifth switching elements, and the pull-up and pull-down switching elements are amorphous thin film transistors (TFTs). The method of claim 1, And the stages are built in the liquid crystal panel. The method of claim 1, Each of the clock pulses is repeatedly output with a predetermined period, and each of the clock pulses are sequentially output to each other. The method of claim 1, And the start pulse is supplied to a first stage which outputs a scan pulse first of the stages. The method of claim 1, And the channel width of the fifth switching element is larger than the channel width of the third switching element.

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