KR101232147B1 - A liquid crystal display device and a method for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof, which can increase a lifetime of a stage, comprising: a plurality of stages sequentially driving a gate line of a liquid crystal panel by outputting scan pulses; At least one dummy stage supplied with scan pulses from any one of the stages to disable any second stage; And at least one dummy gate line receiving the scan pulse output from the dummy stage.

LCD, shift register, scan pulse, pull-up switching element, pull-down switching element

Description

[0001] The present invention relates to a liquid crystal display device and a method of driving the same,

1 is a view showing a conventional shift register

2 is a view showing a liquid crystal display device according to an embodiment of the present invention.

3 shows an RC rod connected in parallel with a dummy stage.

4 shows an RC rod connected in series with a dummy stage;

5 is a view showing the shape of the output terminal provided in the dummy stage

FIG. 6 is a detailed configuration diagram of the second stage of FIG. 2.

7 is a diagram illustrating a circuit configuration of a node controller and an output unit provided in the second stage.

8 is a view showing first to third stages having the circuit configuration of FIG.

FIG. 9 is a diagram illustrating a scan pulse output from a stage of FIG. 8 and timing signals of various signals supplied to the stage.

* Explanation of symbols on the main parts of the drawings

BST1 to BSTn: stage BSTn + 1: dummy stage

CLK1 to CLK4: Clock pulse SP: Start pulse

VDD: first voltage source VSS: second voltage source

Vout1 to Voutn + 1: Scan pulse 200: Liquid crystal panel

PXL: Pixel GL1 to GLn: Gate Line

GLn + 1: dummy gate lines DL1 to DLm: data line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of extending the life of a shift register.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a drain terminal and a source terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The timing controller controls the driving timings of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or depressurizes the input power source to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display device. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a view showing a conventional shift register.

As shown in FIG. 1, the conventional shift register includes n stages AST1 to ASTn and one dummy stage ASTn + 1 connected dependently to each other. Here, each of the stages AST1 to ASTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 sequentially from the first stage AST1 to the dummy stage ASTn + 1. To Voutn + 1). In this case, scan pulses Vout1 to Voutn output from the stages AST1 to ASTn except for the dummy stage ASTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

The entire stages AST1 to ASTn + 1 of the shift register configured as described above are configured with the first voltage source VDD and the second voltage source VSS, and the first to fourth clock pulses CLK1 to CLK4 having sequential phase differences with each other. Two clock pulses are received. Here, the first voltage source VDD means a positive voltage source, and the second voltage source VSS means a ground voltage.

Meanwhile, the first stage AST1 positioned at the uppermost side of the stages AST1 to ASTn + 1 may include a start pulse (in addition to the first voltage source VDD, the second voltage source VSS, and the two clock pulses). SP).

The operation of the conventional shift register configured as described above will be described in detail as follows.

First, when a start pulse SP from a timing controller (not shown) is applied to the first stage AST1, the first stage AST1 is enabled in response to the start pulse SP.

Subsequently, the enabled first stage AST1 receives the first and second clock pulses CLK1 to CLK2 from the timing controller, and outputs the first scan pulse Vout1, and the first gate line and the first gate line. It is supplied together to the 2 stage AST2. Then, the second stage AST2 is enabled in response to the first scan pulse Vout1.

Subsequently, the enabled second stage AST2 receives the second and third clock pulses CLK2 and CLK3 from the timing controller and outputs a second scan pulse Vout2, and the second gate line, The third stage AST3 and the first stage AST1 are supplied together. Then, the third stage AST3 is enabled in response to the second scan pulse Vout2, and the first stage AST1 is disabled in response to the second scan pulse Vout2. A second voltage source VSS is supplied to the first gate line.

Subsequently, the enabled third stage AST3 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller, and outputs a third scan pulse Vout3, and the third gate line, The fourth stage AST4 and the second stage AST2 are supplied together. Then, the fourth stage AST4 is enabled in response to the third scan pulse Vout3, and the second stage AST2 is disabled in response to the third scan pulse Vout3. A second voltage source VSS is supplied to the second gate line.

In this manner, the fourth to nth scan pulses Voutn are sequentially output to the remaining fourth to nth stages AST4 to ASTn and sequentially applied to the fourth to nth gate lines. As a result, the first to nth gate lines are sequentially scanned by the sequentially output first to nth scan pulses Vout1 to Voutn.

Meanwhile, the dummy stage ASTn + 1 is enabled in response to the nth scan pulse Voutn from the nth stage ASTn, and then receives two clock pulses from the timing controller. One scan pulse Voutn + 1 is supplied to the nth stage ASTn so that the nth stage ASTn is disabled to provide the second voltage source VSS to the nth gate line. In other words, the dummy stage ASTn + 1 merely provides the n + 1 scan pulse Voutn + 1 so that the nth stage ASTn can output the second voltage source VSS. The n + 1th scan pulse Voutn + 1 is not supplied to the gate line. Therefore, the total number of stages including the dummy stages ASTn + 1 is always greater than the number of gate lines.

In general, the first to nth stages ASTn and the dummy stage ASTn + 1 may include a node controller for controlling charge and discharge states of the first and second nodes, and According to the state, the first scan pulse Vout1 or the second voltage source VSS is output and has an output part which supplies the same to the gate line of the liquid crystal panel.

Here, the first node and the second node are alternately charged and discharged. Specifically, when the first node is charged, the second node maintains a discharged state, and when the second node is charged The first node is maintained in a discharged state.

In this case, when the first node is in a charged state, a scan pulse is output from the pull-up switching device of the output unit, and when the second node is in a charged state, a second voltage source is output from the pull-down switching device of the output unit. Of course, the scan pulse output from the pull-up switching element and the second voltage source output from the pull-down switching element are supplied to the corresponding gate line. The gate terminal of the pull-up switching element is connected to the first node, the drain terminal is connected to a clock line to which a clock pulse is applied, and the source terminal is connected to the gate line. The clock pulse is periodically supplied to the drain terminal of the pull-up switching device. In this case, the pull-up switching device outputs any one of the clock pulses input for each period at a specific time point. The clock pulse output at this particular time point is a scan pulse for driving the gate line. This specific time point means a time point at which the first node is charged. That is, the pull-up switching device outputs, as a scan pulse, the clock pulse input at the specific time point (ie, the time point at which the first node is charged) among the clock pulses which are periodically input to its drain terminal. Done. After the output of the scan pulse, the pull-up switching device outputs one scan pulse per frame as the first node is kept in a discharge state until the next frame starts. However, since the clock pulses are output several times during one frame, even when the pull-up switching device is turned off, that is, even when the first node is discharged, the clock pulses continue to the drain terminal of the pull-up switching device. Will be entered.

In other words, the pull-up switching device is turned on only once for one frame, and outputs a clock pulse input to its drain terminal as a scan pulse during this turn-on period. Thereafter, the pull-up switching device is turned off until the next frame starts, so that the pull-up switching device outputs it as a scan pulse no matter how clock pulse is input to its drain terminal during this turn-off period. Can not. However, as the clock pulse is periodically applied to the drain terminal of the pull-up switching device, a coupling phenomenon occurs between the first node to which the gate terminal of the pull-up switching device is connected and the drain terminal of the pull-up switching device. . Due to such a coupling phenomenon, the first node is continuously charged with a predetermined voltage corresponding to the clock pulse. Then, the first node may be kept in a charged state at any moment. In other words, the first node may remain charged at an unwanted timing. In this case, the first node may be maintained in the charging state more than once in one frame, whereby the pull-up switching device may be turned on more than once in one frame. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses during one frame may occur due to the coupling phenomenon as described above.

Of course, the above coupling phenomenon is prevented by the discharge transistor. This discharge transistor discharges the first node of the stage to which it belongs in response to the output from the next stage. This prevents the first node from being charged. However, when this discharge transistor deteriorates, the pull-up transistor generates multiple outputs by the coupling phenomenon. The deterioration of the discharge transistor is caused by the dummy stage showing a different connection relationship from the remaining stages. If this is explained in more detail as follows.

That is, the dummy stage provided in the conventional shift register lastly outputs a scan pulse and supplies it to the nth stage. However, the dummy stage does not supply a scan pulse to the gate line. In other words, although the first to nth stages are connected to the first to nth gate lines, the dummy stage is not connected to the gate line. Since the gate line acts as a load, the scan pulse output from the dummy stage not connected to the gate line has a larger value than the scan pulse output from the remaining stages.

The scan pulse output from this dummy stage is supplied to the discharge transistor provided in the previous stage, that is, the nth stage. However, since the scan pulse outputted from this dummy stage has a larger value than the scan pulse outputted from the next stage, the discharge transistor of the nth stage supplied with this scan pulse is easily degraded. Then, the discharge of the first node of the n-th stage is difficult. As a result, the n-th stage generates multiple outputs by the coupling phenomenon described above. The multiple outputs from this n stage are supplied to the previous stage, that is, the n-1 stage. By this multi-output instead of the normal scan pulse, the discharge transistor provided in the n-th stage is also easily degraded in the manner described above.

With this principle, all the discharge transistors provided in all the stages deteriorate, so that each stage generates multiple outputs.

As such, when one stage outputs two or more scan pulses in one frame, the quality of an image displayed on the liquid crystal panel is degraded.

The present invention has been made to solve the above problems, the liquid crystal display device and its driving method that can delay the timing of the multi output by reducing the output of the dummy stage to prevent deterioration of the switching device for discharge The purpose is to provide.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a plurality of stages sequentially outputting scan pulses to sequentially drive gate lines of a liquid crystal panel; At least one dummy stage receiving scan pulses from any one of the stages to disable any second stage; And at least one dummy gate line supplied with the scan pulse output from the dummy stage.

In addition, the liquid crystal display according to the present invention for achieving the above object, a plurality of stages for sequentially driving the gate lines of the liquid crystal panel by outputting the scan pulse; At least one dummy stage receiving scan pulses from any one of the stages to disable any second stage; And an RC rod supplied with the scan pulse output from the dummy stage.

In addition, the driving method of the liquid crystal display according to the present invention for achieving the above object, a plurality of stages for sequentially driving the gate lines of the liquid crystal panel by sequentially outputting the scan pulse, and any of the stages A driving method of a liquid crystal display device comprising at least one dummy stage receiving a scan pulse from a first stage and disabling an arbitrary second stage, the method comprising: outputting a scan pulse from the dummy stage; And supplying a scan pulse from the dummy stage to the dummy gate line and the second stage.

In addition, the driving method of the liquid crystal display according to the present invention for achieving the above object, a plurality of stages for sequentially driving the gate lines of the liquid crystal panel by sequentially outputting the scan pulse, and any of the stages A driving method of a liquid crystal display device comprising at least one dummy stage receiving a scan pulse from a first stage and disabling an arbitrary second stage, the method comprising: outputting a scan pulse from the dummy stage; And supplying a scan pulse from the dummy stage to the RC rod and the second stage.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a liquid crystal display according to an exemplary embodiment of the present invention is defined by a plurality of gate lines GL1 through GLn + 1 and a plurality of data lines DL1 through DLm perpendicularly intersecting with each other. The liquid crystal panel 200 includes a plurality of pixels PXL, and a shift register for driving the gate lines GL1 to GLn + 1 of the liquid crystal panel 200.

In order to reduce the size of the liquid crystal display, the shift register may be embedded on the liquid crystal panel 200.

The shift register is composed of n stages BST1 to BSTn and one dummy stage BSTn + 1 connected to each other. Here, each of the stages BST1 to BSTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 is sequentially performed from the first stage BST1 to the dummy stage BSTn + 1. To Voutn + 1). In this case, the scan pulses Vout1 to Voutn output from the stages BST1 to BSTn + 1 are sequentially supplied to the gate lines GL1 to GLn + 1 of the liquid crystal panel 200 (not shown). As a result, the gate lines GL1 to GLn + 1 are sequentially scanned. That is, the first to nth stages BST1 to BSTn are connected to the first to nth gate lines GL1 to GLn, and the dummy stage BSTn + 1 is connected to the dummy gate line GLn + 1. .

The liquid crystal display according to the exemplary embodiment of the present invention may include two or more dummy stages according to a connection relationship between stages provided in the shift register.

Each stage BST2 to BSTn except for the first stage BST1 and the dummy stage BSTn + 1 has first to third output lines 241a to 241c for outputting the scan pulses Vout1 to Voutn. .

Here, the first output line 241a of each stage BST2 to BSTn electrically connects each stage BST2 to BSTn and each gate line, and the second output line 241b of each stage BST2 to BSTn. ) Electrically connects between its first output line 241a and the next stage, and the third output line 241c of each stage BST2 to BSTn is connected to its first output line 241a. However, the stages are electrically connected.

For example, the first output line 241a of the second stage BST2 electrically connects the second stage BST2 and the second gate line GL2 to form the first output line 241a of the second stage BST2. The second output line 241b electrically connects the first output line 241a of the second stage BST2 and the third stage BST3, and the third output line 241c of the second stage BST2. ) Electrically connects the first output line 241a of the second stage BST2 and the first stage BST1.

The first stage BST1 has first and second output lines 241a and 241b, and the dummy stage BSTn + 1 has first and third output lines 241a and 241c. That is, the first output line 241a of the first stage BST1 electrically connects between the first stage BST1 and the first gate line GL1 and the second stage of the first stage BST1. The output line 241b electrically connects the first output line 241a of the first stage BST1 and the second stage BST2.

The first output line 241a of the dummy stage BSTn + 1 electrically connects the dummy stage BSTn + 1 and the dummy gate line GLn + 1 to the dummy stage BSTn + 1. The third output line 241c electrically connects the first output line 241a of the dummy stage BSTn + 1 and the nth stage BSTn.

Each stage BST1 to BSTn + 1 supplies scan pulses to its corresponding gate line through its first output line 241a, and transmits the scan pulses from its own stage through its second output line 241b. And the scan pulse through its third output line 241c to the stage located earlier from itself.

On the other hand, the entire stages BST1 to BSTn + 1 of the shift registers configured as described above are configured with the first voltage source VDD and the second voltage source VSS, and the first to fourth clock pulses circulating with sequential phase differences. Two clock pulses of CLK1 to CLK4) are applied. Here, the first voltage source VDD refers to a positive voltage source as a high potential voltage source, and the second voltage source VSS refers to a negative voltage source as a low potential voltage source.

Here, the first stage BST1 located at the top of the stages BST1 to BSTn + 1 and the dummy stage BSTn + 1 located at the bottom thereof are the first voltage source VDD and the second voltage source ( VSS) and a start pulse SP in addition to two clock pulses among the first to fourth clock pulses CLK1 to CLK4.

On the other hand, as described above, the first to fourth clock pulses (CLK1 to CLK4) are phase-delayed by one pulse width each other and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is less than the second clock pulse CLK2. Phase delayed by a pulse width is output, the fourth clock pulse (CLK4) is phase-delayed output by one pulse width than the third clock pulse (CLK3), the first clock pulse (CLK1) is output to the fourth clock Phase delayed by one pulse width than pulse CLK4 is output.

Meanwhile, the start pulse SP applied to the first stage BST1 among the stages BST1 to BSTn + 1 is output earlier than the clock pulses CLK1 to CLK4. That is, the start pulse SP is output by one clock pulse width ahead of the first clock pulse CLK1. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is output first in every frame, the first to fourth clock pulses CLK4 are sequentially output. In this case, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Accordingly, the first clock pulse CLK1 is output in a period between the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Meanwhile, the shift register according to the present invention may use one or more clock pulses. That is, the shift register according to the present invention may use only the first clock pulses CLK1 of the first to fourth clock pulses CLK4, or may use only the first and second clock pulses CLK1 and CLK2. Alternatively, only the first to third clock pulses CLK1 to CLK3 may be used. In addition, the shift register according to the present invention may use four or more clock pulses sequentially output.

The operation of the shift register constructed as described above will be described in detail as follows.

First, when a start pulse SP from a timing controller (not shown) is applied to the first stage BST1, the first stage BST1 is enabled in response to the start pulse SP.

Subsequently, the enabled first stage BST1 receives the first and second clock pulses CLK1 to CLK2 from the timing controller and outputs the first scan pulse Vout1, and the first gate line GL1. ) And the second stage BST2 together. Then, the second stage BST2 is enabled in response to the first scan pulse Vout1.

Subsequently, the enabled second stage BST2 receives the second and third clock pulses CLK2 and CLK3 from the timing controller and outputs a second scan pulse Vout2, which is then output to the second gate line VST2. GL2), the third stage BST3 and the first stage BST1 are supplied together. Then, the third stage BST3 is enabled in response to the second scan pulse Vout2, and the first stage BST1 is disabled in response to the second scan pulse Vout2. The second voltage source VSS is supplied to the first gate line GL1.

Subsequently, the enabled third stage BST3 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller and outputs a third scan pulse Vout3, which is then output to the third gate line VST3. GL3), 4th stage BST4, and 2nd stage BST2 are supplied together. Then, the fourth stage BST4 is enabled in response to the third scan pulse Vout3, and the second stage BST2 is disabled in response to the third scan pulse Vout3. The second voltage source VSS is supplied to the second gate line GL2.

In this manner, the fourth to nth scan pulses Voutn are sequentially output to the remaining fourth to nth stages BST4 to BSTn and sequentially applied to the fourth to nth gate lines GLn. As a result, the first to nth gate lines GLn are sequentially scanned by the sequentially output first to nth scan pulses Vout1 to Voutn.

At this time, the dummy stage BSTn + 1 is enabled in response to the nth scan pulse Voutn from the nth stage BSTn, and then the first and second clock pulses CLK1, CLK2 is input to output the n + 1th scan pulse Voutn + 1 and is supplied to the dummy gate line GLn + 1 and the nth stage BSTn. Then, in response to the n + 1 th scan pulse Voutn + 1, the n th stage BSTn is disabled to supply the second voltage source VSS to the n th gate line GLn.

On the other hand, the dummy stage BSTn + 1 is disabled by the start pulse SP.

As described above, the dummy stage BSTn + 1 operates in the same manner as the first to nth stages BST1 to BSTn. That is, as the first to nth stages BST1 to BSTn supply scan pulses to their respective gate lines, the dummy stage BSTn + 1 also has its own gate line (dummy gate line ( Supply the scan pulse to GLn + 1)). That is, each of the gate lines GL1 to GLn + 1 serves as one load, and the dummy stages BSTn + 1 are also connected to the gate line (dummy gate line GLn + 1), so that the other stages It will have the same load condition. Therefore, the magnitude of the scan pulse Voutn + 1 output from the dummy stage BSTn + 1 and the magnitude of each scan pulse Vout1 to Voutn output from the remaining stages BST1 to BSTn become the same. Therefore, malfunction of each stage BST1 to BSTn + 1 due to the coupling phenomenon as described above can be prevented.

The dummy gate line GLn + 1 and the first to nth gate lines GL1 to GLn may be formed of the same material and may have the same shape. That is, it is preferable to form the same resistance and capacitance of the first to nth gate lines GL1 to GLn and the dummy gate line GLn + 1.

Meanwhile, TFT (Thin Film Transistor) is a thin film transistor, CST is a storage capacitance, and CLC is a liquid crystal capacitance.

Here, the dummy gate line GLn + 1 may be formed in a zigzag shape to further increase the resistance component of the dummy gate line GLn + 1.

Meanwhile, the liquid crystal display according to the present invention may include an RC rod instead of the dummy gate line GLn + 1.

3 is a view showing an RC rod connected in parallel with a dummy stage.

The dummy stage BSTn + 1 is connected in parallel with the RC rod 340 as shown in FIG. The RC rod 340 includes a plurality of resistors R connected in series with each other, and a plurality of capacitors C connected in parallel to each node between the resistors R. Here, the dummy stage BSTn + 1 described above has only one third output line 241c, and the RC rod 340 is connected in parallel to one side of the third output line 241c.

4 is a diagram illustrating an RC rod connected in series with a dummy stage. As shown in the figure, the RC rod 340 includes the third output line 271c and nth of the dummy stage BSTn + 1. It may be connected in series between the input terminals of the stage BSTn.

FIG. 5 is a view showing the shape of an output terminal provided in the dummy stage. As shown in the figure, the third output line 241c of the dummy stage BSTn + 1 itself is formed in a zigzag shape to separate the output terminal. The RC rod can be formed without using the resistor R.

Meanwhile, the configuration of each stage BST1 to BSTn + 1 provided in the shift register according to the embodiment of the present invention will be described in more detail as follows. Here, since the configurations of the second to nth stages BST2 to BSTn and the dummy stages BSTn + 1 are the same, only the second stage BST2 will be representatively described.

FIG. 6 is a detailed configuration diagram of the second stage of FIG. 2.

That is, as illustrated in FIG. 6, the second stage BST2 includes a node controller 300a that controls charging and discharging of the first node Q and charging and discharging of the second node QB. The output unit 300b outputs a scan pulse or a second voltage source VSS according to the states of the first and second nodes QB and supplies them to the second gate line GL2 of the liquid crystal panel 200. It includes.

The output unit 300b may include a pull-up transistor Tru that scan pulses to a second gate line GL2 when the first node Q is in a charged state, and the second node QB is charged. And a pull-down transistor Trd for supplying a second voltage source VSS to the second gate line GL2 in a state.

Here, the first node Q and the second node QB are alternately charged and discharged. Specifically, when the first node Q is in a charged state, the second node QB is discharged. The first node Q is discharged when the second node QB is in a charged state. The charging and discharging states of the first node Q and the second node QB are controlled by a plurality of switching elements (not shown) provided in the node controller 300a.

The first stage, the third to nth stages BST3 to BSTn, and the dummy stage BSTn + 1 also have the same configuration as the second stage BST2.

Here, a circuit configuration of the node controller 300a and the output unit 300b included in the second stage BST2 will be described.

7 is a diagram illustrating a circuit configuration of a node controller and an output unit provided in the second stage.

The node controller 300a includes first to sixth NMOS transistors Tr1 to Tr6, as illustrated in FIG. 7.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, the first NMOS transistor Tr1 of the second stage BST2 sets the first node Q to the first voltage source VDD in response to the first scan pulse Vout1 from the first stage BST1. Charge with. For this purpose, the gate terminal of the first NMOS transistor Tr1 is connected to the output 300b of the first stage BST1, the drain terminal is connected to a power line for transmitting the first voltage source VDD, and the source The terminal is connected to the first node Q.

The second NMOS transistor Tr2 discharges the second node QB to the second voltage source VSS in response to the scan pulse from the previous stage. That is, in response to the first scan pulse Vout1 from the first stage BST1, the second NMOS transistor Tr2 of the second stage BST2 connects the second node QB to the second voltage source ( VSS). To this end, the gate terminal of the second NMOS transistor Tr2 is connected to the output 300b of the first stage BST1, the drain terminal is connected to the second node QB, and the source terminal is connected to the second node QB. It is connected to a power supply line that transmits a voltage source VSS.

The third NMOS transistor Tr3 charges the second node QB to the first voltage source VDD in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the third NMOS transistor Tr3 of the second stage BST2 is connected to the third clock pulse CLK3 (clock pulse synchronized with the third scan pulse Vout3 output from the third stage BST3). In response, the second node QB is charged with the first voltage source VDD. To this end, the gate terminal of the third NMOS transistor Tr3 is connected to a clock line for transmitting the third clock pulse CLK3, and the drain terminal is connected to a power line for transmitting the first voltage source VDD. The source terminal is connected to the second node QB.

The fourth NMOS transistor Tr4 discharges the first node Q to the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. To this end, a gate terminal of the fourth NMOS transistor Tr4 is connected to the second node QB, a drain terminal is connected to the first node Q, and a source terminal of the fourth voltage source VSS is connected to the first node QB. It is connected to the transmitting power line.

The fifth NMOS transistor Tr5 discharges the second node QB to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to the first node Q, the drain terminal is connected to the second node QB, and the source terminal transmits the second voltage source VSS. Is connected to the power supply line.

The sixth NMOS transistor Tr6 is the discharge transistor described above, and discharges the first node Q to the second voltage source VSS in response to the scan pulse output from the next stage. That is, the sixth NMOS transistor Tr6 discharges the first node Q to the second voltage source VSS in response to the third scan pulse from the third stage BST3. To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to the output 300b of the third stage BST3, the drain terminal is connected to the first node Q, and the source terminal of the sixth NMOS transistor Tr6 is connected to the first node Q. 2 is connected to a power supply line that transmits a voltage source VSS.

The output unit 300b includes a pull-up transistor Tru and a pull-down transistor Trd.

The pull-up transistor Tru is clocked ahead of the clock pulse applied to the gate terminal of the third NMOS transistor Tr3 by one clock pulse width in response to the first voltage source VDD charged in the first node Q. Output a pulse. That is, the pull-up transistor Tru outputs the second clock pulse CLK2 that is one pulse width ahead of the third clock pulse CLK3. The output second clock pulse CLK2 is supplied to the gate line connected to the stage to which it belongs, the stage at the previous stage, and the stage at the next stage. That is, the pull-up transistor Tru of the second stage BST2 outputs the second clock pulse CLK2 as a second scan pulse Vout2 for driving the second gate line GL2. The second scan pulse Vout2 is supplied to the second gate line GL2, the first stage BST1, and the third stage BST3. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the drain terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the source terminal is connected to the second gate. Commonly connected to the line GL2, the first stage BST1, and the third stage BST3. Here, the second scan pulse Vout2 supplied to the first stage BST1 disables the first stage BST1, and the second scan pulse Vout2 supplied to the third stage BST3 is The third stage BST3 is enabled.

The pull-down transistor Trd outputs the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage in the previous stage, and the stage in the next stage. That is, the pull-down transistor Trd supplies the second voltage source VSS to the second gate line GL2, the first stage BST1, and the third stage BST3. The second voltage source VSS supplied to the second gate line GL2 functions as a signal for deactivating the second gate line GL2. For this purpose, the gate terminal of the pull-down transistor Trd is connected to the second node QB, and the drain terminal is connected to the second gate line GL2, the first stage BST1, and the third stage BST3. Commonly connected, the source terminal is connected to a power line for transmitting the second voltage source (VSS).

Meanwhile, the first NMOS transistor Tr1 illustrated in FIG. 7 may receive the scan pulses from the previous stage instead of the first voltage source VDD and supply the scan pulses to the first node Q. In this case, the first NMOS transistor Tr1 charges the scan pulse to the first node Q in response to the scan pulse from the previous stage. To this end, the gate terminal and the source terminal of the first NMOS transistor Tr1 are connected to the previous stage, and the drain terminal is connected to the first node Q. For example, the gate terminal and the source terminal of the first NMOS transistor Tr1 of the second stage are connected to the first stage, and the drain terminal is connected to the first node Q.

In addition, the first NMOS transistor Tr1 included in the first stage BST1 receives the start pulse SP from the timing controller instead of the first voltage source VDD and receives the start pulse SP first. It can also supply to the node Q. In this case, the first NMOS transistor Tr1 charges the start pulse SP to the first node Q in response to the start pulse SP from the timing controller. For this purpose, the gate terminal and the source terminal of the first NMOS transistor Tr1 are connected to the timing controller, and the drain terminal is connected to the first node Q.

In addition, the third NMOS transistor Tr3 illustrated in FIG. 7 may receive the first voltage source VDD instead of a clock pulse, and supply the first voltage source VDD to the second node QB. In this case, the third NMOS transistor Tr3 charges the first voltage source VDD to the second node QB in response to the first voltage source VDD. To this end, the gate terminal and the drain terminal of the third NMOS transistor Tr3 are connected to the previous stage, and the source terminal is connected to the second node QB.

The first stage BST1, the third to nth stages BSTn, and the dummy stage BSTn + 1 also have the same configuration as the second stage BST2 described above.

However, since the stage before the first stage BST1 does not exist, the first NMOS transistor Tr1 included in the first stage BST1 receives the start pulse SP from the timing controller. To be supplied. That is, the first NMOS transistor Tr1 included in the first stage BST1 charges the first node Q to the first voltage source VDD in response to the start pulse SP from the timing controller. Let's do it. In addition, the second NMOS transistor Tr2 included in the first stage BST1 also receives the start pulse SP from the timing controller. That is, the second NMOS transistor Tr2 provided in the first stage BST1 discharges the second node QB to the second voltage source VSS in response to the start pulse SP from the timing controller. Let's do it.

Further, for the same reason as described above, the source terminal of the pull-up transistor Tru provided in the first stage BST1 is commonly connected to the first gate line GL1 and the first stage BST1, and the pull-down transistor ( The drain terminal of Trd is commonly connected to the first gate line GL1 and the second stage BST2.

There is no stage next to the dummy stage BSTn + 1. In addition, the dummy stage BSTn + 1 supplies the n + 1th scan pulse outputted from the dummy stage BSTn + 1 to a previous stage (that is, the nth stage BSTn) to disable the nth stage BSTn. Function Therefore, the source terminal of the pull-up transistor Tru provided in the dummy stage BSTn + 1 is connected to the dummy gate line GLn + 1 and the n-th stage, and the pull-down transistor Trd of the dummy stage BSTn + 1 is connected. The drain terminal is connected to the dummy gate line GLn + 1 and the nth stage BSTn.

FIG. 8 is a diagram illustrating first to third stages having the circuit configuration of FIG. 7, and FIG. 9 is a diagram illustrating timing diagrams of scan pulses output from the stage of FIG. 8 and various signals supplied to the stage.

First, the operation during the enable period T0 will be described.

During the enable period TO, as shown in FIG. 9, only the start pulse SP output from the timing controller is kept high and the remaining start pulse SP is kept low.

The start pulse SP output from the timing controller is input to the first stage BST1. Specifically, as shown in FIG. 8, the start pulse SP includes the gate terminal of the first NMOS transistor Tr1 and the gate terminal of the second NMOS transistor Tr2 provided in the first stage BST1. Is entered. Then, the first and second NMOS transistors Tr1 and Tr2 are turned on, and the first voltage source VDD is connected to the first node Q through the turned-on first NMOS transistor Tr1. Is approved. Accordingly, the first node Q is charged, and the pull-up transistor Tru having a gate terminal connected to the charged first node Q is turned on. The second voltage source VSS is applied to the second node QB through the turned-on second NMOS transistor Tr2. Accordingly, the second node QB is discharged by the second voltage source VSS, and the pull-down transistor Trd having a gate terminal connected to the second node QB is turned off.

On the other hand, the start pulse SP output from the timing controller during the enable period T0 is also supplied to the dummy stages BSTn + 1 and the second to nth stages BST2 to BSTn. That is, the start pulse SP is supplied to the discharge unit 300c provided in the dummy stage BSTn + 1 and the discharge unit 300c provided in the second to nth stages BST2 to BSTn. Specifically, the start pulse SP may include a gate terminal of a ninth NMOS transistor Tr9 provided in the dummy stage BSTn + 1, and a ninth NMOS provided in the second to nth stages BST2 to BSTn. It is input to the gate terminal of the transistor Tr9. Accordingly, each of the ninth NMOS transistors Tr9 included in the dummy stages BSTn + 1 and the second to nth stages BST2 to BSTn is turned on. In this case, the turned-on ninth The second voltage source VSS is applied to the first node Q of the stages BST2 to BSTn + 1 through the NMOS transistor Tr9. Accordingly, the pull-up transistor Tru having a gate terminal connected to the first node Q of the stages BST2 to BSTn + 1 is turned off.

As such, during the enable period T0, as illustrated in FIG. 9, the first node Q of the first stage BST1 is charged with the first voltage source VDD and the second node ( The first stage BST1 is enabled by discharging QB to the second voltage source VSS.

On the other hand, the start pulse SP output in the enable period T0 is also supplied to the gate terminal of the sixth NMOS transistor Tr6 provided in the dummy stage BSTn + 1. As the sixth NMOS transistor Tr6 of the dummy stage BSTn + 1 is turned on, the second voltage source VSS is supplied to the first node Q of the dummy stage BSTn + 1. As a result, the first node Q of the dummy stage BSTn + 1 is discharged, and the pull-up transistor Tru having a gate terminal connected to the first node Q is turned off. As a result, the dummy stage BSTn + 1 is disabled in the enable period T0.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 9, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Therefore, the first and second NMOS transistors Tr1 and Tr2 of the first stage BST1 are turned off in response to the low state start pulse SP. In particular, as the first NMOS transistor Tr1 is turned off, the first node Q of the first stage BST1 remains in a floating state.

Meanwhile, as the first node Q of the first stage BST1 is continuously maintained as the first voltage source VDD applied during the enable period T0, the pull-up transistor of the first stage BST1 Tru) remains turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up transistor Tru, the first node Q of the first stage BST1 as shown in FIG. 9. The first voltage source VDD charged to is amplified by bootstrapping. Accordingly, the first clock pulse CLK1 applied to the drain terminal of the pull-up transistor Tru of the first stage BST1 is stably output through the source terminal of the pull-up transistor Tru. In this case, as shown in FIG. 9, the output first clock pulse CLK1 is applied to the first gate line GL1 as a first scan pulse Vout1 for driving the first gate line GL1. Works.

In this case, the first scan pulse Vout1 is supplied to the first gate line GL1 and input to the second stage BST2. Specifically, as illustrated in FIG. 8, the first scan pulse Vout1 may include a gate terminal of the first NMOS transistor Tr1 provided in the second stage BST2, and a gate terminal of the second NMOS transistor Tr2. It is input to the gate terminal. Here, the first scan pulse Vout1 supplied to the second stage BST2 plays the same role as the start pulse SP supplied to the first stage BST1. That is, the second stage BST2 is enabled in response to the first scan pulse Vout1. Specifically, the first node Q of the second stage BST2 is charged to the first voltage source VDD by the first scan pulse Vout1, and the second node QB is discharged. In other words, the first scan pulse Vout1 output from the first stage BST1 during the first period T1 drives the first gate line GL1 and, as shown in FIG. The second stage BST2 is enabled by charging the first node Q of the second stage BST2 and discharging the second node QB.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 9, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

Therefore, as the first scan pulse Vout1 from the first stage BST1 applied in the first period T1 changes to a low state in the second period T2, the first scan pulse Vout1 is applied to the gate terminal. The first and second NMOS transistors Tr2 of the two stages are turned off, so that the first node Q of the second stage BST2 remains in a floating state. Meanwhile, as the first node Q of the second stage BST2 is continuously maintained as the first voltage source VDD applied during the first period T1, the pull-up provided in the second stage BST2 is provided. The transistor Tru remains turned on. In this case, as the second clock pulse CLK2 is applied to the drain terminal of the pull-up transistor Tru of the second stage BST2, the first charge Q of the first stage Q of the second stage BST2 is applied. One voltage source VDD is amplified by bootstrapping. Therefore, the second clock pulse CLK2 applied to the drain terminal of the pull-up transistor Tru is stably output through the source terminal of the pull-up transistor Tru. In this case, as shown in FIG. 9, the second clock pulse CLK2 output from the second stage BST2 is applied to a second gate line GL2 to drive the second gate line GL2. Act as a second scan pulse Vout2.

In this case, the second scan pulse Vout2 output from the second stage BST2 is also input to the first stage BST1. Specifically, as shown in FIG. 8, the second scan pulse Vout2 is input to the gate terminal of the sixth NMOS transistor Tr6 provided in the first stage BST1. Here, as the sixth NMOS transistor Tr6 of the first stage BST1 is turned on by the second scan pulse Vout2, the sixth NMOS transistor with the second voltage source VSS turned on. It is supplied to the first node Q 501 of the first stage BST1 via Tr6. Therefore, as shown in FIG. 9, the first node Q of the first stage BST1 is discharged by the second voltage source VSS. As a result, the pull-up transistor Tru having the gate terminal connected to the first node Q of the first stage BST1 is turned off.

On the other hand, the second clock pulse CLK2 output in the second period T2 is also applied to the gate terminal of the third NMOS transistor Tr3 of the first stage BST1. The third NMOS transistor Tr3 of BST1 is turned on. At this time, the first voltage source VDD is supplied to the second node QB of the first stage BST1 through the turned-on third NMOS transistor Tr3. Accordingly, as shown in FIG. 9, the second node QB of the first stage BST1 is charged by the first voltage source VDD. Then, the pull-down transistor Trd connected to the second node QB of the second stage BST2 is turned on. In this case, a second voltage source VSS is supplied to the first gate line GL1 through the turned-on pull-down transistor Trd. Thus, the second voltage source VSS serves as a signal for deactivating the gate line. That is, during the second period T2, the first stage BST1 is disabled by the second scan pulse Vout2.

On the other hand, during this second period T2, the second scan pulse Vout2 output from the second stage BST2 is also input to the third stage BST3. Specifically, as shown in FIG. 8, the second scan pulse Vout2 is input to the gate terminals of the first and second NMOS transistors Tr1 and Tr2 provided in the third stage BST3. Thus, in the manner as described above, the first node Q of the third stage BST3 is charged and the second node QB is discharged. That is, the third stage BST3 is enabled by the second scan pulse Vout2.

In summary, during the second period T2, the second scan pulse Vout2 is output from the second stage BST2. The second scan pulse Vout2 drives the second gate line GL2, disables the first stage BST1, and enables the third stage BST3.

Thereafter, in the third period T3, the third stage BST3 outputs a third scan pulse Vout3 to drive the third gate line GL3. The third scan pulse Vout3 is also supplied to the second stage BST2 and the fourth stage BST4 to disable the second stage BST2 and to enable the fourth stage BST4. In the fourth period, the fourth stage BST4 outputs the fourth scan pulse Vout4. This fourth scan pulse Vout3 disables the third stage BST3 and enables the fifth stage.

In this manner, scan pulses Voutn + 1 are sequentially output to the dummy stage BSTn + 1. In this case, the scan pulse Voutn + 1 output from the dummy stage BSTn + 1 is supplied to the dummy gate line GLn + 1 and the nth stage BSTn.

When the next frame starts, the start pulse SP is output again from the timing controller, and the dummy stage BSTn + 1 is disabled by the start pulse SP.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the liquid crystal display device and the driving method thereof according to the present invention have the following effects.

The liquid crystal display device according to the present invention includes a dummy gate line connected to a dummy stage of a shift register. Therefore, the load on the output of the dummy stage and the load on the output of the remaining stages can be kept the same. By the same load, the scan pulses output from the dummy stage and the scan pulses output from the remaining stages become equal.

As a result, the liquid crystal display according to the present invention can prevent deterioration of the pull-up transistor and the pull-down transistor provided in each stage, thereby extending the life of the shift register.

Claims (27)

A plurality of stages sequentially outputting scan pulses to sequentially drive gate lines of the liquid crystal panel; At least one dummy stage receiving scan pulses from any one of the stages to disable any second stage; And And at least one dummy gate line receiving the scan pulse output from the dummy stage. delete delete The method of claim 1, Each stage outputs a scan pulse in response to a scan pulse output from a stage previous to it, and outputs a low potential voltage source for deactivating the gate line in response to a scan pulse from the stage next to the stage. To; A first stage of outputting a scan pulse first of the stages outputs the scan pulse in response to a start pulse output once per frame from a timing controller; And, Each stage, A node controller for controlling charge and discharge states of the first and second nodes; And And an output unit configured to output the scan pulse according to the state of the first node and to output the low potential voltage source according to the state of the second node. 5. The method of claim 4, Node control unit of each stage, A first switching element for charging a first node with a high potential voltage source in response to the start pulse or a scan pulse from a previous stage; A second switching element for discharging a second node to a low potential voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching device configured to charge the second node with a high potential voltage source in response to a first clock pulse synchronized with a scan pulse output from the next stage; A fourth switching element configured to discharge the first node to a low potential voltage source in response to the high potential voltage source charged in the second node; A fifth switching device configured to discharge the second node to a low potential voltage source in response to the high potential voltage source charged in the first node; And And a sixth switching element for discharging the first node to a low potential voltage source in response to a scan pulse from a next stage. 6. The method of claim 5, The output unit of each stage, A pull-up switching element configured to output, as a scan pulse, a second clock pulse output before the first clock pulse in response to a high potential voltage source charged in the first node; And And a pull-down switching element for outputting the low potential voltage source in response to the high potential voltage source charged in the second node. 5. The method of claim 4, Node control unit of each stage, A first switching element for charging a first node with the start pulse or the scan pulse in response to the start pulse or the scan pulse from a previous stage; A second switching element for discharging a second node to a low potential voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching element for charging the second node with a high potential voltage source in response to the high potential voltage source; A fourth switching element configured to discharge the first node to a low potential voltage source in response to the high potential voltage source charged in the second node; A fifth switching device configured to discharge the second node to a low potential voltage source in response to a start pulse or a scan pulse charged in the first node; And And a sixth switching element for discharging the first node to a low potential voltage source in response to a scan pulse from a next stage. The method of claim 7, wherein The output unit of each stage, A pull-up switching element configured to output, as a scan pulse, a clock pulse preceding the scan pulse output from a next stage in response to the high potential voltage source charged in the first node; And And a pull-down switching element for outputting the low potential voltage source in response to the high potential voltage source charged in the second node. The method of claim 1, The dummy stage, Output a second scan pulse in response to the first scan pulse output from the last stage; Supply the second scan pulse to the last stage and the dummy gate line; And, And a low potential voltage source to supply the dummy gate line and the last stage in response to a start pulse from the outside. The method of claim 9, The dummy stage, A node controller for controlling charge and discharge states of the first and second nodes; And And an output unit configured to output the second scan pulse or the low potential voltage source according to the states of the first and second nodes. 11. The method of claim 10, The node controller of the dummy stage is A first switching element for charging a first node with a high potential voltage source in response to the scan pulse from the last stage; A second switching element for discharging a second node to a low potential voltage source in response to the scan pulse from the last stage; A third switching device configured to charge the second node with a high potential voltage source in response to a start pulse output from a timing controller; A fourth switching element configured to discharge the first node to a low potential voltage source in response to the high potential voltage source charged in the second node; A fifth switching device configured to discharge the second node to a low potential voltage source in response to the high potential voltage source charged in the first node; And And a sixth switching device for discharging the first node to a low potential voltage source in response to a start pulse output from the timing controller. The method of claim 11, The output unit of the dummy stage, A pull-up switching device for outputting a clock pulse output before the start pulse as a scan pulse in response to a high potential voltage source charged in the first node; And And a pull-down switching element for outputting the low potential voltage source in response to the high potential voltage source charged in the second node. 11. The method of claim 10, The node controller of the dummy stage is A first switching device for charging a first node with the scan pulse in response to the scan pulse from the last stage; A second switching element for discharging a second node to a low potential voltage source in response to the scan pulse from the last stage; A third switching element for charging the second node with the high potential voltage source in response to the high potential voltage source; A fourth switching element configured to discharge the first node to a low potential voltage source in response to the high potential voltage source charged in the second node; A fifth switching device discharging the second node to a low potential voltage source in response to a start pulse charged in the first node; And And a sixth switching element for discharging the first node to a low potential voltage source in response to a start pulse output from a timing controller. The method of claim 13, The output unit of the dummy stage, A pull-up switching element configured to output, as a scan pulse, a third clock pulse output before the start pulse in response to a high potential voltage source charged in the first node; And And a pull-down switching element for outputting the low potential voltage source in response to the high potential voltage source charged in the second node. delete The method of claim 1, And the first stage and the second stage are the same stage. 17. The method of claim 16, And the first and second stages are last stages for driving a last gate line. The method of claim 1, And the dummy gate line has a zigzag shape. A plurality of stages sequentially outputting scan pulses to sequentially drive gate lines of the liquid crystal panel; At least one dummy stage receiving scan pulses from any one of the stages to disable any second stage; And And a RC rod supplied with the scan pulse output from the dummy stage. 20. The method of claim 19, The RC rod includes a plurality of resistors and a plurality of capacitors. 20. The method of claim 19, And the RC rod is connected in series between the output line of the dummy stage and the input terminal of the second stage. 20. The method of claim 19, And the RC rod is connected in parallel to one side of an output line connecting the dummy stage and the second stage and transmitting scan pulses from the dummy stage. 20. The method of claim 19, And the first stage and the second stage are identical to each other. 24. The method of claim 23, And the first stage and the second stage are last stages connected to a last gate line. 20. The method of claim 19, And an output line connecting the dummy stage and the second stage and transmitting a scan pulse from the dummy stage in a zigzag shape. A plurality of stages that sequentially output the scan pulses to drive the gate lines of the liquid crystal panel, and at least one of which receives a scan pulse from any one of the stages and disables the second stage; In the driving method of a liquid crystal display device comprising a dummy stage, Outputting a scan pulse from the dummy stage; And And supplying the scan pulse from the dummy stage to the dummy gate line and the second stage. A plurality of stages that sequentially output the scan pulses to drive the gate lines of the liquid crystal panel, and at least one of which receives a scan pulse from any one of the stages and disables the second stage; In the driving method of a liquid crystal display device comprising a dummy stage, Outputting a scan pulse from the dummy stage; And And supplying the scan pulse from the dummy stage to the RC rod and the second stage.

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