TWI521490B - Display panel and gate driver - Google Patents

Description

Display panel and gate driver

The present invention relates to a display panel, and more particularly to a gate driver for a display panel.

Recently, various liquid crystal display products have become quite popular. In order to effectively increase the viewing area of a liquid crystal display, a display panel technology suitable for a narrow bezel has been continuously proposed.

However, as the resolution of the display continues to increase, the gate driver can drive the display panel for charging for shorter and shorter times. In order to maintain a certain pixel charging rate, the size of a plurality of transistors in the gate driver must be increased. In this way, the gate driver dynamic power consumption and circuit layout area increase, but it is more difficult to apply to narrow frame applications.

Therefore, how to effectively reduce the circuit area of the gate driver while maintaining a good pixel charging rate is one of the current important research and development topics, and has become an urgent target for improvement in related fields.

In order to solve the above problems, one aspect of the present disclosure provides A display panel. The display panel contains multiple gate lines and gate drivers. The gate driver comprises a plurality of serially connected driving stages, wherein each driving stage is configured to output a gate driving signal to a corresponding one of the plurality of gate lines, and the Nth stage driving stage of the driving stage comprises an input unit, a driving unit and Pull down the unit. The input unit is configured to transmit a gate driving signal of the (N-1)th stage driving stage output to the first control node, where N is a positive integer, and the gate driving signal of the (N-1)th stage driving stage output comprises A continuous first pulse and a second pulse. The driving unit is configured to output a gate driving signal according to a voltage level of the first control node. The pull-down unit is configured to pull the gate drive signal to the first voltage after the enable period of the second pulse. The input unit pulls up the voltage level of the first control node to the second voltage during the enabling period of the first pulse wave, and after the enabling period of the second pulse wave, the driving unit drives the first control node The voltage level is pulled up to a third voltage, and the third voltage is greater than the second voltage.

Another aspect of the present disclosure provides a gate driver. The gate driver includes a plurality of serially connected driver stages, and each of the plurality of driver stages includes an input unit, a drive unit, and a pull down unit. The input unit includes a first input, a second input and an output. The first input end of the input unit is configured to receive the front gate drive signal, the second input end of the input unit is configured to receive the first clock signal, and the output end of the input unit is electrically coupled to the control node. The driving unit includes a first input end, a second input end and an output end. The first input end of the driving unit is electrically coupled to the control node, the second input end of the driving unit is configured to receive the second clock signal, and the output end of the driving unit is configured to output the driving signal of the current level, wherein the first time The pulse signal is inverted from the second clock signal. The pull-down unit includes a first switch, a second switch, and a third switch, The fourth switch, the fifth switch, and the sixth switch. The first switch has a first end, a second end, and a control end, wherein the control end of the first switch is configured to receive the first clock signal, and the first end of the first switch is electrically coupled to the control end of the first switch. The second switch has a first end, a second end, and a control end, wherein the control end of the second switch is electrically connected to the control end of the first switch, and the first end of the second switch is electrically connected to the first end of the first switch . The third switch has a first end, a second end, and a control end, wherein the control end of the third switch is configured to receive the driving signal of the front stage, and the first end of the third switch is electrically coupled to the second end of the first switch And the second end of the third switch is configured to receive the first voltage. The fourth switch has a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive the driving signal of the front stage, and the first end of the fourth switch is electrically coupled to the second end of the second switch And the second end of the fourth switch is configured to receive the first voltage. The fifth switch has a first end, a second end, and a control end, wherein the control end of the fifth switch is electrically coupled to the second end of the second switch, and the first end of the fifth switch is electrically coupled to the control node The node is connected, and the second end of the fifth switch is electrically coupled to the output end of the driving unit. The sixth switch has a first end, a second end, and a control end, wherein the control end of the sixth switch is electrically coupled to the second end of the second switch, and the first end of the sixth switch is electrically coupled to the output end of the driving unit And the second end of the sixth switch is configured to receive the first voltage.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. With the above technical solution, considerable technological progress can be achieved, and the industrial use value is widely used. The display panel and the gate driver disclosed in the disclosure can have various driving modes and can provide high charging of the pixel array. Rate, which in turn allows the opening of the display panel The rate is increased, or the area of the gate driver can be reduced to meet the needs of narrow-frame applications.

In order to make the disclosure more obvious, the attached symbols are as follows:

100‧‧‧ display panel

122‧‧‧ pixel array

140‧‧‧Source Driver

GL1, GL2, GL3~GLN‧‧‧ gate line

200a, 300‧‧‧ drive level

G[1], G[2]~G[n-1], G[n]‧‧‧ gate drive signals

240‧‧‧ drive unit

262‧‧‧ Pull-down control circuit

A, B‧‧‧ control node

P1, P2‧‧‧ pulse wave

120‧‧‧ display area

124‧‧‧ pixels

160, 200‧‧ ‧ gate driver

DL1, DL2, DL3, DL4~DLN‧‧‧ data lines

XHC, HC‧‧‧ clock signals

Din‧‧‧ initial pulse wave

220‧‧‧ input unit

260‧‧‧ Pulldown unit

264‧‧‧ Pulldown circuit

VSS, V1, V2, V3, V4, △V‧‧‧ voltage

C‧‧‧ capacitor

T11, T12, T21, T31, T32, T41, T42, T43, T44‧‧‧ switch

T1, T2, T3, T4, T5‧‧‧

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. 2A is a schematic diagram of a gate driver according to an embodiment of the present disclosure; FIG. 2B is a schematic diagram showing a driving stage shown in FIG. 2A according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram according to the present disclosure. A schematic diagram of an Nth stage driver stage is shown in FIG. 4; FIG. 4 is a schematic diagram showing the timing of the operation of the driver stage in FIG. 3 according to an embodiment of the present disclosure; FIG. 5A is according to the disclosure. An embodiment shows a state diagram of each switch in the driving stage of FIG. 3 in the period T1; FIG. 5B illustrates the state of each switch in the driving stage of FIG. 3 in the period T2 according to an embodiment of the present disclosure. FIG. 5C is a schematic diagram showing the state of each switch in the driving stage of FIG. 3 in the period T5 according to an embodiment of the present disclosure; and FIG. 6 is a third diagram according to another embodiment of the present disclosure. Drive level Schematic diagram of the signal timing of the operation.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish the elements described in the same technical terms. Or just operate.

As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within about 20%, preferably within about 10%, and more preferably, It is about five percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, that is, the errors or ranges indicated by "about", "about" or "roughly".

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

FIG. 1 is a schematic diagram of a display panel 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the display panel 100 includes an image display area 120, a source driver 140, and a gate driver 160. image The display area 120 includes a pixel array 122 and a plurality of paintings formed by a plurality of data lines (eg, N data lines DL1 to DLN) and a plurality of gate lines (eg, M gate lines GL1 to GLM). The pixel 124 and the pixel 124 are disposed in the pixel array 122 described above.

The source driver 140 is coupled to the data lines DL1 DL DLN, and is configured to transmit the data signals to the image display area 120 to the corresponding pixels 124 through the data lines DL1 DL DLN, and the gate driver 160 is coupled to the gate lines GL1 GGLM. The output gate driving signals are sequentially transmitted to the gate lines GL1 G GLM and transmitted to the image display area 120 through the gate lines GL1 G GLM to the corresponding pixels 124 .

2A is a schematic diagram of a gate driver 200 in accordance with an embodiment of the present disclosure. As shown in FIG. 2A, the gate driver 200 includes a multi-level driver stage 200a. Each of the driver stages 200a is connected to each other in series, and each stage of the driver stage 200a is used to output a gate drive signal G[n] to a corresponding one of the gate lines GL1 G GLM.

FIG. 2B is a schematic diagram showing the driver stage 200a shown in FIG. 2A according to an embodiment of the present disclosure. Taking the Nth stage driver stage 200a as an example, the Nth stage driver stage 200a includes an input unit 220, a driving unit 240, and a pull down unit 260, where N is a positive integer.

The first input end of the input unit 220 is configured to receive the (N-1)th gate drive signal G[n-1] or the initial pulse Din (when N=1), and the second input of the input unit 220 The clock signal XHC is received, and the output end of the input unit 220 is electrically coupled to the control node A.

The first input end of the driving unit 240 is electrically coupled to the control node A, the second input end of the driving unit 240 is configured to receive the clock signal HC, and the output end of the driving unit 240 is configured to output the gate driving signal G[n] of the current stage. The clock signal XHC and the clock signal HC are opposite to each other.

In operation, the input unit 220 is configured to transmit the gate signal G[n-1] outputted by the (N-1)th stage driving stage 200a or the initial pulse wave Din (when N=1) to the control node A. To adjust the voltage level of the control node A. The driving unit 240 is configured to output the gate driving signal G[n] of the current level according to the voltage level of the control node A. The pull-down unit 260 is electrically coupled to the input unit 220 and the driving unit 240. The pull-down unit 260 is configured to receive the gate signal G[n-1] outputted by the (N-1)th stage driving stage 200a or the initial pulse wave Din (when N=1) and the clock signal XHC to turn the gate The pole drive signal G[n] is pulled down to the voltage VSS.

In addition, the gate driver 200 shown in the present disclosure can generate different types of gate driving signals G[n], and the display array 122 can be driven in different polarities (eg, dot inversion, frame inversion, column). Reverse, column inversion, etc.). Specifically, as shown in FIG. 2A, the first input end of the input unit 220 of the first stage driving stage 200a is further configured to receive an initial pulse wave DIN, and the different polarity driving modes may be transmitted through the initial pulse according to actual needs. The wave DIN is set to complete.

The following paragraphs will set forth various embodiments to explain the functions and applications of the above-described driver stage 200a, but the present invention is not limited to the embodiments listed below.

Please refer to FIG. 3 , which is a schematic diagram of an Nth stage driver stage 300 according to an embodiment of the present disclosure. As shown in FIG. 3, the input unit 220 includes a switch T11 and a switch T12. Control terminal of switch T11 The first input terminal of the input unit 220 is coupled to receive the gate driving signal G[n-1] outputted by the (N-1)th stage driving stage 200a or the initial pulse wave Din (if N=1), and The first end of the switch T11 is electrically coupled to the control end of the switch T11. The control terminal of the switch T12 is electrically coupled to the second input of the input unit 220 to receive the clock signal XHC. The first end of the switch T12 is electrically coupled to the second end of the switch T11, and the second end of the switch T12 is electrically coupled to the output end of the input unit 220 (ie, the control node A). Thus, when both the switch T11 and the switch T12 are turned on, the gate drive signal G[n-1] outputted by the (N-1)th stage of the driver stage 200a can be transmitted to the control node A to adjust the voltage level of the control node A. quasi.

Furthermore, as shown in FIG. 3, the driving unit 240 includes a switch T21 and a capacitor C. The control terminal of the switch T21 is electrically coupled to the first input end of the driving unit 240 (ie, the control node A). The first end of the switch T21 is electrically coupled to the second input end of the driving unit 240 to receive the clock signal. HC, and the second end of the switch T21 is electrically coupled to the output end of the driving unit 240 to output the gate driving signal G[n] of the current stage. The capacitor C is electrically coupled between the control node A and the switch T21 to provide a voltage stabilization function.

The pull-down unit 260 includes a pull-down control circuit 262 and a pull-down circuit 264. The pull-down control circuit 262 is configured to adjust the voltage level of the control node B according to the gate drive signal G[n-1] outputted by the (N-1)th stage drive stage or the initial pulse wave Din (if N=1). The pull-down circuit 264 is electrically coupled to the control node B and is configured to pull down the gate drive signal G[n] of the current stage to the voltage VSS according to the voltage level of the control node B, wherein the voltage VSS is a low level voltage.

Specifically, the pull-down control circuit 262 includes a switch T41 and a switch. T42, switch T43 and switch T44. The control terminal of the switch T41 is configured to receive the clock signal XHC, and the first end of the switch T41 is electrically coupled to the control terminal of the switch T41. The control terminal of the switch T43 is electrically coupled to the second end of the switch T41. The first end of the switch T43 is electrically coupled to the first end of the switch T41, and the second end of the switch T43 is electrically coupled to the control node B. The control terminal of the switch T42 is configured to receive the gate drive signal G[n-1] or the initial pulse Din (if N=1) output from the (N-1)th stage of the driver stage 200a. The control terminal of the switch T42 is configured to receive the gate drive signal G[n-1] outputted by the (N-1)th stage drive stage 200a or the initial pulse wave Din (if N=1), and the first end of the switch T42 is electrically The second end of the switch T42 is coupled to the second end of the switch T42 for receiving the voltage VSS. The control terminal of the switch T44 is configured to receive the gate drive signal G[n-1] outputted by the (N-1)th stage drive stage 200a or the initial pulse wave Din (if N=1), and the first end of the switch T44 is electrically The control node B is coupled, and the second end of the switch T44 is used to receive the voltage VSS.

Next, as shown in FIG. 3, the pull-down circuit 264 includes a switch T32 and a switch T31. The control terminal of the switch T32 is electrically coupled to the control node B. The first end of the switch T32 is electrically coupled to the control node A, and the second end of the switch T32 is configured to receive the gate drive signal G[n] of the current stage. The control terminal of the switch T31 is electrically coupled to the control node B. The first end of the switch T31 is electrically coupled to the second end of the switch T21, and the second end of the switch T31 is configured to receive the voltage VSS.

FIG. 4 is a timing diagram showing the operation of the driving stage 300 in FIG. 3 according to an embodiment of the present disclosure. As shown in Fig. 4, in this embodiment, the initial pulse wave Din is set to have continuous pulse waves P1 and pulse waves P2. In this way, the display array 122 can be driven by dot inversion, column inversion, and the like. The way to operate.

FIG. 5A is a schematic diagram showing the state of each switch in the driving stage 300 of FIG. 3 in the period T1 according to an embodiment of the present disclosure. For convenience of explanation, please refer to FIG. 4, FIG. 2B and FIG. 5A together, and the operation of the driver stage 300 will be described together with the above drawings. In addition, the first stage drive stage 300 will be described below as an example. The operation of the subsequent stages of the driver stage 300 can be similarly derived by considering the initial pulse wave Din described below as the gate drive signal G[n-1] outputted by the pre-drive stage 300.

As shown in FIG. 4 and FIG. 5A, during the period T1 (that is, during the enable period of the pulse wave P1), the pulse wave P1 of the initial pulse Din is input to the switch T11 and the switch T42, and the switch T11 and the switch T42 are turned on. . Since the clock signal XHC is a high level voltage at this time, the switch T12 and the switch T41 are thus turned on, and the switch T43 and the switch T44 are also turned on. As such, the voltage level of the control node B can be pulled down to the voltage VSS via the switch T44 to turn off the switch T32 and the switch T31. The input unit 220 can transmit the initial pulse Din to the control node A to pull the voltage level of the control node A to the voltage V1, thereby turning on the switch T21. Therefore, the switch T21 can output the clock signal HC having a low voltage level to the gate drive signal G[1] of the stage.

It should be noted that in various embodiments of the present disclosure, the voltage difference between the switches T32 is determined by the voltage level of the control node A and the gate drive signal G[1] of the stage. The conventional gate driver mostly determines the voltage difference between the voltage level of the control node A and the voltage VSS to determine the voltage difference of the switch of the pull-down circuit, and the driving electrode 300 shown in the present disclosure can reduce the number of the switch T32 by this arrangement. The voltage difference between one end and the second end causes leakage of the switch T32 The current can be significantly reduced, thereby improving the operational reliability of the driver stage 300.

FIG. 5B is a schematic diagram showing the state of each switch in the driving stage 300 of FIG. 3 in the period T2 according to an embodiment of the present disclosure. As shown in FIGS. 4 and 5B, during the period T2 (that is, the time between the enable period of the pulse wave P1 and the enable period of the pulse wave P2), the pulse wave P1 of the initial pulse Din enters the disable period. During this period, the clock signal XHC is also switched to the low level voltage. Therefore, the switch T11, the switch T12, the switch T41, the switch T42, the switch T43, the switch T44, the switch T32, and the switch T31 are all turned off. Since the voltage level of the control node A has been pulled up to the voltage V1 in the previous period T1, the switch T21 can remain turned on. In this way, during the period T2, the clock signal HC is switched to the high level voltage, and is output as the current gate driving signal G[1] having the high level voltage via the switch T21, so that the pixel array 122 is pre-processed. Charging operation. In addition, the gate drive signal G[1] of this stage recharges the control node A via the capacitor C, and pulls the voltage level of the control node A up to the voltage V2.

Furthermore, as shown in FIG. 4, during the period T3, the initial pulse Din enters the enable period of the pulse wave P2, and the clock signal XHC switches to the high voltage level. At this time, the state of each switch of the driving stage 300 is the same as that of the previous FIG. 5A, that is, the switch T11, the switch T12, the switch T2, the switch T41, the switch T42, the switch T43 and the switch T44 are turned on, and the switch T32 and the switch T31. For shutdown.

At the same time, the clock signal HC is switched to the low voltage level, and the voltage level of the control node A is pulled down to the voltage V1 via the driving unit 240. However, in practice, since the voltage level of the control node A has been charged in the period T2 The voltage is increased to a higher voltage V2, so during the period T3, the voltage level of the control node A is only pulled down to the voltage V3, wherein the voltage V3 is higher than the voltage V1, and V3 = V1 + ΔV. In various embodiments, ΔV is approximately 1 to 3V.

Referring again to FIG. 4, during the period T4 (ie, after the enable period of the pulse wave P2), the initial pulse Din is switched to the low voltage level, and the clock signal XHC is also switched to the low level voltage. At this time, the state of each switch of the driving stage 300 is the same as that of the previous FIG. 5B, that is, the switch T11, the switch T12, the switch T32, the switch T31, the switch T41, the switch T42, the switch T43 and the switch T44 are turned off, and the switch T21 is conductive. At this time, the clock signal HC is switched to the high level voltage, and is output as the current gate driving signal G[1] having the high level voltage via the switch T21, so that the pixel array 122 performs the operation of writing the data signal.

At the same time, the gate drive signal G[1] of this stage will again charge the control node A via the capacitor C, and pull the voltage level of the control node A up to the voltage V2. As previously stated, in practice, the voltage level of the control node A has risen to a higher voltage V3 during the time period T3. Therefore, under the same charging time, the voltage level of the control node A can be pulled up to a higher voltage V4 during the period T4, and the gate driving signal G[1] of the current stage is also increased, wherein the voltage V4 It is higher than the voltage V2, and the voltage V4=V2+ΔV.

That is to say, the driver stage 300 can drive the gate driving signal G[1] with a higher voltage level when the pixel array 122 performs the operation of writing the data signal (ie, the period T4), and causes the drawing. The plurality of pixels 124 in the prime array 122 can have a better charging rate. Therefore, the size of the plurality of pixels 124 in the pixel array 122 can be reduced to improve the opening of the display panel 200. Aperture ratio. Alternatively, the size of the plurality of switches in the driver stage 300 can be reduced to reduce the area of the gate driver 160 to better meet the needs of narrow bezel applications.

FIG. 5C is a schematic diagram showing the state of each switch in the driving stage 300 of FIG. 3 in the period T5 according to an embodiment of the present disclosure. As shown in FIG. 4 and FIG. 5C, at the time period T5, the initial pulse wave Din and the clock signal HC are both low level voltages, and the clock signal XHC is a high level voltage. Therefore, the switch T12, the switch T41, and the switch T43 are turned on, and the switch T11, the switch T42, and the switch T43 are turned off. The clock signal XHC can pull the voltage level of the control node B to a high level voltage via the switch T43, thereby turning on the switch T32 and the switch T31. Thus, the voltage level of the control node A and the gate drive signal G[1] of the current stage are both pulled down to a low level voltage (for example, voltage VSS).

FIG. 6 is a timing diagram showing the operation of the driving stage 300 in FIG. 3 according to another embodiment of the present disclosure. As shown in FIG. 4, in this embodiment, the initial pulse wave Din can also be set to have only a single pulse wave P1, so that the display array 122 can be operated in a driving manner such as frame inversion and column inversion. For the operation of having only a single pulse wave P1, reference may be made to the operation description between the time period T1 and the time period T2 in the foregoing embodiment, and the details are not repeated herein.

In various embodiments of the present disclosure, each switch may be a transistor of each type, such as a metal oxide semiconductor field effect transistor (MOSFET), a bottom gate transistor, a top gate transistor, a thin film transistor, or the like. Wait. The foregoing is merely illustrative, and the invention is not limited thereto.

In summary, the display panel and the gate driver disclosed in the present disclosure can have various driving modes, and can provide a higher charging rate of the pixel array, thereby increasing the aperture ratio of the display panel or enabling the gate. The area of the pole drive is reduced to meet the needs of narrow bezel applications.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

300‧‧‧Driver

G[n], G[n-1]‧‧‧ gate drive signal

240‧‧‧ drive unit

260‧‧‧ Pulldown unit

264‧‧‧ Pulldown circuit

C‧‧‧ capacitor

T11, T12, T21, T31, T32, T41, T42, T43, T44‧‧‧ switch

XHC, HC‧‧‧ clock signals

Din‧‧‧ initial pulse wave

220‧‧‧ input unit

262‧‧‧ Pull-down control circuit

A, B‧‧‧ control node

VSS‧‧‧ voltage

Claims (9)

A display panel comprising: a plurality of gate lines; and a gate driver comprising a plurality of serially connected driver stages, wherein each driver stage is configured to output a gate drive signal to a corresponding one of the gate lines The Nth stage driver stage of the driver stage includes: an input unit for transmitting the gate driving signal outputted by an (N-1)th stage driving stage to a first control node, where N a positive integer, and the gate driving signal outputted by the (N-1)th stage driving stage includes a continuous first pulse wave and a second pulse wave; a driving unit configured to be according to the first control node a voltage level to output the gate drive signal; and a pull-down unit for pulling the gate drive signal to a first voltage after the second pulse is enabled, wherein the first pulse During the enabling period, the input unit pulls up the voltage level of the first control node to a second voltage, and after the enabling period of the second pulse wave, the driving unit voltages the first control node Level up to a third voltage, and the third voltage is greater than the second voltage Between the enabling period of the first pulse wave and the enabling period of the second pulse wave, the driving unit pulls up the voltage level of the first control node to a fourth voltage, and the third The voltage is greater than or equal to the fourth voltage. The display panel of claim 1, wherein the input unit transmits the gate driving signal of the (N-1)th stage driving stage according to a first clock signal, the input unit comprising: a first switch, a first end, a second end, and a control end, wherein the control end of the first switch is configured to receive the gate drive signal output by the (N-1)th stage drive stage, the first switch The first end is electrically coupled to the control end of the first switch; and the second switch includes a first end, a second end, and a control end, wherein the control end of the second switch is configured to receive The first clock signal is electrically coupled to the second end of the first switch, and the second end of the second switch is electrically coupled to the first control node. The display panel of claim 2, wherein the driving unit outputs the gate driving signal according to a voltage level of the first control node and a second clock signal, the first clock signal and the second time The driving signal comprises: a first switch, a first end, a second end, and a control end, wherein the control end of the first switch is electrically coupled to the first control node, The first end of the first switch is configured to receive the second clock signal, and the second end of the first switch is configured to output the gate driving signal; and a capacitor is electrically coupled to the first Between the control node and the first switch. The display panel of claim 3, wherein the pull-down unit comprises: a pull-down control circuit for outputting the driver stage according to the (N-1)th stage a gate drive signal adjusts a voltage level of a second control node; and a pull-down circuit electrically coupled to the second control node for pulling down the gate drive signal according to a voltage level of the second control node To the first voltage. The display panel of claim 4, wherein the pull-down control circuit comprises: a second switch comprising a first end, a second end, and a control end, wherein the control end of the second switch is configured to receive the a first clock signal, the first end of the second switch is electrically coupled to the control end of the second switch; a third switch includes a first end, a second end, and a control end, wherein the The control terminal of the third switch is electrically coupled to the second end of the second switch, the first end of the third switch is electrically coupled to the first end of the second switch, and the third switch is The second end is electrically coupled to the second control node; the fourth switch includes a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive the first (N) The first driving end of the fourth switch is electrically coupled to the second end of the second switch, and the second end of the fourth switch is configured to receive the gate driving signal. The first voltage; a fifth switch comprising a first end, a second end, and a control end, wherein the fifth switch The control terminal is configured to receive the gate driving signal of the output of the (N-1)th driving stage, the first end of the fifth switch is electrically coupled to the second control node, and the fifth switch The two ends are configured to receive the first voltage. The display panel of claim 4, wherein the pull-down circuit comprises: a second switch comprising a first end, a second end, and a control end, wherein the control end of the second switch is electrically coupled to the a second control node, the first end of the second switch is electrically coupled to the first control node, and the second end of the second switch is configured to receive the gate drive signal; and a third switch includes a first end, a second end, and a control end, wherein the control end of the third switch is electrically coupled to the second control node, and the first end of the third switch is electrically coupled to the first switch The second end of the third switch is configured to receive the first voltage. A gate driver comprising a plurality of serially connected driver stages, each of the driver stages comprising: an input unit comprising a first input terminal, a second input terminal and an output terminal, wherein The first input end of the input unit is configured to receive a pre-gate drive signal, the second input end of the input unit is configured to receive a first clock signal, and the output end of the input unit is electrically coupled Connected to a control node; a driving unit includes a first input end, a second input end, and an output end, wherein the first input end of the driving unit is electrically coupled to the control node, and the driving unit The second input terminal is configured to receive a second clock signal, and the output end of the driving unit is configured to output a current gate driving signal, wherein the first clock signal and the second clock signal are inverted; And a pull unit, including: a first switch having a first end, a second end, and a control end, wherein the control end of the first switch is configured to receive the first clock signal, and the first end of the first switch is electrically The second switch has a first end, a second end, and a control end, wherein the control end of the second switch is electrically connected to the first switch a first end of the second switch electrically connected to the first end of the first switch; a third switch having a first end, a second end, and a control end, wherein the third end The control terminal of the switch is configured to receive the front gate drive signal, the first end of the third switch is electrically coupled to the second end of the first switch, and the second end of the third switch is used Receiving a first voltage; a fourth switch having a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive the pre-gate drive signal, the fourth The first end of the switch is electrically coupled to the second end of the second switch, and the second end of the fourth switch Receiving the first voltage; a fifth switch having a first end, a second end, and a control end, wherein the control end of the fifth switch is electrically coupled to the second end of the second switch, The first end of the fifth switch is electrically coupled to the node of the control node, and the second end of the fifth switch is electrically coupled to the output end of the driving unit; and a sixth switch has a first One end, one second end, and one control The second end of the sixth switch is electrically coupled to the second end of the second switch, the first end of the sixth switch is electrically coupled to the output end of the driving unit, and the sixth The second end of the switch is for receiving the first voltage. The gate driver of claim 7, wherein the input unit comprises: a seventh switch having a first end, a second end, and a control end, wherein the control end of the seventh switch is electrically coupled The first input end of the input unit, and the first end of the seventh switch is electrically coupled to the control end of the seventh switch; and an eighth switch having a first end and a second end a control terminal, wherein the control terminal of the eighth switch is electrically coupled to the second input end of the input unit, the first end of the eighth switch is electrically coupled to the second end of the seventh switch, The second end of the eighth switch is electrically coupled to the output end of the input unit. The gate driver of claim 7, wherein the driving unit comprises: a seventh switch having a first end, a second end, and a control end, wherein the control end of the seventh switch is electrically coupled The first input end of the seventh switch is electrically coupled to the second input end of the seventh switch, and the second end of the seventh switch is electrically coupled to the drive unit The output; and A capacitor is electrically coupled between the control end of the seventh switch and the second end of the seventh switch.