TWI533272B - Display device and driving method thereof - Google Patents

Description

Display device and driving method thereof

The present invention relates to a display device and a driving method thereof, and more particularly to a display device with a shift register and a driving method thereof.

In recent years, liquid crystal displays and organic light emitting diode displays have become the mainstream of display devices, and have occupied the vast majority of applications in displays such as mobile devices, computers, and televisions.

In addition to displaying image quality, the design of the narrow bezel is also the goal of many display manufacturers, and Gate on Array (GOA) has been the main design for narrow frame without cost. One way. However, the physical characteristics of the gate drive circuit substrate technology make the display still less than the traditional gate drive chip (Gate IC) technology in terms of reliability and lifetime.

Many techniques are used today to stabilize the display and increase the life cycle of the display, but the use of past conventional operational timings may result in improper display operation and damage to the display.

In summary, how to design the operation timing to stabilize the display and increase The long life cycle of the display is one of the current research and development topics.

In one aspect of the present invention, a display device is provided. The display device includes a shift register, and the shift register includes a pre-stage shift register unit electrically coupled to each other and a stage shift register unit. The shift register unit of the present stage comprises an output circuit, an output control circuit, a disable circuit, a disable control circuit and a driver. The output circuit is configured to output a scanning signal of a current level having a pulse wave of a uniform level when a potential signal and a potential of a control node of the stage shift register unit are enabled; the output control circuit is electrically coupled The output circuit and the control node are configured to control the potential of the control node according to a pre-scan signal and a first enable voltage provided by the pre-stage shift register unit; the disable circuit is electrically coupled to the output control circuit and the control a node, when the disable circuit control signal is enabled, the disable circuit is configured to maintain the potential of the control node at an inactive level; the disable control circuit is electrically coupled to the disable circuit for receiving the A control signal is provided, and when the first control signal is enabled, an disable circuit control signal having an enable level is provided. The driver is electrically coupled to the shift register for providing the first control signal and the first enable voltage, and after the display device is activated, the first control signal reaches the enable level earlier than the first enable voltage.

Another aspect of the present invention provides a driving method for driving a display device including a shift register, the shift register including a pre-stage shift register unit electrically coupled to each other and a stage Shift the scratchpad unit. The shift register unit of the stage includes an output circuit, an output control circuit, and a disable Circuit and a disable control circuit. The driving method includes the following steps: providing a first control signal and a first enabling voltage, wherein after the display device is activated, the first control signal reaches a uniform level before the first enabling voltage; when the first control When the signal is enabled, the disable control circuit provides an disable circuit control signal with an enable level; when the disable circuit control signal is enabled, the disable stage shifts the stage The potential of one of the bit temporary storage units is maintained at an inactive level; according to a pre-scan signal and a first enable voltage provided by the pre-stage shift register unit, the output control circuit controls the shift of the stage The potential of the control node of the temporary storage unit; and when the potential of the one-time pulse signal and the control node is the enable level, the output circuit outputs the current-level scan signal having the pulse wave of the enable level.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. With the above technical solution, the display device and the driving method thereof provided by the present invention can enable the display panel to operate normally and stably, and can further extend the life of the display device. The above description will be described in detail in the following embodiments, and further explanation of the technical solutions of the present invention will be provided.

In order to make the case more obvious and easy to understand, the attached symbols are as follows:

100‧‧‧ display device

110‧‧‧ drive

111‧‧‧Control Module

112‧‧‧ initial module

113‧‧‧Power Module

114‧‧‧Delay module

115‧‧‧Control unit

116‧‧‧ level shifting unit

120‧‧‧ display panel

122‧‧‧Shift register

HC‧‧‧ clock signal

ST‧‧‧Start signal

LC‧‧‧Control signal

LC’‧‧‧Control Signal

LC”‧‧‧Control Signal

VGH‧‧‧Energy voltage

VGH1‧‧‧Energy voltage

200 ₁ ~ 200 _n ‧‧‧Shift register unit

210‧‧‧Output circuit

220‧‧‧Output control circuit

230‧‧‧ disable circuit

240‧‧‧ disable control circuit

C1~Cn‧‧‧ disable circuit control signal

Q(1)~Q(n)‧‧‧ control node

G(1)~G(n)‧‧‧ scan signal

HC ₁ ~HC _n ‧‧‧ clock signal

300‧‧‧Shift register unit

310‧‧‧Output circuit

320‧‧‧Output control circuit

330‧‧‧ disable circuit

340‧‧‧ disable control circuit

OUT1‧‧‧ output

S‧‧‧ control signal

T1~T20‧‧‧O crystal

Cp‧‧‧ capacitor

VSS‧‧‧ disable voltage

410‧‧‧ drive

412‧‧‧ initial module

414‧‧‧resistance

T1~t4‧‧‧ time point

500‧‧‧ drive method

S501, S502, S503, S504, S505‧‧‧ steps

600‧‧‧Shift register unit

230 ₁ ~ 230 _n ‧‧‧ disable subcircuit

240 ₁ ~ 240 _n ‧‧‧ disable control subcircuit

LC1~LCm‧‧‧ control signal

C11~C1m‧‧‧ disable circuit control sub-signal

700‧‧‧Shift register unit

330 ₁ ~330 _n ‧‧‧ disable subcircuit

340 ₁ ~ 340 _n ‧‧‧ disable control subcircuit

The above and other objects, features, advantages and embodiments of the present invention can be more clearly understood. The description of the drawings is as follows: FIG. 1 is a schematic view of a display device according to an embodiment of the present invention; Is shown in the shift register according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a shift register unit according to an embodiment of the present invention; FIG. 4A is a schematic diagram of a driver according to another embodiment of the present invention; FIG. 4B is a diagram according to an embodiment of the present invention; The signal timing diagram of the shift register unit is shown; FIG. 5 is a flowchart of the driving method according to an embodiment of the present invention; and FIG. 6 is a shift temporary storage according to an embodiment of the present invention. FIG. 7 is a circuit diagram of a shift register unit according to an embodiment of the present invention; and FIG. 8 is a signal timing diagram of the shift register unit according to an embodiment of the present invention.

The present invention will be more fully described in the present specification by reference to the accompanying drawings, in which FIG. However, the present invention is implemented in many different forms and should not be limited to the embodiments set forth in this specification. The description of the embodiments is intended to be thorough and complete, and the scope of the present invention will be fully described by those of ordinary skill in the art. The same reference numbers are used herein to refer to like elements.

When a component is referred to as "connected" or "coupled" to another component It can be directly connected or coupled to another component, or an additional component can be present.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the present invention. The display device 100 includes a driver 110 and a display panel 120. The driver 110 includes a control module 111, an initial module 112, a power module 113, and a delay module 114. The display panel 120 includes a shift register 122. The driver 110 is used to drive the display panel 120 to display an image.

The control module 111 includes a control unit 115 and a level-shift unit 116. The control module 111 is configured to generate the start signal ST, the clock signal HC, and the control signal LC. The control unit 115 is configured to generate a signal, and the level shifting unit 116 is configured to adjust the signal output by the control unit 115. The bit is such that the adjusted signal has sufficient voltage and becomes the input signal of the display panel 120. Further, the adjusted signal is the input signal of the shift register 122.

In some embodiments, the control unit can be a microprocessor.

The initial module 112 is configured to provide a control signal LC ′, wherein the control signal LC ′ provided by the control module 111 and the control signal LC ′ provided by the initial module 112 form a control signal LC, and the control signal LC is used to drive the display. The shift register 122 in the panel 120.

The power module 113 is configured to provide the consistent voltage VGH to the level shifting unit 116, the initial module 112, and the delay module 114 in the control module 111.

The delay module 114 is configured to delay the enable voltage VGH provided by the power module 113 to form a delayed enable voltage VGH1, and the delay module 114 is further configured to provide the enable voltage VGH1 to the shift register 122. In addition, the control signal LC reaches the enable level earlier than the enable voltage VGH1. For example, the enable level can be, for example, a high voltage level, which enables the circuit to operate normally. The ability to conduct a specific switch in the circuit can be achieved to achieve the corresponding function of the circuit. Further, the control signal LC' provided by the initial module 112 reaches the enable level earlier than the enable voltage VGH1 (for example, as shown in FIG. 4B below). On the other hand, the control signal LC also arrives at the enable level earlier than the start signal ST.

In some embodiments, the enable level is not limited to a single voltage value, and the enable level can be any one of the voltage intervals exceeding a threshold voltage.

In some embodiments, the delay module 114 can be an electrical series inverter.

The structure of the shift register 122 included in the display panel 120 will be further explained with reference to FIG. FIG. 2 is a schematic diagram of a shift register 122 according to an embodiment of the present invention. The shift register 122 includes a plurality of shift register units 200 ₁ 200 200 _{n for} outputting a scan signal G ( 1)~G(n), wherein the shift register unit 200 ₁ and the shift register unit 200 ₂ are electrically coupled to each other, and the remaining shift register units 200 ₂ - 200 _n are adjacent between the two The connection relationship is similar to the connection relationship between the shift register unit 200 ₁ and the shift register unit 200 ₂ . For example, the shift register unit 200 _(n-1) and the shift register unit 200 _n are electrically coupled to each other.

In the present embodiment, based on the above connection relationship, when the shift temporary storage unit 200 _{2 is} referred to as the current stage shift temporary storage unit, the shift temporary storage unit 200 ₁ is referred to as a front stage shift temporary storage unit.

Each of the shift register units 200 ₁ to 200 _n includes an output circuit 210, an output control circuit 220, an disable circuit 230, and an disable control circuit 240. In some embodiments, the output circuit 210 is also referred to as a pull-up circuit, the output control circuit 220 is also referred to as a pull-up control circuit, the disable circuit 230 is also referred to as a pull-down circuit, and the disable control circuit 240 is also referred to as a pull-down control circuit. .

Taking the shift register unit 200 ₁ as an example, the output circuit 210 is electrically coupled to the output control circuit 220 and the control node Q(1). The input signals of the output circuit 210 are the clock signal HC ₁ and the control node Q (1). potential, wherein, when the potential of the clock signal HC ₁ and the control node Q (1) when the level is enabled, the output circuit 210 outputs a pulse for enabling the level of the scanning signals G (1), the general In other words, the scanning signals G(1)~G(n) sequentially generate driving pulses of high level, and the shift register units 200 ₁ ~ 200 _{n of the stages} have similar operating modes.

On the other hand, the clock signals HC ₁ to HC _n are generated based on the clock signal HC outputted by the control module 111. Generally, the clock signal HC includes a plurality of clock sub-signals. For example, the clock signal HC may include two complementary sub-signals, and the complementary sub-signals are repeatedly arranged to generate corresponding clock signals HC ₁ ~HC _n (similar to the content of the patent publication No. US 7406146 B2) On the other hand, the clock signal HC may also include a plurality of clock signals having different phases, wherein the clock signals having different phases may be repeatedly arranged to generate the clock signals HC ₁ to HC _n ( Similar to the patent publication number US 2013/0127797 A1). However, the above embodiment is only based on the embodiment in which the clock signals HC ₁ to HCn are generated based on the clock signal HC, and the manner in which the clock signals HC ₁ to HC _n are generated based on the clock signal HC is not affected by the above embodiment. Limited.

It should be noted that in the clock signals HC ₁ ~HC _n , each k pulse signals are a group, and the instantaneous pulse signals HC ₁ ~HC _k are a group, and the clock signals HC _(k+1) ~HC _{( 2k)} , the clock signals HC _(2k+1) ~ HC _(3k) and other clock signals are the same as the clock signals HC ₁ ~ HC _k . For example, if k is 8, the clock signals HC ₁ to HC ₈ are a group, and the clock signals HC ₉ to HC ₁₆ and the clock signals HC ₁₇ to ₂₄ are the same as the clock signals HC ₁ to HC _{8 , respectively} .

The output control circuit 220 is electrically coupled to the output circuit 210 and the control node Q(1), and is configured to adjust the potential of the control node Q(1) according to the start signal ST and the enable voltage VGH1, when the start signal ST and the enable voltage VGH1 are activated. When the enable level is enabled, the output control circuit 220 causes the control node Q(1) to have an enable level. When one of the enable signal ST and the enable voltage VGH1 has a disable level, the output control circuit 220 does not cause the control node Q(1) to have an enable level.

The disable circuit 230 is electrically coupled to the output control circuit 220 and the control node Q(1). When the disable circuit control signal C1 has an enable level, the disable circuit 230 is used to shift the temporary storage unit at the non-stage. when the scan signal output of the high level, maintaining the control node Q (1) the potential level at the disable, in other words, the disable circuit 230 to the shift register unit level control node Q ₍₁₎ 200 1 is When the level is disabled, the disable level of the control node Q(1) is further maintained.

In some embodiments, when the disable circuit control signal C1 has an enable level, the disable circuit 230 is further configured to maintain the potential of the scan signal G(1) at the disable level.

The disable control circuit 240 is electrically coupled to the disable circuit 230 and receives the control signal LC. When the control signal LC has an enable level, the disable control circuit 240 is configured to provide the disable circuit control signal C1 having the enable level. In other words, the disable control circuit 240 is configured to output the signal according to the control signal LC. The disable circuit can control the signal C1, and the disable control circuit 240 can output the disable circuit control signal C1 with the enable level only when the control signal LC is the enable level. The output control circuit 220 of the shift register unit 200 ₂ ~ 200 _n receives the corresponding previous stage shift register unit 200 ₁ ~ 200 _(n-1) , respectively, compared with the shift register unit 200 ₁ receiving the start signal ST. The output scan signals G(1)~G(n-1), the output circuit 210 of the shift register unit 200 ₂ ~ 200 _n are electrically coupled to the control nodes Q(2) to Q(n), respectively. The disable circuit 230 of the shift register unit 200 ₂ ~ 200 _n receives the disable circuit control signals C2 C Cn respectively.

In addition, in operation, since the output control circuit 220 is not an ideal circuit, when the display device 100 is activated, if the enable signal VGH1 reaches the enable level earlier than the control signal LC in the conventional signal driving manner. In the case where the output control circuit 220 generates a leakage current due to the enable voltage VGH1, the potentials of the control nodes Q(1) to Q(n) are not a disable level, and the clock signals HC ₁ to HC _n are Each k clock signal is a group. In other words, the clock signals such as the clock signal HC _1, the clock signal HC _(k+1) , and the clock signal HC _(2k+1) have the same potential, therefore, when the clock signal output circuit ₂₀₀₁ of the shift register unit 210 having received HC ₁ enable level, the clock signal HC ₁ is coupled with the output circuit 210 outputs the enable level of the scanning signal G (1) and with the clock signal HC ₁ clock signal the same with the enable level (the clock signal HC _{(k + 1),} the clock signal HC _{(2k + 1),} etc.) are also of the corresponding output circuit 210 generates abnormal The output, that is, the scan signal having the enable level, in turn affects the display panel 120 to display the correct image.

For example, if the clock signals HC ₁ ~ HC _n are in groups of six (the instantaneous pulse signals HC ₇ ~ HC ₁₂ , the clock signals HC ₁₃ ~ HC _18, etc., the clock signals are the same as the clock signals HC ₁ ~ HC ₆ ), and when the clock signal HC ₁ has an enable level, the scan signals G(1), G(7), G(13) corresponding to the clock signals HC ₁ , HC ₇ and HC ₁₃ have an enable level Instead of only the scanning signal G(1) having an enable level, the display panel 120 is caused to display an erroneous image.

However, the control signal LC outputted by the driver 110 proposed in the present case reaches the enable level earlier than the enable voltage VGH1, so the disable control circuit 240 of each shift register unit 200 ₁ ~ 200 _n is no later than enabled. When the voltage VGH1 reaches the enable level, it starts, and keeps the power of the control nodes Q(1)~Q(n) at the disable level, so that after the display device 100 is started, the control nodes Q(1)~Q(n) The potential can maintain the disable level until the output control circuit 220 of each shift register unit 200 ₁ ~ 200 _n pulls up the potential of the corresponding control node Q(1)~Q(n). In other words, before the control module 111 provides the start signal ST, each disable circuit 230 shifts the control nodes Q(1)~Q of the temporary storage unit 200 ₁ ~ 200 _n according to the disable circuit control signals C1 C Cn ( The potential of n) is maintained at the disable level. When the control module provides the start signal ST, the potentials of the control nodes Q(1)~Q(n) can maintain the disable level until each shift register unit 200 The output control circuit 220 of ₁ to 200 _n pulls up the potential of the corresponding control node Q(1) to Q(n). Therefore, compared with the conventional signal driving method, the driver 110 provided in the present invention can ensure the normal operation of the display panel 120.

Referring to FIG. 3 together, FIG. 3 is a circuit diagram of the shift register unit 300 according to an embodiment of the present invention. The shift register unit 300 takes the shift register unit 200 ₁ as an example, and includes an output circuit 310, an output control circuit 320, an disable circuit 330, and an disable control circuit 340. The functions of the output circuit 310, the output control circuit 320, the disable circuit 330, and the disable control circuit 340 are equivalent to the output circuit 210, the output control circuit 220, the disable circuit 230, and the disable control circuit 240 of FIG. The shift register unit 300 shown in FIG. 3 is only one embodiment of the shift register unit 200 ₁ and is not intended to limit the present invention. In addition, the aforementioned patent publication No. US 7406146 B2 and the patent publication number US 2013 The circuit structure of the shift register unit described in /0127797 A1 can also be separately applied to the shift register unit of the present invention.

The output circuit 310 comprises a transistor T1, a first terminal of the transistor T1 receives the clock signal used when HC _1, a second terminal of the transistor T1 coupled to the output terminal OUT1 and outputs scanning signals G (1), and electrical The control terminal of the crystal T1 is used to receive the potential of the control node Q(1). Thus, when the control node Q (1) having a potential of the enable level, the transistor T1 will be turned on, so that the scanning signal G of the output terminal OUT1 (1) having _an electric potential of the HC clock signal.

The output control circuit 320 includes a transistor T2. The first end of the transistor T2 is electrically coupled to the enable voltage VGH1, and the second end of the transistor T2 is electrically connected. The control terminal Q(1) is coupled to the control node Q(1), and the control terminal of the transistor T2 is configured to receive the start signal ST. When the enable signal ST has an enable level, the transistor T2 is turned on and the control node Q(1) has a potential of the enable voltage VGH1, that is, the capacitor Cp stores the potential of the enable voltage VGH1.

The disable circuit 330 includes a transistor T3 and a transistor T4. The first end of the transistor T3 is electrically coupled to the control node Q(1), and the second end of the transistor T3 is electrically coupled to the disable voltage VSS. The control terminal of the transistor T3 receives the disable circuit control signal C1; the first end of the transistor T4 is electrically coupled to the output node OUT1, and the second end of the transistor T4 is electrically coupled to the disable voltage VSS, the transistor T4 The control terminal receives the disable circuit control signal C1. Therefore, when the disable circuit control signal C1 has an enable level, the transistor T3 and the transistor T4 pull down the potentials of the control node Q(1) and the output node OUT1 to the disable level, that is, the scan signal G(1). With a disable level.

In some embodiments, the potential of the disable voltage VSS is zero.

The disable control circuit 340 includes a transistor T5~T10. The first end of the transistor T5 and the control terminal receive the control signal LC. The second end of the transistor T5 is electrically coupled to the control terminal of the transistor T6, and the transistor T7. The first end and the first end of the transistor T9. The first end of the transistor T6 receives the control signal LC, and the second end of the transistor T6 is electrically coupled to the first end of the transistor T8 and the transistor T10, and is used for outputting the disable circuit control signal C1 to the disable circuit 330. The control terminals of the transistor T7, the transistor T8, the transistor T9, and the transistor T10 are electrically coupled to the control node Q(1), the transistor T7, the transistor T8, the transistor T9, and the second end of the transistor T10. Electrically coupled to the disable voltage VSS. When the control node Q(1) has an enable level, the transistor T7, electricity The crystal T8, the transistor T9 and the transistor T10 are turned on, and then the disable circuit control signal C1 is pulled down to the disable voltage VSS, so the disable control circuit 340 outputs the disable circuit control signal C1 with the disable level; When the node Q(1) has a disable level and the control signal LC has an enable level, the disable circuit control signal C1 has an enable level. At this time, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 is turned off, so when the enable level of the control signal LC is conducted to the transistor T5 and the transistor T6, the disable circuit control signal C1 is pulled to the enable level of the control signal LC or substantially equal to the enable of the control signal LC. Level.

In addition, the transistor T2 of the output control circuit 320 receives the enable voltage VGH1 having the enable level, so that the transistor T2 generates the leakage current as described above, thereby charging the capacitor Cp (ie, the potential of the control node Q(1) rises. In the case where the disable circuit 330 does not have the potential to pull down the control node Q(1), the potential of the control node Q(1) causes the transistor T1 to be turned on. Subsequently, when the pulse signal HC ₁ has an enable level, if the control signal LC cannot pull down the potential of the control node Q(1) to the disable level, all the outputs of the clock signal HC _{1 are} electrically coupled. The circuit 310 outputs a scanning signal G(1) having an enable level, thereby causing the display panel 120 to operate abnormally.

The control signal LC (ie, the control signal LC' of FIG. 1) provided by the initial module 112 in FIG. 1 of the present invention reaches the enable level earlier than the enable voltage VGH1. Therefore, the enable voltage VGH1 reaches the enable level. Before the level, the control signal LC will cause the disable circuit 330 to pull down the potential of the control node Q(1) to the disable level, thereby preventing the output circuit 310 from being abnormally turned on.

In addition, as shown in Figure 3, the transistor T11 is electrically coupled to the control Between the node Q (1) and the disable voltage VSS, the control terminal of the transistor T11 is used to receive the control signal S, and the transistor T12 is electrically coupled between the output node OUT1 and the disable voltage VSS, and the transistor T12 The control terminal is configured to receive the control signal S, wherein the control signal S is used to control the potentials of the output node OUT1 and the control node Q(1).

In some embodiments, the control signal S can be the scan signal G(2) or the scan signal G(3). If the shift register unit 300 is the shift register unit 200i, the control signal S can be a scan signal. G(i+1) or G(i+2), where i is a positive integer.

Referring to FIG. 4A and FIG. 4B together, FIG. 4A is a schematic diagram of the driver 410 according to an embodiment of the present invention. The initial module 412 of the driver 410 includes a resistor 414 compared to the driver 110 shown in FIG. The resistor 414 includes a first end and a second end. The first end of the resistor 414 is electrically coupled to the shift register 122, and the second end of the resistor 414 is configured to receive the enable voltage VGH provided by the power module 113. Therefore, when the enable voltage VGH reaches the enable potential, the control signal LC' (ie, the control signal LC) also reaches the enable potential. In addition, since the enable voltage VGH1 reaches the enable level later than the enable voltage VGH, the control signal LC' provided by the initial module 412 reaches the enable level earlier than the enable voltage VGH1.

FIG. 4B is a timing diagram of the signal of the shift register unit 400 according to an embodiment of the present invention. As shown in FIG. 4B, first, at time t1, the power module 113 starts to provide a uniform level. The enable voltage VGH, at the same time, the initial module 112 receives the enable voltage VGH so that the control signal LC' also reaches the enable level, causing the control signal LC to reach the enable level. Bit.

At time t2, the delay module 114 outputs an enable voltage VGH1, wherein the enable voltage VGH1 and the enable voltage VGH have a delay time (t2-t1).

At time t3, the control module 111 starts to output the start signal ST, the control signal LC", and the clock signal HC. Between the time point t1 and the time point t3, since the control module 111 does not output the control signal LC", Therefore, the control signal LC is mainly dominated by the control signal LC'; after the time point t3, the control module 111 starts to output the control signal LC", and the output resistance of the control module 111 is almost zero, resulting in the control generated by the delay module 114. The signal LC' is replaced by the control signal LC" generated by the control module 111, so that the control signal LC after the time point t3 is dominated by the control signal LC".

At the time point t4, the clock signal HC reaching enable level, so that based on the clock signal when the clock signal HC produced by _{HC. 1} begins with enabling level, if the control node Q (1) the potential at the same time enabling potential When the scanning signal G(1) will have an enable potential.

5 is a complete description of the driving method 500 of the display device 100, and FIG. 5 is a flowchart of the driving method 500 according to an embodiment of the present invention. In the embodiment, the driving method 500 is exemplified by driving the two-stage shift temporary storage unit 200 ₁ -200 ₂ , wherein the shift temporary storage unit 200 _{1 is} also referred to as a front-stage shift temporary storage unit, and the shift temporary storage unit The unit 200 _{2 is} also referred to as a shift register unit of the present stage, but is not limited thereto.

In step S501, the driver 110 provides the control signal LC and the enable voltage VGH1, wherein after the display device 100 is started, the control The signal LC reaches the enable level earlier than the enable voltage VGH1.

In the step S502, when the control signal LC is in the enable level, the disable control circuit 240 of the shift register units 200 ₁ - 200 ₂ respectively provides the disable circuit control signal C1 with the enable level and the forbidden The circuit control signal C2.

In step S503, when the disable circuit control signal C1 and the disable circuit control signal C2 are enabled, the disable circuit 230 of the shift register units 200 ₁ - 200 ₂ respectively maintains the control node Q ( 1) The potential of the control node Q(2) is at the disable level.

In step S504, the drive 110 according to the supplied start signal ST and VGH1 enable voltage, output by the shift register unit ₂₀₀₁ is a control circuit 220 for controlling the potential of the control node Q (1); and the shift Temporarily the storage unit ₂₀₀₁ provides a preceding stage scan signal G (1) and the enable voltage VGH1, output by the shift register control circuit unit ₂₀₀₂ controls the shift register unit 220 controls the node Q ₍₂₎ 200 2 of Potential.

In step S505, when the potential of the pulse signal HC ₁ and the control node Q(1) is the enable level, the output circuit 210 of the shift register unit 200 ₁ outputs the pulse wave having the enable level. Level scan signal G(1). When the potential of the pulse signal HC ₂ and the control node Q(2) is the enable level, the output circuit 210 of the shift register unit 200 ₂ outputs the scan signal G of the current level having the pulse wave of the enable level ( 2).

As described above, the display device 100 and the driving method 500 thereof provided by the present invention can effectively stabilize the operation of the shift register 122 in the display panel 120 and prevent erroneous driving due to non-ideality of internal electronic components. the way.

Referring to FIG. 6, FIG. 6 is a schematic diagram of the shift register unit 600 according to an embodiment of the present invention; compared to the shift register unit 200 ₁ shown in FIG. 2, the shift register unit 600 The disable circuit 230 includes a plurality of disable sub-circuits 230 ₁ - 230 _m , and the disable control circuit 240 includes disable control sub-circuits 240 ₁ - 240 _m for respectively receiving different control signals LC1 LCm, and disabling the control circuit The disable circuit control signal C1 generated by 240 includes the disable circuit control sub-signals C11~C1m. The disable sub-circuits 230 ₁ - 230 _m are electrically coupled to the disable control sub-circuits 240 ₁ - 240 _{m , respectively} .

In this embodiment, the output control circuit 220 receives the start signal ST, and the output control circuit 220 can also receive the scan signal output by the previous stage shift register unit.

The disable sub-circuits 230 ₁ to 230 _m respectively receive the disable circuit control sub-signals C11 to C1m generated from the disable control sub-circuits 240 ₁ to 240 _m . Cut-off at 230 and ₁ disable sub-circuit can control the sub-circuit ₂₄₀₁ as an example, when the disable circuit control signal C11 having the sub-level enable, disable the pull-down control node 230 ₁ sub-Q circuit (1) and the scanning signals G (1) To the disable level, when the disable circuit control sub-signal C11 is disabled, the disable sub-circuit 230 ₁ does not operate.

The disable control sub-circuits 240 ₁ to 240 _m determine the potentials of the disable circuit control sub-signals C11 to C1m according to the potential of the control node Q(1) and the potentials of the control signals LC1 to LCm, respectively. Taking the disable control sub-circuit 240 ₁ as an example, when the potential of the control node Q(1) is the disable level and the potential of the control signal LC1 is the enable level, the disable circuit controls the potential of the sub-signal C11 to be enabled. When the potential of the control node Q(1) is the enable level, the disable circuit controls the sub-signal C11 to be the disable level.

Referring to FIG. 7, FIG. 7 is a circuit diagram of the shift register unit 700 according to an embodiment of the present invention. Compared with the shift register unit 300 of FIG. 3, the shift register unit 700 is further A plurality of disable sub-circuits 330 ₁ to 330 ₂ and disable control sub-circuits 340 ₁ to 340 _{2 are included} . Compared with the shift register unit 600 of FIG. 6, the shift register unit 700 takes two disable sub-circuits 330 ₁ to 330 ₂ and the disable control sub-circuits 340 ₁ to 340 ₂ as examples, but the disabler The number of circuits 330 ₁ to 330 _m and the disable control sub-circuits 340 ₁ to 340 _m are not limited to two.

The connection relationship and function of the disable sub-circuit 330 ₁ and the disable control sub-circuit 340 ₁ are similar to the disable circuit 330 and the disable control circuit 340 in FIG. 3; the disable sub-circuit 330 ₂ and the disable control sub-circuit 340 The connection relationship and function of ₂ are similar to the disable circuit 330 and the disable control circuit 340 in FIG. 3, except that the control signals LC1, LC2 received by the disable control sub-circuits 340 ₁ - 340 ₂ are different from the disable circuit 330. Received control signal LC.

Referring to FIG. 8 to illustrate the timing of the control signals LC1 and LC2, FIG. 8 is a timing diagram of the signal of the shift register unit 700 according to an embodiment of the present invention, wherein the shift register unit 700 can be FIG 1 driver 110 is driven, and the control signal LC of FIG. 1 comprises a control signal LC1 ~ LC2, the clock signal HC ₁ ~ HC _n is HC via the clock signal output of sampler driver 110, and via a different delay produce.

First, at time t1, the power module 113 starts to provide the enable voltage VGH with the enable level, and at the same time, the initial module 112 receives the enable voltage VGH so that the control sub-signals LC1 and LC2 also reach the enable level. .

At time t2, the delay module 114 outputs the delayed enable voltage VGH1, wherein the enable voltage VGH1 and the enable voltage VGH have a delay time (t2-t1).

At time t3, the control module 111 starts outputting the start signal ST, the control signal LC (including the control signals LC1, LC2), and the clock signal HC. Between the time point t1 and the time point t3, the control signals LC1, LC2 are mainly dominated by the initial module 112, and the control signals LC1, LC2 both have an enable level; after the time point t3, the control module 111 starts output control. The signal LC1, LC2, and the output resistance of the control module 111 are almost zero, so that the control signals LC1, LC2 are mainly dominated by the control module 111, and the control signals LC1, LC2 will be activated to enable the level. The energy circuits 330 ₁ , 330 ₂ alternately maintain the potential of the control node Q(1) of the shift register unit 700 at the disable level according to the disable circuit control sub-signals C11 and C12 to avoid the disable control sub-circuit. Sustained action produces a serious electrical offset.

At the time point t4, the clock signal HC reaching enable level, so that based on the clock signal when the clock signal HC produced by _{HC. 1} begins with enabling level, if the control node Q (1) the potential at the same time enabling potential When the scanning signal G(1) will have an enable potential.

Therefore, if each of the k signals of the clock signals HC ₁ to HC _n , the instantaneous pulse signals HC ₁ ~ HC _k are a group, and the clock signals HC _(k+1) ~ HC _2k , the clock signal HC _{(2k +1)} ~HC _3k and the like are the same as the clock signals HC ₁ ~HC _k . Before the start signal ST reaches the enable level, the disable sub-circuits 230 ₁ ~ 230 _{m of} each shift register unit 600 will be simultaneously pulled down. Controlling the nodes Q(1)~Q(n) to the disable level, so as to prevent the corresponding output circuit 210 from outputting the scan signals G(1), G(k+1), G(2k+1), etc. abnormally; After the enable signal ST reaches the enable level, the disable sub-circuits 230 ₁ - 230 _{m of} each shift register unit 600 will alternately pull down the control nodes Q(1)~Q(n) to the disable level. Compared with the single disable circuit 230, the plurality of disable sub-circuits 230 ₁ ~ 230 _m can evenly share the current generated by pulling down the potentials of the control nodes Q(1)~Q(n), so that the shift register unit The life of the 700 can be extended.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. With the above technical solution, considerable technological progress can be achieved, and the industrial use value is widely used. In addition to avoiding errors in scanning timing, the display device and the driving method provided in the present invention can effectively extend the life of the display device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present case. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the case. Therefore, the scope of protection of this case is considered. The scope defined in the patent application is subject to change.

100‧‧‧ display device

110‧‧‧ drive

111‧‧‧Control Module

112‧‧‧ initial module

113‧‧‧Power Module

114‧‧‧Delay module

115‧‧‧Control unit

116‧‧‧ level shifting unit

120‧‧‧ display panel

122‧‧‧Shift register

HC‧‧‧ clock signal

ST‧‧‧Start signal

LC‧‧‧Control signal

LC’‧‧‧Control Signal

LC”‧‧‧Control Signal

VGH‧‧‧Energy voltage

VGH1‧‧‧Energy voltage

Claims (11)

A display device includes: a shift register comprising a pre-stage shift register unit electrically coupled to each other and a stage shift register unit, the shift of the stage The temporary storage unit includes: an output circuit for outputting a local level scan of a pulse wave having a uniform level when a potential signal and a potential of a control node of the shift register unit of the present stage are enabled. An output control circuit electrically coupled to the output circuit and the control node for controlling the control node according to a pre-scan signal and a first enable voltage provided by the pre-stage shift register unit a disable circuit, electrically coupled to the output control circuit and the control node for controlling a signal according to an disable circuit, and when the disable circuit control signal is the enable level, the control node The potential is maintained at an inactive level; and an disable control circuit is electrically coupled to the disable circuit for receiving a first control signal, and when the first control signal is the enable level, Providing the disable circuit control with the enable level And a driver electrically coupled to the shift register for providing the first control signal and the first enable voltage, and after the display device is activated, the first control signal is earlier than the first The uniform energy voltage reaches the enabling level. The display device of claim 1, wherein the drive further comprises: An initial module is configured to provide the first control signal having the enable level before the first enable voltage reaches the enable level. The display device of claim 2, wherein the initial module comprises: a resistor, comprising a first end and a second end, the first end is electrically coupled to the shift register, and the second end is configured to receive a a second enable voltage, wherein the second enable voltage reaches the enable level earlier than the first enable voltage. The display device of claim 1, wherein the driver further comprises: a power module for providing a second enable voltage; a delay module electrically coupled to the power module and the shift And a buffer for delaying the second enable voltage to generate the first enable voltage to the output control circuit, so that the first control signal reaches the enable level earlier than the first enable voltage. The display device of any one of claims 1 to 4, wherein the driver further comprises: a control module electrically coupled to the pre-stage shift register unit for providing a one having the enable level The activation signal is such that the potential of the control node of the pre-stage shift register unit has the enable level, wherein after the display device is activated, the first control signal reaches the enable level before the start signal . The display device of claim 5, wherein the disable circuit package a plurality of disable sub-circuits, wherein the disable circuit control signal includes a plurality of disable circuit control sub-signals; and the disable sub-circuit controls the sub-signal according to the disable circuits before the control module provides the start signal Maintaining the potential of the control node of the stage shift register unit at the disable level, wherein the disable circuit control sub-signals have the enable level; when the control module provides the start signal After the disable circuit sub-circuit, the potential of the control node of the current stage shift register unit is maintained at the disable level according to the disable circuit control sub-signals, wherein the disable circuits are The control sub-signal rotates to have the enabling level. A driving method for driving a display device including a shift register, the shift register comprising a pre-stage shift register unit electrically coupled to each other and a stage shift register unit The stage shift register unit includes an output circuit, an output control circuit, an disable circuit, and a disable control circuit, wherein the driving method includes: providing a first control signal and a first enable voltage, After the display device is activated, the first control signal reaches a uniform level before the first enable voltage; when the first control signal is the enable level, the disable control circuit Providing a disable circuit control signal having the enable level; when the disable circuit control signal is the enable level, the disable circuit is configured to shift the control unit to one of the temporary storage units The potential is maintained at an inactive level; And controlling, by the output control circuit, a potential of the control node of the current shift register unit according to a pre-scan signal and the first enable voltage provided by the pre-stage shift register unit; and when a clock is used When the signal and the potential of the control node are the enable level, the output circuit outputs a scan signal of the current level having the pulse wave of the enable level. The driving method of claim 7, wherein the display device further comprises an initial module, and the step of providing the first control signal and the first enabling voltage further comprises: reaching the first enabling voltage The first control signal having the enable level is provided by the initial module before the level is enabled. The driving method of claim 7, wherein the display device further comprises a delay module, wherein the step of providing the first enable voltage further comprises: providing a second enable voltage; and delaying by the delay module The second enable voltage is to provide the first enable voltage. The driving method of any one of claims 7 to 9, wherein the driving method further comprises: outputting an activation signal to control a potential of a control node of the pre-stage shift register unit, wherein the display is After the device is started, the first control signal reaches the enable level earlier than the start signal. The driving method of claim 10, wherein the disable circuit comprises a plurality of disable sub-circuits, the disable circuit control signal includes a plurality of disable circuit control sub-signals, and the potential of the control node is maintained in the The step of aligning includes: controlling the sub-signals according to the disable circuits before outputting the start signal, and simultaneously maintaining the potential of the control node of the shift register unit of the current stage by using the disable sub-circuits In the disable level, wherein the disable circuit control sub-signals have an enable level; and after outputting the start signal, the sub-signals are controlled according to the disable circuits, and by using the disablers The circuit alternately maintains the potential of the control node of the current stage shift register unit at the disable level, wherein the disable circuit controls the sub-signal to have the enable level.