CN107909980B - GOA circuit and liquid crystal display device with same - Google Patents
GOA circuit and liquid crystal display device with same Download PDFInfo
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- CN107909980B CN107909980B CN201711440507.9A CN201711440507A CN107909980B CN 107909980 B CN107909980 B CN 107909980B CN 201711440507 A CN201711440507 A CN 201711440507A CN 107909980 B CN107909980 B CN 107909980B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 29
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 3
- 239000010409 thin film Substances 0.000 claims description 132
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000005540 biological transmission Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 101100134058 Caenorhabditis elegans nth-1 gene Proteins 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 102200007391 rs794726878 Human genes 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The invention discloses a GOA circuit, which comprises a plurality of cascaded GOA units, wherein the nth GOA unit charges the nth horizontal scanning line of a display area, the nth GOA unit comprises a pull-up control circuit, a pull-up control reinforcing circuit, a pull-down circuit, a first pull-down maintaining circuit and a second pull-down maintaining circuit, and n is a positive integer. The GOA circuit can improve the driving capability of the GOA circuit by improving the output capability of the pull-up circuit, thereby improving the charging rate of the liquid crystal display panel. The invention also discloses a liquid crystal display device which is provided with the GOA circuit.
Description
Technical Field
The present invention relates to the field of liquid crystal display technologies, and in particular, to a Gate driver On Array (GOA) circuit and a liquid crystal display device having the same.
Background
The lcd has the advantages of light weight, short size, energy saving, and generally lower radiation index than a CRT (Cathode Ray Tube), so that the lcd gradually replaces the CRT to be widely applied to various electronic products. At present, the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly performed by an IC (Integrated Circuit) externally connected to the panel, and the externally connected IC can control the charging and discharging of each level of the horizontal scanning lines step by step. In the GOA technology, a Gate line scanning driving signal circuit is fabricated on an array substrate by using a TFT (Thin film transistor) liquid crystal display array process to realize driving of Gate line-by-line scanning, so that a driving circuit of a horizontal scanning line can be fabricated on a substrate around a display area by using an original process of a liquid crystal display panel. The GOA technology can reduce the binding procedure of an external IC, improve the productivity, reduce the product cost and make the liquid crystal display panel more suitable for manufacturing narrow-frame or frameless display products.
The main architecture of the GOA circuit includes: the pull-up circuit comprises a pull-up control circuit, a pull-up circuit, a pull-down maintaining circuit and a Boast (bootstrap) capacitor responsible for potential rise. When the pull-up control signal Q (n) is at a high potential, the higher the voltage of the pull-up control signal Q (n), the faster the waveform of the scan drive signal G (n) rises, and the higher the charging rate of the liquid crystal display panel. That is, the waveform of the pull-up control signal q (n) determines the driving capability of the GOA circuit. Therefore, in order to improve the driving capability of the GOA circuit, how to increase the voltage of the pull-up control signal q (n) becomes a problem to be solved.
Disclosure of Invention
Embodiments of the present invention provide a GOA circuit and a liquid crystal display device having the same, in which a pull-up control enhancement circuit is added to the GOA circuit, so as to improve the driving capability of the GOA circuit and further improve the charging rate of a liquid crystal display panel.
The embodiment of the invention provides a GOA circuit, which comprises a plurality of cascaded GOA units, wherein the nth GOA unit charges the nth horizontal scanning line of a display area, and comprises a pull-up control circuit, a pull-up control reinforcing circuit, a pull-down circuit, a first pull-down maintaining circuit and a second pull-down maintaining circuit, wherein n is a positive integer;
the pull-up control circuit receives a starting signal CT and outputs a pull-up control signal Q (n) according to the starting signal CT;
the pull-up circuit receives the pull-up control signal Q (n) and a clock signal C L K, and outputs an nth stage transmission signal ST (n) and an nth stage scanning driving signal G (n) according to the pull-up control signal Q (n) and the clock signal C L K;
the pull-up control enhancement circuit receives the nth stage scanning driving signal G (n) and pulls up the pull-up control signal Q (n) according to the nth stage scanning driving signal G (n);
the pull-down circuit receives a direct-current low-voltage signal Vss, pulls down the pull-up control signal Q (n) according to the direct-current low-voltage signal Vss, and further pulls down the nth-stage scanning driving signal G (n) so that the pull-up control signal Q (n) and the nth-stage scanning driving signal G (n) are in a closed state;
the first pull-down maintaining circuit receives a first low frequency signal L C1 and the dc low voltage signal Vss, and maintains the pull-up control signal q (n) and the nth stage scan driving signal g (n) in an off state according to the first low frequency signal L C1 and the dc low voltage signal Vss;
the second pull-down maintaining circuit receives a second low frequency signal L C2 and the dc low voltage signal Vss, and maintains the pull-up control signal q (n) and the nth stage scan driving signal g (n) in an off state according to the second low frequency signal L C2 and the dc low voltage signal Vss.
When n is 1, the starting signal CT is an initial signal STV; when n >1, the start signal CT is the n-1 th level transfer signal ST (n-1) and the n-1 th level scan driving signal G (n-1) output by the n-1 th level GOA unit.
Wherein the first pull-down sustain circuit and the second pull-down sustain circuit alternately function to maintain the pull-up control signal q (n) and the nth stage scan driving signal g (n) in an off state.
The pull-down circuit also outputs an n +1 th-stage scanning driving signal G (n +1) according to the direct-current low-voltage signal Vss.
Wherein the pull-up control circuit comprises: a first thin film transistor (T11);
when n is 1, the control terminal and the first terminal of the first thin film transistor (T11) input the initial signal STV, and the second terminal thereof is connected to a pull-up control signal point Q, for outputting the pull-up control signal Q (n) according to the initial signal STV;
when n >1, the control terminal of the first thin film transistor (T11) inputs the n-1 ST stage transfer signal ST (n-1), the first terminal thereof inputs the n-1 ST stage scan driving signal G (n-1), and the second terminal thereof is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q (n) according to the n-1 ST stage transfer signal ST (n-1) and the n-1 ST stage scan driving signal G (n-1).
The pull-up circuit comprises a second thin film transistor (T22), a first end of the second thin film transistor is electrically connected with the pull-up control signal point Q and used for receiving the pull-up control signal Q (n), a second end of the second thin film transistor is used for outputting an nth-level transmission signal ST (n) according to the pull-up control signal Q (n) and the clock signal C L K, a third thin film transistor (T21), a first end of the third thin film transistor is electrically connected with the pull-up control signal point Q and used for receiving the pull-up control signal Q (n), a first end of the third thin film transistor is input with the clock signal C L K, a second end of the third thin film transistor is electrically connected with a horizontal scanning line G and used for outputting the nth-level scanning driving signal G (n) according to the pull-up control signal Q (n) and the clock signal C L K;
the pull-up control enhancement circuit includes: a fourth thin film transistor (Tb) and a first capacitor (C1), wherein a control terminal and a first terminal of the fourth thin film transistor (Tb) are electrically connected to the horizontal scanning line G after being electrically connected, and are configured to input the nth-level scanning driving signal G (n), a second terminal of the fourth thin film transistor (Tb) is connected to one terminal of the first capacitor (C1), and another terminal of the first capacitor (C1) is electrically connected to the pull-up control signal point Q, and is configured to pull up the pull-up control signal Q (n) according to the nth-level scanning driving signal G (n);
the pull-down circuit includes: a fifth thin film transistor (T41) and a sixth thin film transistor (T31); a first end of the fifth thin film transistor (T41) inputs the dc low voltage signal Vss, a second end of the fifth thin film transistor is electrically connected to the pull-up control signal point Q, and is configured to pull down the pull-up control signal Q (n) according to the dc low voltage signal Vss, so that the pull-up control signal Q (n) is in an off state (i.e. a low potential), and a control end of the fifth thin film transistor is electrically connected to a control end of the sixth thin film transistor (T31) and is configured to output an n +1 th-stage scanning driving signal G (n +1) according to the dc low voltage signal Vss; the first end of the sixth thin film transistor (T31) inputs the dc low voltage signal Vss, and the second end thereof is electrically connected to the horizontal scanning line G, for pulling down the nth scanning driving signal G (n) according to the dc low voltage signal Vss, so that the nth scanning driving signal G (n) is in a turned-off state;
the first pull-down maintaining circuit comprises a seventh thin film transistor (T51), an eighth thin film transistor (T52), a ninth thin film transistor (T53), a tenth thin film transistor (T54), an eleventh thin film transistor (T42) and a twelfth thin film transistor (T32), wherein a control terminal and a first terminal of the seventh thin film transistor (T51) are electrically connected to a first terminal of the eighth thin film transistor (T52) and a control terminal of the ninth thin film transistor (T53), respectively, a control terminal of the eighth thin film transistor (T52) is electrically connected to the pull-up control signal point Q, a second terminal of the pull-up control signal Q (n) is connected to the DC low voltage signal Vss, a first terminal of the ninth thin film transistor (T53) is electrically connected to the first low voltage signal L C1, a second terminal of the tenth thin film transistor (T54) is electrically connected to the pull-up control signal point Q865, a first terminal of the ninth thin film transistor (T53) is electrically connected to the pull-down transistor (T L) and the DC low voltage signal Vss, a second terminal of the twelfth thin film transistor (T869) is electrically connected to the pull-up control signal point Vss, a second terminal of the switch off, the upper control signal Vss, and the upper control signal Vss, the upper control signal Vss is electrically connected to the upper control signal of the upper control transistor (T865, the upper control signal of the upper thin film transistor (T L C L C8672) according to the lower voltage control signal point Vss, the lower voltage signal point Vss, the lower voltage signal of the upper control signal of the upper thin film transistor (T865, the upper;
the second pull-down maintaining circuit comprises a thirteenth thin film transistor (T61), a fourteenth thin film transistor (T62), a fifteenth thin film transistor (T63), a sixteenth thin film transistor (T64), a seventeenth thin film transistor (T43) and an eighteenth thin film transistor (T33), wherein a control terminal and a first terminal of the thirteenth thin film transistor (T61) are electrically connected to the second low-frequency signal L C2, a second terminal thereof is electrically connected to a first terminal of the fourteenth thin film transistor (T62) and a control terminal of the fifteenth thin film transistor (T63), a control terminal of the fourteenth thin film transistor (T62) is electrically connected to the pull-up control signal point Q for inputting the pull-up control signal Q (n), a second terminal thereof is inputted with the direct current low-voltage signal Vss, a first terminal of the fifteenth thin film transistor (T63C 2), a second terminal thereof is electrically connected to the second low-frequency signal Vss via a second terminal of the sixteenth thin film transistor (T64), a seventeenth thin film transistor (T869) and a pull-down control signal Vss, a second terminal of the scan transistor (T8672) is electrically connected to the pull-up control signal Vss, a second low-voltage signal Vss is electrically connected to the second low-voltage signal Vss-control signal Vss-line (T L C L C2, a seventeenth thin film transistor (T8653) and a second terminal of the second low-voltage signal Vss) via a second low-voltage signal Vss, a second low-voltage signal Vss 27C 8653, a low-voltage signal Vss, a second terminal of the second low-voltage signal Vss-voltage control signal Vss-voltage signal.
The pull-up control signal point Q is electrically connected to the horizontal scanning line G through a second capacitor (Cb).
Wherein the signal period of the first low-frequency signal L C1 and the second low-frequency signal L C2 is 2 times the frame period, the duty ratio is 1/2, and the phase difference between the first low-frequency signal L C1 and the second low-frequency signal L C2 is 1/2 signal periods.
The operating point potentials of the first pull-down maintaining circuit and the second pull-down maintaining circuit are the pull-up control signal q (n) low potential and the first low-frequency signal L C1 high potential, and the pull-up control signal q (n) low potential and the second low-frequency signal L C2 high potential.
Correspondingly, the embodiment of the invention also provides a liquid crystal display device which comprises the GOA circuit for liquid crystal display.
In summary, in the GOA circuit and the liquid crystal display device having the same according to the embodiments of the present invention, the voltage of the pull-up control signal is increased by adding the pull-up control enhancement circuit to the GOA circuit, so that the output capability of the pull-up circuit can be improved, and the driving capability of the GOA circuit can be further improved, thereby improving the charging rate of the liquid crystal display panel.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another GOA circuit according to an embodiment of the present invention.
Fig. 3 is a schematic waveform diagram of a key node signal in the GOA circuit shown in fig. 1 or fig. 2 according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Furthermore, the following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. Directional phrases used in this disclosure, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the invention, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified. In the present specification, the term "step" is used to mean not only an independent step but also a step that is not clearly distinguished from other steps, provided that the action intended by the step is achieved. In the present specification, the numerical range represented by "to" means a range including numerical values before and after "to" as a minimum value and a maximum value, respectively. In the drawings, elements having similar or identical structures are denoted by the same reference numerals.
Embodiments of the present invention provide a Gate driver On Array (GOA) circuit, which can improve the output capability of a pull-up circuit, and further improve the driving capability of the GOA circuit, thereby improving the charging rate of a liquid crystal display panel. A GOA circuit and a liquid crystal display device having the same according to embodiments of the present invention will be described with reference to fig. 1 to 3.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention. The GOA circuit shown in fig. 1 includes a plurality of cascaded GOA units, wherein the nth level GOA unit charges the nth level horizontal scan line of the display area, and the nth level GOA unit at least includes a pull-up control circuit 10, a pull-up circuit 20, a pull-up control enhancement circuit 30, a pull-down circuit 40, a first pull-down sustain circuit 50, and a second pull-down sustain circuit 60, where n is a positive integer.
When n is equal to 1, the pull-up control circuit 10 receives an initial signal STV and outputs a pull-up control signal q (n) according to the initial signal STV;
when n >1, the pull-up control circuit 10 receives the n-1 ST level transmission signal ST (n-1) and the n-1 ST level scan driving signal G (n-1) outputted from the n-1 ST level GOA unit, and outputs a pull-up control signal q (n) according to the n-1 ST level transmission signal ST (n-1) and the n-1 ST level scan driving signal G (n-1).
It can be seen that when n is equal to 1, the initial signal STV is responsible for starting the first-stage GOA unit, and when n >1, the nth-stage GOA unit is started by the nth-1 stage transmission signal ST (n-1) and the nth-1 stage scanning driving signal G (n-1) output by the nth-1 stage GOA unit, so as to gradually turn on the GOA circuit, thereby implementing the line scanning driving, so that the horizontal scanning lines can be charged step by step.
It should be noted that fig. 1 only shows the signal receiving situation of the pull-up control circuit 10 when n > 1.
The pull-up circuit 20 is electrically connected to the pull-up control circuit 10, receives the pull-up control signal q (n) and the clock signal C L K, and outputs an nth-level transmission signal st (n) and an nth-level scanning driving signal g (n) according to the pull-up control signal q (n) and the clock signal C L K.
The pull-up control enhancing circuit 30 is electrically connected to the pull-up control circuit 10 and the pull-up circuit 20, receives the nth scan driving signal g (n), and pulls up the pull-up control signal q (n) according to the nth scan driving signal g (n).
The pull-down circuit 40 is electrically connected to the pull-up control circuit 10, the pull-up circuit 20, and the pull-up control enhancement circuit 30, receives a dc low voltage signal Vss, pulls down the pull-up control signal q (n) according to the dc low voltage signal Vss, and further pulls down the nth scanning driving signal G (n), so that the pull-up control signal q (n) and the nth scanning driving signal G (n) are in a closed state (i.e. low potential), and outputs an n +1 th scanning driving signal G (n +1) according to the dc low voltage signal Vss.
The first pull-down maintaining circuit 50 is electrically connected to the pull-up control circuit 10, the pull-up circuit 20, the pull-up control enhancement circuit 30 and the pull-down circuit 40, receives a first low-frequency signal L C1 and the dc low-voltage signal Vss, and maintains the pull-up control signal q (n) and the nth-stage scan driving signal g (n) in an off state according to the first low-frequency signal L C1 and the dc low-voltage signal Vss.
The second pull-down maintaining circuit 60 is electrically connected to the pull-up control circuit 10, the pull-up circuit 20, the pull-up control enhancement circuit 30, the pull-down circuit 40 and the first pull-down maintaining circuit 50, receives a second low frequency signal L C2 and the dc low voltage signal Vss, and maintains the pull-up control signal q (n) and the nth stage scanning driving signal g (n) in an off state according to the second low frequency signal L C2 and the dc low voltage signal Vss.
In the embodiment of the present invention, the first pull-down maintaining circuit 50 and the second pull-down maintaining circuit 60 alternately function to maintain the pull-up control signal q (n) and the nth stage scan driving signal g (n) in an off state (i.e., in a low state).
In the GOA circuit provided in the embodiments of the present invention, the voltage of the pull-up control signal is increased by adding the pull-up control enhancement circuit to the GOA circuit, so that the output capability of the pull-up circuit can be improved, and the driving capability of the GOA circuit can be further improved, thereby improving the charging rate of the liquid crystal display panel.
Referring to fig. 1 and fig. 2 together, fig. 2 is a schematic structural diagram of another GOA circuit according to an embodiment of the present invention. The GOA circuit shown in fig. 2 includes the pull-up control circuit 10, the pull-up circuit 20, the pull-up control enhancement circuit 30, the pull-down circuit 40, the first pull-down sustain circuit 50, and the second pull-down sustain circuit 60 shown in fig. 1. Wherein the content of the first and second substances,
the pull-up control circuit 10 specifically includes: a first thin film transistor (T11);
when n is 1, the control terminal and the first terminal of the first thin film transistor (T11) input the initial signal STV, and the second terminal thereof is connected to a pull-up control signal point Q, for outputting the pull-up control signal Q (n) according to the initial signal STV;
when n >1, the control terminal of the first thin film transistor (T11) inputs the n-1 ST stage transfer signal ST (n-1), the first terminal thereof inputs the n-1 ST stage scan driving signal G (n-1), and the second terminal thereof is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q (n) according to the n-1 ST stage transfer signal ST (n-1) and the n-1 ST stage scan driving signal G (n-1).
It should be noted that fig. 2 only shows the signal input condition of the pull-up control circuit 10 when n > 1.
The pull-up circuit 20 includes a second thin film transistor (T22) having a control terminal electrically connected to the pull-up control signal point Q for receiving the pull-up control signal Q (n), a first terminal receiving the clock signal C L K, and a second terminal outputting a nth-level transmission signal st (n) according to the pull-up control signal Q (n) and the clock signal C L K, and a third thin film transistor (T21) having a control terminal electrically connected to the pull-up control signal point Q for receiving the pull-up control signal Q (n), a first terminal receiving the clock signal C L K, a second terminal electrically connected to the horizontal scanning line G, and a control terminal outputting the nth-level scanning driving signal G (n) according to the pull-up control signal Q (n) and the clock signal C L K.
The pull-up control enhancing circuit 30 specifically includes: a fourth thin film transistor (Tb) and a first capacitor (C1), wherein the control terminal and the first terminal of the fourth thin film transistor (Tb) are electrically connected to the horizontal scanning line G for inputting the nth scan driving signal G (n), the second terminal of the fourth thin film transistor (Tb) is connected to one terminal of the first capacitor (C1), and the other terminal of the first capacitor (C1) is electrically connected to the pull-up control signal point Q for pulling up the pull-up control signal Q (n) according to the nth scan driving signal G (n). In a specific embodiment, the control terminal, the first terminal and the second terminal of the fourth thin film transistor (Tb) are the gate, the source and the drain thereof, respectively, when the nth stage scan driving signal g (n) is at a high potential, the fourth thin film transistor (Tb) is turned on, and the voltage of the pull-up control signal point Q is increased by the coupling generated by the voltage change of the two terminals of the first capacitor (C1).
The pull-down circuit 40 specifically includes: a fifth thin film transistor (T41) and a sixth thin film transistor (T31); a first end of the fifth thin film transistor (T41) inputs the dc low voltage signal Vss, a second end of the fifth thin film transistor is electrically connected to the pull-up control signal point Q, and is configured to pull down the pull-up control signal Q (n) according to the dc low voltage signal Vss, so that the pull-up control signal Q (n) is in an off state (i.e. a low potential), and a control end of the fifth thin film transistor is electrically connected to a control end of the sixth thin film transistor (T31) and is configured to output an n +1 th-stage scanning driving signal G (n +1) according to the dc low voltage signal Vss; the first end of the sixth thin film transistor (T31) inputs the dc low voltage signal Vss, and the second end thereof is electrically connected to the horizontal scanning line G, for pulling down the nth scanning driving signal G (n) according to the dc low voltage signal Vss, so that the nth scanning driving signal G (n) is in an off state (i.e. a low potential).
The first pull-down maintaining circuit 50 includes a seventh thin film transistor (T51), an eighth thin film transistor (T52), a ninth thin film transistor (T53), a tenth thin film transistor (T54), an eleventh thin film transistor (T42) and a twelfth thin film transistor (T32), wherein a control terminal and a first terminal of the seventh thin film transistor (T51) are electrically connected to the first terminal of the eighth thin film transistor (T L C1), a second terminal of the seventh thin film transistor (T4623) is electrically connected to the pull-up control signal point Q for inputting the pull-up control signal Q (n), a second terminal of the eighth thin film transistor (T52) is electrically connected to the first terminal of the ninth thin film transistor (T53), a first terminal of the ninth thin film transistor (T52) is electrically connected to the pull-up control signal point Q for inputting the DC low voltage signal Vss, a second terminal of the ninth thin film transistor (T53) is electrically connected to the pull-up control signal point Vss, a second terminal of the ninth thin film transistor (T53C 1) is electrically connected to the pull-up control signal Vss, a second terminal of the twelfth thin film transistor (T L C1) for maintaining the state of the low voltage signal Vss and the Vss according to the low voltage signal Vss, the Vss 5, the low voltage signal Vss is electrically connected to the Vss, the Vss 27C L, the Vss 27C 86n, and the Vss 27C 869, and the Vss 27 Vss, the Vss 27, and the Vss, the Vss 27, the Vss 27, and the Vss are electrically connected to the Vss, and the Vss 27.
The second pull-down maintaining circuit 60 specifically includes a thirteenth thin film transistor (T61), a fourteenth thin film transistor (T62), a fifteenth thin film transistor (T63), a sixteenth thin film transistor (T64), a seventeenth thin film transistor (T43) and an eighteenth thin film transistor (T33), wherein a control terminal and a first terminal of the thirteenth thin film transistor (T61) are electrically connected to the second low-frequency signal L C2, a second terminal of the fourteenth thin film transistor (T62) and a control terminal of the fifteenth thin film transistor (T63), respectively, a control terminal of the fourteenth thin film transistor (T62) is electrically connected to the pull-up control signal point Q for inputting the pull-up control signal Q (N), a second terminal of the fourteenth thin film transistor is electrically connected to the DC low-voltage signal Vss, a first terminal of the fifteenth thin film transistor (T63) is electrically connected to the pull-up control signal point Q L C42, a second terminal of the fifteenth thin film transistor (T63) is electrically connected to the DC low-voltage signal Vss via a second low-voltage signal Vss, a second terminal of the second transistor (T L) and a low-voltage signal Vss, a second terminal of the transistor (T L C86n) is electrically connected to the pull-voltage signal Vss, and a second low-voltage signal Vss, a low-voltage signal Vss is electrically connected to the second terminal of the transistor (T L C2, and a second low-voltage signal Vss, a second low-voltage signal Vss transistor (T869, a low-voltage signal Vss, a low-voltage signal Vss, a low-voltage signal Vss, a low-voltage signal Vss.
In the embodiment of the present invention, the pull-up control signal point Q is electrically connected to the horizontal scan line G through a second capacitor (Cb). In an embodiment of the present invention, the second capacitor (Cb) is a Boast (bootstrap) capacitor.
It should be noted that, in the embodiment of the present invention, the signal period of the first low-frequency signal L C1 and the second low-frequency signal L C2 is 2 times of the frame period, the duty ratio is 1/2, and the phase difference between the first low-frequency signal L C1 and the second low-frequency signal L C2 is 1/2 signal periods.
It should be noted that, in the embodiment of the present invention, the operating point potentials of the first pull-down holding circuit 50 and the second pull-down holding circuit 60 are the low potential of the pull-up control signal q (n) and the high potential of the first low-frequency signal L C1 (or the second low-frequency signal L C2).
In the embodiment of the present invention, when the nth scanning driving signal g (n) is at a high potential, the fourth thin film transistor (Tb) is turned on, and the voltage of the pull-up control signal q (n) is increased by the coupling generated by the voltage variation at the two ends of the first capacitor (C1), so as to improve the output capability of the pull-up circuit, further improve the driving capability of the GOA circuit, and thus improve the charging rate of the liquid crystal display panel.
Referring to fig. 1 to 3 together, fig. 3 is a waveform diagram of a key node signal in the GOA circuit shown in fig. 1 or fig. 2 according to an embodiment of the present invention, wherein the waveform diagram includes a clock signal C L K, a pull-up control signal q (N), an nth scan driving signal g (N), an nth transmission signal st (N), a signal of a first signal point S, and a signal of a second signal point N.
As can be seen from the waveform diagram, when the pull-up control signal q (n) is at a high potential, if the clock signal C L K at the high potential is input to the pull-up circuit 20, the pull-up circuit 20 pulls up the pull-up control signal q (n) to the position of the dotted line, and the pull-up control enhancement circuit 30 further pulls up the pull-up control signal q (n) to the position of the solid line, so as to improve the output capability of the pull-up circuit 20, and further improve the driving capability of the GOA circuit, thereby improving the charging rate of the liquid crystal display panel.
Correspondingly, the embodiment of the invention also provides a liquid crystal display device which comprises the GOA circuit for liquid crystal display shown in the above fig. 1 and fig. 2. For example, the liquid crystal display device may include, but is not limited to, a Mobile phone (e.g., an Android Mobile phone, an iOS Mobile phone, etc.) having a liquid crystal display panel, a tablet computer, an MID (Mobile Internet Devices), a PDA (Personal Digital Assistant), a notebook computer, a television, an electronic paper, a Digital photo frame, and the like.
According to the embodiment of the invention, the pull-up control strengthening circuit is added between the pull-up control circuit and the pull-up circuit of the GOA circuit to improve the voltage of the pull-up control signal, so that the output capability of the pull-up circuit can be improved, the driving capability of the GOA circuit is further improved, and the charging rate of the liquid crystal display panel is further improved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The GOA circuit and the liquid crystal display device having the same provided in the embodiments of the present invention are described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (7)
1. A GOA circuit is characterized by comprising a plurality of cascaded GOA units, wherein the nth GOA unit charges the nth horizontal scanning line of a display area, the nth GOA unit comprises a pull-up control circuit, a pull-up control reinforcing circuit, a pull-down circuit, a first pull-down maintaining circuit and a second pull-down maintaining circuit, and n is a positive integer;
the pull-up control circuit receives a start signal CT and outputs a pull-up control signal q (n) according to the start signal CT, wherein when n is 1, the start signal CT is an initial signal STV, and when n is greater than 1, the start signal CT is an n-1-th-level transmission signal ST (n-1) and an n-1-th-level scanning driving signal G (n-1) output by an n-1-th-level GOA unit; wherein the pull-up control circuit comprises: a first thin film transistor (T11), when n is 1, a control terminal and a first terminal of the first thin film transistor (T11) input the initial signal STV, and a second terminal thereof is connected to a pull-up control signal point Q, for outputting the pull-up control signal Q (n) according to the initial signal STV; when n >1, a control terminal of the first thin film transistor (T11) inputs the n-1 th-stage transfer signal ST (n-1), a first terminal thereof inputs the n-1 th-stage scan driving signal G (n-1), and a second terminal thereof is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q (n) according to the n-1 th-stage transfer signal ST (n-1) and the n-1 th-stage scan driving signal G (n-1);
the pull-up circuit receives the pull-up control signal Q (n) and a clock signal C L K, and outputs an nth stage transmission signal ST (n) and an nth stage scanning drive signal G (n) according to the pull-up control signal Q (n) and the clock signal C L K, wherein the pull-up circuit includes a second thin film transistor (T22) having a control terminal electrically connected to the pull-up control signal point Q for receiving the pull-up control signal Q (n), a first terminal input to the clock signal C L K, a second terminal for outputting the nth stage transmission signal ST (n) according to the pull-up control signal Q (n) and the clock signal C L K, a third thin film transistor (T21) having a control terminal electrically connected to the pull-up control signal point Q for receiving the pull-up control signal Q (n), a first terminal input to the clock signal C L K, a second terminal electrically connected to the horizontal scanning line G for outputting the pull-up control signal Q (n) and the pull-up control signal G (n) according to the pull-up control signal C L K;
the pull-up control enhancement circuit receives the nth stage scan driving signal g (n) and pulls up the pull-up control signal q (n) according to the nth stage scan driving signal g (n), wherein the pull-up control enhancement circuit comprises: a fourth thin film transistor (Tb) and a first capacitor (C1), wherein a control terminal and a first terminal of the fourth thin film transistor (Tb) are electrically connected to the horizontal scanning line G after being electrically connected, and are configured to input the nth-level scanning driving signal G (n), a second terminal of the fourth thin film transistor (Tb) is connected to one terminal of the first capacitor (C1), and another terminal of the first capacitor (C1) is electrically connected to the pull-up control signal point Q, and is configured to pull up the pull-up control signal Q (n) according to the nth-level scanning driving signal G (n);
the pull-down circuit receives a direct-current low-voltage signal Vss, and pulls down the pull-up control signal q (n) according to the direct-current low-voltage signal Vss, so as to pull down the nth-stage scanning driving signal g (n), so that the pull-up control signal q (n) and the nth-stage scanning driving signal g (n) are in a closed state, wherein the pull-down circuit includes: a fifth thin film transistor (T41) and a sixth thin film transistor (T31); a first end of the fifth thin film transistor (T41) inputs the dc low voltage signal Vss, a second end of the fifth thin film transistor is electrically connected to the pull-up control signal point Q, and is configured to pull down the pull-up control signal Q (n) according to the dc low voltage signal Vss, so as to make the pull-up control signal Q (n) in an off state, and a control end of the fifth thin film transistor is electrically connected to a control end of the sixth thin film transistor (T31) and is configured to output an n + 1-th scan driving signal G (n +1) according to the dc low voltage signal Vss; the first end of the sixth thin film transistor (T31) inputs the dc low voltage signal Vss, and the second end thereof is electrically connected to the horizontal scanning line G, for pulling down the nth scanning driving signal G (n) according to the dc low voltage signal Vss, so that the nth scanning driving signal G (n) is in a turned-off state;
the first pull-down maintaining circuit receives a first low-frequency signal L C1 and the DC low-voltage signal Vss, and maintains the pull-up control signal Q (n) and the nth stage scan drive signal G (n) in an off state according to the first low-frequency signal L C1 and the DC low-voltage signal Vss, wherein the first pull-down maintaining circuit comprises a seventh thin film transistor (T51), an eighth thin film transistor (T52), a ninth thin film transistor (T53), a tenth thin film transistor (T54), an eleventh thin film transistor (T42) and a twelfth thin film transistor (T32), a control terminal and a first terminal of the seventh thin film transistor (T51) input the first low-frequency signal L C1, a second terminal of the eighth thin film transistor (T1) is electrically connected with the control terminal of the eighth thin film transistor (T1) and the ninth thin film transistor (T1), a second terminal of the pull-down control signal T1, a second terminal of the second transistor is electrically connected with the first low-frequency signal Vss, a second terminal of the first low-frequency signal T1, a pull-voltage signal T1, a second terminal of the second transistor is connected with the first low-voltage signal Vss (T1) and the second terminal of the first low-voltage signal Vss, a second transistor C1, a second terminal of the low-voltage signal T1, a pull-voltage signal for maintaining the low-frequency signal Q (T1) and a pull-voltage signal Vss, a second terminal of the low-voltage signal T1, a low-voltage signal T1, and a signal for maintaining the low-voltage signal, a signal Vss, a signal, and a signal Vss, and a signal, a signal for maintaining the first low-voltage signal, a signal for maintaining the low-;
the second pull-down maintaining circuit receives a second low-frequency signal L C2 and the DC low-voltage signal Vss, and maintains the pull-up control signal Q (n) and the nth stage scan drive signal G (n) in an off state according to the second low-frequency signal L C2 and the DC low-voltage signal Vss, wherein the second pull-down maintaining circuit includes a thirteenth thin film transistor (T61), a fourteenth thin film transistor (T62), a fifteenth thin film transistor (T63), a sixteenth thin film transistor (T64), a seventeenth thin film transistor (T43) and an eighteenth thin film transistor (T33), a control terminal and a first terminal of the thirteenth thin film transistor (T61) input the second low-frequency signal L C2, a second terminal of the second thin film transistor (T2) is electrically connected with the control terminal of the fourteenth thin film transistor (T2) and the fifteenth thin film transistor (T2), a second terminal of the second pull-down control signal T2 is electrically connected with the second low-frequency signal Vss, and the second terminal of the second low-frequency signal Vss, the second low-voltage signal T2, the second pull-voltage signal T2 is used for maintaining the second low-voltage signal Q (T) at the pull-low-voltage signal Vss, and the second terminal of the second low-voltage signal Vss, and the second low-voltage signal Vss, the second terminal of the second low-frequency signal, and the second low-frequency signal, the second terminal of the second low-frequency signal T2, the second transistor (T2, the second terminal of the second transistor is electrically connected with the second low-frequency signal, and the second low-frequency signal, the second terminal of the second transistor (T2, and the second transistor (T2), and the second low-frequency signal, and the second transistor (T2), and the second low-low.
2. The GOA circuit of claim 1, wherein the first pull-down maintaining circuit and the second pull-down maintaining circuit alternately act to maintain the pull-up control signal Q (n) and the nth stage scan driving signal G (n) in an off state.
3. The GOA circuit of claim 2, wherein the pull-down circuit further outputs the (n +1) th stage scan drive signal G (n +1) in accordance with the dc low voltage signal Vss.
4. The GOA circuit as claimed in claim 3, wherein the pull-up control signal point Q is electrically connected to the horizontal scanning line G through a second capacitor (Cb).
5. A GOA circuit in accordance with any one of claims 1 to 3, wherein the signal period of the first low frequency signal L C1 and the second low frequency signal L C2 is 2 times the frame period, the duty cycle is 1/2, and the phase difference between the first low frequency signal L C1 and the second low frequency signal L C2 is 1/2 signal periods.
6. The GOA circuit of claim 3, wherein the working point potentials of the first pull-down holding circuit and the second pull-down holding circuit are the pull-up control signal Q (n) low and the first low frequency signal L C1 high, and the pull-up control signal Q (n) low and the second low frequency signal L C2 high.
7. A liquid crystal display device comprising the GOA circuit of any one of claims 1 to 6.
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| CN108520724B (en) | 2018-04-18 | 2020-02-28 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108962166A (en) | 2018-07-23 | 2018-12-07 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device with the GOA circuit |
| CN109003588A (en) * | 2018-08-06 | 2018-12-14 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display device |
| WO2020047797A1 (en) * | 2018-09-06 | 2020-03-12 | Boe Technology Group Co., Ltd. | A compensated triple gate driving circuit, a method, and a display apparatus |
| CN109584821B (en) * | 2018-12-19 | 2020-10-09 | 惠科股份有限公司 | Shift register and display device |
| CN109637423A (en) * | 2019-01-21 | 2019-04-16 | 深圳市华星光电半导体显示技术有限公司 | GOA device and gate driving circuit |
| CN113496681A (en) * | 2020-03-18 | 2021-10-12 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
| CN111179813B (en) | 2020-03-18 | 2022-05-17 | 合肥京东方卓印科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN114596817B (en) * | 2022-03-23 | 2023-11-21 | 合肥京东方卓印科技有限公司 | Shift register unit, gate driving circuit, display panel and display device |
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| TWI433460B (en) * | 2010-09-21 | 2014-04-01 | Au Optronics Corp | Nth shift register capable of increasing driving capability and method for increasing driving capability of a shift register |
| KR102023641B1 (en) * | 2013-01-28 | 2019-09-20 | 엘지디스플레이 주식회사 | Shift register and method for driving the same |
| CN104036738B (en) * | 2014-03-27 | 2016-06-01 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driver circuit and display unit |
| TWI521490B (en) * | 2014-04-02 | 2016-02-11 | 友達光電股份有限公司 | Display panel and gate driver |
| KR101575501B1 (en) * | 2014-07-03 | 2015-12-07 | 경희대학교 산학협력단 | Shift register for providing gate driving signal |
| CN105390117B (en) * | 2015-12-28 | 2017-12-22 | 武汉华星光电技术有限公司 | Gate driving circuit and the array base palte using the drive circuit |
| CN106328084A (en) * | 2016-10-18 | 2017-01-11 | 深圳市华星光电技术有限公司 | GOA drive circuit and liquid crystal display device |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |