CN108665865B - Gate drive unit and display device - Google Patents
Gate drive unit and display device Download PDFInfo
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- CN108665865B CN108665865B CN201810455345.4A CN201810455345A CN108665865B CN 108665865 B CN108665865 B CN 108665865B CN 201810455345 A CN201810455345 A CN 201810455345A CN 108665865 B CN108665865 B CN 108665865B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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Abstract
The embodiment of the invention particularly discloses a gate driving unit and a display device, wherein the gate driving unit comprises a pre-charge module, a first node and a second node, wherein the pre-charge module is used for providing a pre-charge signal to the first node according to a preceding-stage transmission signal; the pull-down module is used for providing a low-voltage signal to a first node according to a post-stage transmission signal; the first output module is connected with the precharge module and the pull-down module and is used for generating a current-stage transmission signal according to the potential of the first node and the first clock signal; and the second output module is connected with the first node and used for generating the grid driving signal of the current stage according to the potential of the first node and the power supply voltage signal, so that the second output module is prevented from generating larger alternating current power consumption, and the power consumption of the grid driving unit is directly reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving unit and a display device.
Background
The liquid crystal display device is a display device in which the light transmittance of a light source is changed by utilizing a phenomenon that the alignment direction of liquid crystal molecules is changed by an electric field. Liquid crystal display devices have been widely used in mobile terminals such as mobile phones and large-sized display panels such as flat panel televisions due to advantages of good display quality, small volume, and low power consumption. Most of the liquid crystal displays in the market are projection type liquid crystal displays (lcds), which include a liquid crystal panel and a backlight module (backlight module). The liquid crystal panel has the working principle that liquid crystal molecules are placed between two parallel glass substrates, and a driving voltage is applied to the two glass substrates to control the rotation direction of the liquid crystal molecules, so that the light emission of the backlight module is modulated to generate a picture.
In recent years, the development of liquid crystal displays has shown a trend of high integration and low cost, and integrated display driving is becoming a research hotspot of flat panel display technology. The integrated display driving circuit is realized by using a switching transistor (TFT) as a peripheral circuit such as a gate driving circuit and a source driving circuit, and is formed on a TFT substrate together with a pixel switching transistor. Compared with the traditional circuit (IC) driving mode, the method adopting integrated gate driving can not only reduce the number of peripheral driving chips and the press sealing procedure thereof and reduce the cost, but also make the periphery of the display thinner, make the display module more compact and enhance the mechanical and electrical reliability.
Fig. 1 shows a circuit configuration diagram of a gate driving unit of the related art.
As shown in FIG. 1, the gate driving unit 100 of the prior art includes switching transistors T1-T7 and capacitors C1-C2. The control terminal of the switching transistor T1 receives the previous stage gate driving signal Gn-2, the first path terminal receives the first clock signal clk1, and the second path terminal is connected to the first node Q. The control terminal of the switching transistor T3 receives the post-stage gate driving signal Gn +2, the first path terminal is connected to the first node Q, and the second path terminal receives the third clock signal clk 3. The switch transistor T2 forms an output module of the gate driving unit 100, and has a control terminal connected to the first node Q, a first path terminal receiving the second clock signal clk2, and a second path terminal outputting the present gate driving signal Gn. The switching tubes T4-T7 constitute a stabilizing module of the gate driving unit 100, a control terminal of the switching tube T4 receives the fourth clock signal clk4, a first path terminal is connected to a second path terminal of the switching tube T5, the second path terminal receives the low voltage signal VGL, and an intermediate node between the first path terminal of the switching tube T4 and the second path terminal of the switching tube T5 is connected to an output terminal of the local stage gate driving signal Gn. The first path terminal of the switch transistor T5 is connected to the intermediate node between the first node Q and the control terminal of the switch transistor T2, and the control terminal is connected to the control terminal of the switch transistor T7. The first path terminal of the switch transistor T6 is connected to the intermediate node between the control terminal of the switch transistor T5 and the control terminal of the switch transistor T7, the second path terminal receives the low voltage signal VGL, and the control terminal is connected to the first path terminal of the switch transistor T7. The first path terminal of the switch transistor T7 is connected to the output terminal of the present stage gate driving signal Gn, and the second path terminal receives the low voltage signal VGL. In addition, the first terminal of the capacitor C1 is connected to the control terminal of the switch transistor T2, and the second terminal is connected to the second path terminal of the switch transistor T2. The capacitor C2 has a first terminal connected to the receiving terminal of the second clock signal clk2, and a second terminal connected to the middle node between the control terminal of the switch transistor T5 and the control terminal of the switch transistor T7.
The gate driving unit 100 of the prior art precharges the first node Q1 through the first switch transistor T1, and then turns on the switch transistor T2 through the bootstrap action of the first capacitor C1, and the switch transistor T2 outputs the second clock signal clk2 as the present stage gate driving signal Gn. Since the gate driving signal Gn of the present stage is used for driving the corresponding load, the switch transistor T2 needs to provide a strong driving capability, and therefore the size of the switch transistor T2 is significantly larger than that of the other switch transistors in the gate driving unit, resulting in a larger coupling capacitance of the switch transistor T2. Therefore, it can be seen that the power consumption of the prior art gate driving unit 100 mainly results from the charging and discharging of the switch transistor T2 by the second clock signal clk2, and the large size of the switch transistor T2 causes the power consumption of the prior art gate driving unit 100 to be large.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In view of the above, the present invention provides a gate driving unit and a display device, which are advantageous for reducing power consumption.
According to a first aspect of the present invention, there is provided a gate driving unit comprising: the pre-charge module is used for providing a pre-charge signal to a first node according to a preceding-stage transmission signal; the pull-down module is used for providing a low-voltage signal to the first node according to a post-stage transmission signal; the first output module is connected with the pre-charge module and the pull-down module and is used for generating a current-stage transmission signal according to the potential of the first node and a first clock signal; and the control end of the second output module is connected with the first node, and the input end of the second output module receives a power supply voltage signal and is used for generating a current-level grid driving signal according to the potential of the first node and the power supply voltage signal.
Preferably, the precharge signal is a second clock signal or a power supply voltage signal.
Preferably, the gate driving unit further includes a stabilizing module, which receives a third clock signal and a low voltage signal, and is configured to stabilize the present-stage transmission signal and the present-stage transmission signal according to the third clock signal and the low voltage signal.
Preferably, the precharge module includes a first switch tube, a control end receives the pre-stage transmission signal, a first path end receives the precharge signal, and a second path end is connected to the first node.
Preferably, the first output module includes a second switch tube, a control end is connected to the first node, a first path end receives the second clock signal, and a second path end is used to provide the present-stage transmission signal; and the first end of the first capacitor is connected with the control end of the second switch tube, and the second end of the first capacitor is connected with the second path end of the second switch tube.
Preferably, the second output module includes a third switching tube, a control terminal is connected to the first node, a first path terminal receives the power voltage signal, and a second path terminal is configured to provide the current-stage gate driving signal.
Preferably, the stabilizing module includes fourth to seventh switching tubes and a second capacitor, wherein the fourth switching tube and the fifth switching tube are connected in series between the first node and the low voltage signal receiving end, the fourth switching tube and the middle node of the fifth switching tube and the control end of the sixth switching tube are connected to the second pass end of the second switching tube, the control end of the fourth switching tube receives the third clock signal, the control end of the fifth switching tube is connected to the control end of the seventh switching tube, the first pass end of the seventh switching tube is connected to the second pass end of the second switching tube, the second pass end receives the low voltage signal, the first pass end of the sixth switching tube is connected to the control end of the fifth switching tube, the second pass end receives the low voltage signal, and the second capacitor is connected in series between the first pass end of the second switching tube and the control end of the fifth switching tube.
Preferably, the pull-down module includes an eighth switching tube, a control end receives the post-stage transmission signal, a first path end is connected to a control end of the third switching tube, and a second path end receives the low-voltage signal; a ninth switching tube, a control end of which receives the post-stage transmission signal, a first path end of which is connected with a second path end of the third switching tube, and the second path end of which receives the low-voltage signal; and a tenth switching tube, wherein a control end and a first path end of the sixth switching tube are connected to the second node, the first path end is connected with a middle node of the third switching tube and the ninth switching tube, and the second path end receives the low-voltage signal.
Preferably, the pre-charge module further comprises: an eleventh switching tube connected in series between the second pass end of the first switching tube and the first node; a twelfth switching tube, a control end and a first path end receive the first clock signal, and a second path end is connected with a control end of the eleventh switching tube; a thirteenth switching tube, wherein a control end receives the preceding-stage transmission signal, a first path end is connected with a middle node of a control end of the eleventh switching tube and a second path end of the twelfth switching tube, and the second path end receives the low-voltage signal; and a first end of the third capacitor is connected with the second path end of the eleventh switching tube, and a second end of the third capacitor is connected with the second path end of the fifth switching tube.
According to a second aspect of the present invention, a display device is provided, which includes the gate driving unit.
The gate driving unit and the display device provided by the embodiment of the invention have the beneficial effects that: the second output module in the gate driving unit directly generates the gate driving signal of the current stage according to the power supply voltage VDD, so that the second output module is prevented from generating large alternating current power consumption, and the power consumption of the gate driving unit is directly reduced; in addition, the second output module control signal is controlled by the first node, so that the size of the third transistor connected with the power voltage VDD can be greatly reduced, the required layout area is reduced, and the design of a narrow frame is facilitated. Meanwhile, the grid driving unit provided by the invention simultaneously generates a transmission signal for transmitting the time sequence information and a grid driving signal for driving the load, so that the time sequence between the grid driving units at all levels and the driving effect on the load are more stable. In a preferred embodiment of the present invention, the precharge module of the gate driving unit also directly controls the potential of the first node according to the power supply voltage VDD, so as to effectively reduce ac power consumption of the precharge module, i.e., further reduce power consumption of the gate driving unit. In the gate driving unit provided by the preferred embodiment, the effective time of the gate driving signal is longer by reducing the pre-charging time, so that the display quality of the display device is improved. Also, power consumption of a display device employing the gate driving unit can be effectively reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of a prior art gate drive unit.
Fig. 2 is a schematic structural diagram of a gate driving unit according to the present invention.
Fig. 3 shows a circuit diagram of a gate driving unit according to a first embodiment of the present invention.
Fig. 4 is a timing diagram illustrating the operation of the gate driving unit according to the first embodiment of the present invention.
Fig. 5 shows a simulation of a gate driving unit of the prior art and a gate driving unit of the first embodiment of the present invention at 27 ℃.
Fig. 6 shows a simulation of a gate driving unit of the prior art and a gate driving unit of the first embodiment of the present invention at 60 ℃.
Fig. 7 shows a circuit schematic diagram of a gate driving unit according to a second embodiment of the present invention.
Fig. 8 is a timing diagram illustrating the operation of the gate driving unit according to the second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 2 is a schematic structural diagram of a gate driving unit according to the present invention.
As shown in fig. 2, the gate driving unit 200 includes a pre-charging module 210, a first output module 220, a second output module 230, a stabilizing module 240, and a pull-down module 250. The pre-charge module 210, the first output module 220, the second output module 230, and the stabilization module 240 are connected to a first node Q1. The precharge module 210 receives the preceding stage transmission signal Zn-2 and a second clock signal clk2, wherein the second clock signal clk2 is used as a precharge signal. When the previous pass signal Zn-2 is high, the precharge module 210 provides the second clock signal clk2 to the first node, precharges the first node Q1, and precharges the first node Q1 to a high level. The first output module 220 receives the first clock signal clk1, and is used for outputting the first clock signal clk1 as the present stage transfer signal Zn under the action of the first node Q1. The second output module 230 receives the power voltage signal VDD and outputs the present-stage gate driving signal Gn under the action of the first node Q1.
The pull-down module 250 receives the post-stage transmission signal Zn +2 and the low voltage signal VGL, and is configured to pull down the potentials of the first node Q1 and the present-stage gate driving signal Gn when the post-stage transmission signal Zn +2 is at a high level. The stabilizing module 240 receives the third clock signal clk3 and the low voltage signal VGL, and the stabilizing module 240 is configured to maintain the potential level of the first node Q1, so that the present stage transmission signal Zn and the present stage gate driving signal Gn are kept at a low level.
The gate driving unit 200 provided by the invention outputs the power voltage signal VDD as the gate driving signal Gn of the current stage, and has small coupling capacitance, thereby being beneficial to reducing power consumption. In some other embodiments of the present invention, the precharge signal received by the precharge module 210 is a dc voltage signal, which is beneficial to further reducing power consumption.
Fig. 3 shows a circuit diagram of a gate driving unit according to a first embodiment of the present invention.
As shown in fig. 3, the precharge module 210 includes a first switch T1, a control terminal of the first switch T1 receives the pre-stage transmission signal Zn-2, a first path terminal receives a precharge signal, such as the second clock signal clk2, and a second path terminal is connected to the first node Q1. The structure of the pre-charge module 210 is not limited to this, and may be a plurality of switching tubes or other structures.
The first output module 220 includes a second switch transistor T2 and a first capacitor C1, a control terminal of the second switch transistor T2 is connected to the first node Q1, a first path terminal receives the first clock signal clk1, and a second path terminal is used for providing the present stage transmission signal Zn. The first capacitor C1 is connected in series between the control terminal of the second switch transistor T2 and the second pass terminal.
The second output module 230 includes a third switch transistor T3, a control terminal of the third switch transistor T3 is connected to the first node Q1, a first path terminal receives the power voltage signal VDD, and a second path terminal is used for providing the present stage gate driving signal Gn. The structure of the second output module 230 is not limited to this, and may be a plurality of switching tubes or other structures.
The stabilizing module 240 includes fourth to seventh switching tubes T4-T7. A control terminal of the fourth switching tube T4 receives the third clock signal clk3, a second path terminal receives the low voltage signal VGL, a first path terminal is connected to the second path terminal of the fifth switching tube T5, and an intermediate node between the first path terminal of the fourth switching tube T4 and the second path terminal of the fifth switching tube T5 is connected to the second path terminal of the second switching tube T2. A first path terminal of the fifth switch transistor T5 is connected to the first node Q1, and a control terminal thereof is connected to a control terminal of the seventh switch transistor T7. The control end of the sixth switching tube T6 is connected to the middle node of the second path end of the fifth switching tube T5 and the second path end of the second switching tube T2, the first path end is connected to the control end of the fifth switching tube T5, and the second path end receives the low voltage signal VGL. The first path terminal of the seventh switch transistor T7 is connected to the node of the first capacitor C1 and the second path terminal of the second switch transistor T2, and the second path terminal receives the low voltage signal VGL. The stabilizing module 240 further includes a second capacitor C2, wherein a first terminal of the second capacitor C2 is connected to the first path terminal of the second switch transistor T2, and a second terminal thereof is connected to the control terminal of the fifth switch transistor T5.
The pull-down module 250 includes eighth to tenth switching tubes T8-T10, control terminals of the eighth switching tube T8 and the ninth switching tube T9 receive the post-stage transmission signal Zn +2, a first path terminal of the eighth switching tube T8 is connected to a control terminal of the third switching tube T3, and a second path terminal receives the low voltage signal VGL. A first path terminal of the ninth switching transistor T9 is connected to a second path terminal of the third switching transistor T3, and the second path terminal receives the low voltage signal VGL. A control terminal of the tenth switching transistor T10 and a first path terminal of the sixth switching transistor T6 are connected to the second node Q2, the first path terminal is connected to a second path terminal of the third switching transistor T3, and the second path terminal receives the low voltage signal VGL.
It should be noted that, in the present embodiment, the first to tenth switching tubes T1-T10 are all N-type thin film transistors, and the first path terminal and the second path terminal of each transistor may be interchanged (i.e., the drain and the source may be interchanged), but the implementation of the present invention is not limited thereto.
Fig. 4 is a timing diagram illustrating the operation of the gate driving unit according to the first embodiment of the present invention.
The operation principle of the gate driving unit according to the first embodiment of the present invention will be described in detail with reference to fig. 3 and 4.
As shown in fig. 4, the duty ratios of the first to third clock signals clk1 to clk3 are the same, and are each one-half. And the working process of each stage of gate driving unit comprises a pre-charging stage, a pull-up stage, a pull-down stage and a stabilization stage, which correspond to t1-t4 in fig. 4.
In the pre-charge stage, the pre-stage transmission signal Zn-2 is at a high level, the first switch T1 is turned on, and the first switch T1 provides the pre-charge signal to the first node Q1, so that the potential of the first node Q1 is raised to a high level. The precharge signal is, for example, the second clock signal clk2 or a dc voltage signal, such as the power supply voltage VDD. After the voltage level at the first node Q1 is raised to a high level, the second switch T2 is turned on, and the second switch T2 outputs the first clock signal clk1 as the present stage transmission signal Zn.
In the pull-up stage, the bootstrap effect of the first capacitor C1 is used to further raise the potential of the first node Q1, and the third switch transistor T3 is turned on. Meanwhile, the first clock signal clk1 turns on the sixth switching transistor T6, the sixth switching transistor T6 pulls the potential of the second node Q2 low, the tenth switching transistor T10 turns off, and at this time, the third switching transistor T3 outputs the power voltage VDD as the present-stage gate driving signal Gn.
In the pull-down stage, the post-stage transmission signal Zn +2 is at a high level, the eighth switch transistor T8 and the ninth switch transistor T9 are turned on, the eighth switch transistor T8 pulls the potential of the first node Q1 low, the ninth switch transistor T9 pulls the potential of the gate driving signal Gn of the present stage low, and the second switch transistor T2, the third switch transistor T3 and the sixth switch transistor T6 are turned off.
In the stable phase, the third clock signal clk3 is low, and the fourth switch transistor T4 is turned off. At this time, since the second capacitor C2 charges the second node Q2, the second node Q2 is maintained at a high level, and the fifth switch tube T5, the seventh switch tube T7 and the tenth switch tube T10 are turned on, so that the first node Q1, the current stage transmission signal Zn and the current stage gate driving signal Gn are maintained at a low level, respectively.
Fig. 5 and 6 show simulated schematic diagrams of a gate driving unit of the prior art and a gate driving unit of the first embodiment of the present invention at 27 c and 60 c, respectively.
Wherein curve a represents the output noise of the gate driving unit of the present invention, and curve b represents the output noise of the gate driving unit of the related art. As shown in fig. 5 and 6, the gate driving unit of the present invention uses a direct current as an output source, so that output noise is lower.
Fig. 7 shows a circuit schematic diagram of a gate driving unit according to a second embodiment of the present invention. The gate driving unit of the second embodiment is different from the gate driving unit of the first embodiment of fig. 3 in that: the pre-charge module 210 further includes eleventh to thirteenth switching tubes T11-T13 and a third capacitor C3. The eleventh switching tube T11 is connected in series between the second path terminal of the first switching tube T1 and the first node Q1. The control terminal and the first path terminal of the twelfth switch T12 receive the first clock signal clk1, and the second path terminal is connected to the control terminal of the eleventh switch T11. A control end of the thirteenth switching tube T13 receives the preceding stage transmission signal Zn-2, a first path end is connected to an intermediate node between the control end of the eleventh switching tube T11 and the first path end of the twelfth switching tube T12, and a second path end receives the low voltage signal VGL. A first end of the third capacitor C3 is connected to the second path terminal of the first switch transistor T1, and a second end is connected to the second path terminal of the fifth switch transistor T5.
In addition, the first output module 220, the second output module 230, the stabilizing module 240 and the pull-down module 250 of the present embodiment have the same structure and connection relationship as those of the first embodiment shown in fig. 3, and are not repeated herein.
The first to thirteenth switching tubes T1-T13 mentioned in this embodiment are all N-type thin film transistors, and the first path terminal and the second path terminal of each transistor can be interchanged (i.e. the drain and the source can be interchanged), but the implementation of the present invention is not limited thereto.
Fig. 8 is a timing diagram illustrating the operation of the gate driving unit according to the second embodiment of the present invention.
The operation principle of the gate driving unit according to the second embodiment of the present invention will be described in detail with reference to fig. 7 and 8.
As shown in fig. 8, the duty ratios of the first to third clock signals clk1 to clk3 are the same, and are each one-half. And the working process of each stage of gate driving unit comprises a pre-charging stage, a pull-up stage, a pull-down stage and a stabilization stage, which correspond to t5-t8 in fig. 8.
In the precharge stage, when the previous stage transmission signal Zn-2 is at a high level, the first switch transistor T1 and the thirteenth switch transistor T13 are turned on, the thirteenth switch transistor T13 provides the low voltage signal VGL to the control terminal of the eleventh switch transistor T11, the voltage at the control terminal of the eleventh switch transistor T11 is pulled down, and the eleventh switch transistor T11 is turned off, so that the potential of the first node Q1 does not change.
In the pull-up stage, at this time, the preceding stage transfer signal Zn-2 is at a low level, the first clock signal clk1 is at a high level, the first switch transistor T1 and the thirteenth switch transistor T13 are turned off, the twelfth switch transistor T12 is turned on, the twelfth switch transistor T12 provides the first clock signal clk1 to the control end of the eleventh switch transistor T11, the voltage at the control end of the eleventh switch transistor T11 is pulled up, the eleventh switch transistor T11 is turned on, the bootstrap action of the third capacitor C3 is utilized to raise the potential of the first node Q1, and the second switch transistor T2 and the third switch transistor T3 are turned on. The second switch tube T2 outputs the first clock signal clk1 as the present stage transfer signal Zn; the third switching tube T3 outputs the power supply voltage VDD as the present stage gate driving signal Gn.
In addition, the working principle of the gate driving unit in the pull-down stage and the stabilization stage of the second embodiment of the present invention is the same as that of the first embodiment, and is not repeated herein.
The gate driving unit according to the second embodiment of the present invention improves the effective time of the gate driving signal by reducing the pre-charging time, and finally improves the display quality of the display device.
According to another aspect of the present invention, there is provided a display device including the gate driving unit of the above embodiment.
In summary, the embodiments of the invention provide a gate driving unit and a display device. The second output module in the gate driving unit directly generates the gate driving signal of the current stage according to the power supply voltage VDD, so that the second output module is prevented from generating large alternating current power consumption, and the power consumption of the gate driving unit is directly reduced; in addition, the second output module control signal is controlled by the first node, so that the size of the third transistor connected with the power voltage VDD can be greatly reduced, the required layout area is reduced, and the design of a narrow frame is facilitated. Meanwhile, the grid driving unit provided by the invention simultaneously generates a transmission signal for transmitting the time sequence information and a grid driving signal for driving the load, so that the time sequence between the grid driving units at all levels and the driving effect on the load are more stable. In a preferred embodiment of the present invention, the precharge module of the gate driving unit also directly controls the potential of the first node according to the power supply voltage VDD, so as to effectively reduce ac power consumption of the precharge module, i.e., further reduce power consumption of the gate driving unit. In the gate driving unit provided by the preferred embodiment, the effective time of the gate driving signal is longer by reducing the pre-charging time, so that the display quality of the display device is improved. Also, power consumption of a display device employing the gate driving unit can be effectively reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (9)
1. A gate drive unit, comprising:
the pre-charge module is used for providing a pre-charge signal to a first node according to a preceding-stage transmission signal;
the pull-down module is used for providing a low-voltage signal to the first node according to a post-stage transmission signal;
the first output module is connected with the pre-charge module and the pull-down module and is used for generating a current-stage transmission signal according to the potential of the first node and a first clock signal; and
a second output module, a control end of which is connected with the first node, an input end of which receives a power supply voltage signal and is used for generating a current-stage grid driving signal according to the electric potential of the first node and the power supply voltage signal,
wherein the pre-charge module comprises:
the control end of the first switch tube receives the pre-stage transmission signal, and the first access end of the first switch tube receives the pre-charging signal;
an eleventh switching tube connected in series between the second pass end of the first switching tube and the first node;
a twelfth switching tube, a control end and a first path end receive the first clock signal, and a second path end is connected with a control end of the eleventh switching tube;
and a control end of the thirteenth switching tube receives the preceding-stage transmission signal, a first path end of the thirteenth switching tube is connected with a control end of the eleventh switching tube, and a second path end of the thirteenth switching tube receives the low-voltage signal.
2. The gate driving unit of claim 1, wherein the pre-charge signal is a second clock signal or a power supply voltage signal.
3. A gate drive unit as claimed in claim 1, further comprising:
and the stabilizing module is used for receiving a third clock signal and a low-voltage signal and stabilizing the current-stage transmission signal and the current-stage gate driving signal according to the third clock signal and the low-voltage signal.
4. A gate drive unit as claimed in claim 3, wherein the first output module comprises:
a control end of the second switch tube is connected with the first node, a first path end receives the first clock signal, and a second path end is used for providing the current-stage transmission signal;
and the first end of the first capacitor is connected with the control end of the second switch tube, and the second end of the first capacitor is connected with the second path end of the second switch tube.
5. A gate drive unit as claimed in claim 4, wherein the second output module comprises:
and a control end of the third switching tube is connected with the first node, a first path end receives the power supply voltage signal, and a second path end is used for providing the current-stage grid driving signal.
6. A gate drive unit as claimed in claim 5, wherein the stabilizing module comprises: a fourth to a seventh switch tube and a second capacitor,
wherein the fourth switching tube and the fifth switching tube are connected in series between the first node and the low-voltage signal receiving end,
the middle node of the fourth switching tube and the fifth switching tube and the control end of the sixth switching tube are connected with the second path end of the second switching tube,
the control end of the fourth switching tube receives the third clock signal, the control end of the fifth switching tube is connected with the control end of the seventh switching tube,
the first path end of the seventh switch tube is connected with the second path end of the second switch tube, the second path end receives the low-voltage signal,
the first path end of the sixth switching tube is connected with the control end of the fifth switching tube, the second path end receives the low-voltage signal,
the second capacitor is connected in series between the first pass end of the second switch tube and the control end of the fifth switch tube.
7. A gate drive unit as claimed in claim 6, wherein the pull-down module comprises:
the control end of the eighth switching tube receives the post-stage transmission signal, the first path end is connected with the control end of the third switching tube, and the second path end receives the low-voltage signal;
a ninth switching tube, a control end of which receives the post-stage transmission signal, a first path end of which is connected with a second path end of the third switching tube, and the second path end of which receives the low-voltage signal; and
and a control end of the tenth switching tube and a first path end of the sixth switching tube are connected to the second node, the first path end is connected with a middle node of the third switching tube and the ninth switching tube, and the second path end receives the low-voltage signal.
8. A gate drive unit as claimed in claim 6, wherein the pre-charge module further comprises:
and a first end of the third capacitor is connected with the second path end of the eleventh switching tube, and a second end of the third capacitor is connected with the second path end of the fifth switching tube.
9. A display device comprising the gate driving unit according to any one of claims 1 to 8.
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| CN109192173A (en) * | 2018-10-31 | 2019-01-11 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method, display device |
| CN109272960B (en) * | 2018-11-13 | 2021-08-06 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
| CN109658888B (en) * | 2019-01-02 | 2022-01-14 | 合肥京东方光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN110010055A (en) * | 2019-05-07 | 2019-07-12 | 深圳市华星光电半导体显示技术有限公司 | Driving circuit |
| CN110223651B (en) * | 2019-05-31 | 2020-08-11 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN112382249B (en) * | 2020-11-13 | 2022-04-26 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN115050338B (en) * | 2022-06-15 | 2023-07-25 | Tcl华星光电技术有限公司 | Gate driving circuit, display panel and display device |
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| KR20140020484A (en) * | 2012-08-08 | 2014-02-19 | 삼성디스플레이 주식회사 | Scan driving device and driving method thereof |
| CN104091577B (en) * | 2014-07-15 | 2016-03-09 | 深圳市华星光电技术有限公司 | Be applied to the gate driver circuit of 2D-3D signal setting |
| CN104966500B (en) * | 2015-07-20 | 2017-05-31 | 深圳市华星光电技术有限公司 | Reduce the GOA circuits of power consumption |
| CN105741802B (en) * | 2016-03-28 | 2018-01-30 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN105957556A (en) * | 2016-05-11 | 2016-09-21 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display apparatus, and driving method of shift register unit |
| CN106601208A (en) * | 2017-03-01 | 2017-04-26 | 北京京东方光电科技有限公司 | Shift register unit, driving method thereof, grid drive circuit and display device |
| CN107248398B (en) * | 2017-07-14 | 2020-08-04 | 昆山龙腾光电股份有限公司 | Display device |
| CN107479750B (en) * | 2017-08-08 | 2020-09-01 | 昆山龙腾光电股份有限公司 | Touch display device and control method thereof |
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