CN112382249B

CN112382249B - Gate drive unit, gate drive circuit and display device

Info

Publication number: CN112382249B
Application number: CN202011266327.5A
Authority: CN
Inventors: 柯中乔; 祝伟鹏; 段周雄; 刘建玮
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2020-11-13
Filing date: 2020-11-13
Publication date: 2022-04-26
Anticipated expiration: 2040-11-13
Also published as: CN112382249A

Abstract

The application discloses grid drive unit, gate drive circuit and display device, grid drive unit are used for driving many scanning lines that correspond on the display panel, and grid drive unit includes: the input module is connected with the first node and charges the first node according to the pre-charging signal; the output module is connected with the first node and provides a transmission signal and a plurality of grid driving signals with different time sequences according to the voltage of the first node and a plurality of clock signals; the pull-down stabilizing module is connected with the output end of the output module and is used for maintaining the plurality of grid driving signals at a first low level under the control of the pull-down signals, wherein the output module further comprises a first switch tube which is used for carrying out feedback charging on the input module according to the transmission signals during the opening period of the output module so as to maintain the first node at a high potential, ensure that the first capacitor is bootstrapped without leakage and effectively improve the working stability of the grid driving circuit and the display device.

Description

Gate drive unit, gate drive circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a gate driving unit, a gate driving circuit and a display device.

Background

A Display device is a Display tool that displays Display data on a Display Panel through a transmission device and reflects the Display data to human eyes, and examples of the Display device include a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), an Organic Light-Emitting Diode (OLED) Display, and an electrophoretic Display (EPD).

With the development of display technologies, display panels tend to have high integration and low cost. In the related art, a Gate-driver in Array (GIA) circuit is directly integrated on an Array substrate of a display panel, and the GIA circuit generally includes a plurality of cascaded Gate driving units, each corresponding to one or more rows of pixels corresponding to a scan line, so as to implement a scan driver for the display panel. The integration technology can save the area occupied by the gate driving circuit so as to realize the narrow frame of the display panel. However, the switching tubes in the multi-output gate driving unit in the prior art have a leakage phenomenon, which reduces the stability of the switching tubes, and the multi-output gate driving unit in the prior art often needs cross-stage connection, thereby increasing the layout area of the gate driving circuit and being not beneficial to the implementation of a narrow frame.

Fig. 1 shows a schematic diagram of a gate driving circuit according to the prior art. As shown in fig. 1, in the related art, a display device 100 includes a display panel 110 and a gate driving circuit 120.

The display panel 110 includes pixel units (not shown) arranged in rows and columns and m scan lines transmitting gate driving signals, where m is a non-zero integer.

The gate driving circuit 120 includes a plurality of cascade gate driving units 121, each gate driving unit 121 corresponding to one row of pixels corresponding to a scan line, and generates an output signal in response to a start pulse signal and shifts the output signal according to a clock. As the resolution is higher, the width of the gate driving circuit 120 is increased, and the frame of the display panel 110 is increased accordingly.

Fig. 2 is a schematic circuit diagram illustrating the gate driving unit in fig. 1, where n is an integer greater than 4, and the nth gate driving unit 121 includes a capacitor C1 and first to sixteenth switching tubes T1 to T16.

The control terminal of the first switch transistor T1 receives the transfer signal Zn-4 of the n-4 th stage gate driving unit, the first terminal receives the gate driving signal Gn-4 of the n-4 th stage gate driving unit, the second terminal is connected to the first terminal of the third switch transistor T3 at the first node Q, the control terminal of the third switch transistor receives the gate driving signal Gn +4 of the n +4 th stage driving unit, and the second terminal receives the third clock signal CLK 3. The control terminals of the second switch transistor T2 and the fourteenth switch transistor T14 are connected to the first node Q, the first terminal receives the first clock signal CLK1, the second terminal of the second switch transistor T2 outputs the gate driving signal Gn, and the second terminal of the fourteenth switch transistor T14 outputs the transfer signal Zn. The first capacitor C1 has a first terminal connected to the first node Q, and a second terminal connected to the second terminal of the second switch transistor T2.

The eighth switch transistor T8 has a control terminal and a first terminal receiving the first timing signal V1, and a second terminal connected to the second node QB 1. The control end of the fourth switch transistor T4 is connected to the second node QB1, the first end is connected to the first node Q, the second end is connected to the second low level VSQ, and the fourth switch transistor T4 is turned on according to the potential of the second node QB1, so as to pull down the first node Q to the second low level VSQ. The control terminal of the sixth switch transistor T6 is connected to the second node QB1, the first terminal is connected to the output terminal of the gate driving signal Gn, the second terminal is connected to the first low level VGL, and the sixth switch transistor T6 is turned on according to the potential of the second node QB1 to pull down the gate driving signal Gn to the first low level VGL. The control terminal of the fifteenth switch tube T15 is connected to the second node QB1, the first terminal is connected to the output terminal of the transfer signal Zn, the second terminal is connected to the first low level VGL, and the fifteenth switch tube T15 is turned on according to the potential of the second node QB1, so as to pull down the transfer signal Zn to the first low level VGL.

The ninth switch transistor T9 has a control terminal and a second terminal receiving the second timing signal V2, and the first terminal connected to the third node QB 2. The control terminal of the fifth switching tube T5 is connected to the third node QB2, the first terminal is connected to the first node Q, the second terminal is connected to the second low level VSQ, and the fifth switching tube T5 is turned on according to the potential of the third node QB2, so as to pull down the first node Q to the second low level VSQ. The control terminal of the seventh switch transistor T7 is connected to the third node QB2, the first terminal is connected to the output terminal of the gate driving signal Gn, the second terminal is connected to the first low level VGL, and the seventh switch transistor T7 is turned on according to the potential of the third node QB2 to pull down the gate driving signal Gn to the first low level VGL. The control end of the sixteenth switching tube T16 is connected to the third node QB2, the first end is connected to the output end of the transmission signal Zn, the second end is connected to the first low level VGL, and the sixteenth switching tube T16 is configured to be turned on according to the third node QB2, so as to pull down the transmission signal Zn to the first low level VGL.

A control terminal of the tenth switching tube T10 receives the first timing signal V1, a first terminal of the tenth switching tube T10 is connected to the second low level VSQ, a second terminal of the tenth switching tube T10 is connected to the third node QB2, a control terminal of the eleventh switching tube T11 receives the second timing signal V2, the first terminal of the eleventh switching tube T11 is connected to the second node QB1, and the second terminal of the eleventh switching tube T11 is connected to the second low level VSQ. The tenth and eleventh switching tubes T10 and T11 are alternately turned on to maintain the third and second nodes QB2 and QB1 at the second low level VSQ, respectively.

The control terminals of the twelfth and thirteenth switching tubes T12 and T13 are connected to the first node Q, the first terminal is connected to the second low level VSQ, the second terminals are respectively connected to the second node QB1 and the third node QB2, and the twelfth and thirteenth switching tubes T12 and T13 are turned on according to the potential of the first node Q to maintain the second node QB1 and the third node QB2 at the second low level VSQ.

The gate driving unit 121 charges the first node Q in response to the start pulse signal or the output signal Gn-4 of the n-4 th stage gate driving unit and the transfer signal Zn-4. When the voltage of the first node Q is raised to a voltage equal to or greater than the threshold voltage of the pull-up switching tube, the gate driving unit of each stage generates an output signal. The output signal of the gate driving unit of each stage is supplied to one scan line as a gate driving signal. Therefore, when the number of scan lines increases due to an increase in resolution of the display panel, the size of the gate driving circuit increases.

Therefore, further improvement of the gate driving circuit in the prior art is needed to solve the above problems.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a gate driving unit, a gate driving circuit, and a display device, in which the multi-output gate driving unit can provide a plurality of gate driving signals, and the number of elements of the gate driving circuit and the width of the gate driving circuit are reduced while increasing the resolution, thereby realizing a narrow frame of a display panel.

According to an aspect of the present invention, there is provided a gate driving unit for driving a plurality of corresponding scan lines on a display panel, the gate driving unit including: the input module is connected with the first node and charges the first node according to the pre-charging signal; the output module is connected with the first node and provides a transmission signal and a plurality of gate driving signals with different time sequences according to the voltage of the first node and a plurality of clock signals; and the pull-down stabilizing module is connected with the output end of the output module and maintains the plurality of grid driving signals at a first low level under the control of a pull-down signal, wherein the output module further comprises a first switch tube which is used for carrying out feedback charging on the input module according to the transmission signal during the starting period of the output module so as to maintain the first node at a high potential.

Optionally, the output module includes: a control end of the second switching tube is connected with the first node, a first end of the second switching tube is used for receiving a first clock signal in the plurality of clock signals, and a second end of the second switching tube is used for outputting the transmission signal; a plurality of output switching tubes, wherein control ends of the plurality of output switching tubes are connected with the first node, a first end of each output switching tube is used for receiving other clock signals except the first clock signal in the plurality of clock signals, and a second end of each output switching tube is used for outputting respective gate driving signals; and the first end of the first capacitor is connected with the control end of the second switch tube, and the second end of the first capacitor is connected with the second end of the second switch tube.

Optionally, the input module includes: the control end and the first end of the third switching tube receive the pre-charging signal; and the control end of the fourth switching tube receives the pre-charging signal, the first end of the fourth switching tube is connected with the second end of the third switching tube, the second end of the fourth switching tube is connected with the first node, and the middle node of the third switching tube and the fourth switching tube is connected with the second end of the first switching tube.

Optionally, the pull-down stabilizing module includes fifth to eleventh switching tubes, and a plurality of pull-down switching tubes, a control end and a first end of the fifth switching tube receive the first level signal, a second end of the fifth switching tube is provided to be connected to a third node, a control end of the sixth switching tube is connected to the third node, the first end of the fifth switching tube receives the first level signal, the second end of the sixth switching tube is connected to the second node, a control end of the seventh switching tube is connected to the output end of the transmission signal, the first end of the seventh switching tube is connected to the third node, the second end of the seventh switching tube receives the second low level, a control end of the eighth switching tube receives the pre-charge signal, the first end of the eighth switching tube is connected to the second node, the second end of the eighth switching tube receives the second low level, a control end of the ninth switching tube is connected to the second node, the first end of the ninth switching tube is connected to the output end of the transmission signal, and the second end of the eighth switching tube receives the second low level, the control end of the tenth switch tube is connected with the second node, the first end of the tenth switch tube is connected with the first node, the second end of the tenth switch tube is connected with the output end of the transmission signal, the control end of the eleventh switch tube is connected with the output end of the transmission signal, the first end of the eleventh switch tube is connected with the second node, the second end of the eleventh switch tube receives the second low level, the control end of each pull-down switch tube is connected with the second node, the first end of each pull-down switch tube is connected with the second end of the corresponding output switch tube, and the second end of each pull-down switch tube receives the first low level.

Optionally, the pull-down stabilizing module includes a first stabilizing module and a second stabilizing module, and the first stabilizing module and the second stabilizing module alternately operate to stabilize the transmission signal and the plurality of gate driving signals output by the output module.

Optionally, the first stabilizing module includes: a fifth switching tube, wherein the control end receives the reset signal, the first end receives the first timing signal, and the second end is connected with the fourth node; a control end of the seventh switching tube receives a second clock signal, the first end of the seventh switching tube is connected with the first end of the fifth switching tube, and the second end of the seventh switching tube is connected with the fourth node; a control end of the ninth switching tube is connected with the fourth node, a first end of the ninth switching tube is connected with a first end of the fifth switching tube, and a second end of the ninth switching tube is connected with the second node; the control end of the eleventh switching tube receives the pre-charging signal, the first end of the eleventh switching tube is connected with the fourth node, and the second end of the eleventh switching tube receives the first low level; a thirteenth switching tube, a control end receiving the pre-charge signal, a first end connected to the second node, and a second end receiving the first low level; a fifteenth switching tube, a control end of which is connected with the second node, a first end of which is connected with the output end of the transmission signal, and a second end of which receives the second low level; a sixteenth switching tube, a control end of which is connected with the second node, a first end of which is connected with the first node, and a second end of which is connected with the output end of the transmission signal; a seventeenth switching tube, a control end of which is connected with the output end of the transmission signal, a first end of which is connected with the second node, and a second end of which receives the second low level; and the control end of each first pull-down switch tube is connected with the second node, the first end of each first pull-down switch tube is connected with the second end of the corresponding output switch tube, and the second end of each first pull-down switch tube receives the first low level.

Optionally, the second pull-down stabilizing module includes: a sixth switching tube, a control end receives the reset signal, a first end is connected with the fifth node, and a second end receives the second timing signal; the control end of the eighth switching tube receives a second clock signal, the first end of the eighth switching tube is connected with the fifth node, and the second end of the eighth switching tube is connected with the second end of the sixth switching tube; a tenth switching tube, a control end of which is connected with the fifth node, a first end of which is connected with the third node, and a second end of which is connected with the second end of the sixth switching tube; a twelfth switching tube, a control end receives the pre-charge signal, a first end is connected with the fifth node, and a second end receives the first low level; a fourteenth switching tube, a control end of which receives the pre-charge signal, a first end of which is connected to the third node, and a second end of which receives the first low level; an eighteenth switching tube, a control end of which is connected with the output end of the transmission signal, a first end of which is connected with the third node, and a second end of which receives the second low level; a nineteenth switching tube, a control end of which is connected with the third node, a first end of which is connected with the first node, and a second end of which is connected with the output end of the transmission signal; a twentieth switching tube, a control end of which is connected with the third node, a first end of which is connected with the output end of the transmission signal, and a second end of which receives the second low level; and the control end of each second pull-down switch tube is connected with the third node, the first end of each second pull-down switch tube is connected with the second end of the corresponding output switch tube, and the second end of each second pull-down switch tube receives the first low level.

According to another aspect of the present invention, there is provided a gate driving circuit, wherein the gate driving circuit comprises a plurality of stages of gate driving units including at least one stage of the gate driving unit.

Optionally, the pre-charge signal of the gate driving unit of the first stage in the multi-stage gate driving unit is a start pulse signal, and the pre-charge signal of each stage of the gate driving unit other than the first stage in the multi-stage gate driving unit is a transfer signal output by the gate driving unit of the previous stage of the gate driving unit.

According to another aspect of the present invention, there is provided a display device, comprising: the gate driving circuit of any one of the above claims, configured to provide a plurality of gate driving signals; a data driving circuit for providing a plurality of gray scale data; and a display panel including a plurality of pixel units arranged in an array, and a plurality of scan lines and a plurality of data lines, wherein the display panel receives the plurality of gate driving signals via the plurality of scan lines to select the plurality of pixel units by rows, and receives the plurality of gray scale data via the plurality of data lines by columns to provide the plurality of gray scale data to the selected pixel units to realize image display.

According to the gate driving unit, the gate driving circuit and the display device, the transfer signal can charge the input module, so that the first node can be charged even if the initial pulse signal or the previous-stage transfer signal is switched to be at a low level, the first capacitor is ensured to be bootstrapped without leakage, and the stability of the gate driving circuit and the display device during working is effectively improved.

Furthermore, the pull-down stabilizing module receives a reset signal, and the function of uniformly resetting a plurality of grid driving units in the grid driving circuit and the display device is realized.

Furthermore, in the gate driving unit, the plurality of switching tubes of the output module are controlled by the voltage of the first node, and the switching tubes with smaller parameters can be adopted, so that the power consumption can be further reduced.

Furthermore, in the gate driving circuit and the display device, each stage of gate driving unit only needs to provide a transmission signal for the next stage of gate driving unit, and cross-stage connection is not needed, so that the frame width of the display device can be further reduced.

Furthermore, in the gate driving unit, the gate driving circuit and the display device, the voltage of the first node can be sufficiently high by increasing the voltage of the first clock signal, so that a better gate driving signal waveform can be obtained.

Furthermore, the first high level is used in the gate driving unit, the gate driving circuit and the display device to replace the first time sequence signal and the second time sequence signal, so that the number of switching tubes required by the pull-down stabilizing module can be reduced, the layout area is further reduced, the design space is increased, and the width of a frame of the display device is favorably reduced.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a gate drive circuit according to the prior art;

fig. 2 is a schematic circuit diagram of the gate driving unit of fig. 1;

FIG. 3 shows a schematic diagram of a gate driver circuit according to a first embodiment of the invention;

fig. 4 shows a circuit configuration diagram of a gate driving unit according to a first embodiment of the present invention;

fig. 5 shows a timing diagram of a gate driving unit according to a first embodiment of the present invention;

FIG. 6 is a timing diagram of a gate driving circuit according to a first embodiment of the present invention;

fig. 7 shows a circuit configuration diagram of a gate driving unit according to a second embodiment of the present invention;

fig. 8 illustrates a package diagram of a gate driving unit according to a second embodiment of the present invention;

fig. 9 shows a timing diagram of a gate driving unit according to a second embodiment of the present invention;

FIG. 10 shows a schematic diagram of a gate driver circuit according to a second embodiment of the invention;

FIG. 11 shows a timing diagram of a gate driving circuit according to a second embodiment of the present invention;

fig. 12A shows waveform diagrams of the first node and the first gate driving signal when the first clock signal voltage is normal;

FIG. 12B illustrates waveforms of the first node and the first gate driving signal after increasing the voltage of the first clock signal;

fig. 13 is a schematic circuit configuration diagram showing a gate driving unit according to a third embodiment of the present invention;

fig. 14 shows an equivalent circuit diagram of a display panel according to a first embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

In the present application, the switch transistor is a transistor that operates in a switching mode to provide a current path, and includes one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switching tube can be a high potential end and a low potential end on a current path respectively, and can also be a low potential end and a high potential end on the current path respectively, and the control end is used for receiving a driving signal to control the on and off of the switching tube.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.

Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Fig. 3 shows a schematic diagram of a gate driving circuit according to a first embodiment of the present invention, and as shown in fig. 3, in this embodiment, a display device 200 includes a display panel 210 and a gate driving circuit 220, wherein the gate driving circuit 220 may be integrated on the same substrate as the display panel 210 to form an integrated gate driving circuit structure.

The display panel 210 includes pixel units (not shown) arranged in rows and columns and m scan lines transmitting gate driving signals, where m is a non-zero integer.

The gate driving circuit 220 includes a plurality of stages of gate driving units 221, and each stage of gate driving unit 221 outputs a corresponding gate driving signal through a corresponding scan line. In this embodiment, each stage of the gate driving unit 221 in the gate driving circuit 220 is connected to the corresponding two scan lines, and provides the gate driving signals G1 to Gm in response to the start pulse signal, so as to turn on the thin film transistors (not shown) in each row of the pixel units row by row.

In an alternative embodiment, each multi-output gate driving unit corresponds to a plurality of rows of pixel cells corresponding to three or more scan lines, and generates output signals in response to a start pulse signal and shifts the signal output according to clock timing, and provides gate driving signals G1 to Gm to turn on the thin film switching tubes in the pixel cells of each row one by one.

Fig. 4 shows a schematic circuit configuration diagram of a gate driving unit according to a first embodiment of the present invention.

Taking the nth stage gate driving unit as an example, where n is an integer greater than 1, the gate driving unit 221 is connected to two scan lines on the display panel, responds to the transfer signal Zn-1 output by the nth-1 stage gate driving unit, and provides the gate driving signals Gn and Gn +1 through the corresponding two scan lines. As shown in fig. 4, the gate driving unit 221 includes an input module 2211, an output module 2212, and a pull-down stabilization module 2213.

The input module 2211 includes a third switch tube T3 and a fourth switch tube T4, control terminals of the third switch tube T3 and the fourth switch tube T4 and a first terminal of the third switch tube T3 receive the transfer signal Zn-1 of the n-1 th stage gate driving unit, a second terminal of the third switch tube T3 is connected with a first terminal of a fourth switch tube T4, and a second terminal of the fourth switch tube T4 is connected to the first node Q.

The output module 2212 provides a gate driving signal according to the voltage of the first node Q and a clock signal. The output module 2212 includes a first switch tube T1, a second switch tube T2, a first capacitor C1, an output switch tube T21, and an output switch tube T22.

The first end of the first capacitor C1, the control ends of the second switch tube T2, the output switch tube T21 and the output switch tube T22 are connected to the first node Q, the first ends of the second switch tube T2, the output switch tube T21 and the output switch tube T22 respectively receive the first clock signal CLK1, the third clock signal CLK3 and the fourth clock signal CLK4, the second end of the first capacitor C1 and the second end of the second switch tube T2 are connected to output the transfer signal Zn, the control end of the first switch tube T1 receives the first clock signal CLK1, the first end of the first switch tube T1 is connected to the second end of the first capacitor C1, the middle node of the third switch tube T3 and the fourth switch tube T4 is connected to the second end of the first switch tube T1, and the second end of the first capacitor C1 is connected to the control end of the eleventh switch tube T11.

The first capacitor C1 is a parasitic capacitor between the control terminal and the second terminal of the second switch transistor T2. It should be understood that, in order to improve the coupling effect of the capacitor, and thus the effect of pulling up the voltage of the first node Q, a separate storage capacitor may be disposed between the control terminal and the second terminal of the second switch transistor T2, and the first capacitor C1 is the sum of the storage capacitor and a parasitic capacitor between the control terminal and the second terminal of the second switch transistor T2.

The transmission signal Zn charges a node between the third switching tube T3 and the fourth switching tube T4 through the first switching tube T1, so that even if the previous-stage transmission signal Zn-1 is switched to a low level, the transmission signal Zn still charges the first node Q through the first switching tube T1 and the fourth switching tube T4, thereby ensuring that the first capacitor C1 is free from self-lifting and leakage, and effectively improving the stability of the gate driving unit 221 during operation.

The pull-down stabilizing module 2213 includes fifth to eleventh switching tubes T5-T11 and pull-down switching tubes T31 and T32. Wherein, a control terminal and a first terminal of a fifth switching tube T5 receive the first level signal VDC, a second terminal and a first terminal of a seventh switching tube T7 are connected to a third node QC, a control terminal of a sixth switching tube T6 is connected to a third node QC, the first terminal receives the first level signal VDC, the second terminal is connected to a second node QB, a control terminal of a seventh switching tube T7 is connected to a control terminal of an eleventh switching tube T11, the second terminal is connected to a second low level VSQ, a control terminal of an eighth switching tube T8 receives the previous transfer signal Zn-1, the first terminal is connected to the second node QB, the second terminal is connected to the second low level VSQ, a ninth switching tube T9 and a tenth switching tube T10 are sequentially connected in series between the first node Q and the second low level VSQ, control terminals of a ninth switching tube T9 and a tenth switching tube T10 are connected to the second node QB, and a middle output terminal of the ninth switching tube T9 and the tenth switching tube T10 are connected to the transfer signal output terminal, the eleventh switching tube T11 has a first terminal connected to the second node QB, a control terminal connected to the output terminal of the transfer signal Zn, and a second terminal connected to the second low level VSQ.

The control terminals of the pull-down switch transistor T31 and the pull-down switch transistor T32 are connected to the second node QB, the second terminals of the pull-down switch transistor T31 and the pull-down switch transistor T32 are connected to the first low level VGL, the first terminal of the pull-down switch transistor T31 is connected to the second terminal of the output switch transistor T21, and the first terminal of the pull-down switch transistor T32 is connected to the second terminal of the output switch transistor T22.

The pull-down switch transistor T31 and the pull-down switch transistor T32 maintain the gate driving signal Gn and the gate driving signal Gn +1 at the first low level VGL according to the potential of the second node QB.

Fig. 5 shows a timing diagram of a gate driving unit according to a first embodiment of the present invention. In the present embodiment, the gate driving unit 221 of the first stage is exemplified, and as for the gate driving unit 221 of the first stage, it supplies the gate driving signals G1 and G2 to the corresponding two scanning lines in response to the start pulse signal STV. In fig. 5, signal waveforms of the start pulse signal STV, the first clock signal CLK1, the first node Q, the third clock signal CLK3, the fourth clock signal CLK4, the gate driving signals G1 and G2, and the second node QB are sequentially shown from top to bottom. The duty ratios of the third clock signal CLK3 and the fourth clock signal CLK4 are the same, and the fourth clock signal CLK4 is delayed from the third clock signal CLK3 by a predetermined time. The working process of each stage of gate driving unit comprises a pre-charging stage, a pull-up stage, a reset stage and a stabilization stage. The gate driving unit according to the embodiment of the present invention will be described in detail with reference to fig. 4 and 5.

During the precharge phase, i.e., the t 1-t 2 phases: the start pulse signal STV is at a high level, the first node Q is precharged through the third transistor T3 and the fourth transistor T4, such that the potential of the first node Q is pulled high, the eighth transistor T8 is turned on, the second node QB is maintained at the second low level VSQ, and the ninth transistor T9, the tenth transistor T10 and the output transistors T31 and T32 are turned off.

In the pull-up stage, i.e., the t 2-t 3 stages: the second switch tube T2 is pre-charged and turned on at the stage T1, the first clock signal CLK1 is switched from low level to high level, and pulls up the potential of the first node Q by the bootstrap action of the first capacitor C1, the second switch tube T2 is turned on completely, and the transfer signal Zn is output by the second switch tube T2, so that the eleventh switch tube T11 is turned on, the voltage of the second node QB is pulled down to the second low level VSQ, and the seventh switch tube T7 is turned on, and the voltage of the third node QC is pulled down to the second low level VSQ, thereby turning off the sixth switch tube T6. Meanwhile, the first node Q of the high level controls the third clock signal CLK3 and the fourth clock signal CLK4 to generate the first gate driving signal Gn and the second gate driving signal Gn +1, respectively; meanwhile, the node between the third switching tube T3 and the fourth switching tube T4 is charged through the first switching tube T1, so that the bootstrap circuit is ensured to be free of electricity leakage.

During the reset phase, i.e. the phases t3 to t 4: the first clock signal CLK1 is at low level, the waveform is reset to low level by the second switch transistor T2, and the potential of the first node Q is coupled to low level via the first capacitor C1; meanwhile, the seventh switch tube T7 and the eleventh switch tube T11 are turned off, the voltage of the second node QB is increased to the voltage represented by the first level signal VDC, so that the ninth switch tube T9 and the tenth switch tube T10 are turned on, the voltage of the point Q of the first node is pulled down to the second low level VSQ, thereby turning off the second switch tube T2, the output switch tube T21 and the output switch tube T22, and turning on the pull-down switch tube T31 and the pull-down switch tube T32, so that the waveform of the gate driving signal is maintained and stabilized at the first low level VGL, and mutual interference of the cascaded gate driving units is avoided.

Fig. 6 shows a timing diagram of a gate driving circuit according to a first embodiment of the present invention. In fig. 6, the start pulse signal STV, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5 and the sixth clock signal CLK6 are sequentially arranged from top to bottom, wherein the period of the first clock signal CLK1 and the second clock signal CLK2 is 2T and the duty ratio is one half, and the period of the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5 and the sixth clock signal CLK6 is 4T and the duty ratio is one quarter.

Fig. 7 shows a circuit configuration diagram of a gate driving unit according to a second embodiment of the present invention.

In this embodiment, the gate driving unit 321 corresponds to three rows of pixels corresponding to three scan lines. Taking the nth stage gate driving unit 321 as an example, the nth stage gate driving unit 321 is responsive to the transfer signal Zn-1 of the nth-1 stage gate driving unit and supplies gate driving signals Gn, Gn +1, and Gn +2 through the corresponding three scan lines.

As shown in fig. 7, the gate driving unit 321 includes an input module 3211, an output module 3212, and a pull-down stabilizing module 3213.

The input module 3211 charges the first node Q in response to the transfer signal Zn-1 of the n-1 th stage gate driving unit.

The input module 3211 includes a third switching tube T3 and a fourth switching tube T4, the third switching tube T3, a control terminal of the fourth switching tube T4, and a first terminal of the third switching tube T3 receive the transmission signal Zn-1 of the (n-1) th stage gate driving unit, and a second terminal of the third switching tube T3 is connected to a first terminal of the fourth switching tube T4.

The output block 3212 is configured to provide gate driving signals through at least three scan lines according to the voltage of the first node Q, a RESET signal RESET, and a clock signal.

The output module 3212 includes a first switch transistor T1, a second switch transistor T2, an output switch transistor T21, an output switch transistor T22, an output switch transistor T23, and a first capacitor C1.

The first end of the first capacitor C1, the control ends of the second switch tube T2, the output switch tube T21, the output switch tube T22 and the output switch tube T23 are connected to the first node Q, the first ends of the second switch tube T2, the output switch tube T21, the output switch tube T22 and the output switch tube T23 respectively receive a first clock signal CLK1, a third clock signal CLK3, a fourth clock signal CLK4 and a fifth clock signal CLK5, the second end of the first capacitor C1 and the second end of the second switch tube T2 are connected to output a transfer signal Zn, the control end of the first switch tube T1 receives the first clock signal CLK1, the first end of the first switch tube T1 is connected to the second end of the first capacitor C1, and the middle nodes of the third switch tube T3 and the fourth switch tube T4 are connected to the second end of the first switch tube T1.

The transmission signal Zn charges a node between the third switching tube T3 and the fourth switching tube T4 through the first switching tube T1, so that even if the previous-stage transmission signal Zn-1 is switched to a low level, the transmission signal Zn still charges the node Q through the first switching tube T1 and the fourth switching tube T4, thereby ensuring that the first capacitor C1 is free from self-lifting and leakage, and effectively improving the stability of the gate driving unit 321 during operation.

The pull-down stabilizing module 3213 includes a first stabilizing module and a second stabilizing module, which alternately operate to stabilize the plurality of gate driving signals Gn-Gn +2 and the transfer signal Zn output by the output module 3212.

The first stabilizing module comprises a fifth switch tube T5, a seventh switch tube T7, a ninth switch tube T9, an eleventh switch tube T11, a thirteenth switch tube T13, a fifteenth switch tube T15, a sixteenth switch tube T16, a seventeenth switch tube T17 and a plurality of first pull-down switch tubes T31-T33.

A control terminal of the fifth switching tube T5 receives the RESET signal RESET, a first terminal receives the first timing signal V1, and a second terminal provides a voltage of the fourth node QC 1; a control terminal of the seventh switching transistor T7 receives a second clock signal CLK2, a first terminal of which is connected to a first terminal of the fifth switching transistor T5, and a second terminal of which is connected to the fourth node QC 1; a control terminal of the ninth switching transistor T9 is connected to the fourth node QC1, a first terminal of the ninth switching transistor T9 is connected to a first terminal of the fifth switching transistor T5, and a second terminal of the ninth switching transistor T9 provides a voltage of the second node QB 1; control ends of an eleventh switch tube T11 and a thirteenth switch tube T13 receive a transmission signal Zn-1 of the (n-1) th-level gate driving unit, first ends of the eleventh switch tube T11 and the thirteenth switch tube T13 are respectively connected with the fourth node QC1 and the second node QB1, and second ends of the eleventh switch tube T11 and the thirteenth switch tube T13 are connected to the first low level; a sixteenth switching tube T16 and a fifteenth switching tube T15 which are sequentially connected in series between the first node Q and the second low-level VSQ, wherein a control end is connected with the second node, and an intermediate node between the fifteenth switching tube T15 and the sixteenth switching tube T16 is connected with the second end of the first capacitor C1; a control terminal of the seventeenth switching transistor T17 is connected to the second terminal of the first capacitor C1, a first terminal of the seventeenth switching transistor T17 is connected to the second node QB1, and a second terminal of the seventeenth switching transistor T17 is connected to the second low level VSQ.

The control terminals of the first pull-down switches T31-T33 are connected to the second node QB1, and the second terminals of the first pull-down switches T31-T33 are connected to the first low level VGL.

The second stabilizing module comprises a sixth switching tube T6, an eighth switching tube T8, a tenth switching tube T10, a twelfth switching tube T12, a fourteenth switching tube T14, an eighteenth switching tube T18, a nineteenth switching tube T19, a twentieth switching tube T20 and a plurality of second pull-down switching tubes T41-T43.

A control end of the sixth switching tube T6 receives the RESET signal RESET, a first end of the sixth switching tube T6 provides a voltage of a fifth node QC2, a second end of the sixth switching tube T6 receives the second timing signal V2, a control end of the eighth switching tube T8 receives the second clock signal CLK2, the first end of the eighth switching tube T8 is connected with the fifth node QC2, and the second end of the sixth switching tube T6 is connected with the second end of the sixth switching tube T6; a control terminal of the tenth switching tube T10 is connected to the fifth node QC2, a first terminal thereof provides the voltage of the third node QB2, and a second terminal thereof is connected to the second terminal of the sixth switching tube T6; control ends of a twelfth switching tube T12 and a fourteenth switching tube T14 receive a transmission signal Zn-1 of the (n-1) th-level gate driving unit, a first end of the twelfth switching tube is respectively connected with a fifth node QC2 and a third node QB2, and a second end of the twelfth switching tube is connected with a first low level VGL; a nineteenth switching tube T19 and a twentieth switching tube T20 which are sequentially connected in series between the first node Q and the second low level VSQ, wherein a control end is connected with the third node QB2, and a middle node between the nineteenth switching tube T19 and the twentieth switching tube T20 is connected with a second end of the first capacitor C1; the eighteenth switching transistor T18 has a control terminal connected to the second terminal of the first capacitor C1, a first terminal connected to the third node QB2, and a second terminal connected to the second low level VSQ.

The control terminals of the second plurality of pull-down switching transistors T41-T43 are connected to the third node QB2, and the second terminals of the second plurality of pull-down switching transistors T41-T43 are connected to the first low level VGL.

The control terminal of the fifth switching transistor T5 and the control terminal of the sixth switching transistor T6 receive the RESET signal RESET, thereby implementing a function of uniformly resetting the plurality of gate driving units 321 in the gate driving circuit 220.

The first pull-down switch T31 and the second pull-down switch T41 alternately provide the first pull-down signal according to the active states of the first node Q, the second node QB1 and the third node QB2 to maintain the gate driving signal Gn at the first low level VGL. The first pull-down switch transistor T32 and the second pull-down switch transistor T42 alternately provide the second pull-down signal according to the active states of the first node Q, the second node QB1 and the third node QB2 to maintain the gate driving signal Gn +1 at the first low level VGL. The first pull-down switch transistor T33 and the second pull-down switch transistor T43 alternately provide the third pull-down signal according to the active states of the first node Q, the second node QB1 and the third node QB2 to maintain the gate driving signal Gn +2 at the first low level VGL.

The first timing signal V1 and the second timing signal V2 are complementary timing signals, and the high and low levels thereof are related to the frame rate, for example, the high and low states of the first timing signal V1 and the second timing signal V2 are switched once per frame. For example, the first timing signal V1 is at a high level, the second timing signal V2 is at a low level, the first timing signal V1 is at a low level, and the second timing signal V2 is at a high level after switching to the next frame.

Fig. 8 illustrates a package diagram of a gate driving unit according to a second embodiment of the present invention.

Taking the nth gate driving unit as an example as shown in fig. 7, the nth gate driving unit is packaged to form a Stage block, and the Stage block at least includes an input terminal for receiving the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the first timing signal V1, the second timing signal V2, the first low level VGL, the second low level VSQ, and the transfer signal Zn-1 provided by the nth-1 gate driving unit, and an output terminal for transmitting the first gate driving signal Gn, the second gate driving signal Gn +1, the third gate driving signal Gn +2, and the transfer signal Zn.

Fig. 9 shows a timing diagram of a gate driving unit according to a second embodiment of the present invention.

In the present embodiment, the gate driving unit 321 of the first stage is exemplified, and as for the gate driving unit 321 of the first stage, it supplies the gate driving signals G1, G2, and G3 to the corresponding three scanning lines in response to the start pulse signal STV. In fig. 9, signal waveforms of the RESET signal RESET, the start pulse signal STV, the first clock signal CLK1, the first node Q, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the gate driving signals G1, G2, and G3, the second node QB1, and the third node QB2 are sequentially shown from top to bottom. The duty ratios of the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5 are the same, the fourth clock signal CLK4 is delayed by a certain time from the third clock signal CLK3, and the fifth clock signal CLK5 is delayed by a certain time from the fourth clock signal CLK 4. The working process of each stage of the gate driving unit comprises a reset stage, a pre-charge stage, a pull-up stage and a stabilization stage. The gate driving unit according to the embodiment of the present invention will be described in detail with reference to fig. 7 and 9.

During the reset phase, i.e. the phases t1 to t 2: the Reset signal Reset turns on the fifth switch transistor T5, and further turns on the ninth switch transistor T9, so as to pull the second node QB1 to a high level to turn on the fifteenth switch transistor T15, the sixteenth switch transistor T16, the pull-down switch transistor T31, the pull-down switch transistor T32 and the pull-down switch transistor T33, and pull down the first gate driving signal Gn, the second gate driving signal Gn +1, the third gate driving signal Gn +2 and the transfer signal Zn to a first level VGL; and pulls QB2 low, the next frame QB1 and QB2 level exchange.

During the precharge phase, i.e., the t 2-t 3 phases: when the start pulse signal STV is at a high level, the eleventh switch transistor T11 and the twelfth switch transistor T12 are turned on, and the fourth node QC1 and the fifth node QC2 are pulled down to the first low level VGL, so that the ninth switch transistor T9 and the tenth switch transistor T10 are turned off; the thirteenth switching tube T13 and the fourteenth switching tube T14 are turned on, and the second node QB1 and the third node QB2 are pulled down to the first low level VGL, so that the fifteenth switching tube T15, the sixteenth switching tube T16, the nineteenth switching tube T19 and the twentieth switching tube T20 are turned off; the first node Q is precharged through the third switch transistor T3 and the fourth switch transistor T4, and the potential of the first node Q is pulled high.

In the pull-up stage, i.e., the t 3-t 4 stages: the second switch tube T2 is already turned on through the pre-charging in the stage T2, the first clock signal CLK1 is raised from low level to high level, and pulls up the potential of the first node Q through the bootstrap action of the first capacitor C1, the second switch tube T2 is fully turned on, outputs the transfer signal Zn through the second switch tube T2, turns on the seventeenth switch tube T17 and the eighteenth switch tube T18, pulls down the voltages of the second node QB1 and the third node QB2 to the second low level VSQ, thereby turning off the pull-down switch tube T31, the pull-down switch tube T32, the pull-down switch tube T33, the pull-down switch tube T41, the pull-down switch tube T42 and the pull-down switch tube T43; the first node Q of the high level controls the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5 to generate the first gate driving signal Gn, the second gate driving signal Gn +1, and the third gate driving signal Gn +2, respectively; meanwhile, the node between the third switching tube T3 and the fourth switching tube T4 is charged through the first switching tube T1, so that the bootstrap circuit is ensured to be free of electricity leakage. At this stage, the fourth node QC1 and the fifth node QC2 are both low and empty (floating), and therefore can be easily pulled down to the second low VSQ.

In the stabilization phase, i.e., the t 4-t 5 phases: the first clock signal CLK1 is at a low level, the transfer signal Zn is reset to a low level by the second switch transistor T2, and the potential of the first node Q is coupled to a low level through the first capacitor C1, at this time, the Q point is not completely turned off, the transfer signal Zn is pulled down to VGL by the first clock signal CLK1 through the second switch transistor T2, the third gate driving signal Gn +2 is pulled down to the first low level VGL by the fifth clock signal CLK5 through the sixth switch transistor T6, and when the transfer signal Zn becomes a low level, the seventeenth switch transistor T17 and the eighteenth switch transistor T18 are turned off; the second clock signal CLK2 is switched from low level to high level, the first switch transistor T7 and the eighth switch transistor T8 are turned on, the fourth node QC1 is charged to high level, and the fifth node QC2 is still at low level, so that the ninth switch transistor T9 is turned on to charge the second node QB 1; when the second node QB1 is switched to a high level, the fifteenth switch tube T15, the sixteenth switch tube T16, the pull-down switch tube T21, the pull-down switch tube T22 and the pull-down switch tube T23 are turned on, so that the transfer signal Z1 and the gate driving signals G1-G3 are pulled down to the first low level VGL, waveforms of the gate driving signals are maintained to be stable at the low level, and the cascaded gate driving units are prevented from interfering with each other.

In the gate driving unit 321, since the plurality of switching transistors in the output block 3212 are controlled by the voltage of the first node Q, a switching transistor with a smaller parameter can be used, and power consumption can be further reduced.

Fig. 10 shows a schematic diagram of a gate driving circuit according to a second embodiment of the present invention.

As shown in fig. 10, taking an example in which two sides each include three stages of gate driving units, the principle of the first to sixth stages of gate driving units R1 to R6 is described.

Taking the first to third stage gate driving units R1 to R3 as an example, the first to sixth stage gate driving units R1 to R6 all receive the first timing signal V1, the second timing signal V2, the first low level signal VGL, and the second low level signal VSQ. The first stage gate driving unit R1 receives the start pulse signal STV1, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5, the second stage gate driving unit R2 receives the transfer signal Z1, the first clock signal CLK1, the second clock signal CLK2, the sixth clock signal CLK6, the seventh clock signal CLK7, and the eighth clock signal CLK8, and the third stage gate driving unit R3 receives the transfer signal Z2, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK 5.

The connection relationships between the fourth-stage driving units R4-R6 and the first-stage gate driving units R1-R3 are similar, and are not repeated herein.

As can be seen from fig. 10, in the gate driving circuit and the display device, each stage of the gate driving unit 321 only needs to provide a transmission signal to the next stage of the gate driving unit 321, and the frame width of the display device can be reduced without cross-stage connection.

Fig. 11 shows a timing diagram of a gate driving circuit according to a second embodiment of the present invention. In fig. 11, the RESET signal RESET, the start pulse signal STV, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7, and the eighth clock signal CLK8 are sequentially arranged from top to bottom. Taking the high-level duration of the start pulse signal STV as 3T, the period of the first clock signal CLK1 and the second clock signal CLK2 is 3T and the duty ratio is one half, and the period of the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7 and the eighth clock signal CLK8 is 6T and the duty ratio is one sixth.

As shown in fig. 11, a pulse signal is supplied to the gate driving circuit shown in fig. 10, thereby causing the gate driving circuit to output a desired waveform.

Fig. 12A shows waveform diagrams of the first node and the first gate driving signal when the first clock signal voltage is normal.

Referring to fig. 7 and 9, when the start pulse signal STV is switched from a low level to a high level, the first node Q is precharged, and when the first clock signal CLK1 is switched from a low level to a high level, the voltage of the first node Q is pulled up (e.g., to 25V). The first node Q is used to control the on/off of the second switch transistor T2, the output switch transistor T21, the output switch transistor T22 and the output switch transistor T23, and in the pull-up stage, the level of the first node Q is pulled up by the bootstrap of the first capacitor C1, and if the voltage of the first clock signal CLK1 is not high enough, the voltage of the first node Q is not high enough, which causes the delayed on of the second switch transistor T2, the output switch transistor T21, the output switch transistor T22 and the output switch transistor T23, so that the waveforms of the transfer signal and the gate driving signals are abnormal, as shown in fig. 12A.

Here, taking the first gate driving signal Gn as an example, the waveforms of the transfer signal Zn, the second gate driving signal Gn +1, and the third gate driving signal Gn +2 are similar, and are not described again.

Fig. 12B illustrates waveforms of the first node and the first gate driving signal after increasing the voltage of the first clock signal.

Referring to fig. 7 and 9, when the start pulse signal STV is switched from a low level to a high level, the first node Q is precharged, the voltage value of the first clock signal CLK1 is increased, and the voltage of the first node Q is pulled up (e.g., to 35V) when the first clock signal CLK1 is switched from a low level to a high level. The first node Q is used for controlling the on and off of the second switch tube T2, the output switch tube T21, the output switch tube T22 and the output switch tube T23, and the level of the first node Q is pulled up by the bootstrap of the first capacitor C1 in the pull-up stage; when the voltage of the first clock signal CLK1 is increased, the voltage of the first node Q is high enough, and the second switch transistor T2, the output switch transistor T21, the output switch transistor T22 and the output switch transistor T23 do not turn on with a delay, so that the waveforms of the transfer signal and the respective gate driving signals are good, as shown in fig. 12B.

Fig. 13 shows a schematic circuit configuration diagram of a gate driving unit according to a third embodiment of the present invention.

As shown in fig. 13, in this embodiment, the gate driving unit 421 corresponds to three rows of pixels corresponding to three scan lines. Taking the nth stage gate driving unit 421 as an example, the nth stage gate driving unit 421 responds to the output signal Zn-1 of the nth-1 stage gate driving unit and supplies gate driving signals Gn, Gn +1, and Gn +2 through the corresponding three scan lines.

As shown in fig. 13, the gate driving unit 421 includes an input module 4211, an output module 4212 and a pull-down stabilizing module 4213.

The input module 4211 charges the first node Q in response to an output signal Zn-1 of the n-1 th stage gate driving unit.

The input module 4211 comprises a third switching tube T3, a fourth switching tube T4, a third switching tube T3, a control end of the fourth switching tube T4 and a first end of the third switching tube T3 receiving the transmission signal Zn-1 of the (n-1) th stage gate driving unit, and a second end of the third switching tube T3 connected with a first end of the fourth switching tube T4.

The output module 4212 is configured to provide gate driving signals through at least three scan lines according to the voltage of the first node Q and a clock signal. The output module 4212 includes a first switch tube T1, a second switch tube T2, an output switch tube T21, an output switch tube T22, an output switch tube T23 and a first capacitor C1.

The pull-down stabilizing module 4213 includes a fifth switching tube T5, a sixth switching tube T6, a seventh switching tube T7, an eighth switching tube T8, a ninth switching tube T9, a tenth switching tube T10, an eleventh switching tube T11, a pull-down switching tube T31, a pull-down switching tube T32, and a pull-down switching tube T33.

The control end and the first end of the fifth switch tube T5 and the first end of the sixth switch tube T6 receive a first level signal VDC, the control end of the sixth switch tube T6 is connected to the second end of the fifth switch tube T5 and the first end of the seventh switch tube T7, the control end of the sixth switch tube T6 is a third node QC, the second end of the seventh switch tube T7 is connected to a second low level VSQ, the second end of the sixth switch tube T6 provides a voltage of the second node QB, the eighth switch tube T8 is connected to the second node QB and the second low level VSQ, and the control end of the eighth switch tube T8 is connected to the control end of the third switch tube T3.

The tenth switching tube T10 and the ninth switching tube T9 are sequentially connected in series between the first node Q and the second low level VSQ, the control terminals of the tenth switching tube T10 and the ninth switching tube T9 are connected to the second node QB, the control terminal of the eleventh switching tube T11 is connected to the second terminal of the tenth switching tube T10 and the second terminal of the first capacitor C1, the first terminal of the eleventh switching tube T11 is connected to the second node QB, and the second terminal of the eleventh switching tube T11 is connected to the second low level VSQ.

The control terminals of the pull-down switch transistor T31, the pull-down switch transistor T31 and the pull-down switch transistor T33 are connected to the second node QB, and the second terminals of the pull-down switch transistor T31, the pull-down switch transistor T31 and the pull-down switch transistor T33 are connected to the first low level VGL.

The pull-down switch tube T31 provides a first pull-down signal according to the active states of the first node Q and the second node QB, the pull-down switch tube T32 provides a second pull-down signal according to the active states of the first node Q and the second node QB, and the pull-down switch tube T33 provides a second pull-down signal according to the active states of the first node Q and the second node QB.

The first end of the pull-down switch tube T31 is connected to the second end of the output switch tube T21, so that the first pull-down signal pulls down the third clock signal CLK3 to form the first gate driving signal Gn; the first end of the pull-down switch tube T32 is connected to the second end of the output switch tube T22, so that the second pull-down signal pulls down the fourth clock signal CLK4 to form a second gate driving signal Gn +1 n; the first terminal of the pull-down switch transistor T33 is connected to the second terminal of the output switch transistor T23, so that the third pull-down signal pulls down the fifth clock signal CLK5 to form the third gate driving signal Gn + 2.

Referring to fig. 7, the gate driving unit 421 shown in fig. 13 uses the first level signal VDC instead of the first timing signal V1 and the second timing signal V2, so as to further simplify the circuit structure, and compared with the pull-down stabilizing module 3213 of the gate driving unit 321, the number of switching tubes used by the pull-down stabilizing module 4213 of the gate driving unit 421 is less, so as to further reduce the layout area, increase the design space, and facilitate further reducing the width of the frame of the display device.

Fig. 14 shows an equivalent circuit diagram of a display panel according to a first embodiment of the present invention, and a display device 600 according to an embodiment of the present invention is illustrated in fig. 14 by taking a liquid crystal display panel as an example. The display device 600 includes a display panel, a gate driving circuit 610, a data driving circuit 620, and a timing control circuit 630. The display panel includes a plurality of pixel units arranged in an array, each including a Thin Film Transistor (TFT) and a plurality of pixel capacitors (C) formed between a pixel electrode and a common electrode_Lc. The timing control circuit 630 is used for controlling the gate driving circuit 610 and the data driving circuit 620 to provide a plurality of gate driving signals and gray scale data synchronized with the data signals, and the display panel receives the plurality of gate driving signals through the plurality of scanning lines to select the plurality of pixel units according to a row and receives the plurality of gray scale data through the plurality of data lines to provide the plurality of gray scale data to the selected pixel units to realize image display.

The gate driving circuit 610 is connected to the gates of the corresponding rows of the thin film switching tubes T via a plurality of scan lines G1 to Gi, respectively, for providing gate driving signals G1 to Gm in a scanning manner, so as to gate the thin film switching tubes of different rows in one image frame period. The gate driving signals G1 to Gm swing between a gate high voltage VGH and a gate low voltage VGL, the gate high voltage VGH being set to be greater than the threshold voltage of the TFT, and the gate low voltage VGL being set to be less than the threshold voltage of the TFT.

The gate driving circuit 610 includes a plurality of stages of gate driving units 611, and each stage of the gate driving units 611 supplies a gate driving signal to at least two scan lines, thereby driving at least two rows of pixel electrodes.

The data driving circuit 620 is connected to the sources of the corresponding rows of the thin film switching tubes T through the data lines S1 to Sj, respectively, and is configured to provide gray scale voltages corresponding to gray scales when the thin film switching tubes T in each row are gated. Where i and j are natural numbers. The drains of the thin film switch tubes T are respectively connected to a corresponding pixel capacitor C_Lc. In the edge-on state, the data driving circuit 620 applies a gray-scale voltage to the pixel capacitor C via the data line and the thin film transistor T_LcThe above. Pixel capacitance C_LcThe applied voltage acts on the liquid crystal molecules to change the orientation of the liquid crystal molecules to achieve a light transmittance corresponding to a gray scale. To maintain the voltage between update periods of the pixel, the pixel capacitance C_LcThe storage capacitor Cs may be connected in parallel to obtain a longer holding time.

In summary, according to the gate driving unit, the gate driving circuit and the display device provided by the invention, the transfer signal can charge the input module, so that the first node can be charged even if the start pulse signal or the previous-stage transfer signal is switched to a low level, the first capacitor is ensured to be bootstrapped without leakage, and the stability of the gate driving circuit and the display device during operation is effectively improved.

Optionally, the pull-down stabilizing module receives a reset signal, so that a function of uniformly resetting a plurality of gate driving units in the gate driving circuit and the display device is realized.

Optionally, in the gate driving unit, the plurality of switching tubes of the output module are controlled by the voltage of the first node, and the switching tubes with smaller parameters may be adopted, so that power consumption may be further reduced.

Optionally, in the gate driving circuit and the display device, each stage of gate driving unit only needs to provide a transmission signal to the next stage of gate driving unit, and cross-stage connection is not needed, so that the frame width of the display device can be further reduced.

Optionally, in the gate driving circuit and the display device, the voltage of the first node may be sufficiently high by increasing the voltage of the first clock signal, so as to obtain a better gate driving signal waveform.

Optionally, the first high level is used in the gate driving circuit and the display device to replace the first timing signal and the second timing signal, so that the number of switching tubes required by the pull-down stabilizing module can be reduced, the layout area is further reduced, the design space is increased, and the width of a frame of the display device is further reduced.

In the gate driving unit according to the embodiment of the invention, a depletion type thin film transistor, for example, a thin film transistor selected from indium gallium zinc oxide (ingan) thin film transistors, may be used as the switching transistor.

It should be noted that as used herein, the words "during", "when" and "when … …" in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

It should be noted that as used herein, the words "during", "when" and "when … …" in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used. For convenience of understanding and better intuition, the waveform diagrams in the drawings of the present invention may be distinguished from actually measured waveform diagrams, and should not be construed as limiting the present invention.

In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A gate driving unit for driving a plurality of corresponding scan lines on a display panel, the gate driving unit comprising:

the input module is connected with the first node and charges the first node according to the pre-charging signal;

the output module is connected with the first node and provides a transmission signal and a plurality of gate driving signals with different time sequences according to the voltage of the first node and a plurality of clock signals; and

the pull-down stabilizing module is connected with the output end of the output module, changes the effective state of a pull-down signal under the control of the pre-charging signal, and maintains the plurality of gate driving signals at a first low level according to the effective state of the pull-down signal;

the output module further comprises a first switch tube, and the first switch tube is used for performing feedback charging on the input module according to the transmission signal under the control of a first clock signal during the starting period of the output module so as to maintain the first node at a high potential.

2. A gate drive unit as claimed in claim 1, wherein the output module comprises:

a control end of the second switching tube is connected with the first node, a first end of the second switching tube is used for receiving a first clock signal in the plurality of clock signals, and a second end of the second switching tube is used for outputting the transmission signal;

a plurality of output switching tubes, wherein control ends of the plurality of output switching tubes are connected with the first node, a first end of each output switching tube is used for receiving other clock signals except the first clock signal in the plurality of clock signals, and a second end of each output switching tube is used for outputting respective gate driving signals;

and the first end of the first capacitor is connected with the control end of the second switch tube, and the second end of the first capacitor is connected with the second end of the second switch tube.

3. A gate drive unit as claimed in claim 1, wherein the input module comprises:

the control end and the first end of the third switching tube receive the pre-charging signal;

a fourth switching tube, a control end of which receives the pre-charge signal, a first end of which is connected with a second end of the third switching tube, and a second end of which is connected with the first node,

and the middle node of the third switching tube and the fourth switching tube is connected with the second end of the first switching tube.

4. The gate driving unit of claim 1, the pull-down stabilizing module comprising fifth to eleventh switching tubes and a plurality of pull-down switching tubes,

the control end and the first end of the fifth switching tube receive the first level signal, the second end is connected with the third node,

the control end of the sixth switching tube is connected with the third node, the first end receives the first level signal, the second end is connected with the second node,

the control end of the seventh switching tube is connected with the output end of the transmission signal, the first end is connected with the third node, the second end receives the second low level,

the control end of the eighth switching tube receives the pre-charge signal, the first end is connected with the second node, the second end receives the second low level,

the control end of the ninth switching tube is connected with the second node, the first end is connected with the output end of the transmission signal, the second end receives the second low level,

the control end of the tenth switching tube is connected with the second node, the first end is connected with the first node, the second end is connected with the output end of the transmission signal,

the control end of the eleventh switch tube is connected with the output end of the transmission signal, the first end is connected with the second node, the second end receives the second low level,

the control end of each pull-down switch tube is connected with the second node, the first end of each pull-down switch tube is connected with the second end of the corresponding output switch tube, and the second end of each pull-down switch tube receives the first low level.

5. The gate driving unit of claim 1, wherein the pull-down stabilization module comprises a first stabilization module and a second stabilization module, the first stabilization module and the second stabilization module alternately operating for stabilizing the transfer signal and the plurality of gate driving signals output by the output module.

6. The gate driving unit of claim 5, the first stabilization module comprising:

a fifth switching tube, wherein the control end receives the reset signal, the first end receives the first timing signal, and the second end is connected with the fourth node;

a control end of the seventh switching tube receives a second clock signal, the first end of the seventh switching tube is connected with the first end of the fifth switching tube, and the second end of the seventh switching tube is connected with the fourth node;

a control end of the ninth switching tube is connected with the fourth node, a first end of the ninth switching tube is connected with a first end of the fifth switching tube, and a second end of the ninth switching tube is connected with the second node;

the control end of the eleventh switching tube receives the pre-charging signal, the first end of the eleventh switching tube is connected with the fourth node, and the second end of the eleventh switching tube receives the first low level;

a thirteenth switching tube, a control end receiving the pre-charge signal, a first end connected to the second node, and a second end receiving the first low level;

a fifteenth switching tube, a control end of which is connected with the second node, a first end of which is connected with the output end of the transmission signal, and a second end of which receives a second low level;

a sixteenth switching tube, a control end of which is connected with the second node, a first end of which is connected with the first node, and a second end of which is connected with the output end of the transmission signal;

a seventeenth switching tube, a control end of which is connected with the output end of the transmission signal, a first end of which is connected with the second node, and a second end of which receives the second low level; and

and the control end of each first pull-down switch tube is connected with the second node, the first end of each first pull-down switch tube is connected with the second end of the corresponding output switch tube, and the second end of each first pull-down switch tube receives the first low level.

7. The gate drive unit of claim 5, the second stabilization module comprising:

a sixth switching tube, a control end receives the reset signal, a first end is connected with the fifth node, and a second end receives the second timing signal;

the control end of the eighth switching tube receives a second clock signal, the first end of the eighth switching tube is connected with the fifth node, and the second end of the eighth switching tube is connected with the second end of the sixth switching tube;

a tenth switching tube, a control end of which is connected with the fifth node, a first end of which is connected with the third node, and a second end of which is connected with the second end of the sixth switching tube;

a twelfth switching tube, a control end receives the pre-charge signal, a first end is connected with the fifth node, and a second end receives the first low level;

a fourteenth switching tube, a control end of which receives the pre-charge signal, a first end of which is connected to the third node, and a second end of which receives the first low level;

an eighteenth switching tube, a control end of which is connected with the output end of the transmission signal, a first end of which is connected with the third node, and a second end of which receives a second low level;

a nineteenth switching tube, a control end of which is connected with the third node, a first end of which is connected with the first node, and a second end of which is connected with the output end of the transmission signal;

a twentieth switching tube, a control end of which is connected with the third node, a first end of which is connected with the output end of the transmission signal, and a second end of which receives the second low level; and

and the control end of each second pull-down switch tube is connected with the third node, the first end of each second pull-down switch tube is connected with the second end of the corresponding output switch tube, and the second end of each second pull-down switch tube receives the first low level.

8. A gate driving circuit, wherein a multi-stage gate driving unit including at least one stage of the gate driving unit as claimed in any one of claims 1 to 7.

9. The gate driving circuit of claim 8, wherein a precharge signal of the gate driving unit of a first stage of the multi-stage gate driving units is a start pulse signal,

the pre-charge signal of each stage of the gate driving unit except the first stage in the multi-stage gate driving unit is a transfer signal output by the gate driving unit of the previous stage of the gate driving unit.

10. A display device, comprising:

a gate drive circuit as claimed in any one of claims 8 or 9, for providing a plurality of gate drive signals;

a data driving circuit for providing a plurality of gray scale data; and

a display panel including a plurality of pixel units arranged in an array, and a plurality of scan lines and a plurality of data lines,

the display panel receives the gate driving signals through the scanning lines to select the pixel units according to rows, and receives the gray scale data through the data lines to provide the gray scale data for the selected pixel units to realize image display.