CN113628596B

CN113628596B - Gate drive unit, gate drive circuit and display device

Info

Publication number: CN113628596B
Application number: CN202110835739.4A
Authority: CN
Inventors: 魏祥利; 邹忠飞; 房耸
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2021-07-23
Filing date: 2021-07-23
Publication date: 2023-02-24
Anticipated expiration: 2041-07-23
Also published as: CN113628596A

Abstract

The invention discloses a gate driving unit, a gate driving circuit and a display device, wherein the gate driving unit comprises: the input module is connected with the first node and charges the first node according to a pre-charging signal; the output module is connected with the first node and provides a gate driving signal and a transmission signal according to the voltage of the first node and a clock signal; the pull-down stabilizing module is connected with the output module and the first node and is used for maintaining the grid driving signal at a low level under the control of a pull-down signal; the output module comprises a first switch tube, and the first switch tube is used for carrying out feedback charging on the input module and the pull-down stabilizing module according to the transfer signal in a bootstrap stage so as to maintain the first node at a high potential. The grid driving unit provided by the invention can effectively prevent the electric leakage of the thin film transistor in the working process, thereby improving the stability of the thin film transistor.

Description

Gate drive unit, gate drive circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a gate driving unit, a gate driving circuit, and a display device.

Background

The Display device displays Display data on the Display Panel through the transmission apparatus, and examples of the Display device include a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), an Organic Light-Emitting Diode (OLED) Display, and an electrophoretic Display (EPD).

With the development of display technologies, display panels tend to have high integration and low cost. In the related art, a Gate-driver in Array (GIA) circuit is directly integrated on an Array substrate of a display panel, and the GIA circuit generally includes a plurality of cascaded Gate driving units, each corresponding to one or more rows of pixels corresponding to a scan line, so as to implement a scan driver for the display panel. The integration technology can save the area occupied by the gate driving circuit, thereby realizing the narrow frame of the display panel. However, when IGZO (Indium Gallium Zinc Oxide) TFTs (Thin Film transistors) are used in the GIA circuit of the prior art, all the TFTs are turned on when Vgs of the TFTs is greater than or equal to zero, so that when the gate driving unit operates, the TFTs inside the GIA circuit have a leakage problem, which reduces the operation stability and causes the gate driving circuit to fail to operate normally or even be damaged.

Therefore, an improved gate driving unit, gate driving circuit and display device are desired to solve the above problems.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a gate driving unit, a gate driving circuit and a display device, which can effectively prevent a leakage current of a thin film transistor during operation, thereby improving the operation stability.

According to an aspect of the present invention, there is provided a gate driving unit for driving a plurality of corresponding scan lines on a display panel, the gate driving unit including: the input module is connected with the first node and charges the first node according to a pre-charging signal; the output module is connected with the first node and provides a gate driving signal and a transmission signal according to the voltage of the first node and a clock signal; the pull-down stabilizing module is connected with the output module and the first node and is used for maintaining the grid driving signal at a low level under the control of a pull-down signal; the output module comprises a first switch tube, and the first switch tube is used for carrying out feedback charging on the input module and the pull-down stabilizing module according to the transfer signal in a bootstrap stage so as to maintain the first node at a high potential.

Optionally, the output module includes: the control end of the output switch tube is connected to the first node, and after the first end receives the clock signal, the second end provides the grid driving signal according to the clock signal; a first pass switch, a control terminal of the first pass switch being connected to the first node, a first terminal receiving the clock signal; a second pass switch, wherein a control end of the second pass switch is connected to the first node, a first end of the second pass switch is connected to a second end of the first pass switch, and the second end of the second pass switch provides the pass signal; and the first end of the first capacitor is connected with the control end of the output switch tube, and the second end of the first capacitor is connected with the second end of the output switch tube.

Optionally, the input module comprises: a control end of the second switch tube receives the first pre-charging signal, and a second end of the second switch tube receives the second pre-charging signal; a control end of the third switching tube receives the first pre-charge signal, a first end of the third switching tube is connected with a second end of the second switching tube, and the second end of the third switching tube is connected to the first node; the first switch tube is used for providing the transmission signal to an intermediate node of the second switch tube and the third switch tube when the first node is in a high level.

Optionally, the pull-down stabilization module includes: the first and second stability units alternately work according to the effective states of a first timing signal and a second timing signal to maintain the gate driving signal and the transfer signal at a first low level; a stability maintenance control unit configured to turn off the first and second stability maintenance units when the first node is at a high level; and a pull-down unit discharging the first node according to a pull-down signal, wherein the first and second dimensionally stable units are further configured to pull down a voltage of the first node to a second low level after the pull-down unit discharges the first node.

Optionally, the first dimensionally stable unit includes: a thirteenth switching tube, wherein a control end and a first end of the thirteenth switching tube receive the first timing signal, and a second end of the thirteenth switching tube is connected to the second node; a fifteenth switch tube, a control end of which receives the first timing signal, a first end of which is connected to a third node, and a second end of which is connected to the second low level; a seventh switching tube and an eighth switching tube connected between the first node and the second low level, wherein control ends of the seventh switching tube and the eighth switching tube are connected to the second node; the control end of the eleventh switching tube is connected to the second node, the first end of the eleventh switching tube is connected with the output end of the grid driving signal, and the second end of the eleventh switching tube is connected to the first low level; the intermediate node of the seventh switching tube and the eighth switching tube is connected with the output end of the transmission signal, so that the switching-off state is maintained when the transmission signal is at a high level.

Optionally, the second dimensionally stable cell includes: a fourteenth switching tube, a control end and a first end of which receive the second timing signal, and a second end of which is connected to a third node; a sixteenth switching tube, wherein a control end of the sixteenth switching tube receives the second timing signal, a first end of the sixteenth switching tube is connected to the second node, and a second end of the sixteenth switching tube is connected to the second low level; a ninth switching tube and a tenth switching tube connected between the first node and the second low level, wherein control ends of the ninth switching tube and the tenth switching tube are connected to the third node; a control end of the twelfth switching tube is connected to the third node, a first end of the twelfth switching tube is connected with an output end of the grid driving signal, and a second end of the twelfth switching tube is connected to a first low level; the intermediate node of the ninth switching tube and the tenth switching tube is connected with the output end of the transmission signal, so that the off state is maintained when the transmission signal is at a high level.

Optionally, the stability-maintaining control unit includes: nineteenth and twentieth switching tubes connected between a second node and the second low level, wherein control ends of the nineteenth and twentieth switching tubes are connected to the first node; seventeenth and eighteenth switching tubes connected between a third node and the second low level, wherein control ends of the seventeenth and eighteenth switching tubes are connected to the first node.

Optionally, the pull-down unit includes: a control end of the fifth switching tube receives a pull-down signal, and a first end of the fifth switching tube is connected to the first node; a control end of the sixth switching tube receives the pull-down signal, a first end of the sixth switching tube is connected with a second end of the fifth switching tube, and a second end of the sixth switching tube is connected to a first low level; the first switch tube is used for providing the transmission signal to an intermediate node of the fifth switch tube and the sixth switch tube when the first node is at a high level.

According to another aspect of the present invention, there is provided a gate driving circuit, wherein the gate driving circuit comprises a plurality of stages of gate driving units as described above.

According to still another aspect of the present invention, there is provided a display device including: the gate driving circuit as described above, for providing a plurality of gate driving signals; a data driving circuit for providing a plurality of gray scale data; and a display panel including a plurality of pixel units arranged in an array, and a plurality of scan lines and a plurality of data lines, wherein the display panel receives the plurality of gate driving signals via the plurality of scan lines to select the plurality of pixel units by rows, and receives the plurality of gray scale data via the plurality of data lines by columns to provide the plurality of gray scale data to the selected pixel units to realize image display.

In summary, in the gate driving unit provided by the present invention, in the bootstrap phase, the transfer signal is respectively charged to the middle nodes of the second switching tube and the third switching tube, and the middle nodes of the fifth switching tube and the sixth switching tube through the first switching tube according to the voltage of the first node, so as to raise the voltage of the nodes, thereby ensuring that the off states of the third switching tube and the fifth switching tube are maintained under the conditions of different temperatures and different bias voltages, effectively avoiding the phenomenon of unstable waveform of the output signal caused by the leakage of the first node in the bootstrap phase, and thus improving the working stability of the gate driving unit and the adaptability to different application scenarios at different temperatures.

Optionally, in the bootstrap phase, the control ends of the eighth switching tube and the tenth switching tube are connected to the second low level, and one path end of the eighth switching tube and the tenth switching tube is also connected to the second low level, so that the intermediate node between the seventh switching tube and the eighth switching tube is connected to the output end for transmitting a signal, and the intermediate node between the ninth switching tube and the tenth switching tube is connected to the output end for transmitting a signal, so as to raise the voltage of the first ends of the eighth switching tube and the tenth switching tube, prevent the first node from leaking electricity through the first node in the bootstrap phase, and thereby improve the stability of the gate driving unit.

Optionally, the first transfer switching tube and the second transfer switching tube are in a series connection structure, and at least one of the first transfer switching tube and the second transfer switching tube is ensured to be in an off state in a stable stage by utilizing a voltage drop when current flows through the switching tubes, so that the situation that the gate driving unit cannot normally work due to the fact that a clock signal is mutually pulled with a second low level through the first transfer switching tube, the second transfer switching tube and the eighth switching tube is prevented. Similarly, the seventh switch tube, the eighth viewing switch tube, the ninth switch tube and the tenth switch tube are respectively in a series structure, and the first node in the pre-charging stage is prevented from electric leakage. The seventeenth switching tube and the eighteenth switching tube, the nineteenth switching tube and the twentieth switching tube respectively adopt a series structure, so that the second node or the third node is pulled down to a second low level due to electric leakage in a stable stage, and the pull-down stabilizing module stops working.

Optionally, the gate driving unit provided by the present invention utilizes the eighth switching tube and the tenth switching tube in the seventh to tenth switching tubes for pulling down the voltage of the first node to pull down the transmission signal, so as to reduce components and parts, thereby reducing the layout structure.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a schematic structural view showing a display device according to an embodiment of the present invention;

fig. 2 illustrates a package structure diagram of the gate driving unit of fig. 1;

FIG. 3 is a schematic diagram of the structure of the gate driving circuit of FIG. 1;

FIG. 4 shows a timing diagram of the gate driving circuit of FIG. 3;

fig. 5 is a circuit configuration diagram illustrating a gate driving unit of fig. 1;

FIG. 6 shows a timing diagram of the gate driving unit in FIG. 5;

fig. 7a to 7c are waveform diagrams illustrating output waveforms of four stages of gate driving units before and after the gate driving circuit according to the embodiment of the present invention at normal temperature;

fig. 8a to 8c are waveform diagrams illustrating output waveforms of four stages of gate driving units before and after a gate driving circuit at a low temperature according to an embodiment of the present invention;

fig. 9a to 9c are waveform diagrams illustrating output waveforms of four stages of gate driving units before and after the gate driving circuit according to the embodiment of the present invention at a high temperature.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

Moreover, it should be further noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1 shows a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 1, in this embodiment, a display device 100 includes a display panel 110, a gate driving circuit 120, and a data driving circuit (not shown) for providing a plurality of gray scale data, wherein the gate driving circuit 120 may be integrated on the same substrate as the display panel 110 to form an integrated gate driving circuit structure.

The display panel 110 includes pixel units (not shown) arranged in a row array, m scan lines for transmitting gate driving signals, and n data lines for transmitting gray scale data, where m and n are non-zero integers.

The gate driving circuit 120 includes a plurality of stages of gate driving units 130, and each stage of gate driving unit 130 outputs a corresponding gate driving signal through a corresponding scan line. In this embodiment, each stage of the gate driving unit 130 in the gate driving circuit 120 is connected to a corresponding one of the scan lines, and provides the gate driving signals G1 to Gm in response to the first and second pre-charge signals, so as to turn on the thin film transistors (not shown) in the pixel units of each row by row.

Fig. 2 shows a package diagram of the gate driving unit of fig. 1. The gate driving unit 130 is packaged to form a Stage block, and the Stage block includes at least a clock terminal CLK for receiving a clock signal, and input terminals for receiving the first timing signal V1, the second timing signal V2, the first low level VGL, and the second low level VSQ, and further includes an input terminal Gn-2 for receiving the first precharge signal, an input terminal Zn-2 for receiving the second precharge signal, an input terminal Zn +2 for receiving the pull-down signal, and output terminals for transmitting the gate driving signal Gn and the transfer signal Zn.

Fig. 3 shows a schematic structural diagram of the gate driving circuit in fig. 2. The pin position of each gate driving unit in fig. 3 is the same as that in the package diagram of the gate driving unit in fig. 4, and the pin name is omitted here.

As shown in fig. 2, two sides of each gate driving unit stage1204 are taken as an example, which introduces the principle of the left first stage gate driving unit stage1 to the first two-zero four-stage gate driving unit stage 1204.

Each stage of gate driving unit receives the first timing signal V1, the second timing signal V2, the first low level VGL, and the second low level VSQ.

In one possible embodiment, the voltage value of the first low level VGL is smaller than that of the second low level VSQ, for example, the voltage value of the first low level VGL is-6V, and the voltage value of the second low level VSQ is-11V.

The first pre-charge signal and the second pre-charge signal of the first stage gate driving unit stage1 are both a first start pulse signal STV1A, the first pre-charge signal and the second pre-charge signal of the second stage gate driving unit stage2 are both a second start pulse signal STV1B, and the pre-charge signals of the remaining gate driving units 130 of each stage are both a gate driving signal Gn-2 and a transfer signal Zn-2 output by the gate driving units of the first two stages of the gate driving unit, wherein the gate driving signal Gn-2 is the first pre-charge signal, and the transfer signal Zn-2 is the second pre-charge signal.

The pull-down signals of the gate driving unit of the second last stage and the gate driving unit of the first last stage are the third start pulse signal STV2, and the pull-down signals of the remaining gate driving units of each stage are the transfer signals Zn +2 output by the gate driving units of the last two stages of the gate driving units.

The clock terminal CLK of the first stage gate driving unit stage1 receives the first clock signal CLK1, the clock terminal CLK of the second stage gate driving unit stage2 receives the second clock signal CLK2, the clock terminal CLK of the third stage gate driving unit stage3 receives the third clock signal CLK3, the clock terminal CLK of the fourth stage gate driving unit stage4 receives the fourth clock signal CLK4 \8230 \ 8230where \823030wherethe clock terminal CLK of the first zero-two stage gate driving unit stage1201 receives the first clock signal CLK1, the clock terminal CLK of the first zero-two stage gate driving unit stage1202 receives the second clock signal CLK2, the clock terminal CLK of the first zero-two stage gate driving unit stage1203 receives the third clock signal CLK3, and the clock terminal CLK of the first zero-two stage gate driving unit stage1204 receives the fourth clock signal CLK4.

The connection relationship between the first stage gate driving unit stage1 at the right side of the gate driving circuit shown in fig. 3 and the first two-zero-four stage gate driving unit 1204 is similar to that at the left side, and is not repeated herein.

Alternatively, the first start pulse signal STV1A, the second start pulse signal STV1B, the first to fourth clock signals CKL1 to CLK4, the first timing signal V1, the second timing signal V2, and the third start pulse signal STV2 are generated by the timing controller.

Fig. 4 shows a timing diagram of the gate driving circuit of fig. 3. In fig. 4, a first start pulse signal STV1A, a second start pulse signal STV1B, a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, a first timing signal V1, a second timing signal V2, a first low level VGL, a second low level VSQ, and a third start pulse signal STV2 are sequentially arranged from top to bottom.

The first start pulse signal STV1A, the second start pulse signal STV1B, and the first to fourth clock signals CLK1 to CLK4 have a period t0 and a duty ratio of 50%. The second start pulse signal STV1B lags the first start pulse signal STV1A by t0/4, the second clock signal CLK2 lags the first clock signal CLK1 by t0/4, the third clock signal CLK3 lags the second clock signal CLK2 by t0/4, and the fourth clock signal CLK4 lags the third clock signal CLK3 by t0/4. The first timing signal V1 and the second timing signal V2 work alternately every frame, for example, if the first timing signal V1 is at a low level and the second timing signal V2 is at a high level in the current frame, the first timing signal V1 is at a high level and the second timing signal V2 is at a low level in the next frame.

Illustratively, the voltage value is 20V when the clock signal is at a high level, and the voltage value is-6V when the clock signal is at a low level; the voltage value of the first time sequence signal V1 and the second time sequence signal V2 is 20V when the high level is high, and the voltage value of the low level is-11V; the first low level VGL is-6V and the second low level VSQ is-11V.

As shown in fig. 4, a pulse signal is supplied to the gate driving circuit 120 shown in fig. 3, thereby causing the gate driving circuit 120 to output a desired waveform.

Fig. 5 shows a circuit configuration diagram of the gate driving unit of fig. 1. Taking the nth stage gate driving unit as an example, where n is an integer greater than 2, the gate driving unit 130 is connected to the scan lines on the display panel 110, and supplies the gate driving signal Gn through the corresponding scan lines in response to the gate driving signal Gn-2 and the transfer signal Zn-2 output from the nth-2 stage gate driving unit. As shown in fig. 5, the gate driving unit 130 includes an input module 131, an output module 132, and a pull-down stabilizing module 133.

The input module 131 includes a second switch transistor T2 and a third switch transistor T3, control terminals of the second switch transistor T2 and the third switch transistor T3 receive the transfer signal Zn-2 (i.e., a second pre-charge signal) output by the n-2 th-stage gate driving unit, a first terminal of the second switch transistor T2 receives the gate driving signal Gn-2 (i.e., a first pre-charge signal) output by the n-2 th-stage gate driving unit, a second terminal of the second switch transistor T2 is connected to a first terminal of the third switch transistor T3, and a second terminal of the third switch transistor T3 is connected to the first node Q.

The output module 132 provides the gate driving signal Gn and the transfer signal Zn according to the voltage of the first node Q and the clock signal CLK. The output module 132 includes a first switch T1, an output switch T4, a first transfer switch T21, a second transfer switch T22, and a first capacitor C1. The control ends of the first switch transistor T1, the output switch transistor T4, the first transfer switch transistor T21, and the second transfer switch transistor T22 are connected to the first node Q. The first end of the first switch tube T1 is connected to the second end of the second pass switch tube T22, and the second end is connected to the second end of the second switch tube T2. A first end of the output switch tube T4 receives the clock signal CLK, a second end outputs the gate driving signal Gn, and a second end of the fourth switch tube T4 is an output end of the gate driving signal Gn. The first terminal of the first pass switch T21 receives the clock signal CLK, and the second terminal is connected to the first terminal of the second pass switch T22. The second end of the second transfer switch tube T22 outputs a transfer signal Zn, and the second end of the twenty-second switch tube T22 is an output end of the transfer signal Zn. The first end of the first capacitor C1 is connected to the control end of the output switch tube T4, and the second end is connected to the second end of the output switch tube T4.

The first capacitor C1 is a parasitic capacitor between the control end and the second end of the output switch tube T4. It should be understood that, in order to improve the coupling effect of the capacitor, and thus improve the effect of pulling up the voltage at the first node Q, a separate storage capacitor may be disposed between the control terminal and the second terminal of the output switch tube T4, and the first capacitor C1 is the sum of the parasitic capacitor between the control terminal and the second terminal of the output switch tube T4 and the storage capacitor.

When the first node Q is at a high level, the transfer signal Zn charges the intermediate node between the second switching tube T2 and the third switching tube T3 through the first switching tube T1 to raise the voltage of the first end of the third switching tube T3, so as to prevent the first node Q from leaking through the third switching tube T3 to cause the incomplete conduction of the output switching tube T4, the first transfer switching tube T21 and the second transfer switching tube T22, thereby affecting the output waveforms of the gate driving signal Gn and the transfer signal Zn, and effectively improving the stability of the gate driving unit 130 during operation.

The pull-down stabilizing module 133 is connected to the output module 132 and the first node Q, and maintains the gate driving signal Gn and the transfer signal Zn at a low level according to the transfer signal Zn +2 of the gate driving unit of the (n + 2) th stage and the voltage of the first node Q.

The pull-down stabilization module 133 includes a first stabilization unit 1331, a second stabilization unit 1332, a stabilization control unit 1333, and a pull-down unit 1334.

The first and

second maintenance units

1331 and 1332 alternately operate according to the active states of the first and second timing signals V1 and V2 to stabilize the gate driving signal Gn and the transfer signal Zn.

The first dimensionally stable unit 1331 includes a thirteenth switching tube T13, a fifteenth switching tube T15, a seventh switching tube T7, an eighth switching tube T8 and an eleventh switching tube T11. The control ends of the thirteenth switching tube T13 and the fifteenth switching tube T15 receive the first timing signal V1; a first end of the thirteenth switching tube T13 is connected to the control end of the fifteenth switching tube T15, and a second end is connected to the second node QB1; a first end of the fifteenth switching tube T15 is connected to the second low level VSQ; the seventh switch tube T7 and the eighth switch tube T8 are connected between the first node Q and the second low level VSQ, and control ends of the seventh switch tube T7 and the eighth switch tube T8 are connected to the second node QB1; the eleventh switching transistor T11 has a control terminal connected to the second node QB1, a first terminal connected to the output terminal of the gate driving signal Gn, and a second terminal connected to the first low level VGL.

The intermediate node of the seventh switch tube T7 and the eighth switch tube T8 is connected to the output end of the transmission signal Zn, so that the seventh switch tube T7 and the eighth switch tube T8 are maintained in an off state when the transmission signal Zn is at a high level, and the output waveform of the gate driving signal Gn and the transmission signal Zn is prevented from being affected by incomplete conduction of the output switch tube T4, the first transmission switch tube T21 and the second transmission switch tube T22 due to leakage of the first node Q.

The second dimensionally stable unit 1332 includes a fourteenth switching tube T14, a sixteenth switching tube T16, a ninth switching tube T9, a tenth switching tube T10 and a twelfth switching tube T12. The control ends of the fourteenth switching tube T14 and the sixteenth switching tube T16 receive the second timing signal V2; a first end of the fourteenth switching tube T14 is connected to the control end of the sixteenth switching tube T16, a second end of the fourteenth switching tube T14 is connected to the third node QB2, and the second end of the fourteenth switching tube T14 is further connected to a second end of the fifteenth switching tube T15; a first end of the sixteenth switching tube T16 is connected to the second low level VSQ, and a second end thereof is connected to the second end of the thirteenth switching tube T13; a ninth switching tube T9 and a tenth switching tube T10 are connected between the first node Q and the second low level VSQ, and control terminals of the ninth switching tube T9 and the tenth switching tube T10 are connected to the third node QB2; the twelfth switching tube has a control terminal connected to the third node QB2, a first terminal connected to the output terminal of the gate driving signal Gn, and a second terminal connected to the first low level VGL.

The intermediate node of the ninth switch tube T9 and the tenth switch tube T10 is connected to the output end of the transmission signal Zn, so that the ninth switch tube T9 and the tenth switch tube T10 are maintained in an off state when the transmission signal Zn is at a high level, and the output switch tube T4, the first transmission switch tube T21 and the second transmission switch tube T22 are prevented from being incompletely turned on due to leakage of the first node Q, thereby affecting the output waveforms of the gate driving signal Gn and the transmission signal Zn.

The stability maintaining control unit 1333 includes seventeenth to twentieth switching tubes T17 to T20. The nineteenth and twentieth switching tubes T19 and T20 are connected between the second node QB1 and the second low level VSQ, and control terminals of the nineteenth and twentieth switching tubes T19 and T20 are connected to the first node Q. The seventeenth switching tube T17 and the eighteenth switching tube T18 are connected between the third node QB2 and the second low level VSQ, and control terminals of the seventeenth switching tube T17 and the eighteenth switching tube T18 are connected to the first node Q.

The pull-down unit discharges the first node Q according to a transfer signal Zn +2 (i.e., a pull-down signal) output from the (n + 2) th stage gate driving unit. The pull-down unit includes a fifth switching tube T5 and a sixth switching tube T6. Control ends of a fifth switching tube T5 and a sixth switching tube T6 receive the transmission signal Zn +2 output by the (n + 2) th-stage gate driving unit, a first end of the fifth switching tube T5 is connected to the first node Q, a second end of the fifth switching tube T5 is connected to the second end of the first switching tube T1, a first end of the sixth switching tube T6 is connected to the second end of the fifth switching tube T5, and a second end of the sixth switching tube T6 is connected to the first low level VGL.

When the first node Q is at a high level, the transmission signal Zn charges the intermediate node between the fifth switching tube T5 and the sixth switching tube T6 through the first switching tube T1 to raise the voltage of the second end of the fifth switching tube T5, so as to ensure that Vgs of the fifth switching tube T5 is less than 0, maintain the off state of the fifth switching tube T5, prevent the first node Q from leaking current through the fifth switching tube T5, cause the incomplete conduction of the output switching tube T4, the first transmission switching tube T21 and the second transmission switching tube T22, and influence the output waveforms of the gate driving signal Gn and the transmission signal Zn, thereby further improving the stability of the gate driving unit 130 during operation.

Fig. 6 shows a timing diagram of the gate driving unit in fig. 5. In fig. 6, the sequence from top to bottom is: a transfer signal Zn-2 of the nth-2 stage gate driving unit, a gate driving signal Gn-2 of the nth-2 stage gate driving unit, a clock signal CLK, a transfer signal Zn +2 of the (n + 2) th stage gate driving unit, a first node Q, a second node QB1, a third node QB2, a gate driving signal Gn, and a transfer signal Zn. The working process of each stage of the grid electrode driving unit comprises a pre-charging stage, a pull-up stage and a stabilizing stage. An embodiment of the gate driving unit of the present invention will be described in detail with reference to fig. 5 and 6.

In the precharge phase, i.e., the phases T1 to T2, the transmission signal Zn-2 of the nth-2 stage gate driving unit is inverted from the low level to the high level, the second switching tube T2 and the third switching tube T3 are turned on, and at the same time, the gate driving signal Gn-2 of the nth-2 stage gate driving unit is inverted from the low level to the high level to precharge the first node Q through the second switching tube T2 and the third switching tube T3, the voltage of the first node Q is raised, the nineteenth switching tube T19 and the twentieth switching tube T20 are turned on, the second node QB1 is pulled down to the second low level VSQ, the seventeenth switching tube T17 and the eighteenth switching tube T18 are turned on, the voltage of the third node QB2 is pulled down to the second low level VSQ, and the pull-down stabilizing module 133 stops working.

In a bootstrap phase, namely, in a phase from T2 to T3, the output switch tube T4, the first transfer switch tube T21 and the second transfer switch tube T22 are already turned on through the precharge phase, the clock signal CLK is inverted from a low level to a high level, the output switch tube T4 outputs the gate driving signal Gn, the first transfer switch tube T21 and the second transfer switch tube T22 output the transfer signal Zn, and simultaneously the voltage of the first node Q is increased by the bootstrap action of the first capacitor C1, so that the output switch tube T4, the first transfer switch tube T21 and the second transfer switch tube T22 are ensured to be fully turned on in the bootstrap phase.

Further, the first switch tube T1 is also turned on through the precharge stage, and the first end of the third switch tube T3 and the second end of the fifth switch tube T5 are charged through the first switch tube T1 when the transmission signal Zn is turned to the high level to raise the voltages thereof, respectively, thereby ensuring that the third switch tube T3 and the fifth switch tube T5 are completely turned off, and effectively avoiding the occurrence of the situation that the output switch tube T4 cannot be sufficiently turned on due to the leakage of the first node Q, thereby affecting the waveform of the gate driving signal Gn.

Further, in the charging phase, the voltages of the second node QB1 and the third node QB2 are both pulled down to the second low level VSQ, and the second terminals of the eighth switch tube T8 and the tenth switch tube T10 are also connected to the second low level VSQ, so that the Vgs is very easy to be turned on and the leakage of the first node Q is caused, therefore, the first terminals of the eighth switch tube T8 and the tenth switch tube T10 are connected to the second terminal of the second transfer switch tube T22, and the voltages of the eighth switch tube T8 and the tenth switch tube T10 are raised by the transfer signal Zn to maintain the turn-off states of the seventh switch tube T7 to the tenth switch tube T10, thereby preventing the leakage of the first node Q.

In a stable stage, that is, after time T3, the transmission signal Zn +2 output by the n +2 th stage gate driving unit is inverted from a low level to a high level, the fifth switching tube T5 and the sixth switching tube T6 are turned on, the voltage of the first node Q is pulled down to a first low level VGL, the seventeenth switching tube T17 to the twentieth switching tube T20 are turned off, the voltages of the second node QB1 and the third node QB2 are not pulled down to a second low level VSQ, and assuming that the current frame of the first timing signal V1 is a high level and the second timing signal V2 is a low level, the thirteenth switching tube T13 is turned on to charge the second node QB1, and meanwhile, the seventh switching tube T7 and the eighth switching tube T8 are turned on, the voltage of the first node Q is further pulled down to the second low level VSQ, so as to completely turn off the output switching tube T4, the first transmission switching tube T21 and the second transmission switching tube T22; further, the eighth switch transistor T8 is turned on to pull down the transmission signal Zn to the second low level VSQ, and the eleventh switch transistor T11 is turned on to pull down the gate driving signal Gn to the first low level VGL, so as to maintain the stability of the output signal and avoid mutual interference of the cascaded gate driving units.

Further, when a voltage drop occurs when a current flows through the switching tubes, voltages of the first end and the second end of the first transfer switching tube T21 and the second end of the second transfer switching tube T22 are different, a voltage of the second end of the second transfer switching tube T22 is a second low level VSQ, the control ends of the first transfer switching tube T21 and the second transfer switching tube T22 are both connected to the first node Q, and the voltages are the second low level VSQ, so that it can be ensured that a Vgs of at least one of the first transfer switching tube T21 and the second transfer switching tube T22 is less than 0 in a stable stage, and the switching-off state is in an off state, thereby effectively reducing a probability that the first transfer switching tube T21 and the second transfer switching tube T22 are both turned on, and preventing the clock signal CLK from being pulled by the first transfer switching tube T21, the second transfer switching tube T22, the eighth switching tube T8 and the second low level VSQ, and causing the gate driving unit to fail to operate normally.

Similarly, the seventeenth switch tube T17 and the eighteenth switch tube T18 are connected in series, and the nineteenth switch tube T19 and the twentieth switch tube T20 are connected in series, so that the second node QB1 and/or the third node QB2 in the stable stage can be effectively prevented from being pulled down to the second low level VSQ, and the stable effect is improved.

Fig. 7a to 7c are waveform diagrams showing output waveforms of four stages of gate driving units before and after the gate driving circuit of the embodiment of the present invention at normal temperature.

Fig. 7a shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 27 ℃ under a bias voltage of 0V, fig. 7b shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 27 ℃ under a bias voltage of-4V, and fig. 7c shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 27 ℃ under a bias voltage of 5V. The left graph of each drawing is the output waveform of the front four-level gate driving unit, and the right graph is the output waveform of the rear four-level gate driving unit.

Therefore, under the conditions of normal temperature and different bias voltages, the gate driving circuit provided by the embodiment of the invention effectively prevents the first node Q from leaking electricity through the switching tube connected with the first node Q, and the gate driving signals have better output waveforms, so that the stability of the gate driving circuit is effectively improved.

Fig. 8a to 8c are waveform diagrams illustrating output waveforms of four stages of gate driving units before and after the gate driving circuit according to the embodiment of the present invention at a low temperature.

Fig. 8a shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 0 ℃ under a bias voltage of 0V, fig. 8b shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 0 ℃ under a bias voltage of-4V, and fig. 8c shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 0 ℃ under a bias voltage of 5V. The left graph of each drawing is the output waveform of the front four-level gate driving unit, and the right graph is the output waveform of the rear four-level gate driving unit.

Therefore, under the conditions of low temperature and different bias voltages, the gate driving circuit provided by the embodiment of the invention effectively prevents the first node Q from leaking electricity through the switching tube connected with the first node Q, and the gate driving signals have better output waveforms, so that the stability of the gate driving circuit is effectively improved.

Fig. 9a shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 70 ℃ under a bias voltage of 0V, fig. 9b shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 70 ℃ under a bias voltage of-5V, and fig. 9c shows output waveforms of gate driving units of four stages before and after the gate driving circuit at 70 ℃ under a bias voltage of 2V. The left graph of each drawing is the output waveform of the front four-level gate driving unit, and the right graph is the output waveform of the rear four-level gate driving unit.

Therefore, under the conditions of high temperature and different bias voltages, the gate driving circuit provided by the embodiment of the invention effectively prevents the first node Q from leaking electricity through the switching tube connected with the first node Q, the gate driving signals all have better output waveforms, and the stability of the gate driving circuit is effectively improved.

In summary, in the gate driving unit provided by the present invention, in the bootstrap phase, according to the voltage of the first node, the transfer signal is respectively charged to the middle nodes of the second switching tube and the third switching tube, and the middle nodes of the fifth switching tube and the sixth switching tube through the first switching tube to raise the node voltage, so as to ensure that the off states of the third switching tube and the fifth switching tube are maintained under the conditions of different temperatures and different bias voltages, and effectively avoid the phenomenon of unstable waveform of the output signal due to the leakage of the first node in the bootstrap phase, thereby improving the working stability of the gate driving unit and the adaptability to different application scenarios at different temperatures.

Optionally, the first transfer switching tube and the second transfer switching tube are in a series connection structure, and at least one of the first transfer switching tube and the second transfer switching tube is ensured to be in an off state in a stable stage by utilizing a voltage drop when current flows through the switching tubes, so that the situation that the gate driving unit cannot normally work due to the fact that a clock signal is mutually pulled with a second low level through the first transfer switching tube, the second transfer switching tube and the eighth switching tube is prevented. Similarly, the seventh switch tube and the eighth switch tube, and the ninth switch tube and the tenth switch tube respectively adopt a series structure, so that the first node in the pre-charging stage is prevented from electric leakage. The seventeenth switching tube and the eighteenth switching tube, the nineteenth switching tube and the twentieth switching tube respectively adopt a series structure, so that the second node or the third node is pulled down to a second low level due to electric leakage in a stable stage, and the pull-down stabilizing module stops working.

Optionally, the gate driving unit provided by the invention utilizes the eighth switching tube and the tenth switching tube in the seventh to tenth switching tubes for pulling down the voltage of the first node to pull down the transmission signal, so as to reduce components, thereby reducing the layout structure and being beneficial to reducing the circuit cost.

It should be noted that the words "during", "when" and "when 8230; \8230when" as used herein in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a start action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the start action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

In accordance with embodiments of the present invention, the foregoing examples are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A gate driving unit for driving a plurality of corresponding scan lines on a display panel, the gate driving unit comprising:

the input module is connected with the first node and charges the first node according to a pre-charging signal;

the output module is connected with the first node and provides a gate driving signal and a transmission signal according to the voltage of the first node and a clock signal; and

the pull-down stabilizing module is connected with the output module and the first node and is used for maintaining the grid driving signal at a low level under the control of a pull-down signal; the pull-down stabilizing module comprises a first stabilizing unit and a second stabilizing unit, wherein the first stabilizing unit and the second stabilizing unit alternately work according to the effective states of a first time sequence signal and a second time sequence signal so as to maintain the gate driving signal and the transfer signal at a first low level; a stability maintenance control unit configured to turn off the first and second stability maintenance units when the first node is at a high level; and a pull-down unit discharging the first node according to a pull-down signal; the first and second stabilizing units are further configured to pull down a voltage of the first node to a second low level after the pull-down unit discharges the first node;

the output module comprises a first switch tube, and the first switch tube is used for performing feedback charging on the input module and the pull-down stabilizing module according to the transfer signal under the control of the voltage of the first node in a bootstrap phase so as to maintain the first node at a high potential.

2. The gate driving unit of claim 1, the output module comprising:

the control end of the output switch tube is connected to the first node, and after the first end receives the clock signal, the second end provides the grid driving signal according to the clock signal;

a first pass switch, a control terminal of the first pass switch is connected to the first node, and a first terminal of the first pass switch receives the clock signal;

a second pass switch, a control end of the second pass switch is connected to the first node, a first end of the second pass switch is connected to a second end of the first pass switch, and the second end of the second pass switch provides the pass signal;

and a first end of the first capacitor is connected with the control end of the output switch tube, and a second end of the first capacitor is connected with the second end of the output switch tube.

3. The gate driving unit of claim 1, the input module comprising:

a control end of the second switch tube receives the first pre-charging signal, and a second end of the second switch tube receives the second pre-charging signal;

a control end of the third switching tube receives the first pre-charge signal, a first end of the third switching tube is connected with a second end of the second switching tube, and the second end of the third switching tube is connected to the first node;

the first switch tube is used for providing the transmission signal to an intermediate node of the second switch tube and the third switch tube when the first node is in a high level.

4. The gate driving unit of claim 1, the first dimensionally stable cell comprising:

a thirteenth switching tube, wherein a control end and a first end of the thirteenth switching tube receive the first timing signal, and a second end of the thirteenth switching tube is connected to the second node;

a fifteenth switching tube, a control end of which receives the first timing signal, a first end of which is connected to the third node, and a second end of which is connected to the second low level;

a seventh switching tube and an eighth switching tube connected between the first node and the second low level, wherein control ends of the seventh switching tube and the eighth switching tube are connected to the second node; and the number of the first and second groups,

a control end of the eleventh switching tube is connected to the second node, a first end of the eleventh switching tube is connected with an output end of the gate driving signal, and a second end of the eleventh switching tube is connected to a first low level;

and the intermediate node of the seventh switching tube and the eighth switching tube is connected with the output end of the transmission signal, so that the switching-off state is maintained when the transmission signal is in a high level.

5. The gate driving unit of claim 1, the second dimension stabilizing unit comprising:

a fourteenth switching tube, a control end and a first end of which receive the second timing signal, and a second end of which is connected to a third node;

a sixteenth switching tube, a control end of the sixteenth switching tube receiving the second timing signal, a first end of the sixteenth switching tube being connected to the second node, and a second end of the sixteenth switching tube being connected to the second low level;

a ninth switching tube and a tenth switching tube connected between the first node and the second low level, wherein control ends of the ninth switching tube and the tenth switching tube are connected to the third node; and

a twelfth switching tube, a control end of which is connected to the third node, a first end of which is connected to the output end of the gate driving signal, and a second end of which is connected to the first low level;

the intermediate node of the ninth switching tube and the tenth switching tube is connected with the output end of the transmission signal, so that the off state is maintained when the transmission signal is at a high level.

6. The gate driving unit of claim 1, the stability-maintaining control unit comprising:

nineteenth and twentieth switching tubes connected between a second node and the second low level, control ends of the nineteenth and twentieth switching tubes being connected to the first node;

seventeenth switching tube and eighteenth switching tube connected between a third node and the second low level, wherein control ends of the seventeenth switching tube and the eighteenth switching tube are connected to the first node.

7. The gate driving unit of claim 1, the pull-down unit comprising:

a control end of the fifth switching tube receives a pull-down signal, and a first end of the fifth switching tube is connected to the first node;

a control end of the sixth switching tube receives the pull-down signal, a first end of the sixth switching tube is connected with a second end of the fifth switching tube, and a second end of the sixth switching tube is connected to a first low level; wherein, the first and the second end of the pipe are connected with each other,

the first switch tube is used for providing the transmission signal to an intermediate node of the fifth switch tube and the sixth switch tube when the first node is at a high level.

8. A gate driving circuit comprising at least one stage of the gate driving unit according to any one of claims 1 to 7.

9. A display device, comprising:

a gate drive circuit as claimed in claim 8, for providing a plurality of gate drive signals;

a data driving circuit for providing a plurality of gray scale data; and

a display panel including a plurality of pixel units arranged in an array, and a plurality of scan lines and a plurality of data lines,

the display panel receives the gate driving signals through the scanning lines to select the pixel units according to lines, and receives the gray scale data through the data lines according to columns to provide the gray scale data for the selected pixel units to realize image display.