CN109272960A - Gate driving circuit and display device - Google Patents
Gate driving circuit and display device Download PDFInfo
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- CN109272960A CN109272960A CN201811345191.XA CN201811345191A CN109272960A CN 109272960 A CN109272960 A CN 109272960A CN 201811345191 A CN201811345191 A CN 201811345191A CN 109272960 A CN109272960 A CN 109272960A
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- 241001269238 Data Species 0.000 claims description 2
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- 239000004973 liquid crystal related substance Substances 0.000 description 14
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Physics & Mathematics (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
This application discloses a kind of gate driving circuits, including cascade multiple drive element of the grid, it is characterised in that, multiple drive element of the grid respectively include: input module, it is connected with first node, according to the first enabling signal and the second enabling signal, charges to first node；First output module is connected in first node with input module, generates the same level gate drive signal according to the first clock signal, and provide the same level gate drive signal in output end；Second output module is connected in first node with input module, generates the same level transmitting signal according to the first clock signal；First node is pulled down to low level signal under the control of second clock signal by the first pull-down module；And the same level grid signal is maintained at low level signal under the control of the first clock signal and second clock signal by stable module, which may be implemented narrow frame and low-power consumption display device, and reduce the generation of band phenomenon.
Description
Technical field
The present invention relates to field of display technology, relate more specifically to gate driving circuit and display device.
Background technique
Liquid crystal display device is change the phenomenon that being changed under the action of electric field using the orientation of liquid crystal molecule
The display device of light source light transmittance.Due to having the advantages that display is high-quality, small in size and low in energy consumption, liquid crystal display device is
It is widely used in the mobile terminal of such as mobile phone and the large scale display panel of such as flat panel TV.Liquid on existing market
Crystal display is largely projection-type liquid crystal display comprising liquid crystal display panel and backlight module (backlight module).
The working principle of liquid crystal display panel is liquid crystal molecule to be placed among the parallel glass substrate of two panels, and apply on two panels glass substrate
Add driving voltage to control the direction of rotation of liquid crystal molecule, generation picture is modulated to the luminous of backlight module.
The development of liquid crystal display device in recent years presents the development trend of high integration, low cost, integrative display
Driving is increasingly becoming the research hotspot of flat panel display.So-called integrative display driving circuit refers to gate driving circuit and source
The peripheral circuits such as pole driving circuit using switching tube (Thin Film Transistor, TFT) realize and with pixel switch pipe one
It rises and is made in TFT substrate.It is compared with traditional circuit (IC) driving method, uses the method for integrated gate driving not only can be with
The quantity and its press seal program of reduction peripheral driver chip reduce cost, and make display periphery more slim, so that aobvious
Show that device mould group is more compact, mechanically and electrically reliability is enhanced.
The basic functional principle of liquid crystal display panel and driving circuit are as follows: gate driving circuit is upper by what is be electrically connected with grid line
Pull transistor sends out gate drive signal to grid line, sequentially opens the TFT of every a line, then simultaneously by source electrode drive circuit
The pixel unit of one full line is charged to respectively required voltage, to show different grayscale.I.e. first by the grid of the first row
Driving circuit, which passes through to pull up transistor, opens the thin film transistor (TFT) of the first row, then by source electrode drive circuit to the picture of the first row
Plain unit charges.When the pixel unit of the first row is charged, gate driving circuit just closes the row thin film transistor (TFT), so
The gate driving circuit of the second row is pulled up transistor by it and opens the thin film transistor (TFT) of the second row afterwards, then by source drive electricity
It charges to the pixel unit of the second row on road.So sequentially go down, when the pixel unit for last line of having substituted the bad for the good, just again
It charges to the pixel unit of the first row.
But for large-sized liquid crystal display device, the load of gate driving circuit driving is very big, and to display
Uniformity requirements it is higher, the gate drive signal for requiring gate driving circuit output voltage values larger and stable in this way is existing
Technology is generally solved the problem above-mentioned using the number and size of the switch element, capacitor that increase in gate driving circuit, but
It is the narrow frame design that the above method is unfavorable for liquid crystal display device, and power consumption is big.
Therefore, it is necessary to provide improved technical solution to overcome the above technical problem existing in the prior art.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of gate driving circuit and display device, it can be in output electricity
While pressure is worth larger and stable gate drive signal, be conducive to narrow frame design, and small power consumption.
A kind of gate driving circuit, including cascade multiple drive element of the grid, institute are provided according to an aspect of the present invention
State multiple drive element of the grid respectively include: input module is connected with first node, opens according to the first enabling signal and second
Dynamic signal, charges to first node；First output module is connected in the first node with the input module, according to
First clock signal generates the same level gate drive signal, and provides the same level gate drive signal in output end；Second is defeated
Module out is connected in the first node with the input module, generates the same level transmitting signal according to the first clock signal；First
Pull-down module is connected with the first node, and the first node is pulled down to low electricity under the control of second clock signal
Ordinary mail number；And stable module, it is connected with the first node and output end, in first clock signal and described second
Under the control of clock signal, the same level grid signal is maintained at the low level signal.
Preferably, the multiple drive element of the grid includes the starting grade gate driving list that grade is associated in the first order and the second level
Multiple first intergrade drive element of the grid except the first and described starting grade drive element of the grid, each starting grade grid
The first enabling signal and the second enabling signal of pole driving unit are outside the outside of the gate driving circuit provides first
Enabling signal；First enabling signal of each first intergrade drive element of the grid is to be separated by the prime gate driving of level-one
The same level gate drive signal that unit provides, second enabling signal are to be separated by the prime drive element of the grid of level-one to mention
The described the same level supplied transmits signal.
Preferably, the input module also receives third enabling signal and the 4th enabling signal, is started according to the third
Signal and the 4th enabling signal carry out charge and discharge to the first node.
Preferably, the multiple drive element of the grid includes the termination grade grid that grade is associated in afterbody and penultimate stage
Driving unit and the multiple second intergrade drive element of the grid terminated except grade drive element of the grid, each end
Only the third enabling signal and the 4th enabling signal of grade drive element of the grid are respectively that the external of the gate driving circuit provides
The second external start signal；The third enabling signal of each second intergrade drive element of the grid is after being separated by level-one
The same level gate drive signal that grade drive element of the grid provides, the 4th enabling signal is the rear class grid for being separated by level-one
Described the same level that driving unit provides transmits signal.
Preferably, the stable module includes: the first stable module, is used for described according to first clock signal
Grade grid signal is maintained at the low level signal；Second stable module is used for described according to the second clock signal
Grade grid signal be maintained at the low level signal, wherein the drive element of the grid work when, first stable module and
Second stable module is alternately opened.
Preferably, the input module includes: first switch tube, and control terminal receives second enabling signal, and first is logical
Terminal receives first enabling signal, and alternate path end is connect with the first node.
Preferably, first output module includes: second switch, and control terminal is connect with the first node, and first
Path terminal is for receiving first clock signal, and alternate path end is for generating the same level gate drive signal；First capacitor, even
It is connected between the control terminal of the second switch and alternate path end.
Preferably, second output module includes: that sixteenmo closes pipe, and control terminal is connect with the first node, the
One path terminal is for receiving first clock signal, and alternate path end is for generating the same level transmitting signal.
Preferably, first pull-down module includes: third switching tube, and control terminal is for receiving the second clock letter
Number, the first path terminal is connect with the first node, and alternate path end is for receiving the low level signal.
Preferably, second pull-down module includes: the 4th switching tube, and control terminal is connected to the first node, and first
Path terminal is connected to second node for receiving the low level signal, alternate path end and the stable module；5th switch
Pipe, control terminal are connected to first node, and the first path terminal is for receiving the low level signal, alternate path end and the stabilization
Module is connected to third node.
Preferably, first stable module includes: the 6th switching tube, and control terminal and the first path terminal are shorted to receive
The first clock signal is stated, alternate path end is connected to second node；8th switching tube, control terminal are connected to the second node,
First path terminal is connect with the first node, and alternate path end is for receiving the low level signal；9th switching tube, control
End is connected to the second node, and the first path terminal is connect with the same level gate drive signal output end, and alternate path end is for connecing
Receive the low level signal；Tenth switching tube, control terminal to the second node, the first path terminal and the same level transmitting signal output
End connection, alternate path end is for receiving the low level signal.
Preferably, second stable module includes: the 11st switching tube, and control terminal and the first path terminal are shorted to receive
The second clock signal, alternate path end are connected to third node；13rd switching tube, control terminal are connected to the third section
Point, the first path terminal are connect with the first node, and alternate path end is for receiving the low level signal；14th switch
Pipe, control terminal are connected to the third node, and the first path terminal is connect with the same level gate drive signal output end, alternate path end
For receiving the low level signal；15th switching tube, control terminal to the third node, the first path terminal and the same level are transmitted
Signal output end connection, alternate path end is for receiving the low level signal.
Preferably, the stable module further include: the 7th switching tube, control terminal reception first clock signal, first
For path terminal for receiving the low level signal, alternate path end is connected to the third node；12nd switching tube, control terminal
Receive the second clock signal, for the first path terminal for receiving the low level signal, alternate path end is connected to described the
Two nodes；Wherein, when first clock signal is effective, the low level signal is provided to by the 7th switching tube conducting
When the third node, the second clock signal are effective, the 12nd switching tube conducting provides the low level signal
To the second node.
According to another aspect of the present invention ,-kind of display device is provided characterized by comprising above-mentioned gate driving
Circuit, for providing multiple gate drive signals；Data drive circuit, for providing multiple luma datas；And display panel,
The display panel includes the multiple pixel units and a plurality of grid line and multiple data lines for being arranged in array, the display surface
Plate receives the multiple gate drive signal via a plurality of grid line, so that the multiple pixel unit is selected by row, with
And the multiple luma data is received by column via the multiple data lines, to be supplied to selected pixel unit to realize figure
As display.
Gate driving circuit and display device of the embodiment of the present invention.Wherein, gate driving circuit includes successively cascading
Multiple drive element of the grid, when one of drive element of the grid carry out pixel charging when, only to the picture for being separated by level-one with it
Element is pre-charged, and the quantity of the grid line opened simultaneously is reduced, and reduces the friendship of adjacent drive element of the grid output waveform
The folded period can avoid the phenomenon that band occur in display, promote the display quality of display device.
In a preferred embodiment, drive element of the grid provided by the invention only needs outside two clock signals and one
The enabling signal that portion provides reduces required layout area to reduce the quantity and load of signal line of signal wire, is conducive to narrow
The design of frame, while advantageously reducing the power consumption of circuit.
In a preferred embodiment, the transmitting signal of each drive element of the grid and gate drive signal pass through different ends
Son output reduces influence of the signal transmitting to gate driving, so that the fan-out capability of drive element of the grid is strong.
In a preferred embodiment, provide it is a kind of can bilateral scanning gate driving circuit, there is forward scan and reversed
Both of which is scanned, the use freedom degree of display panel is increased, provides the driving method of elasticity for liquid crystal display panel.
In a preferred embodiment, the first stable module and the second stable module are alternately opened, and stability is good.Similarly,
It can be also effectively reduced using the power consumption of the display device of above-mentioned drive element of the grid.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 shows the framework signal of n-th grade of drive element of the grid in the gate driving circuit of first embodiment of the invention
Figure.
Fig. 2 shows the structural representations of n-th grade of drive element of the grid in the gate driving circuit of first embodiment of the invention
Figure.
Fig. 3 shows the circuit diagram of the drive element of the grid of first embodiment of the invention.
Fig. 4 shows the schematic block diagram of 12 grades of drive element of the grid in the gate driving circuit of the embodiment of the present invention.
Fig. 5 shows the timing diagram of the clock signal and enabling signal of gate driving circuit in Fig. 3.
Fig. 6 shows the working waveform figure of the drive element of the grid of first embodiment of the invention.
Fig. 7 shows the waveform diagram of the gate drive signal of multiple drive element of the grid of first embodiment of the invention.
Fig. 8 shows the circuit diagram of the drive element of the grid of second embodiment of the invention.
Fig. 9 shows the circuit diagram of the drive element of the grid of third embodiment of the invention.
Figure 10 shows the circuit diagram of the drive element of the grid of fourth embodiment of the invention.
Figure 11 shows the circuit diagram of the drive element of the grid of fifth embodiment of the invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.In addition, may not show in figure
Certain well known parts out.
Many specific details of the invention, such as structure, material, size, the processing work of component is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Gate driving circuit (also referred to as shift register) of the invention includes that multistage drive element of the grid (also referred to as shifts
Deposit unit), every level-one drive element of the grid is corresponding with every a line grid line on display panel respectively to be electrically connected, thus will
Gate drive signal is sequentially gradually applied on every a line grid line, and the connection relationship between drive element of the grid will hereinafter
It is described in detail.
Fig. 1 shows the framework signal of n-th grade of drive element of the grid in the gate driving circuit of first embodiment of the invention
Figure.The gate driving circuit of the present embodiment, including multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid is used
A corresponding grid line on driving display panel.As shown in Figure 1, every level-one drive element of the grid all includes prime signal
Input terminal 11, the first clock signal input terminal 12, second clock signal input part 13, low level signal input terminal 14 and the same level letter
Number output end 15.Wherein, prime signal input part 11 is used to receive the same level gate drive signal of previous stage drive element of the grid
And the same level transmits signal.In some embodiments of the invention, prime signal input part 11 is also used for receiving enabling signal.The
One clock signal input terminal 12 and second clock signal input part 13 are for receiving clock signal.Low level signal input terminal 14 is used
In reception low level signal.The same level signal output end 15 is for exporting the same level gate drive signal and the same level transmitting signal, wherein
The same level gate drive signal, which is used to drive, to be used to drive a corresponding grid on display panel with n-th grade of drive element of the grid
Line, the same level transmitting signal are used to control the pre-charge process of next stage drive element of the grid.
Fig. 2 shows the structural representations of n-th grade of drive element of the grid in the gate driving circuit of first embodiment of the invention
Figure.As shown in Fig. 2, drive element of the grid 100 include input module 110, the first output module 120, the second output module 130,
First pull-down module 140, the second pull-down module 150 and stable module 160.
Prime signal input part in the input terminal and Fig. 1 of input module 110 is connected for receiving higher level's driving signal Gn-
2 and higher level transmit signal Zn-2, output end connect with first node Q, is used for according to higher level's driving signal Gn-2 and higher level's transmitting
Signal Zn-2 is pre-charged first node Q.In conjunction with as shown in fig.1, the first output module 120 and first node Q and the
The connection of one clock signal input terminal 12 is to export the clock signal clk 1 received for this according to the control voltage of first node Q
Grade gate drive signal Gn.Second output module 130 is connect with first node Q and the first clock signal input terminal according to first
The clock signal clk 1 received is exported and transmits signal Zn for the same level by the control voltage of node Q.First pull-down module 140 and
Two clock signal input terminals are connected with low level signal input terminal to receive clock signal clk 3 and low level signal VGL respectively,
For low level signal VGL to be provided to first node Q to drag down the electricity of first node Q according to the clock signal clk 3 received
Position.Second pull-down module 150 is connect with first node Q, low level signal input terminal and stable module 160, for according to the
Low level signal VGL is provided to stable module 160 by the control voltage of one node Q.Stable module 160 and the first clock signal are defeated
Enter end, second clock signal input part and the connection of low level signal input terminal, for believing according to clock signal clk 1 and clock
Low level signal VGL is alternately provided to first node Q, the same level gate drive signal output end and the same level transmitting letter by number CLK3
Number output end.
The drive element of the grid of the embodiment of the present invention 3 signal wires that it is only necessary to be connected with main path, are respectively used to connect
2 clock signals and low level signal VGL are received, and 1 signal wire being connected with neighboring gates driving unit, before receiving
Grade gate drive signal Gn-2 and prime transmit signal Zn-2.The clock signal input terminal and clock of adjacent drive element of the grid
The clock signal that signal input part receives is different.For example, first order drive element of the grid receives clock signal clk 1 and clock
Signal CLK3, third level drive element of the grid receive clock signal clk 2 and clock signal clk 4, and so on.
Fig. 3 shows the circuit diagram of the drive element of the grid of first embodiment of the invention.As shown in figure 3, input module
310 include first switch tube T1, and the control terminal of first switch tube T1 receives prime and transmits signal Zn-2, the first path terminal receives
Prime gate drive signal Gn-2, alternate path end are connect with first node Q.
First output module 120 includes second switch T2 and first capacitor C1, the control terminal of second switch T2 and the
One node Q connection, the first path terminal are connect to receive clock signal clk 1 with the first clock signal input terminal, alternate path end with
Output end is connected to export the same level gate drive signal Gn, and first capacitor C1 is connected to the control terminal and second of second switch T2
Between path terminal.
Wherein, first capacitor C1 is the parasitic capacitance between the control terminal and alternate path end of second switch T2.Certainly,
It will be appreciated by those skilled in the art that can also be arranged between the control terminal and alternate path end of second switch T2
Separate storage capacitor, at this point, first capacitor C1 is the parasitic capacitance between the control terminal and alternate path end of second switch T2
The sum of with separate storage capacitor.
Second output module 130 includes that sixteenmo closes pipe T16, and sixteenmo closes the control terminal and first node Q of pipe T16
Connection, the first path terminal are connect to receive clock signal clk 1, alternate path end and output end with the first clock signal input terminal
Connection is to export the same level transmitting signal Zn.
First pull-down module 140 includes third switch transistor T 3, and the control terminal and second clock signal of third switch transistor T 3 are defeated
Enter end connection to receive clock signal clk 3, the first path terminal is connected with first node Q, and alternate path end and low level signal are defeated
Enter end connection to receive low level signal VGL.It should be noted that the structure of the first pull-down module 330 is not limited only to above-mentioned structure,
It is also possible to the structure of other multiple switch pipe combinations, those skilled in the art can select as the case may be.
Second pull-down module 150 includes the 4th and the 5th switch transistor T 4 and T5, the 4th switch transistor T 4 and the 5th switch transistor T 5
Control terminal connect with first node Q, the first path terminal and low level signal of the 4th switch transistor T 4 and the 5th switch transistor T 5 are defeated
Enter end connection to receive low level signal VGL, alternate path end and the stable module of the 4th switch transistor T 4 and the 5th switch transistor T 5
160 are connected to second node QB1 and third node QB2.When first node Q is high potential, the 4th switch transistor T 4 and the 5th is opened
Pipe T5 conducting is closed, low level signal VGL is provided to second node QB1 and third node QB2.
Specifically, stable module 160 includes the first stable module 161 and the second stable module 162.First stable module
161 include the 6th to the tenth switch transistor T 6-T10.The control terminal of 6th switch transistor T 6 and the first path terminal are shorted to receive clock
Signal CLK1, alternate path end are connect with second node QB1.The control terminal of 7th switch transistor T 7 and the first of the 6th switch transistor T 6
Path terminal connection, the first path terminal are connect with low level signal input terminal, and alternate path end is connect with third node QB2.8th
The control terminal of switch transistor T 8 is connect with second node QB1, and the first path terminal is connect with first node Q, alternate path end and low electricity
Flat signal input part connection.The control terminal of 9th switch transistor T 9 is connect with second node QB1, and the first path terminal and the same level grid drive
Dynamic signal output end connection, alternate path end is connect with low level signal input terminal.The control terminal and second of tenth switch transistor T 10
Node QB1 connection, the first path terminal are connect with the same level transmitting signal output end, and alternate path end and low level signal input terminal connect
It connects.
Second stable module 162 includes the 11st to the 15th switch transistor T 11-T15.The control of 11st switch transistor T 11
End and the first path terminal are shorted to receive clock signal clk 3, and alternate path end is connect with third node QB2.12nd switching tube
The control terminal of T12 is connect with the first path terminal of the 11st switch transistor T 11, and the first path terminal and low level signal input terminal connect
It connects, alternate path end is connect with second node QB1.The control terminal of 13rd switch transistor T 13 is connect with third node QB2, and second
Path terminal is connect with low level signal input terminal, and the first path terminal is connect with first node Q.The control of 14th switch transistor T 14
End is connect with third node QB2, and alternate path end is connect with low level signal input terminal, the first path terminal and the same level gate driving
Signal output end connection.The control terminal of 15th switch transistor T 15 is connect with third node QB2, and alternate path end and low level are believed
The connection of number input terminal, the first path terminal are transmitted signal output end with the same level and are connect.
Fig. 4 shows the schematic block diagram of 12 grades of drive element of the grid in the gate driving circuit of the embodiment of the present invention.It is aobvious
Showing device 200 includes on gate driving circuit and display panel 210 including the multiple pixel units for being arranged in array, each pixel
Unit includes pixel electrode and the transistor for the on or off pixel electrode, the transistor are, for example, film crystal
It manages (thin-film transistor, TFT).In display panel 210, it is located at same a line (in " row " such as corresponding diagram
Shown in transverse direction) pixel unit in each transistor grid be connected and to the fringe region of display panel 210 draw
One grid line, to form gate lines G ate1 to Gate12, as shown in Figure 3.
Gate driving circuit according to an embodiment of the present invention is, for example, integrated gate drive circuitry (Gate Driver in
Array is abbreviated as GIA) 220, including successively cascade multiple drive element of the grid.Multiple drive element of the grid respectively with it is aobvious
Show that the grid line on panel 210 is corresponding to be connected.Via grid line by the pixel unit on row selection display panel 210.Via number
Corresponding grayscale signal is provided to realize that image is shown by column according to line.
In a preferred embodiment, the gate driving circuit 220 of the embodiment of the present invention is sided configuration, the multiple grid
Driving unit includes two groups of drive element of the grid, and two groups of drive element of the grid cascade respectively is set to display panel 210
The left and right sides, including first part 220a and second part 220b.First group of drive element of the grid is set to first part 220a
In, second group of drive element of the grid is set in second part 220b.As shown in Figure 1, first group of drive element of the grid Stage1
It is located in first part 220a to Stage12, second group of drive element of the grid Stage1 to Stage12 is located at second part 220b
In.
In preferred embodiment of the present invention, every grid line is charged by two groups of drive element of the grid respectively, such as Fig. 4
Shown, gate lines G ate1 is driven by the grid in the drive element of the grid Stage1 and second part 220b in first part 220a
Moving cell Stage1 charges jointly, can further improve the driving capability of gate driving circuit.
For the drive element of the grid of every level-one, the first clock signal input terminal and second clock signal input part difference
It is connected with multiple clock lines to receive two clock signals in clock signal clk 1-CLK8, such as first order gate driving list
First Stage1 receives clock signal clk 1 and clock signal clk 3, and second level drive element of the grid Stage2 receives clock signal
CLK5 and clock signal clk 7.
When drive element of the grid is first order drive element of the grid and second level drive element of the grid, the gate driving
The prime signal input part of unit is for inputting enabling signal STV1.
When drive element of the grid is the third level any drive element of the grid into n-th grade of drive element of the grid, the grid
The prime signal input part of pole driving unit is electrically connected to the same level signal output end of the i-th -2 grades drive element of the grid.
Gate driving circuit according to this embodiment generates multiple gate drivings using cascade multiple drive element of the grid
Signal selects the pixel unit of corresponding line for being provided to grid line.In sided configuration, which includes using
First part and second part in driving grid line.It is only necessary to 10 signals on main path for multiple drive element of the grid
Line is respectively used to transmission start signal STV1, low level signal VGL and clock signal clk 1 to CLK8.Adjacent grid drives
Relatively narrow layout area is only needed on interconnection path between moving cell, is respectively used to transmission prime signal Qi-2.
In contrast, in the gate driving circuit of the prior art, if using similar sided configuration, multiple grids
Driving unit is respectively necessary for 12 signal wires in main path, be respectively used to transmission start signal STV1, low level signal VGL, when
Clock signal CLK1 to CLK8 and the first stabilization signal V1 and the second stabilization signal V2.It is mutual between adjacent drive element of the grid
Wider layout area is needed on access path, is respectively used to the same level signal Qi-4 of the drive element of the grid of level Four before transmitting.
The gate driving circuit of the gate driving circuit of the embodiment of the present invention compared with the existing technology reduces every level-one grid
The quantity of signal wire needed for the driving circuit of pole, so as to reduce corresponding layout area and load of signal line, so as to
Realize narrow frame, low-power consumption display device.
It should be noted that although describing the gate driving circuit using sided configuration in this embodiment, it is of the invention
It is without being limited thereto.When being applied to the gate driving circuit of one-sided configuration, gate driving circuit of the invention also can reduce adjacent
Drive element of the grid between interconnection path on layout area, reduce the quantity of signal wire, obtain and reduce layout area
Beneficial effect.
Fig. 5 shows the timing diagram of the clock signal and enabling signal of gate driving circuit in Fig. 3.
As shown in figure 5, clock signal clk 1-CLK8 is square-wave signal, clock cycle 8T, duty ratio 1/4, starting
Signal STV1 is single pulse signal, high level lasting time 4T.T is the predetermined clock period, such as clock signal of system is most
Minor clock period or its integral multiple.
It referring to fig. 4, all include being used for transmission starting on the first part of gate driving circuit and the main path of second part
Signal STV1 and clock signal clk 1 to CLK8 signal wire.Failing edge of the clock signal clk 1-CLK4 in enabling signal STV1
Starting, phase successively delay 2T.Clock signal clk 5-CLK8 phase compared with clock signal STV1-STV4 successively delays 1T, when
Phase successively delays 2T between clock signal CLK5-CLK8.
Fig. 6 shows the working waveform figure of the drive element of the grid of first embodiment of the invention, and abscissa indicates time (s),
Ordinate indicates signal level (V).Referring to Fig. 3 and Fig. 6, to the present invention by taking first order drive element of the grid Stage1 as an example
The working principle of the drive element of the grid of first embodiment is described in detail.
As described above, the prime signal input part of first order drive element of the grid Stage1 is for receiving enabling signal
STV1, the first clock signal input terminal, second clock signal input part, low level signal input terminal receive clock signal respectively
CLK1, CLK3 and low level signal VGL.
In the first stage, when enabling signal STV1 becomes high level from low level, first switch tube T1 conducting, first is opened
It closes pipe T1 and enabling signal STV1 is supplied to first node Q, first node Q is pre-charged, the current potential of first node Q is by low
Level becomes high level, the 4th switch transistor T 4 and the 5th switch transistor T 5 is connected, the 4th switch transistor T 4 and the 5th switch transistor T 5 will be low
Level signal VGL is respectively supplied to second node QB1 and third node QB2, by the electricity of second node QB1 and third node QB2
Down for low level, the 8th to the tenth switch transistor T 8-T10 and the 13rd switching tube to the 15th switch transistor T 13-T15 are turned off for position.
In second stage, when clock signal CLK1 is high level by low level raising, by the bootstrapping of first capacitor C1
Effect, the current potential of first node Q continues to increase, because second switch T2 and sixteenmo close pipe T16 in the first stage by
It opens, so it is sufficiently conductive to close pipe T16 in second node second switch T2 and sixteenmo, via second switch T2 and the
Sixteenmo closes pipe T16 and exports the same level gate drive signal Gn and the same level transmitting signal Zn.
It should be noted that in the present invention, control terminal and the alternate path end of second switch T2 can be directly used
Between parasitic capacitance as first capacitor C1, can also be in the control of second switch T2 or in order to promote pull-up effect
Separate storage capacitor is set between end and alternate path end.Wherein, the parasitism electricity of the separate storage capacitor and second switch T2
Hold cylinder barrel in parallel to be equal between the control terminal and alternate path end of second switch T2 as first capacitor C1, i.e. first capacitor C1
Parasitic capacitance and the sum of separate storage capacitor.
In the phase III, when clock signal CLK1 becomes low level, pipe is closed by second switch T2 and sixteenmo
The current potential of first node Q is dragged down output waveform down for low level, while by the coupling of first capacitor C1 by T16.
In fourth stage, when clock signal CLK3 becomes high level from low level, third switch transistor T 3 is connected, and third is opened
It closes pipe T3 and low level signal VGL is supplied to first node Q, by the current potential of first node Q down for low level.Work as clock simultaneously
When signal CLK1 and clock signal clk 3 alternately become high level from low level, second node QB1 and third node QB2 are alternately
High level, the first stable module 161 and the second stable module 162 are alternately opened, so that first node Q, the same level gate driving are believed
The current potential of number output end and the same level transmitting signal output end stabilizes to low level.Specifically, when clock signal CLK1 is high level
When, the 6th switch transistor T 6 and the conducting of the 7th switch transistor T 7, second node QB1 are high level, the 8th to the tenth switch transistor T 8-T10
Low level signal VGL is provided to first node Q, the same level gate drive signal output end and the same level transmitting letter respectively by conducting
Number output end.When clock signal CLK3 is high level, the 11st switch transistor T 11 and the conducting of the 12nd switch transistor T 12, third section
Point QB2 is high level, and low level signal VGL is provided to first segment respectively by the 13rd to the 15th switch transistor T 13-T15 conducting
Point Q, the same level gate drive signal output end and the same level transmit signal output end.
Fig. 7 shows the waveform diagram of the gate drive signal of multiple drive element of the grid of first embodiment of the invention, horizontal seat
Mark indicates time (s), and ordinate indicates signal level (V).
Compared with the gate driving circuit of the prior art, the gate driving circuit of the embodiment of the present invention reduces every level-one grid
The quantity of signal wire needed for the driving circuit of pole, advantageously reduces power consumption.In addition, as shown in curve g1 and curve g2, the present invention
It is only overlapping between the output waveform of next stage drive element of the grid when the gate driving circuit of embodiment charges to pixel
A cycle, thus the phenomenon that advantageously accounting for band.
Fig. 8 shows the circuit diagram of the drive element of the grid of second embodiment of the invention.As shown in figure 8, in the present invention
In second embodiment, the control terminal of the 6th switch transistor T 6 in control module 360 and the first path terminal are shorted to receive first surely
Determine signal V1, the control terminal of the 11st switch transistor T 11 and the first path terminal are shorted to receive the second stabilization signal V2.
In addition, the lower drawing-die of the input module 310 of the present embodiment, the first output module 320, the second output module 330, first
The structure and connection relationship of block 340 and the second pull-down module 350 are identical as first embodiment shown in Fig. 3, no longer superfluous herein
It states.
Fig. 9 shows the circuit diagram of the drive element of the grid of third embodiment of the invention.As shown in figure 9, in this implementation
In example, the control terminal of the third switch transistor T 3 in the first pull-down module 440 receives junior and transmits signal Zn+2, with second embodiment
The drive element of the grid of offer is compared, and the drive element of the grid of the present embodiment can be further reduced the quantity of signal wire, so as to
To reduce corresponding layout area and load of signal line, so as to realize narrow frame, low-power consumption display device.
In addition, input module 410, the first output module 420, the drop-down of the second output module 430, second in the present embodiment
The structure and connection relationship of module 450 and stable module 460 are identical as the second embodiment shown in Fig. 8.
Figure 10 shows the circuit diagram of the drive element of the grid of fourth embodiment of the invention.It is preferably carried out in the present invention
In example, a kind of drive element of the grid that can be used for bilateral scanning is provided, specifically, the input module 510 includes first switch
Pipe T1 and the 17th switch transistor T 17, the control terminal of first switch tube T1 receive prime and transmit signal Zn-2, and the first path terminal receives
Prime gate drive signal Gn-2, alternate path end are connect with first node Q.Under the control terminal of 17th switch transistor T 17 receives
Grade transmitting signal Zn+2, the first path terminal receive junior's gate drive signal Gn+2, and alternate path end is connect with first node Q.
It should be noted that for (n-1)th grade and n-th grade of drive element of the grid, the control terminal of the 17th switch transistor T 17 with
First path terminal is shorted to receive the enabling signal STV2 of external offer.
Figure 11 shows the circuit diagram of the drive element of the grid of fifth embodiment of the invention.It is driven with the grid shown in Figure 10
Moving cell is compared, in the drive element of the grid that fifth embodiment of the invention provides, the 6th switch transistor T 6 in control module 660
Control terminal and the first path terminal are shorted to receive the first stabilization signal V1, the control terminal and the first access of the 11st switch transistor T 11
End is shorted to receive the second stabilization signal V2.
In addition, the lower drawing-die of the input module 610 of the present embodiment, the first output module 620, the second output module 630, first
The structure and connection relationship of block 640 and the second pull-down module 650 are identical as fourth embodiment shown in Fig. 10, no longer superfluous herein
It states.
It should be noted that the first to the 17th switch transistor T 1-T17 can use such as non-crystalline silicon tft, oxide TFT
Or the switch elements such as low temperature polycrystalline silicon N-TFT and realize.Such as in embodiments of the present invention, the first to the 17th switching tube
T1-T17 is N-type TFT, and the first path terminal of each transistor and alternate path end can be interchanged (i.e. drain electrode and
Source electrode can be interchanged), but of the invention it is practiced without limitation to this.
In conclusion gate driving circuit and display device of the embodiment of the present invention.Wherein, gate driving circuit includes
Successively cascade multiple drive element of the grid are only separated by with it when one of drive element of the grid carries out pixel charging
The pixel of level-one is pre-charged, and the quantity of the grid line opened simultaneously is reduced, and reduces adjacent drive element of the grid output
The overlapping period of waveform can avoid the phenomenon that band occur in display, promote the display quality of display device.
Drive element of the grid provided by the invention only needs two clock signals and an external enabling signal provided,
To reduce the quantity and load of signal line of signal wire, required layout area is reduced, is conducive to the design of narrow frame, has simultaneously
Conducive to the power consumption for reducing circuit.
In a preferred embodiment, drive element of the grid provided by the invention only needs outside two clock signals and one
The enabling signal that portion provides reduces required layout area to reduce the quantity and load of signal line of signal wire, is conducive to narrow
The design of frame, while advantageously reducing the power consumption of circuit.In preferred embodiment, the transmitting of each drive element of the grid is believed
Number and gate drive signal exported by different terminal, reduce signal and transmit influence to gate driving, so that grid drives
The fan-out capability of moving cell is strong.
In a preferred embodiment, provide it is a kind of can bilateral scanning gate driving circuit, there is forward scan and reversed
Both of which is scanned, the use freedom degree of display panel is increased, provides the driving method of elasticity for liquid crystal display panel.
In a preferred embodiment, the first stable module and the second stable module are alternately opened, and stability is good.Similarly,
It can be also effectively reduced using the power consumption of the display device of above-mentioned drive element of the grid.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.
Claims (14)
1. a kind of gate driving circuit, including cascade multiple drive element of the grid, which is characterized in that the multiple gate driving
Unit respectively include:
Input module is connected with first node, according to the first enabling signal and the second enabling signal, fills to first node
Electricity；
First output module, is connected in the first node with the input module, generates the same level grid according to the first clock signal
Pole driving signal, and the same level gate drive signal is provided in output end；
Second output module is connected in the first node with the input module, generates the same level according to the first clock signal and passes
Delivery signal；
First pull-down module is connected with the first node, will be under the first node under the control of second clock signal
It is pulled to low level signal；And
Stable module is connected with the first node and output end, believes in first clock signal and the second clock
Number control under, the same level grid signal is maintained at the low level signal.
2. gate driving circuit according to claim 1, which is characterized in that the multiple drive element of the grid includes cascade
Multiple first except the starting grade drive element of the grid and the starting grade drive element of the grid of the first order and the second level
Intergrade drive element of the grid,
The first enabling signal and the second enabling signal of each starting grade drive element of the grid are the gate driving circuit
External the first external start signal provided；
First enabling signal of each first intergrade drive element of the grid is the prime drive element of the grid for being separated by level-one
The same level gate drive signal provided, second enabling signal are to be separated by the prime drive element of the grid of level-one to provide
Described the same level transmits signal.
3. gate driving circuit according to claim 1, which is characterized in that the input module also receives third starting letter
Number and the 4th enabling signal, charge and discharge are carried out to the first node according to the third enabling signal and the 4th enabling signal.
4. gate driving circuit according to claim 3, which is characterized in that the multiple drive element of the grid includes cascade
It is more except afterbody and the termination grade drive element of the grid and the termination grade drive element of the grid of penultimate stage
A second intergrade drive element of the grid,
Each third enabling signal for terminating grade drive element of the grid and the 4th enabling signal are respectively the gate driving
External the second external start signal provided of circuit；
The third enabling signal of each second intergrade drive element of the grid is the rear class drive element of the grid for being separated by level-one
The same level gate drive signal provided, the 4th enabling signal are to be separated by the rear class drive element of the grid of level-one to provide
Described the same level transmits signal.
5. gate driving circuit according to claim 1, which is characterized in that the stable module includes:
First stable module is believed for the same level grid signal to be maintained at the low level according to first clock signal
Number；
Second stable module is believed for the same level grid signal to be maintained at the low level according to the second clock signal
Number,
Wherein, when the drive element of the grid works, first stable module and second stable module are alternately opened.
6. gate driving circuit according to claim 1, which is characterized in that the input module includes:
First switch tube, control terminal reception second enabling signal, the first path terminal reception first enabling signal, second
Path terminal is connect with the first node.
7. gate driving circuit according to claim 1, which is characterized in that first output module includes:
Second switch, control terminal are connect with the first node, and the first path terminal is used to receive first clock signal, the
Two path terminals are for generating the same level gate drive signal；
First capacitor is connected between the control terminal of the second switch and alternate path end.
8. gate driving circuit according to claim 1, which is characterized in that second output module includes:
Sixteenmo closes pipe, and control terminal is connect with the first node, and the first path terminal is used to receive first clock signal,
Alternate path end is for generating the same level transmitting signal.
9. gate driving circuit according to claim 1, which is characterized in that first pull-down module includes:
Third switching tube, for receiving the second clock signal, the first path terminal is connect control terminal with the first node, the
Two path terminals are for receiving the low level signal.
10. gate driving circuit according to claim 1, which is characterized in that second pull-down module includes:
4th switching tube, control terminal are connected to the first node, and the first path terminal is for receiving the low level signal, and second
Path terminal and the stable module are connected to second node；
5th switching tube, control terminal are connected to first node, and the first path terminal is for receiving the low level signal, alternate path
End is connected to third node with the stable module.
11. gate driving circuit according to claim 5, which is characterized in that first stable module includes:
6th switching tube, control terminal and the first path terminal are shorted to receive first clock signal, and alternate path end is connected to
Second node；
8th switching tube, control terminal are connected to the second node, and the first path terminal is connect with the first node, alternate path
End is for receiving the low level signal；
9th switching tube, control terminal are connected to the second node, and the first path terminal and the same level gate drive signal output end connect
It connects, alternate path end is for receiving the low level signal；
Tenth switching tube, control terminal to the second node, the first path terminal are connect with the same level transmitting signal output end, and second is logical
Terminal is for receiving the low level signal.
12. gate driving circuit according to claim 5, which is characterized in that second stable module includes:
11st switching tube, control terminal and the first path terminal are shorted to receive the second clock signal, the connection of alternate path end
To third node；
13rd switching tube, control terminal are connected to the third node, and the first path terminal is connect with the first node, and second is logical
Terminal is for receiving the low level signal；
14th switching tube, control terminal are connected to the third node, the first path terminal and the same level gate drive signal output end
Connection, alternate path end is for receiving the low level signal；
15th switching tube, control terminal to the third node, the first path terminal are connect with the same level transmitting signal output end, and second
Path terminal is for receiving the low level signal.
13. gate driving circuit according to claim 5, which is characterized in that the stable module further include:
7th switching tube, control terminal receive first clock signal, and the first path terminal is used to receive the low level signal, the
Two path terminals are connected to the third node；
12nd switching tube, control terminal receive the second clock signal, and the first path terminal is used to receive the low level signal,
Alternate path end is connected to the second node；
Wherein, when first clock signal is effective, the low level signal is provided to described by the 7th switching tube conducting
Third node,
When the second clock signal is effective, the low level signal is provided to described the by the 12nd switching tube conducting
Two nodes.
14. a kind of display device characterized by comprising
Gate driving circuit according to any one of claim 1 to 13, for providing multiple gate drive signals；
Data drive circuit, for providing multiple luma datas；And
Display panel, the display panel include the multiple pixel units and a plurality of grid line and a plurality of data for being arranged in array
Line,
Wherein, the display panel receives the multiple gate drive signal via a plurality of grid line, thus by row selection
The multiple pixel unit, and the multiple luma data is received by column via the multiple data lines, to be supplied to choosing
Fixed pixel unit is to realize that image is shown.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354309A (en) * | 2020-04-15 | 2020-06-30 | 京东方科技集团股份有限公司 | Display driving module, display driving method and display device |
| CN112908235A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN112908276A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| CN113628596A (en) * | 2021-07-23 | 2021-11-09 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN113741726A (en) * | 2021-07-30 | 2021-12-03 | 惠科股份有限公司 | Drive circuit, four-stage drive circuit and display panel |
| WO2024000328A1 (en) * | 2022-06-29 | 2024-01-04 | 京东方科技集团股份有限公司 | Display driving circuit and display device |
| CN117456924A (en) * | 2023-12-25 | 2024-01-26 | 惠科股份有限公司 | Driving circuit and display device |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226979A (en) * | 2013-02-18 | 2013-07-31 | 合肥京东方光电科技有限公司 | Bidirectional shifting register unit, bidirectional shifting register and display device |
| US20130243150A1 (en) * | 2011-04-21 | 2013-09-19 | Lg Display Co., Ltd. | Shift register |
| CN103680453A (en) * | 2013-12-20 | 2014-03-26 | 深圳市华星光电技术有限公司 | Array substrate row driving circuit |
| CN103996390A (en) * | 2014-05-26 | 2014-08-20 | 昆山龙腾光电有限公司 | Gate driving circuit and display device using same |
| WO2015000187A1 (en) * | 2013-07-03 | 2015-01-08 | 深圳市华星光电技术有限公司 | Array substrate row driving circuit |
| CN104517575A (en) * | 2014-12-15 | 2015-04-15 | 深圳市华星光电技术有限公司 | Shifting register and level-transmission gate drive circuit |
| CN205984242U (en) * | 2016-08-30 | 2017-02-22 | 合肥京东方光电科技有限公司 | Shifting register unit, gate driving circuit and display device |
| CN206864164U (en) * | 2017-11-07 | 2018-01-09 | 深圳市华星光电半导体显示技术有限公司 | GOA circuits |
| CN107622758A (en) * | 2016-07-14 | 2018-01-23 | 三星显示有限公司 | Gate driving circuit and the display device with gate driving circuit |
| CN108154860A (en) * | 2018-01-19 | 2018-06-12 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and display device |
| WO2018145452A1 (en) * | 2017-02-09 | 2018-08-16 | Boe Technology Group Co., Ltd. | Shift register unit and driving method therefor |
| CN108665865A (en) * | 2018-05-14 | 2018-10-16 | 昆山龙腾光电有限公司 | Drive element of the grid and display device |
-
2018
- 2018-11-13 CN CN201811345191.XA patent/CN109272960B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130243150A1 (en) * | 2011-04-21 | 2013-09-19 | Lg Display Co., Ltd. | Shift register |
| CN103226979A (en) * | 2013-02-18 | 2013-07-31 | 合肥京东方光电科技有限公司 | Bidirectional shifting register unit, bidirectional shifting register and display device |
| WO2015000187A1 (en) * | 2013-07-03 | 2015-01-08 | 深圳市华星光电技术有限公司 | Array substrate row driving circuit |
| CN103680453A (en) * | 2013-12-20 | 2014-03-26 | 深圳市华星光电技术有限公司 | Array substrate row driving circuit |
| CN103996390A (en) * | 2014-05-26 | 2014-08-20 | 昆山龙腾光电有限公司 | Gate driving circuit and display device using same |
| CN104517575A (en) * | 2014-12-15 | 2015-04-15 | 深圳市华星光电技术有限公司 | Shifting register and level-transmission gate drive circuit |
| CN107622758A (en) * | 2016-07-14 | 2018-01-23 | 三星显示有限公司 | Gate driving circuit and the display device with gate driving circuit |
| CN205984242U (en) * | 2016-08-30 | 2017-02-22 | 合肥京东方光电科技有限公司 | Shifting register unit, gate driving circuit and display device |
| WO2018145452A1 (en) * | 2017-02-09 | 2018-08-16 | Boe Technology Group Co., Ltd. | Shift register unit and driving method therefor |
| CN206864164U (en) * | 2017-11-07 | 2018-01-09 | 深圳市华星光电半导体显示技术有限公司 | GOA circuits |
| CN108154860A (en) * | 2018-01-19 | 2018-06-12 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and display device |
| CN108665865A (en) * | 2018-05-14 | 2018-10-16 | 昆山龙腾光电有限公司 | Drive element of the grid and display device |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354309A (en) * | 2020-04-15 | 2020-06-30 | 京东方科技集团股份有限公司 | Display driving module, display driving method and display device |
| US12014692B2 (en) | 2020-04-15 | 2024-06-18 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display driving module, method for driving the same and display device |
| CN112908235A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN112908276A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| CN112908235B (en) * | 2021-01-26 | 2022-09-23 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN113628596A (en) * | 2021-07-23 | 2021-11-09 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN113628596B (en) * | 2021-07-23 | 2023-02-24 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN113741726A (en) * | 2021-07-30 | 2021-12-03 | 惠科股份有限公司 | Drive circuit, four-stage drive circuit and display panel |
| US11942020B2 (en) | 2021-07-30 | 2024-03-26 | HKC Corporation Limited | Driving circuit, four-stage driving circuit and display panel |
| WO2024000328A1 (en) * | 2022-06-29 | 2024-01-04 | 京东方科技集团股份有限公司 | Display driving circuit and display device |
| CN117456924A (en) * | 2023-12-25 | 2024-01-26 | 惠科股份有限公司 | Driving circuit and display device |
| CN117456924B (en) * | 2023-12-25 | 2024-04-19 | 惠科股份有限公司 | Driving circuit and display device |
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| CN109272960B (en) | 2021-08-06 |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
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