CN104036747A - Electronic device capable of reducing number of driver chips - Google Patents
Electronic device capable of reducing number of driver chips Download PDFInfo
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- CN104036747A CN104036747A CN201410265151.XA CN201410265151A CN104036747A CN 104036747 A CN104036747 A CN 104036747A CN 201410265151 A CN201410265151 A CN 201410265151A CN 104036747 A CN104036747 A CN 104036747A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Disclosed is an electronic device (100) capable of reducing the number of driver chips. The electronic device (100) comprises a time schedule controller (10), a grid electrode driver chip (20), a source electrode driver chip (30), a pixel unit matrix (60) and a multiplexer (40). The multiplexer (40) comprises a plurality of first signal output ends connected with the pixel unit matrix (60); the time schedule controller (10) is used for generating enable signals to the multiplexer (40). Therefore, the multiplexer (40) can output scanning signals to the pixel unit matrix through the corresponding first signal output ends. The electronic device can reduce the number of channels of the driver chips.
Description
Technical field
The present invention relates to a kind of electronic installation, particularly a kind of electronic installation with Presentation Function.
Background technology
At present, the display device such as LCD (liquid crystal display, liquid crystal display) display are very general, and along with the needs of large scale screen, LCD display device also starts to develop to large scale.But along with the increase of screen size, required grid (gate) drives chip and source electrode (source) to drive the quantity of chip also greatly to increase, and has caused the rising of cost.
Summary of the invention
The invention provides a kind of electronic installation that drives chip that reduces, can use the demonstration of a small amount of driving chip drives large scale screen.
Reduce an electronic installation that drives chip, comprise time schedule controller, grid drive chip, source driving chip and matrix of pixel cells, this grid drive chip comprises that at least one drives signal output part, for generation of scanning drive signal, this source driving chip is for generation of display drive signals, this matrix of pixel cells comprises some pixel cells that matrix form distributes that are, it is characterized in that, this electronic installation also comprises: at least one multiplexer, each comprises a signal input part, some signal output parts and some Enable Pins, wherein, this signal input part connects with a corresponding driving signal output part of grid drive chip, the scanning drive signal producing for receiving driving signal output part corresponding to this grid drive chip, these some signal output parts are connected respectively with the several rows pixel cell in this matrix of pixel cells, wherein, this time schedule controller is electrically connected with some Enable Pins of multiplexer, for producing successively the some Enable Pins of enable signal to multiplexer, when in these some first Enable Pins one of multiplexer receives enable signal, by corresponding signal output part output scanning signal to matrix of pixel cells, and the pixel cell of gated sweep corresponding row.
Wherein, this time schedule controller comprises some enable signal output terminals, each in some enable signal output terminals of this time schedule controller is electrically connected respectively with these some Enable Pins of this multiplexer, thereby controls these some enable signal output terminals and output enable signal to successively some Enable Pins of multiplexer.
Wherein, electronic installation also comprises a level shifter, this level shifter is connected between some enable signal output terminals of this time schedule controller and some Enable Pins of this this at least one multiplexer, after the enable signal of each output of the enable signal output terminal of this time schedule controller is boosted, exports the Enable Pin that this multiplexer is corresponding to.
Wherein, this multiplexer comprises multiple path selecting circuits, and each path selecting circuit comprises one the one NMOS pipe and first phase inverter that boosts; This first phase inverter that boosts comprises input end and output terminal, the signal input part that the source electrode of the one NMOS pipe is corresponding with this multiplexer connects, the drain electrode of an one NMOS pipe signal output part corresponding with this multiplexer connects, grid is connected with this first output terminal that boosts phase inverter, this first input end of phase inverter Enable Pin corresponding with this multiplexer of boosting connects, and this first boosts phase inverter for the signal of corresponding Enable Pin being carried out to anti-phase rear output.
Wherein, this multiplexer also comprises one first voltage end and a second voltage end, this electronic installation also comprises power supply, and the first voltage end of this first and second multiplexer and second voltage end are connected with this power supply and obtain respectively high level voltage and low level voltage; This path selecting circuit also comprises one the 2nd NMOS pipe and second phase inverter that boosts, and this second phase inverter that boosts comprises input end and output terminal; The source electrode of the 2nd NMOS pipe is connected with the second voltage end of this multiplexer, drain electrode connects with the corresponding signal output part of multiplexer, grid is connected with the second output terminal that boosts phase inverter, and this second input end that boosts phase inverter is connected with this first the boost output terminal of phase inverter and grid of a NMOS pipe.
Wherein, the enable signal that time schedule controller produces is high level signal, the enable signal that produces a high level when time schedule controller is during to an Enable Pin of multiplexer, a NMOS pipe conducting in the routing switch of the corresponding Enable Pin that connects this multiplexer, thus the signal output part that this routing switch is connected is exported corresponding scanning drive signal or display drive signals.
Wherein, this first phase inverter and second phase inverter that boosts that boosts includes the 3rd NMOS pipe, the 4th NMOS pipe the 5th NMOS pipe and electric capacity; The grid of the 3rd NMOS pipe is connected with input end, and source electrode is connected with the second voltage end of this multiplexer, and drain electrode is connected with the source electrode of the 4th NMOS pipe and is connected with this output terminal; The drain electrode of this four NMOS pipe is connected with the first voltage end of this multiplexer, and grid is connected with the source electrode of the 5th NMOS pipe; The grid of the 5th NMOS pipe is connected and is connected with the first voltage end of this multiplexer with drain electrode, and the source electrode of the 5th NMOS pipe is also connected with one end of this electric capacity, and the other end of this electric capacity is connected with this output terminal.
Wherein, this electronic installation also comprises array basal plate, and this multiplexer and this matrix of pixel cells are arranged in this array base palte, and this grid drive chip, source driving chip, time schedule controller and level shifter are all positioned at outside this array base palte.
Wherein, this electronic installation also comprises array basal plate, and this multiplexer, this matrix of pixel cells and level shifter are arranged in this array base palte, this grid drive chip, source driving chip, time schedule controller, is positioned at outside this array base palte.
Wherein, this electronic installation also comprises a shift register, this time schedule controller only comprises an enable signal output terminal, this enable signal output terminal is for output enable signal, this level shifter is connected with this enable signal output terminal, and for the enable signal of this enable signal output terminal output is boosted; This shift register is connected between some Enable Pins of this level shifter and this multiplexer, imposes on successively some Enable Pins of this multiplexer for the enable signal after this level shifter is boosted.
The electronic installation that drives chip that reduces of the present invention, can use a small amount of grid drive chip to drive the turntable driving realizing large scale screen.
Brief description of the drawings
Fig. 1 is the structural representation of the electronic installation of the reduced driving chip in first embodiment of the invention.
Fig. 2 is the concrete structure figure of the multiplexer in the electronic installation of the reduced driving chip in an embodiment of the present invention.
Fig. 3 is the sequential chart of the input/output signal of the multiplexer in an embodiment of the present invention.
Fig. 4 is the concrete structure figure of the phase inverter that boosts in the multiplexer in an embodiment of the present invention.
Fig. 5 is the structural representation of the electronic installation of the reduced driving chip in second embodiment of the invention.
Fig. 6 is the structural representation of the electronic installation of the reduced driving chip in third embodiment of the invention.
Embodiment
The present invention refers to Fig. 1, for can reduce the structural representation of electronic installation 100 that drives chip.This electronic installation 100 comprises time schedule controller 10, grid drive chip 20, source driving chip 30, at least one multiplexer 40 and matrix of pixel cells 60.
Wherein, this grid drive chip 20 comprises that at least one drives signal output part 201, for generation of scanning drive signal G.This source driving chip 30 is for generation of display drive signals D.In the present invention, the number of this grid drive chip 20 is one.The number of this source driving chip 30 is at least one, for producing respectively display drive signals D to this matrix of pixel cells 60.
, each multiplexer 40 also comprises a signal input part 41 and some signal output part G1～Gn.Wherein, the signal input part 41 of this multiplexer 40 connects with a corresponding driving signal output part 201 of this grid drive chip 20, the scanning drive signal G that drives signal output part 201 to produce for receiving the correspondence of this grid drive chip 20.The number of multiplexer 40 equates with the number of the driving signal output part 201 of this grid drive chip 20.
This multiplexer 40 also comprises some Enable Pin E1～En.This time schedule controller 10 is all electrically connected with the Enable Pin E1～En of this multiplexer 40, for producing successively the Enable Pin E1～En of enable signal to this multiplexer 40.Thereby the Enable Pin E1～En of this multiplexer 40 receives respectively enable signal successively.
This matrix of pixel cells 60 comprises some pixel cell (not shown) that matrix form distributes that are.Some signal output part G1～Gn of this multiplexer 40 are connected respectively with the several rows pixel cell in this matrix of pixel cells 60.When in Enable Pin E1～En one of this multiplexer 40 receives enable signal, by output scanning signal G of the correspondence in signal output part G1～Gn to matrix of pixel cells 60, and the pixel cell of gated sweep corresponding row.
Thereby, in the present invention, by this at least one multiplexer 40, can reduce the number of the driving signal output part 201 of grid drive chip 20, reduce the passage number of grid drive chip 20, can realize the turntable driving to matrix of pixel cells 60.
Wherein, one that in Fig. 1, has only illustrated this grid drive chip 20 drives signal output part 201, obviously, the number of this driving signal output part 201 can be greater than one, when the driving signal output part 201 of this grid drive chip 20 is while being multiple, the number of this multiplexer 40 is also multiple, and each multiplexer 40 connects with corresponding driving signal output part 201 and carries out function described in the invention.
Wherein, in the time that the utmost point drives the number of the driving signal output part 201 of chip 20 and the number of this multiplexer 40 to be one, the number of the signal output part G1～Gn of this multiplexer 40 equals the maximum number of lines of this matrix of pixel cells 60.When the utmost point is when to drive the number of the driving signal output part 201 of chip 20 and the number of this multiplexer 40 be multiple, the number of all signal output part G1～Gn of the plurality of multiplexer 40 and equal the maximum number of lines of this matrix of pixel cells 60.
Wherein, as shown in Figure 1, in first embodiment of the invention, this time schedule controller 10 comprises some enable signal output terminal EA.Each in some enable signal output terminal EA of this time schedule controller 10 is electrically connected respectively with the Enable Pin E1～En of this multiplexer 40, thereby controls these some enable signal output terminal EA and output enable signal to successively the Enable Pin E1～En of multiplexer 40.
Wherein, as shown in Figure 1, in the present embodiment, this electronic installation 100 also comprises a level shifter 70.This level shifter 70 is connected between some enable signal output terminal EA of this time schedule controller 10 and the Enable Pin E1～En of this multiplexer 40, for exporting the Enable Pin of these multiplexer 40 correspondences after the enable signal of each output of the enable signal output terminal EA of this time schedule controller 10 is boosted to.
Wherein, this multiplexer 40 comprises the first voltage end Vdd and second voltage end VGL, this electronic installation 100 also comprises a power supply 78, this power supply 78 is connected with the first voltage end Vdd and the second voltage end VGL of this multiplexer 40 respectively, and provides the first voltage Vdd and second voltage VGL for this multiplexer 40.This power supply 78 is also connected with level shifter 70 and this grid drive chip 20, and provide operating voltage for this level shifter 70 and grid drive chip 20, wherein, in the present embodiment, this power supply 78 for the operating voltage that this level shifter 70 and grid drive chip 20 provide be tertiary voltage VGH and second voltage VGL.In the present embodiment.In the present embodiment, the first voltage Vdd and the tertiary voltage VGH of this first voltage end VGH access are high level voltage, and second of this second voltage end VGL access is ground voltage, i.e. low level voltage.
This power supply 78 can be a battery, the positive pole of battery and negative pole respectively with multiplexer 40 with the first voltage end VGH and second voltage end VGL be connected, and provide respectively high level voltage and low level voltage for the first voltage end Vdd and the second voltage end VGL of this multiplexer 40.In other embodiments, this power supply 78 can be the electric pressure converter of a multioutlet, and this first, second, third voltage is provided respectively.
Seeing also Fig. 2, is the cut-away view of multiplexer 40.Wherein, this multiplexer 40 comprises multiple path selecting circuits 42.Each path selecting circuit 42 comprises one the one NMOS pipe Q1, first phase inverter (boost inverter) B1 that boosts.This first phase inverter (boost inverter) B1 that boosts comprises input end i1 and output terminal o1.The source electrode of the one NMOS pipe Q1 is connected with this signal input part 41, the drain electrode of the one NMOS pipe Q1 connects with a corresponding signal output part, grid is connected with this first output terminal o1 that boosts phase inverter B1, and this first input end i1 that boosts phase inverter B1 connects with a corresponding Enable Pin.This first boosts phase inverter B1 for the signal of corresponding Enable Pin being carried out to anti-phase rear output.
In the present embodiment, the enable signal that this time schedule controller 10 produces is low level signal.Thereby, in the time that time schedule controller 10 produces a low level enable signal in the Enable Pin E1～En of multiplexer 40 one, in the corresponding routing switch 42 that connects this Enable Pin, first boosts phase inverter B1 by after anti-phase this low level enable signal, output high level signal to the NMOS manages the grid of Q1 and makes a NMOS pipe Q1 conducting, thereby makes the signal output part output scanning that this routing switch 42 connects drive one corresponding in signal G1～Gn.
Wherein, as shown in Figure 2, this path selecting circuit 42 also comprises one the 2nd NMOS pipe Q2 and the second phase inverter B2 that boosts.This second phase inverter B2 that boosts comprises input end i2 and output terminal o2.The 2nd NMOS pipe source electrode of Q2 is connected with the second voltage end VGL of this multiplexer 40, drains and corresponding this signal output part connection, and the boost output terminal o2 of phase inverter B2 of grid and second is connected.This second input end i2 that boosts phase inverter B2 is connected with this first grid that boosts the output terminal o1 of phase inverter B2 and NMOS pipe Q1.Wherein, in the time that time schedule controller 10 produces low level enable signal, this first boost phase inverter B1 by anti-phase this low level enable signal and output high level signal, this high level signal is carried out again the anti-phase and output low level signal grid to this 2nd NMOS pipe Q2 by this second phase inverter B2 that boosts, thereby the 2nd NMOS pipe Q2 cut-off, and do not affect the output of the signal output part that this path selecting circuit 42 connects.
Referring to Fig. 3, is the sequential chart of the input/output signal of multiplexer 40 of the present invention.Wherein, this grid drive chip 20 continues the scanning drive signal G for generation of high level in the sweep time of a frame picture in T, this time schedule controller 10 produces low level enable signal successively to the Enable Pin E1～En according to multiplexer 40, thereby as previously mentioned, the signal output part of the connection of multiple path selecting circuits 42 of this multiplexer 40 is exported the scanning drive signal G1～Gn of high level successively.
Seeing also Fig. 4, is the cut-away view of the phase inverter that boosts of the present invention.Wherein, first of each path selecting circuit 42 phase inverter B1 and second phase inverter B2 that boosts that boosts is identical, therefore also only describe as example taking the first phase inverter B1 that boosts at this.
This first phase inverter B1 that boosts comprises the 3rd NMOS pipe Q3, the 4th NMOS pipe Q4, the 5th NMOS pipe Q5 and capacitor C 1.The grid of the 3rd NMOS pipe Q3 is connected with input end i1, thereby source electrode is connected ground connection with this second voltage end VGL, and drain electrode is connected and is connected with this output terminal o1 with the source electrode of the 4th NMOS pipe Q4.The drain electrode of this four NMOS pipe Q4 is connected with the first voltage end Vdd, and grid is connected with the source electrode of the 5th NMOS pipe Q5.The grid of the 5th NMOS pipe Q5 is connected and is connected with this first voltage end Vdd with drain electrode.The source electrode of the 5th NMOS pipe Q5 is also connected with one end of this capacitor C 1, and the other end of this capacitor C 1 is connected with this output terminal o1.Wherein the voltage of this first voltage end Vdd is 5V or other positive voltages.
When Enable Pin is not when the enable signal of output low level is to this input end i1, the 3rd NMOS pipe Q3 conducting, thereby this first boost output terminal o1 of phase inverter B1 by the 3rd NMOS pipe Q3 ground connection of this conducting in low level, thereby do not export this scanning drive signal.Now, the 4th NMOS pipe Q4, the 5th NMOS pipe Q5 conducting, this first voltage end Vdd charges to capacitor C 1 by the 5th NMOS pipe Q5.
When the enable signal of an Enable Pin output low level of this correspondence is during to this input end i1, the 3rd NMOS pipe Q3 cut-off, now the stray capacitance on output terminal o1 is filled height by Q4, output terminal o1 is coupled the 4th NMOS tube grid is raised to the high voltage that exceedes Vdd through capacitor C 1 simultaneously, increases by the 4th NMOS pipe Q4 driving force.The scanning drive signal of now output terminal o1 output high level.
In the present embodiment, for the tertiary voltage VGH providing for this level shifter 70 and grid drive chip 20 is provided boost the first voltage Vdd that phase inverter B2 provides of the phase inverter B1 and second that boosts of this multiplexer 40, (electric current is large so just to make a NMOS pipe Q1 and the 2nd NMOS pipe Q2 operate in linear zone, discharge and recharge fast), make a NMOS pipe Q1 and the 2nd NMOS pipe Q2 just can reach enough charging and discharging capabilities by less size.
In the present embodiment, as shown in Figure 1, this electronic installation 100 also comprises array basal plate 101, in first embodiment of the invention, this multiplexer 40 and this matrix of pixel cells 60 are arranged in this array base palte 101, and this grid drive chip 10, source driving chip 20, time schedule controller 10 and level shifter 70 are all positioned at outside this array base palte 101.
Refer to Fig. 5, in the second embodiment, this multiplexer 40, this matrix of pixel cells 60 and this level shifter 70 are all arranged in this array base palte 101.
Refer to Fig. 6, in the 3rd embodiment, this electronic installation 100 also comprises a shift register 90.In the present embodiment, this time schedule controller 10 only comprises an enable signal output terminal E, and this enable signal output terminal E is for output enable signal.This level shifter 70 is connected with this enable signal output terminal E, and for the enable signal of this enable signal output terminal E output is boosted.This shift register 90 is connected between the Enable Pin E1～En of this level shifter 70 and this multiplexer 40, imposes on successively the Enable Pin E1～En of this multiplexer 40 for the enable signal after this level shifter 70 is boosted.Thereby the Enable Pin E1～En of this multiplexer 40 receives enable signal successively, and respectively by signal output part G1～Gn output scanning signal successively.
Wherein, in the 3rd embodiment, this multiplexer 40, this matrix of pixel cells 60 and this level shifter 70, this shift register 90 are all arranged in this array base palte 101.
Wherein, this electronic installation 100 can be LCD TV, liquid crystal display, mobile phone, panel computer, notebook computer etc.
Thereby electronic installation 100 of the present invention, only needs a grid drive chip 20 and a multiplexer to realize large-sized electronic installation 100 is carried out to turntable driving, has greatly reduced the quantity of grid drive chip, save cost.
Above embodiment has been described in detail the present invention, but these are not construed as limiting the invention.Protection scope of the present invention is not limited with above-mentioned embodiment, as long as the equivalence that those of ordinary skill in the art do according to disclosed content is modified or changed, all should include in the protection domain of recording in claims.
Claims (10)
1. an electronic installation that drives chip be can reduce, time schedule controller, grid drive chip, source driving chip and matrix of pixel cells comprised; This grid drive chip comprises that at least one drives signal output part, for generation of scanning drive signal, this source driving chip is for generation of display drive signals, and this matrix of pixel cells comprises some pixel cells that matrix form distributes that are, it is characterized in that, this electronic installation also comprises:
At least one multiplexer, each comprises a signal input part, some signal output parts and some Enable Pins, wherein, this signal input part connects with a corresponding driving signal output part of grid drive chip, the scanning drive signal producing for receiving driving signal output part corresponding to this grid drive chip, these some signal output parts are connected respectively with the several rows pixel cell in this matrix of pixel cells;
Wherein, this time schedule controller is electrically connected with some Enable Pins of multiplexer, for producing successively the some Enable Pins of enable signal to multiplexer; When in these some first Enable Pins one of multiplexer receives enable signal, by corresponding signal output part output scanning signal to matrix of pixel cells, and the pixel cell of gated sweep corresponding row.
2. electronic installation as claimed in claim 1, it is characterized in that, this sequence controller comprises some enable signal output terminals, each in some enable signal output terminals of time schedule controller is electrically connected respectively with these some Enable Pins of multiplexer, thereby controls these some enable signal output terminals and output enable signal to successively some Enable Pins of multiplexer.
3. electronic installation as claimed in claim 1, it is characterized in that, electronic installation also comprises a level shifter, this level shifter is connected between some enable signal output terminals of time schedule controller and some Enable Pins of this at least one multiplexer, after the enable signal of each output of the enable signal output terminal of this time schedule controller is boosted, exports the Enable Pin that this multiplexer is corresponding to.
4. electronic installation as claimed in claim 3, is characterized in that, this multiplexer comprises multiple path selecting circuits, and each path selecting circuit comprises one the one NMOS pipe and first phase inverter that boosts; This first phase inverter that boosts comprises input end and output terminal, the signal input part that the source electrode of the one NMOS pipe is corresponding with this multiplexer connects, the drain electrode of an one NMOS pipe signal output part corresponding with this multiplexer connects, grid is connected with this first output terminal that boosts phase inverter, this first input end of phase inverter Enable Pin corresponding with this multiplexer of boosting connects, and this first boosts phase inverter for the signal of corresponding Enable Pin being carried out to anti-phase rear output.
5. electronic installation as claimed in claim 4, it is characterized in that, this multiplexer also comprises one first voltage end and a second voltage end, this electronic installation also comprises power supply, and the first voltage end of this first and second multiplexer and second voltage end are connected with this power supply and obtain respectively high level voltage and low level voltage; This path selecting circuit also comprises one the 2nd NMOS pipe and second phase inverter that boosts, and this second phase inverter that boosts comprises input end and output terminal; The source electrode of the 2nd NMOS pipe is connected with the second voltage end of this multiplexer, drain electrode connects with the corresponding signal output part of multiplexer, grid is connected with the second output terminal that boosts phase inverter, and this second input end that boosts phase inverter is connected with this first the boost output terminal of phase inverter and grid of a NMOS pipe.
6. electronic installation as claimed in claim 4, it is characterized in that, the enable signal that time schedule controller produces is high level signal, the enable signal that produces a high level when time schedule controller is during to an Enable Pin of multiplexer, a NMOS pipe conducting in the routing switch of the corresponding Enable Pin that connects this multiplexer, thus the signal output part that this routing switch is connected is exported corresponding scanning drive signal or display drive signals.
7. electronic installation as claimed in claim 5, is characterized in that, this first phase inverter and second phase inverter that boosts that boosts includes the 3rd NMOS pipe, the 4th NMOS pipe the 5th NMOS pipe and electric capacity; The grid of the 3rd NMOS pipe is connected with input end, and source electrode is connected with the second voltage end of this multiplexer, and drain electrode is connected with the source electrode of the 4th NMOS pipe and is connected with this output terminal; The drain electrode of this four NMOS pipe is connected with the first voltage end of this multiplexer, and grid is connected with the source electrode of the 5th NMOS pipe; The grid of the 5th NMOS pipe is connected and is connected with the first voltage end of this multiplexer with drain electrode, and the source electrode of the 5th NMOS pipe is also connected with one end of this electric capacity, and the other end of this electric capacity is connected with this output terminal.
8. electronic installation as claimed in claim 3, it is characterized in that, this electronic installation also comprises array basal plate, multiplexer and matrix of pixel cells are arranged in this array base palte, and this grid drive chip, source driving chip, time schedule controller and level shifter are all positioned at outside this array base palte.
9. electronic installation as claimed in claim 3, it is characterized in that, this electronic installation also comprises array basal plate, multiplexer, matrix of pixel cells and level shifter are arranged in this array base palte, grid drive chip, source driving chip, time schedule controller, are positioned at outside this array base palte.
10. electronic installation as claimed in claim 1, it is characterized in that, this electronic installation also comprises a shift register, this time schedule controller only comprises an enable signal output terminal, this enable signal output terminal is for output enable signal, this level shifter is connected with this enable signal output terminal, and for the enable signal of this enable signal output terminal output is boosted; This shift register is connected between some Enable Pins of this level shifter and this multiplexer, imposes on successively some Enable Pins of this multiplexer for the enable signal after this level shifter is boosted.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410265151.XA CN104036747A (en) | 2014-06-13 | 2014-06-13 | Electronic device capable of reducing number of driver chips |
| US14/777,208 US9830874B2 (en) | 2014-06-13 | 2014-06-27 | Electronic device having smaller number of drive chips |
| PCT/CN2014/080960 WO2015188406A1 (en) | 2014-06-13 | 2014-06-27 | Electronic device capable of reducing driving chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410265151.XA CN104036747A (en) | 2014-06-13 | 2014-06-13 | Electronic device capable of reducing number of driver chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104036747A true CN104036747A (en) | 2014-09-10 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410265151.XA Pending CN104036747A (en) | 2014-06-13 | 2014-06-13 | Electronic device capable of reducing number of driver chips |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9830874B2 (en) |
| CN (1) | CN104036747A (en) |
| WO (1) | WO2015188406A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2015188406A1 (en) | 2015-12-17 |
| US20170186392A1 (en) | 2017-06-29 |
| US9830874B2 (en) | 2017-11-28 |
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Application publication date: 20140910 |