CN101950520B - Level shifter, generation method of clock output signal and plane display device thereof - Google Patents
Level shifter, generation method of clock output signal and plane display device thereof Download PDFInfo
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- CN101950520B CN101950520B CN 201010264052 CN201010264052A CN101950520B CN 101950520 B CN101950520 B CN 101950520B CN 201010264052 CN201010264052 CN 201010264052 CN 201010264052 A CN201010264052 A CN 201010264052A CN 101950520 B CN101950520 B CN 101950520B
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Abstract
The invention relates to a level shifter, a generation method of a clock output signal and a plane display device thereof. The level shifter comprises at least one level shift unit for generating the corresponding clock output signal; the level shift unit is used for respectively receiving the corresponding clock input signal so that the corresponding clock input signal is progressively pulled up to the first reference voltage and becomes a part of the corresponding clock output signal since the clock input signal shares the charge with a plurality of different auxiliary reference voltage sources, or the corresponding clock input signal is progressively pulled down to the second reference voltage and becomes a part of the corresponding clock output signal since the clock input signal shares the charge together with different auxiliary reference voltage sources.
Description
Technical field
The invention relates to the display technique field, and particularly relevant for the production method of a kind of level shifter, clock output signal and corresponding flat display apparatus.
Background technology
Along with development of science and technology, flat display apparatus, advantages such as for example liquid crystal indicator is light owing to having, thin and low radiation, and replace the cathode ray tube (CRT) display device gradually.Typical liquid crystal indicator generally comprises display base plate, circuit board and is arranged on gate driver circuit and the source electrode drive circuit on the display base plate.Circuit board is provided with time schedule controller, in order to a plurality of gate driver circuit and source electrode drive circuits of controlling signal to be provided.Gate driver circuit is used to drive many gate lines on the display base plate, and source electrode drive circuit is used for exporting picture signal on the display base plate many data lines.Gate driver circuit and source electrode drive circuit generally are arranged on the display base plate with tape carrier package (TCP) or glass flip chip encapsulation technology.In addition, gate driver circuit can also directly be formed on the display base plate, promptly so-called grid array circuit (Gate-On-Array Circuit, GOA Circuit).And this structure that in display base plate, directly forms gate driver circuit comprises shift registor (Shift Register); Shift registor comprises the level (Stage) that a plurality of cascades couple, thereby is arranged at the gate line on the display base plate to produce the activation in regular turn of a plurality of gate driving pulse.
(Gate On Array, GOA) in the circuit design, level shifter is arranged on the circuit board provides gate driving pulse required energy respectively to produce two required voltages of clock signal to grid on the array of present two phases (2-phase).Because the progression of the bigger and coupled shift registor that connects of voltage amplitude (being the voltage difference between noble potential and the electronegative potential) of these two clock signals is more, stray capacitance is quite big, so its power consumption is big.For improving above-mentioned defective, industry general using electric charge is shared the power consumption that technology reduces level shifter.Because above-mentioned two clock signals generally have antipole property; It is before the two polarity transformation that the electric charge that therefore present industry adopts is shared technology; The two is joined so that the two shares electric charge mutually to middle voltage, by the output buffer of level shifter the two is amplified to target voltage respectively more afterwards.Only, the polarity of above-mentioned two clock signals is just in time opposite, and when wherein a clock signal will rise, another clock signal must descend, thereby these two clock signals can't be in electronegative potential simultaneously or noble potential lacks Waveform Design elasticity.
In addition; GOA circuit for other heterogeneous (for example four phases); If the noble potential time of the multi-phase clock signal of its use exists part to overlap, the electric charge that then above-mentioned two phase clock signal is adopted is shared technology and can't be applied to this, thereby the power consumption of heterogeneous level shifter is bigger.
Summary of the invention
The object of the invention is to provide a kind of level shifter exactly, and it can reduce power consumption.
A purpose more of the present invention provides a kind of production method of clock output signal, and its range of application is wide and can reduce power consumption.
Another purpose of the present invention provides a kind of flat display apparatus, and it can reduce power consumption.
The present invention proposes a kind of level shifter, and it comprises at least one level shift units, and wherein each level shift units is in order to producing a corresponding clock output signal, and each level shift units comprises amplifier and control circuit respectively.Amplifier comprises input end, positive power source terminal, negative power end and output terminal, this input end receive clock input signal, and positive power source terminal receives first reference voltage, and negative power end receives second reference voltage, and first reference voltage is greater than second reference voltage.Control circuit receives a control signal with in the corresponding clock output signal of output terminal output, wherein this control signal activation when the height of this clock input signal/low level toggle edges, and this control circuit comprises CS and a plurality of assist control switch.Wherein, CS is electrically coupled between the output terminal of output terminal and control circuit of amplifier; The assist control switch is electrically coupled to respectively between the output terminal of one of a plurality of different auxiliary reference voltage sources and control circuit, and wherein the voltage level of these a plurality of different auxiliary reference voltage sources is between this first reference voltage and this second reference voltage.CS and assist control switch are in different moment conductings; So that corresponding clock output signal is shared electric charge with different auxiliary reference voltage sources respectively and by a progressive part that is pulled up to first reference voltage and becomes corresponding clock output signal from second reference voltage, perhaps share electric charge with different auxiliary reference voltage sources respectively and by a progressive part that is pulled low to second reference voltage and becomes corresponding clock output signal from first reference voltage.
The present invention also proposes a kind of production method of clock output signal, and it is applied to mate the level shifter of grid array circuit.The production method of above-mentioned clock output signal comprises and receives corresponding a clock input signal and a control signal, wherein this control signal activation when the height of this clock input signal/low level toggle edges; And make corresponding clock input signal share electric charge with a plurality of different auxiliary reference voltage sources respectively and by a progressive part that is pulled up to first reference voltage and becomes corresponding clock output signal; Or making corresponding clock input signal share electric charge with different auxiliary reference voltage sources respectively and by a progressive part that is pulled low to second reference voltage and becomes corresponding clock output signal, the voltage level of wherein should be a plurality of different auxiliary reference voltage sources is between this first reference voltage and this second reference voltage and the rising edge of the rising edge of this control signal and this clock input signal or drop edge are overlapping.
The present invention proposes a kind of flat display apparatus in addition, it comprise time schedule controller, level shifter with the grid array shift registor.Time schedule controller is in order to produce control signal and at least one clock input signal, wherein this control signal activation when the height of this clock input signal/low level toggle edges.Level shifter receives control signal and aforesaid at least one clock input signal, and produces corresponding at least one clock output signal of at least one clock input signal therewith.The grid array shift registor receives aforesaid at least one clock output signal to produce a plurality of gate driving pulse.Wherein, level shifter comprises at least one level shift units, and each level shift units comprises amplifier and control circuit.Amplifier comprises input end, positive power source terminal, negative power end and output terminal; This input end receives corresponding clock input signal; Positive power source terminal receives first reference voltage, and negative power end receives second reference voltage, and first reference voltage is greater than second reference voltage.Control circuit is in the corresponding clock output signal of output terminal output, and this control circuit comprises CS and a plurality of assist control switch.Wherein, CS is electrically coupled between the output terminal of output terminal and control circuit of amplifier; The assist control switch is electrically coupled to respectively between the output terminal of one of a plurality of different auxiliary reference voltage sources and control circuit.CS and assist control switch are in different moment conductings; So that corresponding clock output signal is shared electric charge with different auxiliary reference voltage sources respectively and by a progressive part that is pulled up to first reference voltage and becomes corresponding clock output signal from second reference voltage; Perhaps from first reference voltage respectively with different auxiliary reference voltage sources by a progressive part that is pulled low to second reference voltage and becomes corresponding clock output signal, wherein the voltage level of these a plurality of different auxiliary reference voltage sources is between this first reference voltage and this second reference voltage.
In preferred embodiment of the present invention, one of them the suspension joint electric capacity through a correspondence at least in the first above-mentioned reference voltage, second reference voltage and the different auxiliary reference voltage source provides.
In one embodiment of the invention, do not overlap mutually between above-mentioned a plurality of clock output signals that level shift units produced.And in another embodiment, then can partly weigh mutually between above-mentioned a plurality of clock output signals that level shift units produced.
Level shifter of the present invention through each level shifter each clock input signal is carried out processing and amplifying and electric charge is shared processing to obtain corresponding clock output signal; And because clock output signal carries out electric charge with different auxiliary reference voltage sources and shares; Therefore it can reduce power consumption significantly, saves energy.In addition, level shifter of the present invention and electric charge are shared technology and both can be applied to grid on the array of two phases (Gate On Array GOA) in the circuit, also can be applied to surpass in the GOA circuit of two phases (for example four phases), and its range of application is wider.
For let above and other objects of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Fig. 1 illustrates the synoptic diagram of the flat display apparatus that discloses for one embodiment of the invention.
Fig. 2 illustrates the synoptic diagram of the level shift units that discloses for one embodiment of the invention.
Fig. 3 illustrates the sequential chart into various signals shown in Figure 2.
Fig. 4 illustrates the sequential chart of various signals of the level shifter of the GOA circuit that is applied to four phases that discloses for one embodiment of the invention.
Fig. 5 illustrates the sequential chart of various signals of the level shifter of the GOA circuit that is applied to four phases that discloses for another embodiment of the present invention.
Fig. 6 illustrates the synoptic diagram of the level shift units that discloses for another embodiment of the present invention.
[main element label declaration]
100: flat display apparatus 110: circuit board
120: display base plate 111: time schedule controller
112,200,300: level shifter 123: the grid array shift registor
GL
1～GL
m: gate line CS: control signal
CLK
1～CLK
n: clock input signal CLK
Out1～CLK
Outn: clock output signal
VGH: the first reference voltage VGL: second reference voltage
VGL1, GND, VGH1, VGH2: auxiliary reference voltage source
S
1: CS S
2～S
5: the assist control switch
CS: control signal 210: amplifier
220: control circuit 221: the output terminal of control circuit
Embodiment
See also Fig. 1, it illustrates the synoptic diagram of a kind of flat display apparatus that discloses for one embodiment of the invention.As shown in Figure 1, flat display apparatus 100 comprises circuit board 110 and display base plate 120.Circuit board 110 is provided with time schedule controller 111 and level shifter 112.Be provided with many gate lines G L in the viewing area of display base plate 120 (not indicating)
1～GL
m, the outer peripheral areas of display base plate 120 (not indicating) then is provided with grid array shift registor 123.Wherein, time schedule controller 111 is in order to produce at least more than one clock input signal CLK
1～CLK
nAnd control signal CS.Level shifter 112 receives control signal CS and clock input signal CLK
1～CLK
nThereby produce corresponding clock output signal CLK it is carried out relevant treatment
Out1～CLK
OutnGrid array shift registor 123 receive clocks output signal CLK
Out1～CLK
OutnAnd according to clock output signal CLK
Out1～CLK
OutnAnd produce a plurality of gate driving pulse with the gate lines G L on the activation display base plate 120 in order
1～GL
mWherein, level shifter 112 comprises more than one level shift units (figure do not show), and each level shift units (for example: CLK receives control signal CS and a clock input signal respectively
n), and according to control signal CS and to clock input signal (for example: CLK
n) handle and (for example: CLK produce corresponding clock output signal
Outn).
See also Fig. 2, it illustrates the synoptic diagram of the level shift units that discloses for one embodiment of the invention.As shown in Figure 2, the level shift units 200 that the embodiment of the invention disclosed comprises amplifier 210 and control circuit 220.Amplifier 210 comprises input end, positive power source terminal, negative power end and output terminal.The input end receive clock input signal CLK of amplifier 210
n, positive power source terminal receives the first reference voltage VGH, and negative power end receives the second reference voltage VGL, and wherein the first reference voltage VGH is greater than the second reference voltage VGL.Control circuit 220 is electrically coupled to output terminal and a plurality of auxiliary reference voltage source of amplifier 210, like VGL
1, GND, VGH
1And VGH
2Deng, export corresponding clock output signal CLK with output terminal 221 in control circuit 220
Outn Control circuit 220 comprises CS S
1And assist control switch S
2～S
5, wherein, CS S
1Be electrically coupled between the output terminal 221 of output terminal and control circuit 220 of amplifier 210, and each assist control switch S
2～S
5Be electrically coupled to respectively between the output terminal 221 of auxiliary reference voltage source and control circuit 220 of a correspondence.These auxiliary reference voltage source V GL
1, GND, VGH
1And VGH
2Current potential between the second reference voltage VGL and the first reference voltage VGH, and these auxiliary reference voltage source V GL
1, GND, VGH
1And VGH
2Current potential have nothing in common with each other.In the present embodiment, the second reference voltage VGL and auxiliary reference voltage source V GL
1Be negative potential, auxiliary reference voltage source GND is an earth potential, and the first reference voltage VGH and auxiliary reference voltage source V GH
1And VGH
2Be positive potential, and VGL＜VGL
1＜GND＜VGH
1＜VGH
2＜VGH.Certainly, it will be appreciated by persons skilled in the art that the size of the first reference voltage VGH and the second reference voltage VGL and the number of auxiliary reference voltage source can set according to actual needs.
See also Fig. 3, it illustrates the sequential chart into various signals shown in Figure 2.Please consult Fig. 2-3 in the lump, the principle of work of the level shift units that below will specifically introduce the embodiment of the invention and disclosed.
Particularly, the clock input signal CLK that receives when the amplifier of level shift units 200 210
nWhen being in electronegative potential, amplifier 210 with the second reference voltage VGL that negative power end received as output, the CS S1 conducting in this moment control circuit 220, so the clock output signal CLK that exported of the output terminal 221 of control circuit 220
OutnBe exactly the second reference voltage VGL that negative power end received of amplifier 210.
When making clock input signal CLK
nWhen noble potential was changed, control circuit 220 was at first with the control of suspension control signal CS and by CS S from electronegative potential
1And conducting assist control switch S
5Thus, the output terminal 221 of control circuit 220 just can with auxiliary reference voltage source V GL
1Share electric charge, and make clock output signal CLK
OutnCurrent potential will be pulled up to current potential VGL from the second reference voltage VGL
1After this, control signal CS makes the assist control switch S
5End and conducting assist control switch S
4Can share electric charge and make clock output signal CLK with auxiliary reference voltage GND because of the output terminal 221 of control circuit 220 thus
OutnFrom current potential VGL
1Be pulled up to current potential GND.The rest may be inferred, continuing through ending the assist control switch S
4And conducting assist control switch S
3, by the assist control switch S
3And conducting assist control switch S
2And to ending the assist control switch S
2And conducting CS S once more
1Process after, the current potential on the output terminal 221 of control circuit 220 progressively is pulled up to the first reference voltage VGH as as shown in Figure 3.
That is to say the assist control switch S
2～S
5With CS S
1The clock control of suspension control signal CS and conducting in turn; And in this process, clock output signal CLK
OutnFrom the second reference voltage VGL respectively with different auxiliary reference voltage source V GL
1, GND, VGH
1And VGH
2Share electric charge and be pulled up to the first reference voltage VGH gradually and be stabilized on the first reference voltage VGH.In addition, auxiliary reference voltage source V GL
1, GND, VGH
1And VGH
2Current potential also will become clock output signal CLK
OutnA part.In other words, clock output signal CLK
OutnBe not to be directly to be pulled up to the first reference voltage VGH by the second reference voltage VGL, but through with different auxiliary reference voltage source V GL
1, GND, VGH
1And VGH
2Share electric charge and be pulled up to the first reference voltage VGH step by step, so the power of its consumption is less.
Relatively, as clock input signal CLK
nFrom noble potential when electronegative potential is changed, the control of control circuit 220 suspension control signal CS and pass through conducting CS S in regular turn
1, by CS S
1And conducting assist control switch S
2, by the assist control switch S
2And conducting assist control switch S
3, by the assist control switch S
3And conducting assist control switch S
4, by the assist control switch S
4And conducting assist control switch S
5, and by the assist control switch S
1And conducting CS S once more
1Operating process.By this, the output terminal 221 of control circuit 220 will be begun one by one and each auxiliary reference voltage source V GH by the first reference voltage VGH
2, VGH
1, GND and VGL
1Share electric charge mutually, and finally be pulled low to the second reference voltage VGL.
Therefore, level shifter of the present invention is through each level shifter and to each clock input signal (CLK
1～CLK
n) carry out processing and amplifying and electric charge and share processing to obtain corresponding clock output signal (CLK
Out1～CLK
Outn), and because clock output signal (CLK
Out1～CLK
Outn) carry out electric charge with different auxiliary reference voltage source V GH2, VGH1, GND and VGL1 and share and change once the way that the way that draws high (dragging down) current potential is multistage drawing high (a dragging down) current potential, so it can reduce power consumption significantly, saves energy.
In addition; It will be understood by those skilled in the art that; It is that each independent clock input signal CLKn is handled that disclosed electric charge is shared technology; Therefore level shifter of the present invention both can be applied on the array of two phases grid (Gate On Array GOA) in the circuit, also can be applied in the GOA circuit of three-phase above (for example four phases).
Particularly, the level shifter with the GOA circuit that is applied to four phases below is that example describes.See also Fig. 4, it illustrates the sequential chart of various signals of the level shifter of the GOA circuit that is applied to four phases that discloses for one embodiment of the invention.As shown in Figure 4, level shifter receives four clock input signal CLK
1～CLK
4And control signal CS, and to clock input signal CLK
1～CLK
4Handle and produce four corresponding clock output signal CLK
Out1～CLK
Out4In the present embodiment, four clock input signal CLK
1～CLK
4Activation during (enable period) do not overlap mutually, likewise, four corresponding clock output signal CLK
Out1～CLK
Out4Activation during also do not overlap mutually (non-overlap).In addition, each clock output signal CLK
Out1～CLK
Out4When carrying out the conversion of high electronegative potential, all utilize the electric charge shown in Fig. 2-3 to share technology respectively to draw high or to drag down current potential step by step.
See also Fig. 5, it illustrates the sequential chart of various signals of the level shifter of the GOA circuit that is applied to four phases that discloses for another embodiment of the present invention.As shown in Figure 5, the difference of present embodiment and embodiment shown in Figure 4 is clock input signal CLK
1～CLK
4Activation during overlap mutually, likewise, four corresponding clock output signal CLK
Out1～CLK
Out4Activation during also overlap mutually (overlap).
In addition; It will be understood by those skilled in the art that; The first reference voltage VGH, the second reference voltage VGL and auxiliary reference voltage source V GL1, GND, VGH1 and VGH2 can utilize special circuit to provide among the present invention; Charge pump (charge pump) circuit for example, still, it also can adopt existing circuit to provide.See also Fig. 6, it illustrates the synoptic diagram of the level shift units that discloses for another embodiment of the present invention.As shown in Figure 6, the level shift units 300 that present embodiment disclosed is similar with level shift units 200 shown in Figure 2, and its difference only is auxiliary reference voltage source V GH
1With VGL
1Provide through suspension joint electric capacity, and this suspension joint electric capacity can be the perhaps stray capacitance in the flat-panel screens of actual electrical.
In sum; Level shifter of the present invention through each level shifter each clock input signal is carried out processing and amplifying and electric charge is shared processing to obtain corresponding clock output signal; And because clock output signal carries out electric charge with different auxiliary reference voltage sources and shares; Therefore can reduce power consumption significantly, save energy.In addition, level shifter of the present invention and electric charge are shared technology and both can be applied in the GOA circuit of two phases, also can be applied in the GOA circuit of three-phase above (for example three-phase or four phases), and its range of application is wider.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Any those skilled in the art; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (9)
1. a level shifter comprises at least one level shift units, and wherein each this at least one level shift units is in order to producing a corresponding clock output signal, and this at least one level shift units comprises respectively:
One amplifier, it comprises:
One input end receives a clock input signal;
One positive power source terminal receives one first reference voltage;
One negative power end receives one second reference voltage, and wherein this first reference voltage is greater than this second reference voltage; And
One output terminal; And
One control circuit receives a control signal with in this corresponding clock output signal of the output terminal of this control circuit output, wherein this control signal activation when the height of this clock input signal/low level toggle edges, and wherein this control circuit comprises:
One CS is electrically coupled between this output terminal of this output terminal and this control circuit of this amplifier; And
A plurality of assist control switches; Be electrically coupled to respectively between this output terminal of one of a plurality of different auxiliary reference voltage sources and this control circuit, wherein the voltage level of these a plurality of different auxiliary reference voltage sources is between this first reference voltage and this second reference voltage;
Wherein, This CS and these a plurality of assist control switches are in different moment conductings; So that clock output signal that should correspondence is shared electric charge with these a plurality of different auxiliary reference voltage sources respectively and by a progressive part that is pulled up to this first reference voltage and becomes this corresponding clock output signal from this second reference voltage, perhaps share electric charge with these a plurality of different auxiliary reference voltage sources respectively and by a progressive part that is pulled low to this second reference voltage and becomes this corresponding clock output signal from this first reference voltage.
2. level shifter according to claim 1, wherein one of at least suspension joint electric capacity through a correspondence in a plurality of different auxiliary reference voltage sources of this first reference voltage, this second reference voltage and this provides.
3. level shifter according to claim 1 does not overlap mutually between a plurality of clock output signals that wherein those level shift units produced and the rising edge or the drop edge of the rising edge of this control signal and this clock input signal are overlapping.
4. level shifter according to claim 1, partly the rising edge of the rising edge of overlapping and this control signal and this clock input signal or drop edge are overlapping mutually between a plurality of clock output signals that wherein those level shift units produced.
5. the production method of a clock output signal is applied to mate the level shifter of grid array circuit, and the production method of this clock output signal comprises:
Receive a corresponding clock input signal and a control signal, wherein this control signal activation when the height of this clock input signal/low level toggle edges; And
Make this corresponding clock input signal share electric charge with a plurality of different auxiliary reference voltage sources respectively and by a progressive part that is pulled up to one first reference voltage and becomes this corresponding clock output signal; Or make this corresponding clock input signal share electric charge with these a plurality of different auxiliary reference voltage sources respectively and by a progressive part that is pulled low to one second reference voltage and becomes this corresponding clock output signal, wherein the voltage level of these a plurality of different auxiliary reference voltage sources be between this first reference voltage and this second reference voltage and the rising edge of the rising edge of this control signal and this clock input signal or drop edge for overlapping.
6. the production method of clock output signal according to claim 5, wherein providing one of at least in a plurality of different auxiliary reference voltage sources of this first reference voltage, this second reference voltage and this through at least one corresponding suspension joint electric capacity.
7. flat display apparatus comprises:
Time schedule controller, in order to produce a control signal and at least one clock input signal, wherein this control signal activation when the height of this clock input signal/low level toggle edges;
One level shifter receives this control signal and this at least one clock input signal, and produces and corresponding at least one clock output signal of this at least one clock input signal; And
One grid array shift registor receives this at least one clock output signal to produce a plurality of gate driving pulse;
Wherein, this level shifter comprises at least one level shift units, and each this level shift units comprises:
One amplifier, it comprises:
One input end receives the corresponding clock input signal of one in this at least one clock input signal;
One positive power source terminal receives one first reference voltage;
One negative power end receives one second reference voltage; And
One output terminal; And
One control circuit, the clock output signal of the correspondence in this at least one clock output signal of output terminal output of this control circuit, wherein this control circuit comprises:
One CS is electrically coupled between this output terminal of this output terminal and this control circuit of this amplifier; And
A plurality of assist control switches; Be electrically coupled to respectively between this output terminal of one of a plurality of different auxiliary reference voltage sources and this control circuit; Wherein this CS is distinguished conductings through this control signal in the different moment with these a plurality of assist control switches; Be pulled up to one first reference voltage and become the part of this corresponding clock output signal by progressive so that clock output signal that should correspondence is shared electric charge with a plurality of different auxiliary reference voltage sources respectively; Or make this corresponding clock input signal share electric charge with these a plurality of different auxiliary reference voltage sources respectively and be pulled low to one second reference voltage and become the part of this corresponding clock output signal by progressive, wherein the voltage level of these a plurality of different auxiliary reference voltage sources is between this first reference voltage and this second reference voltage.
8. flat-panel screens according to claim 7 does not overlap mutually between those clock output signals that wherein this level shifter produced and the rising edge or the drop edge of the rising edge of this control signal and this clock input signal are overlapping.
9. flat-panel screens according to claim 7, partly the rising edge of the rising edge of overlapping and this control signal and this clock input signal or drop edge are overlapping mutually between those clock output signals that wherein this level shifter produced.
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| CN 201010264052 CN101950520B (en) | 2010-08-25 | 2010-08-25 | Level shifter, generation method of clock output signal and plane display device thereof |
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|---|---|---|---|
| CN 201010264052 CN101950520B (en) | 2010-08-25 | 2010-08-25 | Level shifter, generation method of clock output signal and plane display device thereof |
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| CN101950520B true CN101950520B (en) | 2012-12-26 |
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| CN101587700A (en) * | 2009-06-26 | 2009-11-25 | 友达光电股份有限公司 | Liquid crystal display and method for driving same |
| CN101707054A (en) * | 2009-12-02 | 2010-05-12 | 友达光电股份有限公司 | Liquid crystal display (LCD) device and driving method thereof |
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| CN1492507A (en) * | 1996-12-26 | 2004-04-28 | 三菱电机株式会社 | Semiconductor device |
| US6864920B1 (en) * | 2001-08-24 | 2005-03-08 | Eastman Kodak Company | High voltage reset method for increasing the dynamic range of a CMOS image sensor |
| CN1877668A (en) * | 2005-06-03 | 2006-12-13 | 三星电子株式会社 | Apparatus and method for driving gate lines in a flat panel display |
| CN101452682A (en) * | 2007-12-06 | 2009-06-10 | 奕力科技股份有限公司 | Driving circuit of display and correlation method thereof |
| CN101582686A (en) * | 2009-06-05 | 2009-11-18 | 友达光电股份有限公司 | Power level shifter, liquid crystal display device and charge sharing method |
| CN101587700A (en) * | 2009-06-26 | 2009-11-25 | 友达光电股份有限公司 | Liquid crystal display and method for driving same |
| CN101707054A (en) * | 2009-12-02 | 2010-05-12 | 友达光电股份有限公司 | Liquid crystal display (LCD) device and driving method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI630591B (en) * | 2017-05-11 | 2018-07-21 | 友達光電股份有限公司 | Displaying device and protecting circuit thereof |
| WO2020015179A1 (en) * | 2018-07-17 | 2020-01-23 | 深圳市华星光电技术有限公司 | Driving method for goa circuit and driving device for goa circuit |
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| Publication number | Publication date |
|---|---|
| CN101950520A (en) | 2011-01-19 |
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