CN101510443A - Shift register capable of reducing coupling effect - Google Patents
Shift register capable of reducing coupling effect Download PDFInfo
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- CN101510443A CN101510443A CNA2009101340531A CN200910134053A CN101510443A CN 101510443 A CN101510443 A CN 101510443A CN A2009101340531 A CNA2009101340531 A CN A2009101340531A CN 200910134053 A CN200910134053 A CN 200910134053A CN 101510443 A CN101510443 A CN 101510443A
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Abstract
The invention provides a shift register that can reduce coupling effect. In a plurality of serially connected shift registration units of the shift register, each shift registration unit consists of a boosting circuit, an input circuit, a pull-down circuit, a compensation circuit, an input end, an output end and a node. Each shift registration unit receives input voltage at the input end and provides output voltage at the output end. The input circuit transmits the input voltage to the node according to a first clock pulse signal. The boosting circuit provides the output voltage according to a second clock pulse signal and the potential of the node. The pull-down circuit provides voltage to the node according to a third clock pulse signal. The compensation circuit is coupled to the input circuit, the pull-down circuit and the node and is used for maintaining the potential of the node according to the second clock pulse signal or the third clock pulse signal. The shift register has the advantages of simple structure and anti-noise function and the like.
Description
Technical field
The present invention relates to a kind of shift register, relate in particular to a kind of shift register that can reduce coupling effect.
Background technology
Because LCD (liquid crystal display) has low radiation, volume is little and advantage such as low power consuming, replace traditional cathode-ray tube display (cathode ray tube display) gradually, thereby be widely used in notebook computer, personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information products such as mobile phone.The mode of conventional liquid crystal is to utilize the external drive chip to drive pixel on the panel with display image, but in order to reduce component number and to reduce manufacturing cost, developing into gradually in recent years directly is made in driving circuit structure on the display panel, for example gate driver circuit (gate driver) is integrated in liquid crystal panel (gate on array, technology GOA).
Please refer to Fig. 1, Fig. 1 is the simplification block schematic diagram of liquid crystal indicator 100 in the prior art.Fig. 1 has only shown the part-structure of liquid crystal indicator 100, comprises many gate lines G L (1)～GL (N), shift register (shift register) 110, gate generator 120 and power supply generator 130.Gate generator 120 can provide the required initial pulse signal VST of shift register 110 running and two clock pulse signal CLK1 and CLK2, and power supply generator 130 can provide shift register 110 runnings required operating voltage VDD and VSS.Shift register 110 includes multi-stage shift registering units connected in series SR (1)～SR (N), and its output terminal is respectively coupled to corresponding gate lines G L (1)～GL (N).According to clock pulse signal CLK1, CLK2 and initial pulse signal VST, shift register 110 can be exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) respectively in regular turn.
Please refer to Fig. 2, Fig. 2 be n level shifting deposit unit SR (n) among multistage shifting deposit unit SR (the 1)～SR (N) of prior art synoptic diagram (n between 1 and N between integer).Shifting deposit unit SR (n) comprises input end IN (n), output terminal OUT (n), input circuit (input circuit) 10, promotes circuit 20 (pull-up circuit), two pull-down circuits (pull-downcircuit) 30 and 34, and holding circuit 40.The input end IN (n) of shifting deposit unit SR (N) is coupled to the output terminal OUT (n-1) of previous stage shifting deposit unit SR (n-1), and the output terminal OUT (n) of shifting deposit unit SR (n) is coupled to input end IN (n+1) and the gate lines G L (n) of next stage shifting deposit unit SR (n+1).
Pull-down circuit 30 comprises transistor switch T3～T6, the transistor switch T3 and the T4 of serial connection receive reverse each other clock pulse signal CLK1 and CLK2 respectively at grid, and produce the grid control signal to transistor switch T5 and T6 according to this, therefore transistor switch T5 can control signal guided path between end points Q (n) and the voltage source V SS according to the current potential of its grid, and transistor switch T6 can come the signal guided path between control output end OUT (n) and the voltage source V SS according to the current potential of its grid.Pull-down circuit 34 comprises transistor switch T7～T10, the transistor switch T7 and the T8 of serial connection receive reverse each other clock pulse signal CLK2 and CLK1 respectively at grid, and produce the grid control signal to transistor switch T9 and T10 according to this, therefore transistor switch T9 can control signal guided path between end points Q (n) and the voltage source V SS according to the current potential of its grid, and transistor switch T10 can come the signal guided path between control output end OUT (n) and the voltage source V SS according to the current potential of its grid.
Holding circuit 40 comprises transistor switch T11～T13, and the grid of transistor switch T11 is coupled to output terminal OUT (n), is used at gate drive signal GS (n) when the noble potential, and the grid of transistor switch T5 and T6 is maintained electronegative potential VSS; The grid of transistor switch T12 is coupled to input end IN (n), is used at gate drive signal GS (n-1) when the noble potential, and the grid of transistor switch T9 and T10 is maintained electronegative potential VSS; The grid of transistor switch T13 is coupled to output terminal OUT (n), is used at gate drive signal GS (n) when the noble potential, and the grid of transistor switch T9 and T10 is maintained electronegative potential VSS.
Please refer to Fig. 3, Fig. 3 is the sequential chart of liquid crystal indicator 100 when running of prior art.In the liquid crystal indicator 100 of prior art, the dutycycle of clock pulse signal CLK1 and CLK2 (duty cycle) is all 1/2, and the tool opposite phase.First order shifting deposit unit SR (1) produces first order gate drive signal GS (1) according to initial pulse signal VST, and the second level to the N level shifting deposit unit SR (2)～SR (N) then produces the second level to the N level gate drive signal GS (2)～GS (N) (Fig. 3 only shows gate drive signal GS (1), GS (n-1) and GS (n)) according to the output signal of previous stage shifting deposit unit respectively.That is gate drive signal GS (1)～GS (N-1) is respectively activation shifting deposit unit SR (2)～required initial pulse signal of SR (N).
The liquid crystal indicator 100 of prior art is carried out pulling and is done between time point t1 to t3, carry out drop-down action after time point t3.Between time point t1 and t2, clock pulse signal CLK1 has electronegative potential, and clock pulse signal CLK2 and gate drive signal GS (n_1) tool noble potential, this moment, transistor switch T1 can be switched on, the current potential of end points Q (n) can be drawn high to noble potential VDD, and transistor switch T2 also can be switched on.When time point t2, clock pulse signal CLK1 switches to noble potential by electronegative potential, and therefore the gate drive signal GS (n) of tool noble potential can be provided by the transistor switch T2 (during clock pulse signal CLK1 tool noble potential) between time point t2 and t3 of conducting.On the other hand, pull-down circuit 30 and 40 is responsible for 50% drop-down action respectively with the complimentary fashion running.Between time point t3 and t4, clock pulse signal CLK1 is an electronegative potential, clock pulse signal CLK2 is a noble potential, and the input signal of shifting deposit unit SR (N) (gate drive signal GS (n-1)) and output signal (gate drive signal GS (n)) are all electronegative potential, this moment, the grid of transistor switch T5 and T6 maintained electronegative potential VSS in fact, and the grid of transistor switch T9 and T10 maintains noble potential VDD in fact.In like manner, between time point t4 and t5, clock pulse signal CLK1 is a noble potential, clock pulse signal CLK2 is an electronegative potential, and the output signal of shifting deposit unit SR (N) (gate drive signal GS (n)) is an electronegative potential, this moment, the grid of transistor switch T5 and T6 maintained noble potential VDD in fact, and the grid of transistor switch T9 and T10 maintains electronegative potential VSS in fact.At n level shifting deposit unit SR (n), the current potential of end points Q (n) only needs change to some extent between time point t1 and t3, then wishes At All Other Times stably to maintain electronegative potential.Under the ideal case, transistor switch T2 can fully be closed, and this moment, clock pulse signal CLK1 can not influence the current potential of end points Q (n).Yet under practical situation, clock pulse signal CLK1 can be coupled to end points Q (n) by the stray capacitance of transistor switch T2, make the current potential of end points Q (n) can produce fluctuation (for example when time point t4, t5 and t6), therefore can influence the running of liquid crystal indicator 100 along with clock pulse signal CLK1.
Summary of the invention
For overcoming the defective of prior art, the invention provides a kind of shift register that can reduce coupling effect, it comprises the shifting deposit unit of a plurality of serial connections, and wherein each shifting deposit unit comprises: input end is used for receiving input voltage; Output terminal is used to provide output voltage; Node; Input circuit is used for according to the 3rd clock pulse signal this input voltage being reached this node; Promote circuit, be used for providing this output voltage at this output terminal according to the current potential of first clock pulse signal and this node; First pull-down circuit is used for providing first voltage to this node according to the second clock pulse signal; And compensating circuit, be coupled to this input circuit, this first pull-down circuit and this node, be used for keeping the current potential of this node according to this second or the 3rd clock pulse signal.
Aforesaid shift register, wherein this lifting circuit comprises first switch, and this first switch comprises: first end is used for receiving this first clock signal; Second end is coupled to this output terminal; And control end, be coupled to this node.
Aforesaid shift register, wherein this first switch comprises thin film transistor (TFT).
Aforesaid shift register, wherein this input circuit comprises: second switch.This second switch comprises: first end is coupled to this input end; Second end is coupled to this node; And control end, be coupled to this input end.
Aforesaid shift register, wherein this input circuit also comprises: the 3rd switch.The 3rd switch comprises: first end is coupled to this input end; Second end is coupled to this node; And control end, be used for receiving the 3rd clock signal.
Aforesaid shift register, wherein this compensating circuit comprises: first electric capacity, be coupled between the control end of this node and the 3rd switch, be used for keeping the current potential of this node according to the 3rd clock signal.
Aforesaid shift register, wherein this second switch and the 3rd switch comprise thin film transistor (TFT).
Aforesaid shift register, wherein this input circuit comprises: second switch.This second switch comprises: first end is coupled to this input end; Second end is coupled to this node; And control end, be used for receiving this first clock signal, this second clock signal, or the 3rd clock signal.
Aforesaid shift register, wherein this input circuit also comprises: the 3rd switch.The 3rd switch comprises: first end is coupled to this input end; Second end is coupled to this node; And control end, be used for receiving the 3rd clock signal.
Aforesaid shift register, wherein this compensating circuit comprises: first electric capacity, be coupled between the control end of this node and the 3rd switch, be used for keeping the current potential of this node according to the 3rd clock signal.
Aforesaid shift register, wherein this second switch and the 3rd switch comprise thin film transistor (TFT).
Aforesaid shift register, wherein this first pull-down circuit comprises the 4th switch, and the 4th switch comprises: first end is coupled to this node; Second end is used for receiving this first voltage; And control end, be used for receiving this second clock signal.
Aforesaid shift register, wherein this compensating circuit comprises: second electric capacity, be coupled between the control end of this node and the 4th switch, be used for keeping the current potential of this node according to this second clock signal.
Aforesaid shift register, wherein the 4th switch comprises thin film transistor (TFT).
Aforesaid shift register also comprises second pull-down circuit, and being used for provides second voltage or tertiary voltage to this output terminal according to this second or the 3rd clock signal.
Aforesaid shift register, wherein this second pull-down circuit comprises: the 5th switch and the 6th switch.The 5th switch comprises: first end is coupled to this output terminal; Second end is used for receiving this second voltage; And control end, be used for receiving this second clock signal.The 6th switch comprises: first end is coupled to this output terminal; Second end is used for receiving tertiary voltage; And control end, be used for receiving the 3rd clock signal.
Aforesaid shift register, wherein this first voltage, this second voltage and this tertiary voltage are had equal potentials in fact.
Aforesaid shift register, wherein the 5th switch and the 6th switch comprise thin film transistor (TFT).
Aforesaid shift register also comprises pre-pull-down circuit, and being used for provides the 4th voltage to this output terminal or this first end points according to feedback voltage.
Aforesaid shift register, wherein this feedback voltage is the output voltage of the next stage shifting deposit unit in the shifting deposit unit of these a plurality of serial connections.
Aforesaid shift register, wherein this pre-pull-down circuit comprises: minion is closed and octavo is closed.This minion is closed and comprised: first end is coupled to this output terminal; Second end is used for receiving the 4th voltage; And control end, be used for receiving this feedback voltage.This octavo is closed and comprised: first end is coupled to this node; Second end is used for receiving the 4th voltage; And control end, be used for receiving this feedback voltage.
Aforesaid shift register, wherein this first voltage and the 4th voltage are had equal potentials in fact.
Aforesaid shift register, wherein this minion pass and this octavo are closed and are comprised thin film transistor (TFT).
Aforesaid shift register, wherein this compensating circuit comprises: first electric capacity, be coupled to this input circuit and this node, be used for keeping the current potential of this node according to the 3rd clock signal; And second electric capacity, be coupled to this first pull-down circuit and this node, be used for keeping the current potential of this node according to this second clock signal.
Aforesaid shift register, wherein each clock signal maintains the low level time and is longer than the time that maintains high level.
Aforesaid shift register, wherein the dutycycle of each clock signal is neither greater than 1/3.
Aforesaid shift register, wherein each clock signal time of maintaining high level is equal to each other.
Aforesaid shift register, wherein the input voltage of this shifting deposit unit is the output voltage of previous stage shifting deposit unit.
The present invention has simple in structure and the noise resisting ability advantages of higher.
Description of drawings
Fig. 1 is the simplification block schematic diagram of liquid crystal indicator in the prior art.
Fig. 2 is the synoptic diagram of n level shifting deposit unit in the multistage shifting deposit unit of prior art.
Fig. 3 is the sequential chart of liquid crystal indicator when running of prior art.
Fig. 4 is the simplification block schematic diagram of liquid crystal indicator among the present invention.
Fig. 5 is the synoptic diagram of n level shifting deposit unit in the first embodiment of the invention.
Fig. 6 is the sequential chart of liquid crystal indicator when running of first embodiment of the invention.
Fig. 7 is the synoptic diagram of n level shifting deposit unit in the second embodiment of the invention.
Fig. 8 is the synoptic diagram of n level shifting deposit unit in the third embodiment of the invention.
Fig. 9 is the synoptic diagram of n level shifting deposit unit in the fourth embodiment of the invention.
Figure 10 is the synoptic diagram of n level shifting deposit unit in the fifth embodiment of the invention.
Figure 11 is the synoptic diagram of n level shifting deposit unit in the sixth embodiment of the invention.
Figure 12 is the sequential chart of sixth embodiment of the invention when running.
Figure 13 a to Figure 13 d is the synoptic diagram of input circuit embodiment of the present invention.
Wherein, description of reference numerals is as follows:
100,200 liquid crystal indicators, 10～12 input circuits
110,210 shift registers 20,21 promote circuit
120,220 gate generators, 30～34 pull-down circuits
130,230 power supply generators, 40 holding circuits
CLK1～CLKM clock pulse signal 41 compensating circuits
VST initial pulse signal 51 pre-pull-down circuits
T1～T8 transistor switch C1, C2 electric capacity
VSS, VDD voltage source t1～t6 time point
Q (n) end points IN (n) input end
OUT (n), OUT (1)～OUT (N) output terminal
GL (n), GL (1)～GL (N) gate line
SR (n-1), SR (n), SR (n+1), SR (1)～SR (N) shifting deposit unit
GS (n-1), GS (n), GS (1)～GS (N) gate drive signal
Embodiment
Please refer to Fig. 4, Fig. 4 is the simplification block schematic diagram of liquid crystal indicator 200 among the present invention.Fig. 4 has shown many gate lines G L (1)～GL (N), shift register 210, gate generator 220 and the power supply generator 230 of liquid crystal indicator 200.Gate generator 220 can provide the required initial pulse signal VST of shift register 210 runnings and many group clock pulse signal CLK1～CLKM, and power supply generator 230 can provide shift register 210 runnings required operating voltage VDD and VSS.Shift register 210 includes multi-stage shift registering units connected in series SR (1)～SR (N), and its output terminal is respectively coupled to corresponding gate lines G L (1)～GL (N).According to clock pulse signal CLK1～CLKM and initial pulse signal VST, shift register 210 can be exported gate drive signal GS (1)～GS (N) respectively to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N).First order shifting deposit unit SR (1) produces first order gate drive signal GS (1) according to initial pulse signal VST, and the signal that the second level to the N level shifting deposit unit SR (2)～SR (N) is then produced according to the previous stage shifting deposit unit respectively produces the second level to the N level gate drive signal GS (2)～GS (N).
Please refer to Fig. 5, Fig. 5 is the electrical block diagram of n level shifting deposit unit SR (n) in the first embodiment of the invention.Shifting deposit unit SR (n) comprises input end IN (n), output terminal OUT (n), input circuit 11, promotes circuit 21, pull-down circuit 31, and compensating circuit 41.The input end IN (n) of shifting deposit unit SR (N) is coupled to the output terminal OUT (n-1) of previous stage shifting deposit unit SR (N-1), and the output terminal OUT (n) of shifting deposit unit SR (N) then is coupled to the input end IN (n+1) of next stage shifting deposit unit SR (n+1).First embodiment of the invention uses three groups of clock pulse signal CLK1～CLK3 to drive each shifting deposit unit.
Input circuit 11 comprises transistor switch T1, its grid and drain electrode all are coupled to input end IN (n) to receive gate drive signal GS (n-1), therefore and source electrode is coupled to end points Q (n), can come signal guided path between control input end IN (n) and the end points Q (n) according to gate drive signal GS (n-1).Promote circuit 21 and comprise transistor switch T2, its grid is coupled to end points Q (n), drain electrode is coupled to gate generator 220 with receive clock pulse signal CLK1, therefore and source electrode is coupled to output terminal OUT (n), can control signal guided path between clock pulse signal CLK1 and the output terminal OUT (n) according to the current potential of end points Q (n).Pull-down circuit 31 comprises transistor switch T3, its grid is coupled to gate generator 220 with receive clock pulse signal CLK2, drain electrode is coupled to end points Q (n), and source electrode is coupled to a voltage source V SS that the negative potential operating voltage is provided, and therefore can come the signal guided path between control voltage source VSS and the end points Q (n) according to the current potential of clock pulse signal CLK2.Compensating circuit 41 comprises two capacitor C 1 and C2, is coupled to input circuit 11, pull-down circuit 31 and end points Q (n).Capacitor C 1 is coupled between gate generator 220 and the end points Q (n), keeps the current potential of end points Q (n) with foundation clock pulse signal CLK3.Capacitor C 2 is coupled between the grid and end points Q (n) of transistor switch T3, keeps the current potential of end points Q (n) with foundation clock pulse signal CLK2.
Please refer to Fig. 6, Fig. 6 is the sequential chart of liquid crystal indicator 200 when running of first embodiment of the invention.The present invention's this moment uses three groups of clock pulse signal CLK1～CLK3 to drive each grade shifting deposit unit, the dutycycle of clock pulse signal CLK1～CLK3 is neither greater than 1/3, and each clock pulse signal maintains the time of noble potential in its cycle identical with the time that initial pulse signal VST maintains noble potential.First order shifting deposit unit SR (1) produces first order gate drive signal GS (1) according to initial pulse signal VST, and the second level to the N level shifting deposit unit SR (2)～SR (N) then produces the second level to the N level gate drive signal GS (2)～GS (N) (Fig. 6 only shows gate drive signal GS (1), GS (n-1) and GS (n)) according to the output signal of previous stage shifting deposit unit respectively.That is gate drive signal GS (1)～GS (N-1) is respectively activation shifting deposit unit SR (2)～required initial pulse signal of SR (N).
Liquid crystal indicator 200 of the present invention clock pulse signal CLK1 or CLK3 have noble potential during carry out roping and do.For instance, between time point t1 and t2, clock pulse signal CLK1 and CLK2 have electronegative potential, and clock pulse signal CLK3 and gate drive signal GS (n-1) have noble potential, this moment, transistor switch T1 can be switched on, the current potential of end points Q (n) can be drawn high to noble potential VDD, and transistor switch T2 also can be switched on.When time point t2, clock pulse signal CLK1 switches to noble potential by electronegative potential, and this moment, the Q point voltage was owing to the cause of the stray capacitance of transistor switch T2 is further raised, so this moment, transistor switch T2 was conducting.Therefore can provide the gate drive signal GS with noble potential (n) by the transistor switch T2 (during clock pulse signal CLK1 tool noble potential) between time point t2 and t3 of conducting.
Liquid crystal indicator 200 of the present invention clock pulse signal CLK2 have noble potential during carry out drop-down running.For instance, between time point t3 and t4, clock pulse signal CLK2 has noble potential, and this moment, transistor switch T3 can be switched on, and the current potential of end points Q (n) can be pulled low to electronegative potential VSS.After finishing drop-down action, the current potential that using compensation circuit 41 of the present invention is offset end points Q (n) is along with the situation of clock pulse signal fluctuation, and the current potential of end points Q (n) is stably maintained electronegative potential.For instance, when time point t4, clock pulse signal CLK2 switches to electronegative potential by noble potential, and clock pulse signal CLK3 switches to noble potential by electronegative potential, and this moment can be by the cancel each other potential fluctuation of end points Q (n) of capacitor C 1 and C2; When time point t5, clock pulse signal CLK1 switches to noble potential by electronegative potential, and clock pulse signal CLK3 switches to electronegative potential by noble potential, and can offset the potential fluctuation of end points Q (n) this moment by capacitor C 1; When time point t6, clock pulse signal CLK1 switches to electronegative potential by noble potential, and clock pulse signal CLK2 switches to noble potential by electronegative potential, and can offset the potential fluctuation of end points Q (n) this moment by capacitor C 2.
Please refer to Fig. 7, Fig. 7 is the electrical block diagram of n level shifting deposit unit SR (n) in the second embodiment of the invention.The shifting deposit unit SR (n) of second embodiment comprises input end IN (n), output terminal OUT (n), input circuit 11, promotes circuit 21, pull-down circuit 31, compensating circuit 41, and pre-pull-down circuit 51.The second embodiment of the invention and first example structure are similar, and difference is that second embodiment of the invention also comprises pre-pull-down circuit 51.Pre-pull-down circuit 51 comprises transistor switch T4 and T5: the grid of transistor switch T4 is coupled to the output terminal OUT (n+1) of next stage shifting deposit unit SR (n+1) to receive gate drive signal GS (n+1), drain electrode is coupled to end points Q (n), and source electrode is coupled to voltage source V SS, therefore can come the signal guided path between control voltage source VSS and the end points Q (n) according to the current potential of gate drive signal GS (n+1); The grid of transistor switch T5 is coupled to the output terminal OUT (n+1) of next stage shifting deposit unit SR (n+1) to receive gate drive signal GS (n+1), drain electrode is coupled to output terminal OUT (n), and source electrode is coupled to voltage source V SS, therefore can come the signal guided path between control voltage source VSS and the output terminal OUT (n) according to the current potential of gate drive signal GS (n+1).The operation principles of the second embodiment of the invention and first embodiment is similar, can be explained by sequential chart shown in Figure 6 equally.Simultaneously, second embodiment of the invention also can be kept the level of end points Q (n) and output terminal OUT (n) by pre-pull-down circuit 51, for example when having noble potential end points Q (n) and output terminal OUT (n) is maintained the level of VSS at gate drive signal GS (n+1).
Please refer to Fig. 8, Fig. 8 is the electrical block diagram of n level shifting deposit unit SR (n) in the third embodiment of the invention.The shifting deposit unit SR (n) of the 3rd embodiment comprises input end IN (n), output terminal OUT (n), input circuit 11, promote circuit 21, two pull-down circuits 31 and 32, and compensating circuit 41.The third embodiment of the invention and first example structure are similar, and difference is that third embodiment of the invention also comprises pull-down circuit 32.Pull-down circuit 32 comprises transistor switch T6 and T7; The grid of transistor switch T6 is coupled to gate generator 220 with receive clock pulse signal CLK2, drain electrode is coupled to output terminal OUT (n), and source electrode is coupled to voltage source V SS, therefore can come the signal guided path between control voltage source VSS and the output terminal OUT (n) according to the current potential of clock pulse signal CLK2; The grid of transistor switch T7 is coupled to gate generator 220 with receive clock pulse signal CLK3, drain electrode is coupled to output terminal OUT (n), and source electrode is coupled to voltage source V SS, therefore can come the signal guided path between control voltage source VSS and the output terminal OUT (n) according to the current potential of clock pulse signal CLK3.The operation principles of the third embodiment of the invention and first embodiment is similar, can be explained by sequential chart shown in Figure 6 equally.Simultaneously, third embodiment of the invention also can be kept the level of output terminal OUT (n) by pull-down circuit 32, for example output terminal OUT (n) is maintained the level of VSS respectively when clock pulse signal CLK2 and CLK3 tool noble potential.
Please refer to Fig. 9, Fig. 9 is the electrical block diagram of n level shifting deposit unit SR (n) in the fourth embodiment of the invention.The shifting deposit unit SR (n) of the 4th embodiment comprises input end IN (n), output terminal OUT (n), input circuit 12, promotes circuit 21, pull-down circuit 31, and compensating circuit 41.The fourth embodiment of the invention and first example structure are similar, and difference is that the input circuit 12 of fourth embodiment of the invention comprises two transistor switch T1 and T8.The grid of transistor switch T1 and drain electrode all are coupled to input end IN (n) to receive gate drive signal GS (n-1), therefore and source electrode is coupled to end points Q (n), input end IN (n) that can control according to gate drive signal GS (n-1) and the signal guided path between the end points Q (n); The grid of transistor switch T8 is coupled to gate generator 220 with receive clock pulse signal CLK3, drain electrode is coupled to input end IN (n) to receive gate drive signal GS (n-1), and source electrode is coupled to end points Q (n), therefore can come the signal guided path between control input end IN (n) and the end points Q (n) according to the current potential of clock pulse signal CLK3.The operation principles of the fourth embodiment of the invention and first embodiment is similar, can be explained by sequential chart shown in Figure 6 equally.Simultaneously, fourth embodiment of the invention also can be kept the level of end points Q (n) by the transistor switch T8 of input circuit 12, for example end points Q (n) is maintained the level of gate drive signal GS (n-1) when clock pulse signal CLK3 has noble potential.
Please refer to Figure 10, Figure 10 is the electrical block diagram of n level shifting deposit unit SR (n) in the fifth embodiment of the invention.The shifting deposit unit SR (n) of the 5th embodiment comprises input end IN (n), output terminal OUT (n), input circuit 12, promotes circuit 21, two pull-down circuits 31 and 32, compensating circuit 41, and pre-pull-down circuit 51.The fifth embodiment of the invention and first example structure are similar, and difference is that fifth embodiment of the invention also comprises pull-down circuit 32 and pre-pull-down circuit 51, and the input circuit 12 of fifth embodiment of the invention comprises two transistor switch T1 and T8.The structure of input circuit 12, pull-down circuit 32 and pre-pull-down circuit 51 such as Fig. 7～shown in Figure 9.The operation principles of the fifth embodiment of the invention and first embodiment is similar, can be explained by sequential chart shown in Figure 6 equally.Simultaneously, fifth embodiment of the invention also can be kept the level of end points Q (n) and output terminal OUT (n) by pre-pull-down circuit 51, can keep the level of output terminal OUT (n) by pull-down circuit 32 in addition, and also can keep the level of end points Q (n) by the transistor switch T8 of input circuit 12.
Please refer to Figure 11, Figure 11 is the electrical block diagram of n level shifting deposit unit SR (n) in the sixth embodiment of the invention.Sixth embodiment of the invention is identical with the 5th example structure, and difference is that sixth embodiment of the invention uses four groups of clock pulse signal CLK1～CLK4 to drive shifting deposit unit SR (n).Input circuit 12 operates according to clock pulse signal CLK4, promotes circuit 21 and operates according to clock pulse signal CLK1, and pull-down circuit 32 operates according to clock pulse signal CLK2, CLK3, and pull-down circuit 31 operates according to clock pulse signal CLK2.The shifting deposit unit SR (n) of sixth embodiment of the invention can keep the current potential of end points Q (n) equally by compensating circuit 41.
Please refer to Figure 12, Figure 12 is the sequential chart of sixth embodiment of the invention when running.The present invention's this moment uses four groups of clock pulse signal CLK1～CLK4 to drive each grade shifting deposit unit, the dutycycle of clock pulse signal CLK1～CLK4 is neither greater than 1/4, and each clock pulse signal maintains the time of noble potential in its cycle identical with the time that initial pulse signal VST maintains noble potential.The liquid crystal indicator 200 of sixth embodiment of the invention is being carried out the roping work during clock pulse signal CLK1, CLK2 or the CLK4 tool noble potential.For instance, between time point t1 and t2, clock pulse signal CLK1～CLK3 has electronegative potential, and clock pulse signal CLK4 and gate drive signal GS (n-1) have noble potential, this moment, transistor switch T1 and T6 can be switched on, the current potential of end points Q (n) can be drawn high to noble potential VDD, and transistor switch T2 also can be switched on.When time point t2, clock pulse signal CLK1 switches to noble potential by electronegative potential, therefore can provide the gate drive signal GS with noble potential (n) by the transistor switch T2 (when clock pulse signal CLK1 has noble potential) between time point t2 and t3 of conducting.When time point t3, clock pulse signal CLK2 switches to noble potential by electronegative potential, therefore can drag down the current potential of output terminal OUT (n) by the transistor switch T6 of conducting.
Then, the liquid crystal indicator 200 of sixth embodiment of the invention clock pulse signal CLK3 have noble potential during carry out drop-down running.For instance, between time point t3 and t4, clock pulse signal CLK3 switches to noble potential by electronegative potential, and this moment, voltage source V SS can drag down the current potential of end points Q (n) by the transistor switch T3 of conducting.After finishing drop-down action, the current potential that using compensation circuit 41 of the present invention is offset end points Q (n) is along with the situation of clock pulse signal fluctuation, and the current potential of end points Q (n) is stably maintained electronegative potential.For instance, when time point t4, clock pulse signal CLK2 switches to electronegative potential by noble potential, and clock pulse signal CLK3 switches to noble potential by electronegative potential, and can offset the potential fluctuation of end points Q (n) this moment by capacitor C 2; When time point t5, clock pulse signal CLK3 switches to electronegative potential by noble potential, and clock pulse signal CLK4 switches to noble potential by electronegative potential, and can offset the potential fluctuation of end points Q (n) this moment by capacitor C 1 and C2; When time point t6, clock pulse signal CLK1 switches to noble potential by electronegative potential, and clock pulse signal CLK4 switches to electronegative potential by noble potential, and can offset the potential fluctuation of end points Q (n) this moment by capacitor C 1.
In aforementioned the present invention first to the 6th embodiment, input circuit 11 and 12 transistor switch T1 are that (thin film transistor, TFT), its drain and gate is connected to each other for the thin film transistor (TFT) of diode connected mode.Yet the transistor switch T1 in the input circuit 11 of the present invention and 12 also can adopt other structure, shown in Figure 13 a～Figure 13 d.In the embodiment of Figure 13 a～Figure 13 c, the drain electrode of transistor switch T1 is coupled to input end IN (n) to receive gate drive signal GS (n-1), source electrode is coupled to end points Q (n), and grid then is coupled to gate generator 220 to receive clock pulse signal CLK1, CLK2 or the CLK3 corresponding to gate drive signal GS (n-1).In the embodiment of Figure 13 d, the drain electrode of transistor switch T1 is coupled to input end IN (n) to receive gate drive signal GS (n-1), and source electrode is coupled to end points Q (n), and grid then is coupled to the voltage source V DD with noble potential.
Fig. 5 is to Figure 10 shows that the embodiment that uses three groups of clock pulse signal CLK1～CLK3, Figure 11 and the embodiment that Figure 12 shows that four groups of clock pulse signal CLK1～CLK4 of use, however the present invention also can use more groups of clock pulse signals to drive each shifting deposit unit.Transistor switch T1～the T8 of previous embodiment can comprise the element of thin film transistor switch or other similar functions.The present invention keeps the current potential of end points Q (n) by compensating circuit 41, can eliminate the coupling effect of clock pulse signal to shifting deposit unit, has simple in structure and the noise resisting ability advantages of higher.
The above only is the preferred embodiments of the present invention, and all equivalences of doing according to claim of the present invention change and modify, and all should belong to scope of the present invention.
Claims (28)
1. shift register that can reduce coupling effect, it comprises the shifting deposit unit of a plurality of serial connections, and wherein each shifting deposit unit comprises:
Input end is used for receiving input voltage;
Output terminal is used to provide output voltage;
Node;
Promote circuit, be used for providing this output voltage at this output terminal according to the current potential of first clock pulse signal and this node;
Input circuit is used for according to the second clock pulse signal this input voltage being reached this node;
First pull-down circuit is used for providing first voltage to this node according to the 3rd clock pulse signal; And
Compensating circuit is coupled to this input circuit, this first pull-down circuit and this node, is used for keeping according to this second clock signal or the 3rd clock pulse signal the current potential of this node.
2. shift register as claimed in claim 1, wherein this lifting circuit comprises first switch, and this first switch comprises:
First end is used for receiving this first clock pulse signal;
Second end is coupled to this output terminal; And
Control end is coupled to this node.
3. shift register as claimed in claim 2, wherein this first switch comprises thin film transistor (TFT).
4. shift register as claimed in claim 1, wherein this input circuit comprises:
Second switch, it comprises:
First end is coupled to this input end;
Second end is coupled to this node; And
Control end is coupled to this input end.
5. shift register as claimed in claim 1, wherein this input circuit also comprises:
The 3rd switch, it comprises:
First end is coupled to this input end;
Second end is coupled to this node; And
Control end is used for receiving the 3rd clock pulse signal.
6. shift register as claimed in claim 5, wherein this compensating circuit comprises:
First electric capacity is coupled between the control end of this node and the 3rd switch, is used for keeping according to the 3rd clock pulse signal the current potential of this node.
7. shift register as claimed in claim 5, wherein this second switch and the 3rd switch comprise thin film transistor (TFT).
8. shift register as claimed in claim 1, wherein this input circuit comprises:
Second switch, it comprises:
First end is coupled to this input end;
Second end is coupled to this node; And
Control end is used for receiving this first clock pulse signal, this second clock pulse signal, or the 3rd clock pulse signal.
9. shift register as claimed in claim 8, wherein this input circuit also comprises:
The 3rd switch, it comprises:
First end is coupled to this input end;
Second end is coupled to this node; And
Control end is used for receiving the 3rd clock pulse signal.
10. shift register as claimed in claim 9, wherein this compensating circuit comprises:
First electric capacity is coupled between the control end of this node and the 3rd switch, is used for keeping according to the 3rd clock pulse signal the current potential of this node.
11. shift register as claimed in claim 8, wherein this second switch and the 3rd switch comprise thin film transistor (TFT).
12. shift register as claimed in claim 1, wherein this first pull-down circuit comprises the 4th switch, and the 4th switch comprises:
First end is coupled to this node;
Second end is used for receiving this first voltage; And
Control end is used for receiving this second clock pulse signal.
13. shift register as claimed in claim 12, wherein this compensating circuit comprises:
Second electric capacity is coupled between the control end of this node and the 4th switch, is used for keeping according to this second clock pulse signal the current potential of this node.
14. shift register as claimed in claim 12, wherein the 4th switch comprises thin film transistor (TFT).
15. shift register as claimed in claim 1 also comprises second pull-down circuit, being used for provides second voltage or tertiary voltage to this output terminal according to this second or the 3rd clock pulse signal.
16. shift register as claimed in claim 15, wherein this second pull-down circuit comprises:
The 5th switch, it comprises:
First end is coupled to this output terminal;
Second end is used for receiving this second voltage; And
Control end is used for receiving this second clock pulse signal; And
The 6th switch, it comprises:
First end is coupled to this output terminal;
Second end is used for receiving tertiary voltage; And
Control end is used for receiving the 3rd clock pulse signal.
17. shift register as claimed in claim 16, wherein this first voltage, this second voltage and this tertiary voltage are had equal potentials in fact.
18. shift register as claimed in claim 17, wherein the 5th switch and the 6th switch comprise thin film transistor (TFT).
19. shift register as claimed in claim 1 also comprises pre-pull-down circuit, being used for provides the 4th voltage to this output terminal or this first end points according to feedback voltage.
20. shift register as claimed in claim 19, wherein this feedback voltage is the output voltage of the next stage shifting deposit unit in the shifting deposit unit of these a plurality of serial connections.
21. shift register as claimed in claim 19, wherein this pre-pull-down circuit comprises:
Minion is closed, and it comprises:
First end is coupled to this output terminal;
Second end is used for receiving the 4th voltage; And
Control end is used for receiving this feedback voltage; And
Octavo is closed, and it comprises:
First end is coupled to this node;
Second end is used for receiving the 4th voltage; And
Control end is used for receiving this feedback voltage.
22. shift register as claimed in claim 21, wherein this first voltage and the 4th voltage are had equal potentials in fact.
23. shift register as claimed in claim 21, wherein this minion pass and this octavo are closed and are comprised thin film transistor (TFT).
24. shift register as claimed in claim 1, wherein this compensating circuit comprises:
First electric capacity is coupled to this input circuit and this node, is used for keeping according to the 3rd clock pulse signal the current potential of this node; And
Second electric capacity is coupled to this first pull-down circuit and this node, is used for keeping according to this second clock pulse signal the current potential of this node.
25. shift register as claimed in claim 1, wherein each clock pulse signal maintains the low level time and is longer than the time that maintains high level.
26. shift register as claimed in claim 1, wherein the dutycycle of each clock pulse signal is neither greater than 1/3.
27. shift register as claimed in claim 1, wherein each clock pulse signal time of maintaining high level is equal to each other.
28. shift register as claimed in claim 1, wherein the input voltage of this shifting deposit unit is the output voltage of previous stage shifting deposit unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009101340531A CN101510443A (en) | 2009-04-08 | 2009-04-08 | Shift register capable of reducing coupling effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009101340531A CN101510443A (en) | 2009-04-08 | 2009-04-08 | Shift register capable of reducing coupling effect |
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| CN101510443A true CN101510443A (en) | 2009-08-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2009101340531A Pending CN101510443A (en) | 2009-04-08 | 2009-04-08 | Shift register capable of reducing coupling effect |
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