CN110619834A - Multi-clock potential conversion circuit and multi-clock gate driving circuit - Google Patents
Multi-clock potential conversion circuit and multi-clock gate driving circuit Download PDFInfo
- Publication number
- CN110619834A CN110619834A CN201910768317.2A CN201910768317A CN110619834A CN 110619834 A CN110619834 A CN 110619834A CN 201910768317 A CN201910768317 A CN 201910768317A CN 110619834 A CN110619834 A CN 110619834A
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- Prior art keywords
- clock
- shift register
- circuit
- register unit
- display
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
A multi-clock potential converting circuit and a multi-clock gate driving circuit. The multi-clock pulse potential conversion circuit comprises a shift register unit and a clock pulse voltage lifting circuit. The shift register unit is configured to output a plurality of shift register clock signals according to the control clock signal. The clock pulse voltage lifting circuit is connected with the shift register unit and correspondingly outputs the display clock pulse signals according to the shift register clock pulse signals. The multi-clock potential conversion circuit saves the clock control circuit from outputting the multi-clock display signals, saves the input and output interface resources of the clock control circuit, simplifies the external circuit of the gate driving circuit substrate and reduces the production cost of the display device.
Description
[ technical field ] A method for producing a semiconductor device
The present disclosure relates to the field of display technologies, and more particularly to a multi-clock potential converting circuit and a multi-clock gate driving circuit.
[ background of the invention ]
With the development of Gate On Array (GOA) panels, multi-clock panel driving is becoming an important trend.
Please refer to fig. 1, fig. 2 and fig. 3, which are schematic diagrams of a conventional two-input-channel four-output-channel voltage converting circuit block, a conventional four-input-channel four-output-channel voltage converting circuit block, and a conventional twelve-input-twelve-output-channel voltage converting circuit block, respectively. In addition, the circuit architecture of fig. 1 and fig. 2 is difficult to satisfy the actual driving requirement, and further the multiple potential converters are used for potential conversion, which results in the increase of the manufacturing cost of the gate driving circuit substrate.
Although the circuit structure of fig. 3 has enough output channels, it needs to occupy twelve input/output interfaces of the clock control circuit at the same time, and if the input/output interfaces are newly opened for the clock control circuit, the production cost of the display device will be greatly increased even if the input/output interfaces are newly opened.
Therefore, it is desirable to provide a clock control apparatus and a driving method thereof to solve the problems of the prior art.
[ summary of the invention ]
To solve the above problems, the present disclosure provides a multi-clock voltage converting circuit and a multi-clock gate driving circuit, which can output multi-clock display signals, save the input/output interface resources of the clock control circuit, simplify the external circuit of the gate driving circuit substrate, and reduce the production cost of the display device.
To achieve the above object, the present disclosure provides a multi-clock level conversion circuit configured to output a plurality of display clock signals for controlling a display screen of a display device according to a control clock signal. Includes a shift register unit configured to output a plurality of shift register clock signals according to the control clock signal. And the clock pulse voltage lifting circuit is connected with the shift register unit and correspondingly outputs the display clock pulse signals according to the shift register clock pulse signals.
In one embodiment of the present disclosure, the shift register unit further includes a multiplexing interface device, and the multiplexing interface device is connected to the clock control circuit.
In one embodiment of the present disclosure, the multiplexing interface device comprises 2 input/output interfaces.
In one embodiment of the present disclosure, the shift register unit is composed of a plurality of D flip-flops.
In one embodiment of the present disclosure, the shift register unit further outputs other signals than the shift register clock signal.
In one embodiment of the present disclosure, the shift register unit is connected to the clock voltage boost circuit through a plurality of shift register contacts.
To achieve the above object, the present disclosure also provides a multi-clock gate driving circuit configured to output a plurality of display clock signals for controlling a display screen of a display device, including:
a clock control circuit configured to output a control clock signal. A shift register unit comprising a multiplexing interface device, the shift register unit being connected to the clock control circuit through the multiplexing interface device, the shift register unit being configured to output a plurality of shift register clock signals according to the control clock signal. The clock voltage raising circuit is configured to be connected with the shift register unit, and the clock voltage raising circuit receives the plurality of shift register clock signals and correspondingly generates the plurality of display clock signals according to the initial clock signal. The shift register unit is composed of a plurality of D triggers.
In one embodiment of the present disclosure, the shift register unit is connected to the clock voltage boost circuit through a plurality of shift register contacts.
In one embodiment of the present disclosure, the shift register unit further outputs other signals than the shift register clock signal.
In one embodiment of the present disclosure, the multiplexing interface device includes two input/output interfaces.
In order to make the aforementioned and other aspects of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below:
[ description of the drawings ]
FIG. 1 is a block diagram of a conventional dual-input-channel four-output-channel potential conversion circuit;
FIG. 2 is a block diagram of a conventional four-input-channel and four-output-channel voltage level shifting circuit;
FIG. 3 is a block diagram of a conventional twelve-input twelve-output channel level shift circuit;
FIG. 4 is a block diagram of a multi-clock level shift circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a shift register cell layout according to an embodiment of the present disclosure;
FIG. 6 is a diagram illustrating clock waveforms outputted through a shift register unit according to an embodiment of the present disclosure.
FIG. 7 is a block diagram of a multi-clock gate driving circuit according to an embodiment of the present disclosure.
[ detailed description ] embodiments
The following description of the embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure.
In the drawings, elements having similar structures are denoted by the same reference numerals.
Referring to fig. 4, fig. 4 is a block diagram of a multi-clock voltage converting circuit according to an embodiment of the disclosure. Wherein, the multi-clock potential converting circuit 40 is configured to output a plurality of display clock signals for controlling the display screen of the display device according to the control clock signal. The plurality of display clock signals include a first display clock signal CK1, a second display clock signal CK2, a third display clock signal CK3, a fourth display clock signal CK4, a fifth display clock signal CK5, a sixth display clock signal CK6, a seventh display clock signal CK7, an eighth display clock signal CK8, an eighth display clock signal CK8, a ninth display clock signal CK9, a tenth display clock signal CK10, an eleventh display clock signal CK11, and a twelfth display clock signal CK 12. The multi-clock level shifter 40 includes a shift register unit 401 and a clock voltage raising circuit 402. The shift register unit 401 is configured to output a plurality of shift register clock signals according to the control clock signal, the shift register clock signals including a first shift register clock signal CK1', a second shift register clock signal CK2', a third shift register clock signal CK3', a fourth shift register clock signal CK4', a fifth shift register clock signal CK5', a sixth shift register clock signal CK6', a seventh shift register clock signal CK7', an eighth shift register clock signal CK8', a ninth shift register clock signal CK9', a tenth shift register clock signal CK10', an eleventh shift register clock signal CK11', and a twelfth shift register clock signal CK 12'. The clock voltage boosting circuit 402 is configured to be connected to the shift register unit 401, and the clock voltage boosting circuit 402 respectively boosts each of the shift register clock signals according to the shift register clock signals and correspondingly outputs the display clock signals.
In some embodiments of the present disclosure, the shift register unit 401 further outputs an OTHS signal other than the shift register clock signal.
In one embodiment of the present disclosure, the clock voltage boost circuit 402 processes signals only through the register clock signal contact that outputs the shift register clock signal, and does not process other signals OTHS output by the shift register unit 401, and the clock voltage boost circuit 402 outputs the other signals OTHS, thereby achieving the effect of filtering the register clock signal.
In one embodiment of the present disclosure, the clock voltage boosting circuit 402 processes all signals output by the shift register unit 401, in other words, when the shift register unit 401 outputs other signals OTHS, the clock voltage boosting circuit 402 boosts the other signals OTHS and outputs the boosted signals, so as to achieve the effect that the clock voltage boosting circuit 402 boosts all signals output by the shift register unit 401.
Referring to fig. 5, fig. 5 is a schematic diagram of a shift register unit layout according to an embodiment of the present disclosure. The shift register unit 401 receives a control clock signal CK and a shift clock signal CP. The shift register unit consists of a plurality of D triggers, wherein the D triggers comprise a first D trigger D1, a second D trigger D2, a D interface of the second D trigger D2 is connected with a Q interface of a first D trigger D1, a third D trigger D3, a D interface of the third D trigger D3 is connected with a Q interface of a second D trigger D2, a fourth D trigger D4, a D interface of the fourth D trigger D4 is connected with a Q interface of a third D trigger D3, a fifth D trigger D5, a D interface of a fifth D trigger D5 is connected with a Q interface of a fourth D trigger D4, a sixth D trigger D6, a D interface of the sixth D trigger D6 is connected with a Q interface of a fifth D trigger D5, a seventh D trigger D7, a seventh D trigger D7 is connected with a sixth D interface of a sixth D6, an eighth D interface of a sixth D trigger D6, a seventh D interface of a seventh D trigger D6 is connected with a Q interface of an eighth D8, a Q interface of an eighth D8, A ninth D flip-flop D9, a D interface of the ninth D flip-flop D9 is connected to the Q interface of the eighth D flip-flop D8, a tenth D flip-flop D10, a D interface of the tenth D flip-flop D10 is connected to the Q interface of the ninth D flip-flop D9, an eleventh D flip-flop D11, and a D interface of the eleventh D flip-flop D11 is connected to the Q interface of the tenth D flip-flop D10. In other words, between the D flip-flops arranged adjacently, the Q interface of the D flip-flop arranged in the previous stage is connected to the D interface of the D flip-flop arranged in the next stage. The D flip-flops respectively receive the shift clock signal CP and are respectively connected with a return-to-zero point R.
In one embodiment of the present disclosure, the shift register unit further includes a multiplexing interface device, and the multiplexing interface device is connected to the clock control circuit.
In one embodiment of the present disclosure, the multiplexing interface device includes 2 input/output interfaces, and the shift register unit 401 receives the control clock signal CK and the shift clock signal CP through the multiplexing interface device, respectively.
Referring to fig. 4 and 5, the shift register unit is connected to the clock voltage boosting circuit through a plurality of shift register contacts. The shift register contacts include a first shift register contact disposed between the CK output terminal and the D interface of the first D flip-flop D1, a second shift register contact disposed between the Q interfaces of the second D flip-flop D2 and the first D flip-flop D1, a third shift register contact disposed between the Q interfaces of the third D flip-flop D3 and the second D flip-flop D2, a fourth shift register contact disposed between the Q interfaces of the fourth D flip-flop D4 and the third D flip-flop D3, a fifth shift register contact disposed between the Q interfaces of the fifth D flip-flop D5 and the fourth D flip-flop D4, a sixth shift register contact disposed between the Q interfaces of the sixth D flip-flop D6 and the fifth D flip-flop D5, a seventh shift register contact disposed between the Q interfaces of the seventh D7 and the sixth D flip-flop D3, and an eighth shift register contact disposed between the Q interfaces of the eighth D8 and the eighth D7, A ninth shift register contact disposed between the ninth D flip-flop D9 and the Q interface of the eighth D flip-flop D8, a tenth shift register contact disposed between the tenth D flip-flop D10 and the Q interface of the ninth D flip-flop D9, an eleventh shift register contact disposed between the eleventh D flip-flop D11 and the Q interface of the tenth D flip-flop D10, and a twelfth shift register contact disposed to be connected to the Q interface of the eleventh D flip-flop D11. The number of D flip-flops is less than the number of shift register contacts.
In one embodiment of the present disclosure, the number of D flip-flops is 1 less than the number of shift register contacts.
Referring to fig. 5 and fig. 6, fig. 6 is a schematic diagram showing clock waveforms of output signals of shift register contacts of a shift register unit according to an embodiment of the present disclosure. As shown, the shift register unit 401 generates the shift register clock signals, and the phases of the shift register clock signals are determined by the rising edge of the shift clock signal CP and the control clock signal CK. More specifically, each time the shift clock signal CP reaches a rising edge, the shift register contacts sequentially output a control clock signal CK.
Referring to FIG. 7, FIG. 7 is a block diagram of a multi-clock gate driving circuit according to an embodiment of the present disclosure. The multi-clock gate driving circuit 70 is configured to output a plurality of display clock signals for controlling a display screen of the display device. The multi-clock gate driving circuit 70 includes a clock control circuit 703, a shift register unit 701 and a clock voltage boosting circuit 702. The clock control circuit 703 is configured to output a control clock signal CK, a shift clock signal CP and other signals OTHS. The shift register unit 701 includes a multiplexing interface device configured to output a plurality of shift register clock signals. The clock voltage boost circuit 702 is connected to the shift register unit 701, and the clock voltage boost circuit 702 receives the shift register clock signals and generates the display clock signals according to the initial clock signal, wherein the shift register unit is composed of a plurality of D flip-flops.
In one embodiment of the present disclosure, the shift register unit 701 is connected to the clock control circuit 703 through a multiplexing interface device.
In summary, the present disclosure provides a multi-clock level converting circuit and a multi-clock gate driving circuit for outputting a display clock signal for controlling a display screen of a display device. The multi-clock potential conversion circuit includes a shift register unit configured to output a plurality of shift register clock signals. And the clock pulse voltage lifting circuit is connected with the shift register unit, receives the plurality of shift register clock pulse signals and correspondingly generates the plurality of display clock pulse signals according to the initial clock pulse signal. Wherein, the number of the shift register clock signals is the same as that of the display clock signals. The multi-clock potential conversion circuit saves the clock control circuit from outputting the multi-clock display signals, saves the input and output interface resources of the clock control circuit, simplifies the external circuit of the gate driving circuit substrate and reduces the production cost of the display device.
The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and refinements may be made by those skilled in the art without departing from the principle of the present disclosure, and these modifications and refinements should also be construed as the protection scope of the present disclosure.
Claims (10)
1. A multi-clock potential converting circuit configured to output a plurality of display clock signals for controlling a display screen of a display device according to a control clock signal, comprising:
a shift register unit configured to output a plurality of shift register clock signals according to the control clock signal; and
and the clock voltage lifting circuit is configured to be connected with the shift register unit and correspondingly outputs the plurality of display clock signals according to the plurality of shift register clock signals.
2. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit further comprises a multiplexing interface device, the multiplexing interface device being connected to the clock control circuit.
3. The multi-clock potential conversion circuit of claim 2, wherein the multiplexing interface means comprises 2 input-output interfaces.
4. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit is comprised of a plurality of D flip-flops.
5. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit further outputs other signals than the shift register clock signal.
6. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit is connected to the clock voltage boost circuit through a plurality of shift register contacts.
7. A multi-clock gate driving circuit configured to output a plurality of display clock signals for controlling a display screen of a display device, comprising:
a clock control circuit configured to output a control clock signal;
a shift register unit comprising a multiplexing interface device, the shift register unit configured to be connected with the clock control circuit through the multiplexing interface device, the shift register unit configured to output a plurality of shift register clock signals according to the control clock signal; and
the clock voltage lifting circuit is configured to be connected with the shift register unit, receives the plurality of shift register clock signals and correspondingly generates the plurality of display clock signals according to the initial clock signal;
the shift register unit is composed of a plurality of D triggers.
8. The multi-clock gate driver circuit of claim 7, wherein the shift register unit is connected to the clock voltage boost circuit through a plurality of shift register contacts.
9. The multi-clock gate driver circuit of claim 7, wherein the shift register unit further outputs other signals than the shift register clock signal.
10. The multi-clock gate driver circuit of claim 7, wherein the multiplexing interface device comprises 2 input/output interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910768317.2A CN110619834B (en) | 2019-08-20 | 2019-08-20 | Multi-clock potential conversion circuit and multi-clock gate driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910768317.2A CN110619834B (en) | 2019-08-20 | 2019-08-20 | Multi-clock potential conversion circuit and multi-clock gate driving circuit |
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| CN110619834A true CN110619834A (en) | 2019-12-27 |
| CN110619834B CN110619834B (en) | 2022-10-04 |
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| CN111128088A (en) * | 2020-01-17 | 2020-05-08 | Tcl华星光电技术有限公司 | Driving circuit and display panel applying same |
| CN111261093A (en) * | 2020-03-25 | 2020-06-09 | Tcl华星光电技术有限公司 | Display panel |
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| CN111261093B (en) * | 2020-03-25 | 2021-08-24 | Tcl华星光电技术有限公司 | Display panel |
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| CN110619834B (en) | 2022-10-04 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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