CN101937718A - Bidirectional shift register - Google Patents
Bidirectional shift register Download PDFInfo
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- CN101937718A CN101937718A CN2010102467161A CN201010246716A CN101937718A CN 101937718 A CN101937718 A CN 101937718A CN 2010102467161 A CN2010102467161 A CN 2010102467161A CN 201010246716 A CN201010246716 A CN 201010246716A CN 101937718 A CN101937718 A CN 101937718A
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Abstract
The invention relates to a bidirectional shift register, comprising a multistage tandem shift register unit; wherein an (n-1)th stage shift register unit in the multistage tandem shift register provides an (n-1) stage output voltage according to a first clock pulse signal and an (n-1) stage input voltage; an n stage shift register unit in the multistage tandem shift register unit provides an n stage output voltage according to a second clock pulse signal and an n stage input voltage; and an (n+1) stage shift register unit in the multistage tandem shift register unit provides an (n+1) output voltage according to a third clock pulse signal and an (n+1) stage input voltage. The shift register of liquid crystal display in the invention comprises a multistage shift register unit connected in series, and the register unit at each stage comprises an input circuit in symmetrical structure and a pull-down circuit, so that the liquid crystal display can be all operated in a forward scanning mode and a reverse scanning mode.
Description
Technical field
The present invention relates to a kind of shift register, refer to a kind of bidirectional shift register that is applied to LCD especially.
Background technology
LCD (liquid crystal display, LCD) have low radiation, volume is little and advantage such as low power consuming, replace traditional cathode-ray tube display (cathode ray tube display gradually, CRT), thereby be widely used in notebook computer, personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information products such as mobile phone.The mode of conventional liquid crystal is to utilize the external drive chip to drive chip on the panel with display image, but in order to reduce component number and to reduce manufacturing cost, developing into gradually in recent years directly is made in driving circuit structure on the display panel, for example adopt gate driver circuit (gate driver) is integrated in liquid crystal panel (gate on array, technology GOA).
Fig. 1 is the simplification block schematic diagram of a liquid crystal indicator 100 in the prior art.Fig. 1 has only shown the part-structure of liquid crystal indicator 100, comprises many gate lines G L (1)～GL (N), a shift register (two-phase shift register) 110, one time clock generator 120 and a power supply unit 130.Gate generator 120 can provide shift register 110 operations required initial pulse signal VST and two clock pulse signal CK1 and CK2, and power supply unit 130 can provide shift register 110 operations required bias voltage VDD and VSS.
Please refer to Fig. 2, Fig. 2 be a n level shifting deposit unit SR (n) among multistage shifting deposit unit SR (1)～SR (N) synoptic diagram (suppose n between 1 and N between odd number).The shifting deposit unit SR (n) of prior art comprises an output terminal OUT (n), an end points Q (n), one and promotes circuit 15, an input circuit 25, one first pull-down circuit 35, and one second pull-down circuit 40.Shifting deposit unit SR (n) can be in its output terminal OUT (n) output gate drive signal GS (n) to gate lines G L (n).
Formerly in the liquid crystal indicator 100 of technology, shift register 110 only can scan (for example in forward scan mode driving grid line GL (1)～GL (N)) in regular turn with specific direction, and can't support other drive pattern (for example in reverse scan mode driving grid line GL (N)～GL (1)) in regular turn.
Summary of the invention
For overcoming defective of the prior art, the invention provides a kind of bidirectional shift register, it comprises the multi-stage serial connection shifting deposit unit, wherein one (n-1) level shifting deposit unit provides one (n-1) level output voltage according to one first clock pulse signal and one (n-1) level input voltage in this multi-stage serial connection shifting deposit unit, a n level shifting deposit unit provides a n level output voltage according to a second clock pulse signal and a n level input voltage in this multi-stage serial connection shifting deposit unit, and one (n+1) level shifting deposit unit provides one (n+1) level output voltage according to one the 3rd clock pulse signal and one (n+1) level input voltage in this multi-stage serial connection shifting deposit unit.N level shifting deposit unit comprises an output terminal, is used for exporting this n level output voltage; One n level node; One promotes circuit, and its current potential according to this second clock pulse signal and this n level node provides this n level output voltage; One input circuit, be used for receiving this (n-1) level output voltage and this (n+1) level output voltage, and when forward scan with this (n-1) level output voltage as this n level input voltage, when reverse scan with this (n+1) level output voltage as this n level input voltage, and come this lifting circuit of conducting according to this (n-1) level output voltage and this (n+1) level output voltage; An and pull-down circuit, it closes this lifting circuit according to back grade one first voltage that shifting deposit unit transmitted in this multi-stage serial connection shifting deposit unit when forward scan, and one second voltage that is transmitted according to a prime shifting deposit unit in this multi-stage serial connection shifting deposit unit when reverse scan is closed this lifting circuit.
Shift register of the present invention adopts the input circuit and the pull-down circuit of tool symmetrical structure, and liquid crystal indicator all can normally be moved under forward scan pattern and reverse scan pattern, therefore can provide flexible type of drive.
Description of drawings
Fig. 1 is the simplification block schematic diagram of a liquid crystal indicator in the prior art.
Fig. 2 is the synoptic diagram of a n level shifting deposit unit in the liquid crystal indicator of prior art.
Fig. 3 is the simplification block schematic diagram of a liquid crystal indicator among the present invention.
Fig. 4 a～Fig. 4 d is the synoptic diagram of a n level shifting deposit unit in the liquid crystal indicator of the present invention.
Fig. 5 a is the sequential chart of liquid crystal indicator of the present invention when moving under the forward scan pattern.
Fig. 5 b is the sequential chart of liquid crystal indicator of the present invention when moving under the reverse scan pattern.
Fig. 6 is the simplification block schematic diagram of a liquid crystal indicator among the present invention.
Fig. 7 a and Fig. 7 b are the synoptic diagram of a n level shifting deposit unit in the liquid crystal indicator of the present invention.
Fig. 8 a is the sequential chart of liquid crystal indicator of the present invention when moving under the forward scan pattern.
Fig. 8 b is the sequential chart of liquid crystal indicator of the present invention when moving under the reverse scan pattern.
Wherein, description of reference numerals is as follows:
OUT (n) output terminal 110,210,310 shift registers
Q (n) end points 120,220,320 gate generators
10,15 promote circuit 130,230,330 power supply units
21～27 input circuits T1～T9 transistor switch
100,200,300 liquid crystal indicators
30,31,32,35,40 pull-down circuits
GL (1)～GL (N), GL (n-2)～GL (n+2) gate line
SR (1)～SR (N), SR (n-2)～SR (n+2) shifting deposit unit
Embodiment
Please refer to Fig. 3, Fig. 3 is the simplification block schematic diagram of a liquid crystal indicator 200 among the present invention.Fig. 3 has only shown the part-structure of liquid crystal indicator 200, comprises bidirectional shift register (M-phase bi-directional shift register) 210, the one time clock generator 220 and a power supply unit 230 of many gate lines G L (1)～GL (N), a M phase place.Gate generator 220 can provide bidirectional shift register 210 operations required initial pulse signal VST and clock pulse signal CK1～CKM, and power supply unit 230 can provide bidirectional shift register 210 operations required voltage.
Please refer to Fig. 4 a～Fig. 4 d, Fig. 4 a～Fig. 4 d for the synoptic diagram of a n level shifting deposit unit SR (n) in the liquid crystal indicator 200 of the present invention (n be between 1 and N between integer).In the embodiment shown in Fig. 4 a～Fig. 4 d, each shifting deposit unit SR (n) respectively comprises an output terminal OUT (n), an end points Q (n), one and promotes circuit 10, one first pull-down circuit 30, and one second pull-down circuit 40, and comprise input circuit 21～24 respectively.Shifting deposit unit SR (n) can be in its output terminal OUT (n) output gate drive signal GS (n) to gate lines G L (n).
In first to the 3rd embodiment of the present invention shown in Fig. 4 a～Fig. 4 c, input circuit 21～23 respectively comprises transistor switch T1 and T2: the control end of transistor switch T1 is coupled to the output terminal of (n-1) level shifting deposit unit SR (n-1), and second end is coupled to end points Q (n); The control end of transistor switch T2 is coupled to the output terminal of (n+1) level shifting deposit unit SR (n+1), and second end is coupled to end points Q (n).In the input circuit 21 of first embodiment of the invention shown in Fig. 4 a, first end of transistor switch T1 is coupled to power supply unit 230 to receive a bias voltage VDD1, first end of transistor switch T2 is coupled to power supply unit 230 to receive a bias voltage VDD2, and wherein the value of bias voltage VDD1 and VDD2 is higher than the forward voltage of transistor switch T9; In the input circuit 22 of second embodiment of the invention shown in Fig. 4 b, first end of transistor switch T1 is coupled to gate generator 220 with receive clock pulse signal CK1, first end of transistor switch T2 is coupled to gate generator 220 with receive clock pulse signal CK3, and wherein the activation current potential of clock pulse signal CK1 and CK3 is higher than the forward voltage of transistor switch T9; In the input circuit 23 of third embodiment of the invention shown in Fig. 4 c, the control end of transistor switch T1 and first end all are coupled to the output terminal of (n-1) level shifting deposit unit SR (n-1), and the control end of transistor switch T2 and first end all are coupled to the output terminal of (n+1) level shifting deposit unit SR (n+1), and wherein the activation current potential of clock pulse signal CK1 (corresponding to gate drive signal GS (n-1)) and CK3 (corresponding to gate drive signal GS (n+1)) is higher than the forward voltage of transistor switch T9.
In fourth embodiment of the invention shown in Fig. 4 d, input circuit 24 comprises transistor switch T1～T4: first end of transistor switch T1 is coupled to the output terminal of (n-1) level shifting deposit unit SR (n-1), and second end is coupled to end points Q (n); First end of transistor switch T2 is coupled to the output terminal of (n+1) level shifting deposit unit SR (n+1), and the second end utmost point is coupled to end points Q (n); The control end of transistor switch T3 is coupled to the end points Q (n-1) of (n-1) level shifting deposit unit SR (n-1), and first end is coupled to gate generator 220 with receive clock pulse signal CK1, and second end is coupled to the control end of transistor switch T1; The control end of transistor switch T4 is coupled to the end points Q (n+1) of (n+1) level shifting deposit unit SR (n+1), and first end is coupled to gate generator 220 with receive clock pulse signal CK3, and second end is coupled to the control end of transistor switch T2.
In the embodiment shown in Fig. 4 a～Fig. 4 d, first pull-down circuit 30 comprises transistor switch T5 and T6: the control end of transistor switch T5 is coupled to the output terminal of (n+2) level shifting deposit unit SR (n+2), first end is coupled to end points Q (n), and second end is coupled to power supply unit 230 to receive a bias voltage VSS3; The control end of transistor switch T6 is coupled to the output terminal of (n-2) level shifting deposit unit SR (n-2), first end is coupled to end points Q (n), and second end is coupled to power supply unit 230 to receive a bias voltage VSS4, and wherein the value of bias voltage VSS3 and VSS4 is lower than the forward voltage of transistor switch T9.
Please refer to Fig. 5 a and Fig. 5 b, sequential chart when Fig. 5 a move under the forward scan pattern for the liquid crystal indicator 200 of the present invention first to fourth embodiment, and the sequential chart of Fig. 5 b when to be the liquid crystal indicator 200 of the present invention first to fourth embodiment move under the reverse scan pattern.Fig. 5 a and Fig. 5 b have shown gate drive signal GS (n-2)～GS (n+2), clock pulse signal CK1～CK3, and the current potential of end points Q (n-2)～Q (n+2).The output cycle of gate drive signal GS (n-2)～GS (n+2) (tool activation current potential during) is respectively by T
N-2～T
N+2Represent, and shifting deposit unit SR (n-2)～SR (n+2) moves according to clock pulse signal CK3, CK1, CK2, CK3 and CK1 respectively.
When moving under the forward scan pattern shown in Fig. 5 a, liquid crystal indicator 200 is exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) in regular turn.In (n-1) level output period T
N-1The time, clock pulse signal CK1 and gate drive signal GS (n-1) tool activation current potential, transistor switch T1 in the input circuit 21～24 of n level shifting deposit unit SR (n) can be switched on, and then the current potential of end points Q (n) drawn high current potential to bias voltage VDD1, clock pulse signal CK1 or gate drive signal GS (n-1) with turn-on transistor switch T9, because clock pulse signal CK2 maintains the decapacitation current potential at this moment, so n level gate drive signal GS (n) and no-output; In n level output period T
nThe time, clock pulse signal CK2 can switch to the activation current potential and the transistor switch T9 by conducting is sent to output terminal OUT (n), and the n level gate drive signal GS (n) of the exportable tool activation of shifting deposit unit SR (n) this moment current potential is to gate lines G L (n); In (n+1) level output period T
N+1The time, clock pulse signal CK3 and gate drive signal GS (n+1) tool activation current potential, transistor switch T2 in the input circuit 21～24 of n level shifting deposit unit SR (n) can be switched on, and then end points Q (n) maintained current potential identical with bias voltage VDD2, clock pulse signal CK3 or (n+1) level gate drive signal GS (n+1) with turn-on transistor switch T9, because clock pulse signal CK2 is in period T
N+1The time can switch to the decapacitation current potential, therefore this moment n level gate drive signal GS (n) and no-output; In (n+1) level output period T
N+2The time, (n+2) level gate drive signal GS (n+2) tool activation current potential, transistor switch T5 in first pull-down circuit 30 of n level shifting deposit unit SR (n) can be switched on, and then the current potential of end points Q (n) is pulled low to bias voltage VSS3 to close transistor switch T9, therefore this moment n level gate drive signal GS (n) and no-output.
When moving under the reverse scan pattern shown in Fig. 5 b, liquid crystal indicator 200 is exported gate drive signal GS (N)～GS (1) to corresponding gate lines G L (N)～GL (1) by shifting deposit unit SR (N)～SR (1) in regular turn.In (n+1) level output period T
N+1The time, clock pulse signal CK3 and gate drive signal GS (n+1) tool activation current potential, transistor switch T2 in the input circuit 21～24 of n level shifting deposit unit SR (n) can be switched on, and then the current potential of end points Q (n) drawn high current potential to bias voltage VDD2, clock pulse signal CK3 or (n+1) level gate drive signal GS (n+1) with turn-on transistor switch T9, because clock pulse signal CK2 maintains the decapacitation current potential at this moment, so n level gate drive signal GS (n) and no-output; In n level output period T
nThe time, clock pulse signal CK2 can switch to the activation current potential and the transistor switch T9 by conducting is sent to output terminal OUT (n), and the n level gate drive signal GS (n) of the exportable tool activation of shifting deposit unit SR (n) this moment current potential is to gate lines G L (n); In (n-1) level output period T
N-1The time, clock pulse signal CK1 and gate drive signal GS (n-1) tool activation current potential, transistor switch T1 in the input circuit 21～24 of n level shifting deposit unit SR (n) can be switched on, and then end points Q (n) maintained current potential with bias voltage VDD1, clock pulse signal CK1 or gate drive signal GS (n-1) with turn-on transistor switch T9, because clock pulse signal CK2 is in period T
N-1The time can switch to the decapacitation current potential, therefore this moment n level gate drive signal GS (n) and no-output; In period T
N-2The time, (n-2) level gate drive signal GS (n-2) tool activation current potential, transistor switch T6 in first pull-down circuit 30 of n level shifting deposit unit SR (n) can be switched on, and then the current potential of end points Q (n) is pulled low to bias voltage VSS4 to close transistor switch T9, therefore this moment n level gate drive signal GS (n) and no-output.
In liquid crystal indicator 200 of the present invention, input circuit 21～23 adopts the symmetrical structure that comprises transistor switch T1 and T2, input circuit 24 adopts the symmetrical structure that comprises transistor switch T1～T4, and first pull-down circuit 30 adopts the symmetrical structure that comprises transistor switch T5 and T6, therefore liquid crystal indicator 200 all can normally be moved under forward scan pattern and reverse scan pattern.Simultaneously, second pull-down circuit 40 is used for regulated output voltage, it can adopt the different circuit of knowing technology in the association area, only be an example (wherein the current potential of bias voltage VDD is the activation current potential of clock pulse signal CK1～CK3) wherein shown in the 4a～4d, the structure of second pull-down circuit 40 does not influence category of the present invention with relevant operation.On the other hand, transistor switch T1～T9 can be metal oxide semiconductor transistor (metal-oxide-semiconductor, MOS) switch, or the element of tool similar functions.
Please refer to Fig. 6, Fig. 6 is the simplification block schematic diagram of a liquid crystal indicator 300 among the present invention.Fig. 6 has only shown the part-structure of liquid crystal indicator 300, comprises bidirectional shift register 310, a time clock generator 320 and a power supply unit 330 of many gate lines G L (1)～GL (N), a M phase place.Gate generator 320 can provide bidirectional shift register 310 operations required initial pulse signal VST and clock pulse signal CK1～CKM, and power supply unit 330 can provide bidirectional shift register 310 operations required voltage.
Please refer to Fig. 7 a and Fig. 7 b, Fig. 7 a and Fig. 7 b for the synoptic diagram of a n level shifting deposit unit SR (n) in the liquid crystal indicator 300 of the present invention (n be between 1 and N between integer).In the embodiment shown in Fig. 7 a and the 7b, shifting deposit unit SR (n) comprises an output terminal OUT (n), an end points Q (n), one and promotes circuit 10, one first input circuit 26, one second input circuit 27, one first pull-down circuit 31, one second pull-down circuit 32, and one the 3rd pull-down circuit 40.Shifting deposit unit SR (n) can be in its output terminal OUT (n) output gate drive signal GS (n) to gate lines G L (n).
Promote circuit 10 and comprise a transistor switch T9, its control end is coupled to end points Q (n), and first end is coupled to gate generator 320 with receive clock pulse signal CK1, and second end is coupled to output terminal OUT (n).When the current potential of end points Q (n) was higher than the forward voltage of transistor switch T9, clock pulse signal CK1 can be sent to output terminal OUT (n) by the transistor switch T9 of conducting with supply gate drive signal GS (n).
First pull-down circuit 31 comprises transistor switch T5 and T6: first end of transistor switch T5 is coupled to end points Q (n), and second end is coupled to power supply unit 330 to receive a bias voltage VSS1, and wherein the value of bias voltage VSS1 is lower than the forward voltage of transistor switch T9; The control end of transistor switch T6 is coupled to the output terminal of (n+1) level shifting deposit unit SR (n+1), and first end is coupled to the control end of transistor switch T5, and second end is coupled to first control signal.Second pull-down circuit 32 comprises transistor switch T7 and T8: first end of transistor switch T7 is coupled to end points Q (n), and second end is coupled to power supply unit 330 to receive a bias voltage VSS2, and wherein the value of bias voltage VSS2 is lower than the forward voltage of transistor switch T9; The control end of transistor switch T8 is coupled to the output terminal of (n-1) level shifting deposit unit SR (n-1), and first end is coupled to the control end of transistor switch T7, and second end is coupled to second control signal.
Embodiment when Fig. 7 a is depicted as liquid crystal indicator 300 and moves under the forward scan pattern, this moment, first control signal can be the clock pulse signal CK2 that gate generator 320 is provided, and second control signal can be the bias voltage VSS that power supply unit 330 is provided.Embodiment when Fig. 7 b is depicted as liquid crystal indicator 300 and moves under the reverse scan pattern, this moment, first control signal can be the bias voltage VSS that power supply unit 330 is provided, and second control signal can be the clock pulse signal CK2 that gate generator 320 is provided, and wherein the value of bias voltage VSS is lower than the forward voltage of transistor switch T1, T3, T5 and T7.
Please refer to Fig. 8 a and Fig. 8 b, Fig. 8 a is the sequential chart of liquid crystal indicator 300 of the present invention when move under the forward scan pattern, and the sequential chart of Fig. 8 b when to be liquid crystal indicator 300 of the present invention move under the reverse scan pattern.Fig. 8 a and Fig. 8 b have shown gate drive signal GS (n-2)～GS (n+2), clock pulse signal CK1～CK2, and the current potential of end points Q (n-2)～Q (n+2).The output cycle of gate drive signal GS (n-2)～GS (n+2) (tool activation current potential during) is respectively by T
N-2～T
N+2Represent, and shifting deposit unit SR (n-2)～SR (n+2) moves according to clock pulse signal CK1, CK2, CK1, CK2 and CK1 respectively.
When moving under the forward scan pattern shown in Fig. 8 a, liquid crystal indicator 300 is exported gate drive signal GS (1)～GS (N) to corresponding gate lines G L (1)～GL (N) by shifting deposit unit SR (1)～SR (N) in regular turn.In (n-1) level output period T
N-1The time, clock pulse signal CK2, end points Q (n-1) and gate drive signal GS (n-1) tool activation current potential, transistor switch T1 and T2 in first input circuit 26 of n level shifting deposit unit SR (n) can be switched on, and then the current potential of end points Q (n) drawn high current potential to gate drive signal GS (n-1) with turn-on transistor switch T9, because clock pulse signal CK1 maintains the decapacitation current potential at this moment, so n level gate drive signal GS (n) and no-output; In n level output period T
nThe time, clock pulse signal CK1 can switch to the activation current potential and the transistor switch T9 by conducting is sent to output terminal OUT (n), and the n level gate drive signal GS (n) of the exportable tool activation of shifting deposit unit SR (n) this moment current potential is to gate lines G L (n); In (n+1) level output period T
N+1The time, clock pulse signal CK2 and gate drive signal GS (n+1) tool activation current potential, transistor switch T5 and T6 in first pull-down circuit 31 of n level shifting deposit unit SR (n) can be switched on, and then end points Q (n) is pulled low to bias voltage VSS1 closing transistor switch T9, therefore this moment n level gate drive signal GS (n) and no-output.Because the value of bias voltage VSS is lower than the forward voltage of transistor switch T3 and T7, therefore when liquid crystal indicator 300 moved under the forward scan pattern, second input circuit 27 and second pull-down circuit 32 were for closing.
When moving under the reverse scan pattern shown in Fig. 8 b, liquid crystal indicator 300 is exported gate drive signal GS (N)～GS (1) to corresponding gate lines G L (N)～GL (1) by shifting deposit unit SR (N)～SR (1) in regular turn.In (n+1) level output period T
N+1The time, clock pulse signal CK2, end points Q (n+1) and gate drive signal GS (n+1) tool activation current potential, transistor switch T3 and T4 in second input circuit 27 of n level shifting deposit unit SR (n) can be switched on, and then the current potential of end points Q (n) drawn high current potential to gate drive signal GS (n+1) with turn-on transistor switch T9, because clock pulse signal CK1 maintains the decapacitation current potential at this moment, so n level gate drive signal GS (n) and no-output; In n level output period T
nThe time, clock pulse signal CK1 can switch to the activation current potential and the transistor switch T9 by conducting is sent to output terminal OUT (n), and the n level gate drive signal GS (n) of the exportable tool activation of shifting deposit unit SR (n) this moment current potential is to gate lines G L (n); In (n-1) level output period T
N-1The time, clock pulse signal CK2 and gate drive signal GS (n-1) tool activation current potential, transistor switch T7 and T8 in second pull-down circuit 32 of n level shifting deposit unit SR (n) can be switched on, and then end points Q (n) is pulled low to bias voltage VSS2 closing transistor switch T9, therefore this moment n level gate drive signal GS (n) and no-output.Because the value of bias voltage VSS is lower than the forward voltage of transistor switch T1 and T5, therefore when liquid crystal indicator 300 moved under the reverse scan pattern, first input circuit 26 and first pull-down circuit 31 were for closing.
In liquid crystal indicator 300 of the present invention, first input circuit 26 and second input circuit 27 are symmetrical structure, and first pull-down circuit 31 and second pull-down circuit 32 are symmetrical structure.Therefore, by switching first and second control signals, liquid crystal indicator 300 all can normally move under forward scan pattern and reverse scan pattern.Simultaneously, the 3rd pull-down circuit 40 is used for regulated output voltage, it can adopt the different circuit of knowing technology in the association area, only be an example (wherein the current potential of bias voltage VDD is the activation current potential of clock pulse signal CK1～CK2) wherein shown in Fig. 7 a and Fig. 7 b, the structure of the 3rd pull-down circuit 40 does not influence category of the present invention with relevant operation.On the other hand, transistor switch T1～T9 can be the MOS switch, or the element of tool similar functions.
Shift register of the present invention adopts the input circuit and the pull-down circuit of tool symmetrical structure, and liquid crystal indicator all can normally be moved under forward scan pattern and reverse scan pattern, therefore can provide flexible type of drive.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. bidirectional shift register, it comprises the multi-stage serial connection shifting deposit unit, wherein:
One (n-1) level shifting deposit unit provides one (n-1) level output voltage according to one first clock pulse signal and one (n-1) level input voltage in the described multi-stage serial connection shifting deposit unit;
A n level shifting deposit unit provides a n level output voltage according to a second clock pulse signal and a n level input voltage in the described multi-stage serial connection shifting deposit unit;
One (n+1) level shifting deposit unit provides one (n+1) level output voltage according to one the 3rd clock pulse signal and one (n+1) level input voltage in the described multi-stage serial connection shifting deposit unit; And
This n level shifting deposit unit comprises:
One output terminal is used for exporting this n level output voltage;
One n level node;
One promotes circuit, and its current potential according to this second clock pulse signal and this n level node provides this n level output voltage;
One input circuit, be used for receiving this (n-1) level output voltage and this (n+1) level output voltage, and when forward scan with this (n-1) level output voltage as this n level input voltage, when reverse scan with this (n+1) level output voltage as this n level input voltage, and come this lifting circuit of conducting according to this (n-1) level output voltage and this (n+1) level output voltage; And
One pull-down circuit, it closes this lifting circuit according to back grade one first voltage that shifting deposit unit transmitted in the described multi-stage serial connection shifting deposit unit when forward scan, and one second voltage that is transmitted according to a prime shifting deposit unit in the described multi-stage serial connection shifting deposit unit when reverse scan is closed this lifting circuit.
2. shift register as claimed in claim 1, wherein this input circuit comprises:
One first switch, it comprises:
One first end is used for receiving this (n-1) level output voltage;
One second end is coupled to this n level node; And
One control end is coupled to first end of this first switch; And
One second switch, it comprises:
One first end is used for receiving this (n+1) level output voltage;
One second end is coupled to this n level node; And
One control end is coupled to first end of this second switch.
3. shift register as claimed in claim 1, wherein this input circuit comprises:
One first switch, it comprises:
One first end is coupled to one first bias voltage, and wherein the current potential of this first bias voltage is higher than the conducting current potential of this lifting circuit;
One second end is coupled to this n level node; And
One control end is used for receiving this (n-1) level output voltage; And
One second switch, it comprises:
One first end is coupled to one second bias voltage, and wherein the current potential of this second bias voltage is higher than the conducting current potential of this lifting circuit;
One second end is coupled to this n level node; And
One control end is used for receiving this (n+1) level output voltage.
4. shift register as claimed in claim 1, wherein this input circuit comprises:
One first switch, it comprises:
One first end is used for receiving this (n-1) level output voltage;
One second end is coupled to this n level node; And
One control end;
One second switch, it comprises:
One first end is used for receiving this (n+1) level output voltage;
One second end is coupled to this n level node; And
One control end;
One the 3rd switch, it comprises;
One first end is used for receiving this first clock pulse signal;
One second end is coupled to the control end of this first switch; And
One control end is coupled to one (n-1) level node in this (n-1) level shifting deposit unit; And
One the 4th switch, it comprises;
One first end is used for receiving the 3rd clock pulse signal;
One second end is coupled to the control end of this second switch; And
One control end is coupled to one (n+1) level node in this (n+1) level shifting deposit unit.
5. shift register as claimed in claim 1, wherein this pull-down circuit comprises:
One the 5th switch, it comprises:
One first end is coupled to this n level node;
One second end is coupled to one the 3rd bias voltage, and wherein the current potential of the 3rd bias voltage is lower than the conducting current potential of this lifting circuit; And
One control end is used for receiving this first voltage; And
One the 6th switch, it comprises:
One first end is coupled to this n level node;
One second end is coupled to one the 4th bias voltage, and wherein the current potential of the 4th bias voltage is lower than the conducting current potential of this lifting circuit; And
One control end is used for receiving this second voltage.
6. shift register as claimed in claim 5, wherein said multi-stage shift registering units connected in series also comprises:
One (n-2) level shifting deposit unit, it provides one (n-2) level output voltage with as this second voltage according to one the 4th clock pulse signal; And
One (n+2) level shifting deposit unit, it provides one (n+2) level output voltage with as this first voltage according to one the 5th clock pulse signal;
Wherein this first to the 5th clock pulse signal switches between an activation current potential and a decapacitation current potential with a predetermined period respectively, and in this first to the 3rd clock pulse signal this activation current potential of time clock signal tool is only arranged at one time.
7. shift register as claimed in claim 6, wherein this is first identical with the 5th clock pulse signal, and this third and fourth clock pulse signal is identical.
8. shift register as claimed in claim 1, it also moves under one first pattern or one second pattern according to one first control signal and one second control signal, drive described multi-stage serial connection shifting deposit unit in the forward scan mode when wherein this shifting deposit unit moves under this first pattern, drive described multi-stage serial connection shifting deposit unit in the reverse scan mode when under this second pattern, moving, and
This input circuit of this n level shifting deposit unit comprises:
One first input circuit, it comes this lifting circuit of conducting according to this (n-1) level output voltage and this first control signal under this first pattern, and moves according to this (n-1) level output voltage and this second control signal under this second pattern; And
One second input circuit, it comes this lifting circuit of conducting according to this (n+1) level output voltage and this first control signal under this second pattern, and moves according to this (n+1) level output voltage and this second control signal under this first pattern; And
This pull-down circuit of this n level shifting deposit unit comprises:
One first pull-down circuit, it closes this lifting circuit according to this (n+1) level output voltage and this first control signal under this first pattern, and moves according to this (n+1) level output voltage and this second control signal under this second pattern; And
One second pull-down circuit, it closes this lifting circuit according to this (n-1) level output voltage and this first control signal under this second pattern, and moves according to this (n-1) level output voltage and this second control signal under this first pattern.
9. shift register as claimed in claim 8, wherein:
This first input circuit comprises:
One first switch, it comprises:
One first end is used for receiving this (n-1) level output voltage;
One second end is coupled to this n level node; And
One control end;
One second switch, it comprises;
One first end is used for receiving this first control signal;
One second end is coupled to the control end of this first switch; And
One control end is coupled to one (n-1) level node in this (n-1) level shifting deposit unit; And
This second input circuit comprises:
One the 3rd switch, it comprises:
One first end is used for receiving this (n+1) level output voltage;
One second end is coupled to this n level node; And
One control end; And
One the 4th switch, it comprises;
One first end is used for receiving this second control signal;
One second end is coupled to the control end of the 3rd switch; And
One control end is coupled to one (n+1) level node in this (n+1) level shifting deposit unit.
10. shift register as claimed in claim 9, wherein:
This first pull-down circuit comprises:
One the 5th switch, it comprises:
One first end is coupled to this n level node;
One second end is coupled to one first bias voltage, and wherein the current potential of this first bias voltage is lower than the conducting current potential of this this lifting circuit; And
One control end;
One the 6th switch, it comprises:
One first end is coupled to the control end of the 5th switch;
One second end is used for receiving this first control signal; And
One control end is used for receiving this first voltage; And
This second pull-down circuit comprises:
One minion is closed, and it comprises:
One first end is coupled to this n level node;
One second end is coupled to one second bias voltage, and wherein the current potential of this second bias voltage is lower than the conducting current potential of this this lifting circuit; And
One control end; And
One octavo is closed, and it comprises:
One first end is coupled to the control end that this minion is closed;
One second end is used for receiving this second control signal; And
One control end is used for receiving this second voltage.
11. shift register as claimed in claim 10, wherein the current potential of this first control signal is higher than the conducting current potential that this first switch, the 3rd switch, the 5th switch and this minion are closed, and the current potential of this second control signal is lower than the conducting current potential that this first switch, the 3rd switch, the 5th switch and this minion are closed.
12. shift register as claimed in claim 10, wherein this (n+1) level shifting deposit unit provides this (n+1) level output voltage with as this first voltage according to the 3rd clock pulse signal, this (n-1) level shifting deposit unit provides this (n-1) level output voltage with as this second voltage according to this first clock pulse signal, this first to the 3rd clock pulse signal switches between an activation current potential and a decapacitation current potential with a predetermined period respectively, and this activation current potential of time clock signal tool is only arranged in this first and second clock pulse signal at one time, and in this second and the 3rd clock pulse signal this activation current potential of time clock signal tool is only arranged at one time.
13. shift register as claimed in claim 12, wherein this is first identical with the 3rd clock pulse signal.
14. shift register as claimed in claim 1, wherein this lifting circuit comprises:
One the 9th switch, it comprises:
One first end is used for receiving this second clock pulse signal;
One second end is coupled to this output terminal; And
One control end is coupled to this n level node.
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