CN104715707A - Display panel - Google Patents
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- CN104715707A CN104715707A CN201310694631.3A CN201310694631A CN104715707A CN 104715707 A CN104715707 A CN 104715707A CN 201310694631 A CN201310694631 A CN 201310694631A CN 104715707 A CN104715707 A CN 104715707A
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Abstract
The invention provides a display panel which comprises a scanning drive circuit. The scanning drive circuit comprises a plurality of shifting registers connected in series. At least one of the shifting registers comprises a control circuit, a rise circuit and an output circuit, wherein the control circuit is used for controlling the voltage of a first control node according to a start signal and controlling the voltage of a second control node according to a reset signal, the rise circuit is coupled to the control circuit and used for rise of the voltage of the first control node, and the output circuit is coupled to the rise circuit and the control circuit and used for outputting a plurality of gate drive signals at a plurality of output nodes according to the voltage of the first control node. One of the gate drive signals is provided to the next-stage shifting register to be used as a start signal of the next-stage shifting register.
Description
Technical field
The invention relates to a kind of display pannel and display equipment; Display pannel and the display equipment of driving circuit area also effectively can be reduced especially in regard to a kind of driving force with enhancing.
Background technology
Shift register (shift register) is widely used in data drive circuit and the scan drive circuit of display equipment, in order to control the sequential of each data line sampled data signal respectively, and is that each gate line produces sweep signal.In scan drive circuit, shift register in order to produce one scan signal to each gate line, in order to drive the pixel on each gate line.On the other hand, in data drive circuit, shift register chooses signal to each data line in order to export one, makes view data can sequentially be written into each data line.
When the resolution of display equipment increases, required pixel quantity also can increase with the quantity of corresponding control circuit thereupon.But in order to avoid significantly increasing the integrated circuit area of drive device for display, control circuit must be simplified, and the control circuit of simplifying still must keep enough driving forces.In view of this, need a kind of brand-new driving circuit, not only there is the driving force of enhancing, also effectively can simplify circuit area.
Summary of the invention
According to one embodiment of the invention, a kind of display pannel, comprises scan driving circuit.Scan drive circuit comprises the shift register of multiple serial connection, and wherein at least one of shift register comprises control circuit, lifting circuit and output circuit.Control circuit in order to control the voltage of the first Controlling vertex according to an enabling signal, and controls the voltage of the second Controlling vertex according to reset signal.Lifting circuit is coupled to control circuit, in order to the voltage of lifting first Controlling vertex.Output circuit is coupled to lifting circuit and control circuit, exports multiple gate drive signal in order to the voltage according to the first Controlling vertex in multiple output node.The wherein one of gate drive signal is provided to next stage shift register, in order to this enabling signal as next stage shift register.
Accompanying drawing explanation
Fig. 1 is the display equipment calcspar of display according to one embodiment of the invention.
Fig. 2 is display one shift register calcspar.
Fig. 3 is the shift register serial connection calcspar of display according to one embodiment of the invention.
Fig. 4 is the one-to-many shift register calcspar of display according to one embodiment of the invention.
Fig. 5 is the one-to-many shift-register circuit figure of display according to one embodiment of the invention.
Fig. 6 is that each node voltage of display according to one embodiment of the invention changes and signal waveforms.
Fig. 7 shows shift register serial connection calcspar described according to another embodiment of the present invention.
Fig. 8 shows one-to-many shift-register circuit figure described according to another embodiment of the present invention.
Fig. 9 shows each node voltage change described according to another embodiment of the present invention and signal waveforms.
[label declaration]
30 scan drive circuit 100 display equipments
101 display pannel 102 input blocks
110 scan drive circuit 120 data drive circuits
130 picture element matrix 140 control chips
200,400,500,800, SR [1], SR [2], SR [3], SR [N-1], SR [N] shift register
201,401,501,801 control circuit 202,403,503,803 output circuits
402,502,802 lifting circuit 811,812 circuit subelements
Cc1, Cp electric capacity
CK, CK1, CK2, CK3, CK4 clock signal
D1, D2 time interval
G (1), G (2), G (3), G (4), G (5), G (6), G (7), G (8), G (9), G (n-2), G (n-1), G (n), G (n+1), G (n+2), G (3N-5), G (3N-4), G (3N-3), G (3N-2), G (3N-1), G (3N) gate drive signal
M1, M2, Tc1, Tc2, Tc3, TFT1-1, TFT1-2, TFT1-3, TFT2-1, TFT2-2, TFT2-3, Ts1, Ts2, Ts3 transistor
Ncp, P, Q, SP Controlling vertex
OUT, OUT1, OUT2, OUT3 output node
S
startenabling signal S
preChargeprecharging signal
S
resetreset signal T1, T2, T3, T4 time
V
0, V
1, V
2, V
3, V
4, V
gLvoltage
Embodiment
For making manufacture of the present invention, method of operating, target and advantage become apparent, several preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Embodiment:
Fig. 1 is the display equipment calcspar of display according to one embodiment of the invention.As shown in the figure, display equipment 100 can comprise display pannel 101, data drive circuit 120 and a control chip 140, and wherein display pannel 101 comprises scan driving circuit 110 and a picture element matrix 130.Scan drive circuit 110 is in order to produce multiple gate drive signal to drive multiple pixels of picture element matrix 130.Data drive circuit 120 is in order to produce multiple data drive signal to provide view data to multiple pixels of picture element matrix 130.Control chip 140, in order to produce multiple clock signal, comprises clock signal, reset signal and initial pulse etc.
In addition, display equipment 100 can comprise an input block 102 further.Input block 102, for receiving picture signal, shows image to control display pannel 101.According to embodiments of the invention, display equipment 100 can be applicable in an electronic installation, wherein electronic installation has numerous embodiments, comprising: a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop PC, a televisor, a vapour vehicle display, a portable disc are dialled and put device or any device comprising image display function.
According to one embodiment of the invention, scan drive circuit 110 comprises the shift register of multiple serial connection, and it sequentially can produce a gate drive signal to each gate line, in order to drive the pixel on each gate line.
Fig. 2 is display one shift register calcspar.Shift register 200 can comprise control circuit 201 and output circuit 202.Control circuit 201 is according to enabling signal S
startwith reset signal S
resetcontrol the voltage level of Controlling vertex P and Q.Output circuit 202 can comprise transistor M1 and M2, and electric capacity Cc1.Transistor M1 is coupled to Controlling vertex P, in order to its conducting state of voltage switching according to Controlling vertex P.Transistor M2 is coupled to Controlling vertex Q, in order to its conducting state of voltage switching according to Controlling vertex Q.When transistor M1 is switched on, clock signal C K can be transferred into output node OUT, as the gate drive signal exported.When transistor M2 is switched on, the voltage of output node OUT can be reset as low operating voltage V
gL.Because gate drive signal need be transferred into next stage shift register usually; in order to the enabling signal as next stage shift register; therefore; output circuit 202 can configure electric capacity Cc1 usually; in order to the voltage level of lifting Controlling vertex P; to strengthen the driving force of gate drive signal, the voltage of gate drive signal is made enough to start next stage shift register.
Shift register 200 shown in Fig. 2 is shift register one to one, and wherein shift register 200 only exports a gate drive signal.But in order to simplify the circuit area of scan drive circuit further, shift register can be modified to the framework of one-to-many.In other words, exportable many gate drive signals of one-level shift register, in order to drive many gate lines.
Fig. 3 is the shift register serial connection calcspar of display according to one embodiment of the invention.Scan drive circuit 30 can comprise multiple serial connection one-to-many shift register SR [1], SR [2], SR [3] ... SR [N-1], SR [N], wherein N is a positive integer.It should be noted that in order to clear elaboration concept of the present invention, the shift register SR [1] shown in Fig. 3 ~ SR [N] is a pair shift registers more than three.But it is to be understood that any those skilled in the art, without departing from the spirit and scope of the present invention, when concept according to the present invention doing a little change and retouching, implementation goes out a pair two, a pair four or the one-to-many shift register of other form.Therefore, the present invention is not limited to the framework shown in Fig. 3.
As shown in the figure, shift register SR [1] at different levels ~ SR [N] is respectively in order to export three gate drive signals, such as, shift register SR [1] exportable gate drive signal G (1) ~ G (3), shift register SR [2] exportable gate drive signal G (4) ~ G (6), and by that analogy.Except first order shift register SR [1], shift register at different levels can receive the wherein one of multiple gate drive signals that previous stage shift register exports as enabling signal, and first order shift register SR [1] then self controllable coremaking sheet receives the enabling signal S of initial pulse as correspondence
start.In addition, except afterbody shift register SR [N], shift register at different levels can receive the wherein one of multiple gate drive signals that rear stage shift register exports as reset signal (not shown), afterbody shift register SR [N] then self controllable coremaking sheet receiving system reset signal as the reset signal of correspondence.
Fig. 4 is the one-to-many shift register calcspar of display according to one embodiment of the invention.Shift register 400 can comprise control circuit 401, lifting circuit 402 and output circuit 403.Control circuit 401 can according to an enabling signal S
startcontrol a voltage of Controlling vertex P, and according to reset signal S
resetcontrol a voltage of Controlling vertex Q.As above-mentioned, enabling signal S
startcan be the wherein one of multiple gate drive signals that initial pulse or previous stage shift register export, and reset signal S
resetit can be the wherein one of multiple gate drive signals that system reset signal or rear stage shift register export.
Lifting circuit 402 is coupled to control circuit 401, in order to the voltage of lifting Controlling vertex P.Output circuit 403 is coupled to lifting circuit 402 and control circuit 401, exports multiple gate drive signal in order to the voltage according to Controlling vertex P and Q in multiple output node.According to one embodiment of the invention, control circuit 401 can draw high voltage to the first high-voltage level of Controlling vertex P in very first time interval, and lifting circuit 402 can in the voltage of the second time interval further lifting Controlling vertex P to the second high-voltage level higher than the first high-voltage level.Following paragraph does more detailed introduction by one-to-many shift-register circuit proposed by the invention.
Fig. 5 is the one-to-many shift-register circuit figure of display according to one embodiment of the invention.Shift register 500 can comprise control circuit 501, lifting circuit 502 and output circuit 503.Control circuit 501 can according to an enabling signal S
startcontrol a voltage of Controlling vertex P, and according to reset signal S
resetcontrol a voltage of Controlling vertex Q.Output circuit 503 can comprise multiple output unit, and each output unit comprises the transistor that pair of series couples respectively, such as, and transistor TFT1-1 and TFT2-1, TFT1-2 and TFT2-2 and TFT1-3 and TFT2-3.Each output unit receives the input signal of different clock signals as correspondence respectively, and be used to output node OUT1, OUT2 and OUT3 and export corresponding gate drive signal G (n), G (n+1) and G (n+2), wherein n is a positive integer.
According to one embodiment of the invention, transistor TFT1-1 have first end be coupled in order to receive clock signal CK1 an input node, one second end is coupled to Controlling vertex P and the 3rd end is coupled to output node OUT1, and transistor TFT2-1 has, and first end is coupled to output node OUT1, one second end is coupled to Controlling vertex Q and the 3rd end is coupled to low operating voltage V
gL.Similarly, transistor TFT1-2 have first end be coupled in order to receive clock signal CK2 an input node, one second end is coupled to Controlling vertex P and the 3rd end is coupled to output node OUT2, and transistor TFT2-2 has, and first end is coupled to output node OUT2, one second end is coupled to Controlling vertex Q and the 3rd end is coupled to low operating voltage V
gL.Transistor TFT1-3 have first end be coupled in order to receive clock signal CK3 an input node, one second end is coupled to Controlling vertex P and the 3rd end is coupled to output node OUT3, and transistor TFT2-3 has, and first end is coupled to output node OUT3, one second end is coupled to Controlling vertex Q and the 3rd end is coupled to low operating voltage V
gL.
Lifting circuit 502 can comprise electric capacity Cp and multiple lifting element.Electric capacity Cp is connected across between Controlling vertex P and Ncp.First lifting element is coupled to Controlling vertex Ncp, in order to receive enabling signal S
start, and in response to enabling signal S
startcontrol a voltage of Controlling vertex Ncp.Second lifting element is coupled to wherein between one of Controlling vertex Ncp and output node OUT1 ~ OUT3, in order to receive the wherein one of gate drive signal G (n) ~ G (n+2), and in response to the voltage of received gate drive signal further lifting Controlling vertex Ncp.
According to one embodiment of the invention, lifting element can be transistor, such as, and transistor Tc1 and Tc2.Transistor Tc1 has first end and is coupled to Controlling vertex Ncp, the second termination receipts enabling signal S
start, and the 3rd end be coupled to low operating voltage V
gL.Transistor Tc2 has that first end is coupled to Controlling vertex Ncp, the second end is coupled to output node OUT1 and the 3rd end is coupled to input node in order to receive clock signal CK1.According to one embodiment of the invention, lifting circuit 502 can comprise transistor Tc3 further.Transistor Tc3 has first end and is coupled to Controlling vertex Ncp, the second termination receipts reset signal S
reset, and the 3rd end be coupled to low operating voltage V
gL, in order in response to reset signal S
resetreset the voltage of Controlling vertex Ncp.
Fig. 6 is that each node voltage of display according to one embodiment of the invention changes and signal waveforms.According to one embodiment of the invention, enabling signal S
startcan be the gate drive signal G (n-1) that previous stage shift register exports, and reset signal S
resetcan be the gate drive signal G (n+3) that rear stage shift register exports.The circuit of composition graphs 5 and the oscillogram of Fig. 6, do more detailed introduction by the operation of one-to-many shift-register circuit proposed by the invention below.
Suppose that the initial voltage of Controlling vertex P is V
0, wherein voltage V
0can low voltage level be had, such as, low operating voltage V
gLvoltage level.As enabling signal S
starta pulses arrive time, the voltage of Controlling vertex P can be lifted as having high-voltage level V by the control of control circuit 501 is corresponding
1.Now, transistor Tc1 can be switched on, and makes the voltage of Controlling vertex Ncp have low operating voltage V
gLa low voltage level.The same time, transistor TFT1-1, TFT1-2 and TFT1-3 also can be switched on, in order to respectively using the wave form output of clock signal C K1, CK2 and CK3 as gate drive signal G (n) of correspondence, G (n+1) and G (n+2).
When a pulses arrive of clock signal CK1, gate drive signal G (n) can correspondingly produce a pulse, and now, transistor Tc2 can be switched on, and equals high operation voltage V with the voltage drawing high Controlling vertex Ncp to rough
gHa high-voltage level.Now, the voltage of Controlling vertex P can be driven high to another high-voltage level V in response to the change in voltage of Controlling vertex Ncp
2.As shown in Figure 6, Controlling vertex P has high-voltage level V in the very first time interval D1
1, and in the second time interval D2, there is high-voltage level V
2, wherein V
2>V
1.Finally, as reset signal S
reseta pulses arrive time, the voltage of Controlling vertex P can be reset.The same time, the voltage of Controlling vertex Q can have high-voltage level, in order to reset the voltage level of output node OUT1 ~ OUT3.
According to one embodiment of the invention, because the voltage of Controlling vertex Ncp is first in response to enabling signal S
startpulse be charged to low voltage level, then be charged to high-voltage level in response to clock signal C K1 and gate drive signal G (n).Therefore, by the coupling effect of electric capacity Cp, the change in voltage of Controlling vertex Ncp can be coupled to Controlling vertex P, makes the voltage of Controlling vertex P can from voltage V
1be driven high to V
2, in order to strengthen the driving force of shift register, wherein when the electronic component in circuit is by suitable design, V
2-with V
1pressure differential deltap P can close to (V
gH-V
gL).
Compared to the circuit shown in Fig. 2, in preferred embodiment of the present invention, electric capacity in output circuit is cancelled, change the main power using lifting circuit 502 as lifting Controlling vertex P into, thus, the lifting pressure differential deltap P of Controlling vertex P can not decay because of the electric capacity dispersion effect in output circuit.If it should be noted that the electric capacity not cancelling output circuit, then the output unit quantity coupled when output circuit is more, and electric capacity dispersion effect is larger, and what the voltage of Controlling vertex P can be attenuated is more serious.
In preferred embodiment of the present invention, as shown in Figure 6, the voltage of Controlling vertex P effectively can be raised to the high operation voltage V far above system in the second time interval D2
gHa voltage level, thus, effectively enhance the driving force of Controlling vertex P, make the pulse of the clock signal received in each input node can intactly be transferred into output node as grid impulse.It should be noted that in circuit framework proposed by the invention, even if the output unit quantity that output circuit couples increases, the voltage of Controlling vertex P also can not significantly be decayed, and effectively solves the problem of traditional one-to-many shift-register circuit driving force deficiency.
In addition, as above-mentioned, because the gate drive signal of shift register output will be provided to the enabling signal of next stage shift register as this grade of shift register, therefore, except strengthening Controlling vertex P except the voltage lifting ability of the second time interval D2, according to another embodiment of the present invention, control circuit 401/501 can receive a precharging signal further, and control Controlling vertex P in the voltage of the very first time interval D1 according to precharging signal and enabling signal, in order to promote enabling signal further in the driving force of the very first time interval D1.
According to one embodiment of the invention, precharging signal can be the wherein one of multiple gate drive signals that previous stage shift register exports, and the pulse of precharging signal is better with the pulse of arriving at early than enabling signal.Fig. 7 shows shift-register circuit calcspar described according to another embodiment of the present invention.Shift-register circuit 70 can comprise multiple serial connection one-to-many shift register SR [1], SR [2], SR [3] ... SR [N-1], SR [N], wherein N is a positive integer.It should be noted that in order to clear elaboration concept of the present invention, the shift register SR [1] shown in Fig. 7 ~ SR [N] is a pair shift registers more than three.But it is to be understood that any those skilled in the art, without departing from the spirit and scope of the present invention, when concept according to the present invention doing a little change and retouching, implementation goes out a pair two, a pair four or the one-to-many shift register of other form.Therefore, the present invention is not limited to the framework shown in Fig. 3.
Circuit framework shown in Fig. 7 and Fig. 3 duplicate, its difference is only except first order shift register SR [1], shift register at different levels receive multiple gate drive signals that previous stage shift register exports wherein both as enabling signal and precharging signal.Introduction about Fig. 7 with reference to the explanation of figure 3, and can repeat no more in this.Following paragraph does more detailed introduction by control circuit proposed by the invention.
Fig. 8 shows one-to-many shift-register circuit figure described according to another embodiment of the present invention.Shift register 800 can comprise control circuit 801, lifting circuit 802 and output circuit 803.Lifting circuit 802 duplicates with output circuit 503 with the circuit framework of output circuit 803 and the lifting circuit shown in Fig. 5 502, and therefore relevant introduction with reference to the explanation of figure 5, can repeat no more in this.According to one embodiment of the invention, control circuit 801 can comprise multiple circuit subelement, such as, and circuit subelement 811 and 812.Circuit subelement 811 can according to enabling signal S
startwith precharging signal S
preChargecontrol the voltage of Controlling vertex P, circuit subelement 812 can according to reset signal S
resetcontrol the voltage of Controlling vertex Q.It should be noted that control circuit is not shown in circuit subelement in figure when comprising other, therefore the present invention is not limited to the framework shown in Fig. 8.
Circuit subelement 811 can comprise multiple control element.First control element is coupled to Controlling vertex SP, and receives precharging signal S
preCharge, in order in response to precharging signal S
preChargecontrol a voltage of Controlling vertex SP.Second control element is coupled to Controlling vertex P and SP, and receives enabling signal S
start, in order in response to enabling signal S
startthe voltage of lifting Controlling vertex SP.3rd control element is coupled to Controlling vertex SP, and receives input signal CK1, in order to reset the voltage of Controlling vertex SP in response to input signal CK1.
According to one embodiment of the invention, control element can be transistor, such as, and transistor Ts1, Ts2 and Ts3.Transistor Ts1 has first end and the second termination receives precharging signal S
preCharge, and the 3rd end be coupled to Controlling vertex SP.Transistor Ts2 have first end receive enabling signal should, the second end is coupled to Controlling vertex SP and the 3rd end is coupled to Controlling vertex P.Transistor Ts3 has first end and is coupled to Controlling vertex SP, and the second termination receives an input signal CK1 and the 3rd end is coupled to low operating voltage V
gL.
Fig. 9 shows each node voltage change described according to another embodiment of the present invention and signal waveforms.According to one embodiment of the invention, enabling signal S
startcan be the gate drive signal G (n-1) that previous stage shift register exports, precharging signal S
preChargecan be the gate drive signal G (n-2) that previous stage shift register exports, and reset signal S
resetcan be the gate drive signal G (n+3) that rear stage shift register exports.The circuit of composition graphs 8 and the oscillogram of Fig. 9, do more detailed introduction by the operation of control circuit proposed by the invention below.
According to one embodiment of the invention, as precharging signal S
preChargea pulse when the time, T1 arrived at, transistor Ts1 is switched on, and makes the voltage of Controlling vertex SP have third high voltage level V
3.The same time, transistor Ts2 also can the conducting in response to the high-voltage level of Controlling vertex SP.As enabling signal S
starta pulse when the time, T2 arrived at, the voltage of Controlling vertex P can be driven high as having the first high-voltage level V
1, make the voltage of Controlling vertex SP in response to the change in voltage of Controlling vertex P (that is, by V
0-to V
1) be driven high to higher than third high voltage level V
3the 4th high-voltage level V
4.
In embodiments of the invention, utilize precharging signal S
preChargeby transistor Ts1, Controlling vertex SP is charged, and in advance by transistor Ts2 conducting, make as enabling signal S
starta pulses arrive time, the voltage of Controlling vertex SP can by further lifting, and Controlling vertex SP like this just can successfully charge to Controlling vertex P and not have pressure drop, effectively promotes Controlling vertex P in the driving force of the very first time interval D1.
When a pulse of clock signal CK1 is when the time, T3 arrived at, the voltage of Controlling vertex P can be driven high to another high-voltage level V as the above-mentioned change in voltage in response to Controlling vertex Ncp
2.As shown in Figure 9, Controlling vertex P has high-voltage level V in the very first time interval D1
1, and in the second time interval D2, there is high-voltage level V
2, wherein V
2>V
1.The same time (T3), transistor Ts3 can be switched on, and in order to reset the voltage of Controlling vertex SP, and closes transistor Ts2.Finally, as reset signal S
reseta pulse when the time, T4 arrived at, the voltage of Controlling vertex P can be reset.The same time (T4), the voltage of Controlling vertex Q can have high-voltage level, in order to reset the voltage level of output node OUT1 ~ OUT3.
In preferred embodiment of the present invention, Controlling vertex P controls effectively to be promoted in the voltage level of the very first time interval D1 by two stepwises of circuit subelement 811, and the voltage of Controlling vertex P is effectively promoted in the voltage level of the second time interval D2 by the control of lifting circuit 402/502/802, thus, effectively enhance the driving force of Controlling vertex P, the pulse of the clock signal received in each input node is made can be intactly transferred into output node as grid impulse, and the gate drive signal of each shift register output also intactly can be provided to the enabling signal of next stage shift register as this grade of shift register, the problem of effective solution traditional one-to-many shift register driving force deficiency.In addition, be there is by single level shift register the design of multiple output units, also effectively can reduce the circuit area of shift-register circuit, the area of entire scan driving circuit can more be simplified.
It should be noted that in order to clear elaboration concept of the present invention, be a pair three shift registers in the shift register shown in the above embodiments.But it is to be understood that any those skilled in the art, without departing from the spirit and scope of the present invention, when concept according to the present invention doing a little change and retouching, implementation goes out a pair two, a pair four or the one-to-many shift register of other form.Therefore, the present invention is not limited to the framework shown in figure.In addition, in embodiments of the invention, the shift-register circuit of a pair K is to use (K+1) individual clock signal to be better.Such as, in the example of waveform shown in Fig. 6 and Fig. 9,1 contains CK1 ~ CK4 to the clock signal that 3 shift registers use.It is to be noted, however, that the configuration in the clock signal shown in figure in each input endpoint is only the wherein a kind of of multiple possibility embodiment, therefore the present invention is not limited to the clock signal configuration shown in figure.
Do not imply the order of the precedence between any right of priority, priority ranking, each element or the step performed by method in claim in order to the use of ordinal numbers such as " first ", " second " of modified elements itself, and only distinguish the different elements with same names (there is different ordinal number) with making a check mark.
Though the present invention discloses as above with preferred embodiment; so itself and be not used to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended right person of defining.
Claims (10)
1. a display pannel, comprising:
Scan driving circuit, comprises the shift register of multiple serial connection, and wherein at least one of the plurality of shift register comprises:
One control circuit, in order to control the voltage of one first Controlling vertex according to an enabling signal, and controls the voltage of one second Controlling vertex according to a reset signal;
One lifting circuit, is coupled to this control circuit, in order to the voltage of this first Controlling vertex of lifting; And
One output circuit, is coupled to this lifting circuit and this control circuit, exports multiple gate drive signal in order to the voltage according to this first Controlling vertex in multiple output node,
Wherein the wherein one of the plurality of gate drive signal is provided to next stage shift register, in order to this enabling signal as next stage shift register.
2. display pannel according to claim 1, wherein this lifting circuit comprises:
One electric capacity, is coupled between this first Controlling vertex and one the 3rd Controlling vertex;
One the first transistor, has that a first end is coupled to the 3rd Controlling vertex, one second termination receives this enabling signal and one the 3rd end is coupled to a low operating voltage; And
One transistor seconds, has a first end is coupled to the 3rd Controlling vertex, one second end is coupled to the plurality of output node wherein one and one the 3rd end is coupled to an input node, in order to receive an input signal.
3. display pannel according to claim 2, wherein when a pulses arrive of this enabling signal, the voltage of this first Controlling vertex has one first high-voltage level, and this first transistor is switched on, and makes the voltage of the 3rd Controlling vertex have a low voltage level.
4. display pannel according to claim 3, wherein when a pulses arrive of the wherein one of the plurality of gate drive signal, this transistor seconds is switched on, in order to draw high the voltage of the 3rd Controlling vertex according to this input signal, make the voltage of this first Controlling vertex because should the change in voltage of the 3rd Controlling vertex be driven high to one second high-voltage level higher than this first high-voltage level.
5. display pannel according to claim 2, wherein this lifting circuit also comprises:
One third transistor, has that a first end is coupled to the 3rd Controlling vertex, one second termination receives this reset signal and one the 3rd end is coupled to this low operating voltage, in order to because resetting the voltage of the 3rd Controlling vertex by reset signal.
6. display pannel according to claim 1, wherein this control circuit also receives a precharging signal, and the voltage of this first Controlling vertex is controlled according to this precharging signal and this enabling signal, the wherein wherein one of the plurality of gate drive signal that exports for previous stage shift register of this precharging signal, and a pulses arrive of this precharging signal is early than a pulse of this enabling signal.
7. display pannel according to claim 6, wherein this control circuit comprises:
One the 4th transistor, has a first end and one second termination receives this precharging signal and one the 3rd end is coupled to the 4th Controlling vertex; And
One the 5th transistor, has that a first end receives this enabling signal, one second end is coupled to one the 4th Controlling vertex and one the 3rd end is coupled to this first Controlling vertex.
8. display pannel according to claim 7, wherein when a pulses arrive of this precharging signal, the 4th transistor is switched on, and makes the voltage of the 4th Controlling vertex have a third high voltage level, and the 5th transistor is switched on.
9. display pannel according to claim 8, wherein when a pulses arrive of this enabling signal, the voltage of this first Controlling vertex is driven high, and makes the voltage of the 4th Controlling vertex because should the change in voltage of the first Controlling vertex be driven high to one the 4th high-voltage level higher than this third high voltage level.
10. display pannel according to claim 7, wherein this control circuit comprises:
One the 6th transistor, has a first end and is coupled to the 4th Controlling vertex, and one second termination receives this input signal and one the 3rd end is coupled to a low operating voltage, in order to because resetting the voltage of the 4th Controlling vertex by input signal.
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| CN201310694631.3A CN104715707A (en) | 2013-12-17 | 2013-12-17 | Display panel |
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|---|---|---|---|
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| CN (1) | CN104715707A (en) |
Cited By (1)
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| US10096293B2 (en) * | 2015-12-28 | 2018-10-09 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driver and liquid crystal display |
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