CN102800292A - Gate driving circuit - Google Patents
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- CN102800292A CN102800292A CN2012102978537A CN201210297853A CN102800292A CN 102800292 A CN102800292 A CN 102800292A CN 2012102978537 A CN2012102978537 A CN 2012102978537A CN 201210297853 A CN201210297853 A CN 201210297853A CN 102800292 A CN102800292 A CN 102800292A
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Abstract
The invention discloses a gate driving circuit which comprises a plurality of gate driving sub-circuits, wherein each gate driving sub-circuit comprises an upward-pull switch element, a downward-pull switch element and a latch; and the latch is used for respectively carrying out first-stage upward pull and second-stage upward pull on voltage output from the output end of the latch through a first upward pull signal and a second upward pull signal which are respectively input from a first upward pull signal input end and a second upward pull signal end so as to improve a control signal output from the latch to a first control end of the upward-pull switch element. According to the invention, the latches can output very high voltage to the upward-pull switch elements in a time period in which the gate driving sub-circuits output gate voltage, and then the output capability of the upward-pull switch element is improved, so that the sizes of the upward-pull switch elements can be further decreased on the premise of outputting enough gate voltage, therefore, the gate driving circuit is specifically suitable for meeting the design requirements of small-panel liquid crystal display devices.
Description
Technical field
The present invention relates to a kind of driving circuit, particularly a kind of gate driver circuit that is applicable to liquid crystal indicator.
Background technology
(Liquid Crystal Display LCD) possesses plurality of advantages such as frivolous, energy-conservation, radiationless to liquid crystal indicator, has therefore replaced traditional cathode ray tube (CRT) display gradually.LCD is widely used in the electronic equipments such as HD digital TV, desk-top computer, PDA(Personal Digital Assistant), notebook computer, mobile phone, digital camera at present.
With thin film transistor (TFT) (Thin Film Transistor; TFT) liquid crystal indicator is an example; It comprises: display panels and driving circuit, and wherein, display panels comprises many gate lines and many data lines; And adjacent two gate lines and two adjacent data lines intersect to form a pixel cell, and each pixel cell comprises a thin film transistor (TFT) at least.And driving circuit comprises: gate driver circuit (gate drive circuit) and source electrode drive circuit (source drive circuit).Along with the producer pursues the cost degradation of liquid crystal indicator and the raising of manufacturing process; Originally being arranged at driving circuit integrated chip beyond the display panels is set on the glass substrate of display panels and becomes possibility; For example; With grid-driving integrated circuit be arranged at array base palte (Gate Ic in array, thus GIA) go up to simplify the manufacture process of liquid crystal indicator, and reduce production costs.
Display panels with the basic functional principle of driving circuit is: gate driver circuit is seen grid voltage through pulling up transistor of being connected with gate line off to gate line; TFT with each row opens in regular turn; Simultaneously the pixel cell of a full line is charged to required separately voltage by source electrode drive circuit then, to show different gray levels.Promptly at first pull up transistor through it thin film transistor (TFT) of first row is opened, charge by the pixel cell of source electrode drive circuit then first row by the first capable gate driver circuit.When the pixel cell of first row is charged; Gate driver circuit is just closed this row thin film transistor (TFT); The gate driver circuit of second row pulls up transistor through it thin film transistor (TFT) of second row is opened then, is discharged and recharged by the pixel cell of source electrode drive circuit to second row again.So go down in regular turn, when the pixel cell of the last column of having substituted the bad for the good, just again since the first row charging.
But, because narrow frame and high-res (be resolution, the development of small size panel resolution); Design to gate driver circuit has proposed new challenge: on the one hand; Narrow frame has limited the size of gate driver circuit, and the size that pulls up transistor (channel width-over-length ratio) of corresponding output stage also is restricted, and (transistorized driving force is represented with its conduction factor because the driving force that pulls up transistor is directly proportional with its size; The value of the conduction factor is big more; Its driving force is strong more, and the conduction factor then is directly proportional with transistorized channel width-over-length ratio), therefore also promptly reduced the driving force that pulls up transistor if dwindle the size that pulls up transistor; Thereby possibly cause its fan-out capability to reduce, i.e. the voltage of gate driver circuit output reduces; On the other hand; The panel of high-res makes the load of grid cabling bigger; Thereby in order to guarantee the normal demonstration and the display quality of liquid crystal indicator; Even need pulling up transistor of stronger fan-out capability, export enough voltage yet the undertension that the restriction of size but makes latch export to the gate terminal that pulls up transistor pulls up transistor with driving to gate line, thereby caused a contradiction in the gate driver circuit design.
Summary of the invention
The purpose of this invention is to provide a kind of gate driver circuit, to solve the not enough problem of fan-out capability that pulls up transistor of gate driver circuit in the development of available liquid crystal display device miniaturization and high-res.
The present invention proposes gate driver circuit, comprises multistage gate driving electronic circuit, and wherein every grade of gate driving electronic circuit is used for driving respectively the gate line of a correspondence, and every grade of gate driving electronic circuit comprises:
Last drag switch element comprises first input end, first output terminal and first control end, and said first input end receives first clock signal, and said first output terminal is as the output terminal of gate driving electronic circuit;
The element that pulls down switch comprises second input end, second output terminal and second control end, and said second control end receives second clock signal, and said second input end connects a low reference voltage, and said second output terminal connects said first output terminal;
Latch, it comprises:
Draw signal input part on first, be used to receive input first on draw signal;
Draw signal input part on second, be used to receive input second on draw signal;
The latch output terminal; Connect said first control end of going up the drag switch element to output control signals to said first control end of going up the drag switch element; Said latch draws signal according to drawing on signal and said second on said first, so that the control signal of its said latch output terminal output is carried out respectively drawing on the first order and the second level.
According to the described gate driver circuit of preferred embodiment of the present invention; Every grade of gate driving electronic circuit also comprises: on draw electric capacity; It is connected between said first control end and said first output terminal of said upward drag switch element, is used for the control signal that said latch output terminal is exported is carried out drawing on the third level.
According to the described gate driver circuit of preferred embodiment of the present invention, drawing electric capacity on said is the said stray capacitance that goes up the drag switch element.
According to the described gate driver circuit of preferred embodiment of the present invention, said latch comprises:
The 3rd on-off element, it comprises the 3rd input end, the 3rd output terminal and the 3rd control end, said the 3rd input end all is connected on said first with said the 3rd control end and draws signal input part; Coupling capacitance, one of which end connect on said second draws signal input part; The 4th on-off element; It comprises four-input terminal, the 4th output terminal and the 4th control end; Said the 4th control end links to each other with said four-input terminal; And connect the other end of said coupling capacitance and said the 3rd output terminal of said the 3rd on-off element respectively, said the 4th output terminal as said latch output terminal to connect the said drag switch element of going up.
According to the described gate driver circuit of preferred embodiment of the present invention, said latch also comprises:
The pulldown signal input end is used to import the pulldown signal of drop-down said latch output terminal output voltage; The 5th on-off element; It comprises the 5th input end, the 5th output terminal and the 5th control end; Said the 5th control end connects said pulldown signal input end, and said the 5th output terminal connects the 4th output terminal of said the 4th on-off element, and said the 5th input end connects a low reference voltage.
According to the described gate driver circuit of preferred embodiment of the present invention, said pulldown signal input end connects output terminal or the output terminal of downward partial gate driving electronic circuit of the gate driving electronic circuit of the downward third level.
According to the described gate driver circuit of preferred embodiment of the present invention; Every grade of gate driving electronic circuit also comprises: the 6th on-off element; It comprises the 6th input end, the 6th output terminal and the 6th control end; Said the 6th input end connects said said first control end of going up the drag switch element; Node between said first output terminal of the said upward drag switch element of said the 6th output terminal connection and said second output terminal of the said element that pulls down switch, said the 6th control end connects the said said first input end of going up the drag switch element.
According to the described gate driver circuit of preferred embodiment of the present invention, said latch also comprises:
Minion is closed element; It comprises the 7th input end, the 7th output terminal and the 7th control end; Said the 7th control end connects said pulldown signal input end, and said the 7th output terminal connects said the 3rd output terminal of said the 3rd on-off element, and said the 7th input end connects said low reference voltage.
According to the described gate driver circuit of preferred embodiment of the present invention; Every grade of gate driving electronic circuit also comprises: octavo is closed element; It comprises the 8th input end, the 8th output terminal and the 8th control end; Said the 8th control end connects said pulldown signal input end, the node between said first output terminal of the said upward drag switch element of said the 8th output terminal connection and said second output terminal of the said element that pulls down switch, and said the 8th input end connects said low reference voltage.
According to the described gate driver circuit of preferred embodiment of the present invention, every grade of gate driving electronic circuit also comprises: first stablizes electric capacity, and the one of which end connects said first clock signal; The 9th on-off element; It comprises the 9th input end, the 9th output terminal and the 9th control end; Said the 9th output terminal connect said first stablize electric capacity the other end; Said the 9th input end connects said low reference voltage, the node between said first output terminal of the said upward drag switch element of said the 9th control end connection and said second output terminal of the said element that pulls down switch; The tenth on-off element; It comprises the tenth input end, the tenth output terminal and the tenth control end; Node between said first output terminal of the said upward drag switch element of said the tenth output terminal connection and said second output terminal of the said element that pulls down switch; Said the tenth input end connects said low reference voltage, said the tenth control end connect said first stablize electric capacity the other end.
According to the described gate driver circuit of preferred embodiment of the present invention, every grade of gate driving electronic circuit also comprises: second stablizes electric capacity, and the one of which end connects said first clock signal; The 11 on-off element; It comprises the 11 input end, the 11 output terminal and the 11 control end; Said the 11 input end connects said low reference voltage; Said the 11 output terminal connect said second stablize electric capacity the other end, said the 11 control end connects said said first control end of going up the drag switch element; Twelvemo is closed element; It comprises the 12 input end, the 12 output terminal and the 12 control end; Said the 12 input end connects said low reference voltage; Node between said the 11 control end of said the 12 output terminal and said first control end, said the 12 control end connect said second stablize electric capacity the other end; The 13 on-off element; It comprises the 13 input end, the 13 output terminal and the 13 control end; Said the 13 control end connect said second stablize electric capacity the other end; Said the 13 input end connects said low reference voltage, the node between said first output terminal of the said upward drag switch element of said the 13 output terminal connection and said second output terminal of the said element that pulls down switch.
According to the described gate driver circuit of preferred embodiment of the present invention; Said gate driver circuit comprises level Four gate driving electronic circuit at least; And import said first clock signal leading 1/4 cycle of said first clock signal of gate driving electronic circuit at the corresponding levels, import said second clock signal leading 1/4 cycle of said second clock signal of gate driving electronic circuit at the corresponding levels than input next stage gate driving electronic circuit than input next stage gate driving electronic circuit.
According to the described gate driver circuit of preferred embodiment of the present invention; Each grade gate driving electronic circuit in the said gate driver circuit after the gate driving electronic circuit of the second level first on draw signal input part to connect the output terminal of its partial gate driving electronic circuit that makes progress, each grade gate driving electronic circuit in the perhaps said gate driver circuit from first order gate driving electronic circuit after second on draw the output terminal of the gate driving electronic circuit of its upper level of signal input part connection.
With respect to prior art, the invention has the beneficial effects as follows:
The present invention utilize latch first on draw draw on signal input part and second signal input part input first on draw on signal and second and draw signal; Respectively to the output voltage of latch carried out the first order and partial on draw; And can combine to draw on the third level of electric capacity and draw; Thereby in the time period of gate driving electronic circuit output grid voltage; Make the latch very high voltage of drag switch element output that can make progress, thereby make that going up the drag switch element has stronger fan-out capability, therefore guaranteeing that gate driver circuit can export under the prerequisite of enough grid voltages; Can also further reduce to go up drag switch size of component (being breadth length ratio), therefore gate driver circuit of the present invention can meet the designing requirement of liquid crystal indicator miniaturization and high-res development especially.
Certainly, arbitrary product of embodiment of the present invention might not reach above-described all advantages simultaneously.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of instructions, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the overall circuit structural representation of gate driving electronic circuit of the present invention;
Fig. 2 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention one;
Fig. 3 is the sequential synoptic diagram of first kind of form of gate driving electronic circuit in the embodiment of the invention one;
Fig. 4 is the sequential synoptic diagram of second kind of form of gate driving electronic circuit in the embodiment of the invention one;
Fig. 5 is the effect comparison synoptic diagram of gate driver circuit in the present invention and the prior art;
Fig. 6 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention two;
Fig. 7 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention three;
Fig. 8 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention four;
Fig. 9 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention five;
Figure 10 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention six.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To its embodiment of gate driver circuit, method, step and the effect that proposes according to the present invention, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can clearly appear in following the cooperation in the graphic preferred embodiment detailed description of reference.Through the explanation of embodiment, when can being to reach technological means and the effect that predetermined purpose takes to be able to more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.In the accompanying drawings, for clarity, exaggerated the thickness in layer, film and zone.Identical label is represented components identical all the time.
Although the present invention uses first, second, third term such as grade to describe different elements, signal, port, assembly or part, these elements, signal, port, assembly or part do not receive the restriction of these terms.These terms only are to be used for an element, signal, port, assembly or part and another element, signal, port, assembly or part are made a distinction.In the present invention, element, port, assembly or part and another element, port, assembly or part " linking to each other " are appreciated that to be direct electric connection, perhaps also are appreciated that to there being the indirect electric connection of intermediary element.Only if definition is arranged in addition, otherwise all terms used in the present invention (comprising technical term and scientific terminology) have the meaning with those skilled in the art institute common sense.
Gate driver circuit of the present invention comprises multistage gate driving electronic circuit; The corresponding connection of each row gate line on the gate driving electronic circuit of each grade and the liquid crystal panel; And signal is applied on the gate line successively according to the order of sequence, the annexation between the gate driving electronic circuit will be done detailed elaboration hereinafter.
See also Fig. 1, it is for the general structure synoptic diagram of gate driving electronic circuit of the present invention.As shown in Figure 1, it comprises drag switch element M1, element M2 and latch (latch) 21 pull down switch.Last drag switch element M1 comprises first input end, first output terminal and first control end, and first input end connects the output terminal Gn of the first clock signal input end, 22, the first output terminals as the gate driving electronic circuit.The element M2 that pulls down switch comprises second input end, second output terminal and second control end; Second control end connects the second clock signal input end 23; Second output terminal connects first output terminal of going up drag switch element M1, and second input end connects a low reference voltage VGL.
Embodiment one
Fig. 2 is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention one.See also Fig. 2, wherein shown the concrete circuit structure of latch among Fig. 1 21, and present embodiment is preferred implementation of the present invention.The gate driving electronic circuit of present embodiment comprises latch 21, goes up drag switch element M1, the element M2 that pulls down switch, on draw capacitor C 3 and the 6th on-off element M6.First control end of last drag switch element M1 connects the latch output terminal Q of latch 21; The first input end of last drag switch element M1 connects the first clock signal input end 22, and first output terminal of last drag switch element M1 is as the output terminal Gn of gate driving electronic circuit.Second control end of element M2 of pulling down switch connects the second clock signal input end 23, and second output terminal of the element M2 that pulls down switch connects first output terminal of going up drag switch element M1, and second input end of the element M2 that pulls down switch connects a low reference voltage VGL.On draw capacitor C 3 to be connected between the output terminal Gn of latch output terminal Q and gate driving electronic circuit of latch 21, be used for to latch 21 upwards the voltage of first control end output of drag switch element M1 carry out drawing on the third level.Special, for catering in the small size liquid crystal indicator requirement to grid circuit, on to draw capacitor C 3 can be to go up drag switch element M1 stray capacitance.The 6th on-off element M6 comprises the 6th input end, the 6th output terminal and the 6th control end; The 6th input end connects first control end of going up drag switch element M1; Node between first output terminal of the last drag switch element M1 of the 6th output terminal connection and second output terminal of the element M2 that pulls down switch, the 6th control end connects the first input end of going up drag switch element M1.
Present embodiment gate driving electronic circuit first on draw signal input part 24 to connect the output terminal of the partial gate driving electronic circuit that makes progress; Draw the output terminal of the gate driving electronic circuit of signal input part 25 connection upper levels on second, the output terminal of the gate driving electronic circuit of the downward third level of pulldown signal input end 26 connections or the output terminal of downward partial gate driving electronic circuit.Suppose that promptly present embodiment gate driving electronic circuit is a n level gate driving electronic circuit; Wherein, N ≧ 3, the grid voltage of its output is VGn, then drawing the voltage of signal input part 24 inputs on first is VGn-2; Drawing the voltage of signal input part 25 inputs on second is VGn-1, and the voltage of pulldown signal input end 26 inputs is VGn+3 or VGn+2.It should be noted that; Under this connected mode; Because first order gate driving electronic circuit is not to the upper level and the partial gate driving electronic circuit that makes progress; The second level gate driving electronic circuit partial gate driving electronic circuit that do not make progress, thus first order gate driving electronic circuit first on draw the input voltage that draws on signal input part 24 and second on the signal input part 25, and second level gate driving electronic circuit first on draw signal input part 24 all will provide by the external signal circuit.
Certainly; Connected mode between this gate driving electronic circuit is the preferred a kind of embodiment of the present invention; But do not limit the present invention with this; Draw signal input part 25 input to draw this core concept of signal on being used for the first order of latch 21 output voltages and the second level on signal input part 24 and second as long as meet to drawing on first, the variation of any connected mode should be all in protection scope of the present invention.For example draw on first signal input part 24 can connect the upwards output terminal of the 6th grade of gate driving electronic circuit; Draw signal input part 25 can connect the upwards output terminal of level V gate driving electronic circuit on second, also or even all gate driving electronic circuits first on draw the input voltage that draws signal input part 25 on signal input part 24 and second to provide etc. by the external signal circuit all should be in protection scope of the present invention.
See also Fig. 3 and Fig. 4; It is respectively the sequential synoptic diagram of two kinds of forms of gate driving electronic circuit among the embodiment one; Wherein, The input voltage that first kind of form shown in Figure 3 is pulldown signal input end 26 is the sequential synoptic diagram of VGn+3, and the input voltage that second kind of form shown in Figure 4 is pulldown signal input end 26 is the sequential synoptic diagram of VGn+2.Existing sequential chart with first kind of form shown in Figure 3 is an example, and the course of work of gate driving electronic circuit is elaborated.Wherein, For ease of narration; The signal of the input first clock signal input end 22 is called the CLK1 signal, the signal of importing the second clock signal input end 23 is called the CLK3 signal, with drawing the signal of signal input part 24 to be called the Gn-2 signal in the input first; With drawing the signal of signal input part 25 to be called the Gn-1 signal in the input second, the signal of importing pulldown signal input end 26 is called the Gn+3 signal.The course of work of each grade gate driving electronic circuit is divided into 7 sections:
Stage 1: draw the Gn-2 signal of signal input part 24 to serve as start signal in the input first; This moment, the Gn-2 signal was a high level; The 3rd on-off element M3 conducting, the Q2 level point is drawn high, thus the 4th also conducting of on-off element M4; The output terminal Q point of latch 21 begins charging, realizes drawing on the first time to latch 21 output voltages.In addition; Because the Q point voltage is drawn high; Last drag switch element M1 is switched on, the CLK1 low level signal of the first clock signal input end 22 input through last drag switch element M1 output to the gate driving electronic circuit output terminal Gn, but the CLK3 signal of the second clock signal input end, 23 inputs this moment is a high level; The element M2 conducting that pulls down switch, the grid voltage of the output terminal Gn output of gate driving electronic circuit is pulled down to low reference voltage VGL (being that grid voltage VGn low level resets).
The Gn-1 signal that draws signal input part 25 input on 2: the second stages from low to high because this moment, the Gn-2 signal still was a high level, thereby the coupling capacitance C2 lower end Q2 voltage of ordering is coupled once more on the basis in stage 1 and draws high.Because the 4th on-off element M4 is in conducting state, thereby the voltage that the output terminal Q of latch 21 order drawn high on the basis in stage 1 equally, thereby realization was drawn on the second time to latch 21 output voltages.In addition; Drag switch element M1 still is a conducting state on this moment; The CLK1 low level signal of the first clock signal input end, 22 inputs outputs to the output terminal Gn of gate driving electronic circuit through last drag switch element M1; But the CLK3 signal of the second clock signal input end, 23 inputs is a high level still, the element M2 conducting that pulls down switch, and the grid voltage of the output terminal Gn output of gate driving electronic circuit is pulled down to low reference voltage VGL.
The CLK1 signal of 3: the first stages clock signal input end 22 input from low to high, drag switch element M1 is in conducting state on this moment, the high voltage of CLK1 signal through last drag switch element M1 output to the gate driving electronic circuit output terminal Gn.The CLK3 signal of the second clock signal input end, 23 inputs becomes low level, and the element M2 that pulls down switch breaks off.In this stage since on draw capacitor C 3 bootstrapping, the voltage that the output terminal Q of latch 21 order is further drawn high, realization to latch 21 output voltages for the third time on draw, thereby make drag switch element M1 possess a higher fan-out capability.It should be noted that; In the present invention; The stray capacitance that can directly adopt drag switch element M1 as on draw capacitor C 3, perhaps draw effect on promoting, can also adopt an independent capacitance as on draw capacitor C 3; Wherein, this independent capacitance is parallelly connected with the stray capacitance of last drag switch element M1.
The CLK1 signal of 4: the first stages clock signal input end, 22 inputs is kept high level, and the output terminal Gn of gate driving electronic circuit still exports higher grid voltage.The Gn-1 signal that draws signal input part 25 inputs this moment on second from high to low, the Q2 point voltage is dragged down.But because the structure that Q2 point, the 4th on-off element M4, Q orders is equivalent to diode structure, so the voltage that the output terminal Q of latch 21 order keeps original current potential because oppositely end on the contrary, makes the higher fan-out capability of drag switch element M1 maintenance.
The CLK1 signal of 5: the first stages clock signal input end 22 input is by high step-down, the output step-down of the output terminal Gn of gate driving electronic circuit.The CLK3 signal of the second clock signal input end, 23 inputs is uprised by low, the element M2 conducting that pulls down switch, and the grid voltage of the output terminal Gn output of gate driving electronic circuit is pulled down to low reference voltage VGL.
Stage 6: the Gn+3 signal of pulldown signal input end 26 input from low to high, minion is closed element M7 and the 5th on-off element M5 conducting, Q2 point voltage and Q point voltage all are pulled down to low reference voltage VGL.At this moment, the CLK3 signal of the second clock signal input end, 23 inputs keeps high level, and the element M2 that pulls down switch keeps conducting, and the grid voltage of the output terminal Gn output of gate driving electronic circuit is pulled down to low reference voltage VGL.
Stage 7: the Gn+3 signal 3 of pulldown signal input end 26 inputs is kept high level, and Q2 point and Q point are kept low level.
Before on stages 7, the back was to first, drawing the Gn-2 signal of signal input part 24 to uprise voltage by low-voltage once more, the Q point voltage maintains low-voltage through the 6th on-off element M6.Principle is uprised by low for the CLK1 signal when 22 inputs of the first clock signal input end, because of the stray capacitance coupling causes the Q point voltage to be drawn high slightly, but the 6th on-off element M6 conducting this moment, Q point accumulation charge discharging resisting is to the grid cabling, and the Q point voltage is maintained at low-voltage.
The sequential control of second kind of form (shown in Figure 4) only is with respect to sequential control (shown in Figure 3) difference of first kind of form: replace the Gn+3 signal to drop-down signal input part 26 input Gn+2 signals; Thereby in the stage 5; Because the Gn+2 signal is a high level; Therefore minion is closed element M7 and the 5th on-off element M5 conducting, and Q2 point voltage and Q point voltage all are pulled down to low reference voltage VGL.
It should be noted that; Mat is in above-mentioned two kinds of preferable sequential control; First clock signal of input (N level) gate driving electronic circuit first clock signal input end 22 at the corresponding levels and second clock signal of the second clock signal input end 23; Will be respectively than first clock signal of input next stage (N+1 level) the gate driving electronic circuit first clock signal input end 22 and leading 1/4 cycle of second clock signal of the second clock signal input end 23, this 1/4 cycle is equivalent to the shared time in arbitrary stage among the stage 1-7.That is to say; The minimum gate driving electronic circuit that will comprise level Four of gate driver circuit; Gate driving electronic circuit like this level Four respectively is N-2, N-1, N, N+1 level gate driving electronic circuit; If with level Four gate driving electronic circuit as a unit; Supposing in this unit that clock signal that four gate driving electronic circuits insert the first clock signal input end 22 and the second clock signal input end 23 is formed is respectively Group1, Group2, Group3, Group4; And if the clock signal that the first order gate driving electronic circuit (N-2 level) in this unit inserts consists of Group1:CLK1, CLK3, then the method that connects of first clock signal of the correspondence of level Four gate driving electronic circuit and second clock signal is respectively in this unit:
Group1：CLK1，CLK3 Group2：CLK2，CLK4
Group3：CLK3，CLK1 Group4：CLK4，CLK2
Wherein, four/one-period of the leading CLK2 of CLK1, four/one-period of the leading CLK3 of CLK2, four/one-period of the leading CLK4 of CLK3, leading 3/4ths cycles of CLK4 of CLK1.
Description through to the present embodiment sequential control can be seen; The gate driving electronic circuit of present embodiment to the voltage of latch 21 output terminal Q points (that is to say first control end of drag switch element M1) carried out three times on draw that (Gn-2 signal and Gn-1 signal draw on realizing once respectively; On draw capacitor C 3 to draw on realizing once); Thereby in the time period of gate driving electronic circuit output grid voltage (stage 3 and stage 4); Make latch 21 output terminal Q points keep a very high voltage, make that also going up drag switch element M1 has stronger fan-out capability.
See also Fig. 5; It is the effect comparison synoptic diagram of gate driver circuit in the present invention and the prior art; Wherein VQ is the voltage of latch 21 output terminals of the present invention; VQ ' is the voltage of prior art latch output terminal, and VGn is the output voltage of gate driving electronic circuit of the present invention, and VGn ' is the output voltage of prior art gate driving electronic circuit.Can see; Because the present invention has adopted on three grades and has drawn (prior art have only on the two-stage draw); Therefore make the latch 21 higher voltage of drag switch element M1 output that can make progress; The fan-out capability of drag switch element in the raising, thereby (VGn and VGn ' among the figure) overlaps under the essentially identical situation of output waveform that guarantees the gate driving electronic circuit, can further reduce to go up the size (being breadth length ratio) of drag switch element M1.Width with respect to commonly used in the prior art is pulling up transistor of 4500 μ m, and the width of the last drag switch element of the present invention M1 can be reduced to 3000 μ m.
Among the present invention also the gate driving electronic circuit being done local adjustment, so that its structure is more succinct or improve the stability of circuit.
Embodiment two
See also Fig. 6; It is the circuit diagram of the gate driver circuit of the embodiment of the invention two; Comparing difference with Fig. 2 is; Saved the minion among Fig. 2 and closed element M7, and the 3rd control end of the 3rd on-off element M3 receives the CLK3 signal (drawing signal input part 24 in the 3rd control end of the 3rd on-off element M3 connection first among Fig. 2) of the second clock signal input end, 23 inputs.Can see by the oscillogram shown in Fig. 3; When the Gn-2 signal is high level; The CLK3 signal also is a high level, so present embodiment can be at (being the stage 1) conducting of same time the 3rd on-off element M3, so that draw signal VGn-2 to draw the Q point voltage for the first time on first.And make circuit more succinct after saving minion pass element M7.Other circuit structure of present embodiment and the principle of work all embodiment with Fig. 2 are identical, repeat no more at this.
Embodiment three
See also Fig. 7, it is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention three, compares difference with Fig. 2 and only is, has saved the 6th on-off element M6 among Fig. 2.The effect of the 6th on-off element M6 is when CLK1 high level signal warp the 3rd on-off element M3 of the first clock signal input end, 22 inputs exports the output terminal Gn of gate driving electronic circuit to; Stablize voltage that Q orders and transfer to the output terminal Gn of gate driving electronic circuit; Thereby stablize the voltage that Q point and Gn are ordered, also improved the stability of circuit.It is thus clear that the 6th on-off element M6 is not to be a necessary element in the present invention, under the situation that does not have the 6th on-off element M6, the circuit of present embodiment can be realized drawing on the third level to latch 21 output terminal Q point voltages equally.Other circuit structure of present embodiment and the principle of work all embodiment with Fig. 2 are identical, repeat no more at this.
Embodiment four
See also Fig. 8, it is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention four, compares difference with Fig. 2 and is, has saved the 6th on-off element M6 among Fig. 2, increased octavo and closed element M8, and the input signal of pulldown signal input end 26 is Gn+3.Octavo is closed element M8; It comprises the 8th input end, the 8th output terminal and the 8th control end; The 8th control end connects pulldown signal input end 26; Node (being the output terminal Gn of gate driving electronic circuit) between first output terminal of the last drag switch element M1 of the 8th output terminal connection and second output terminal of the said element M2 that pulls down switch, the 8th input end connects low reference voltage VGL.
In conjunction with the sequential chart referring to Fig. 3, when the Gn+3 signal of drop-down signal input part 26 inputs is high level, i.e. stage 6 and stage 7, this moment, octavo was closed element M8 conducting, and the voltage of the output terminal Gn of gate driving electronic circuit is pulled down to low reference voltage VGL.Because at 6 o'clock stages CLK1 signal is low level; 7 o'clock stages CLK1 signal is a high level; So octavo close element M8 can prevent stage 6 and 7 o'clock stages because of on the unexpected conducting of drag switch element M1 the low level voltage and the high level voltage of CLK1 signal are exported from the gate driving electronic circuit; Can prevent the fluctuation of gate voltage signal, improve the stability of circuit.Other circuit structure of present embodiment and the principle of work all embodiment with Fig. 2 are identical, repeat no more at this.
Embodiment five
See also Fig. 9; It is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention five; Comparing difference with Fig. 2 is; Saved the 6th on-off element M6 among Fig. 2, increased by first and stablized electric capacity C1, the 9th on-off element M9 and the tenth on-off element M10, and the input signal of pulldown signal input end 26 has been Gn+3.First stablizes between the 9th output terminal that electric capacity C1 is arranged on the first clock signal input end 22 and the 9th on-off element M9.The 9th on-off element M9 comprises the 9th input end, the 9th output terminal and the 9th control end; The other end of electric capacity C1 is stablized in the 9th output terminal connection first; The 9th input end connects low reference voltage VGL, the node (being the output terminal Gn of gate driving electronic circuit) between first output terminal of the last drag switch element M1 of the 9th control end connection and second output terminal of the said element M2 that pulls down switch.The tenth on-off element M10; It comprises the tenth input end, the tenth output terminal and the tenth control end; Node (being the output terminal Gn of gate driving electronic circuit) between first output terminal of the last drag switch element M1 of the tenth output terminal connection and second output terminal of the said element M2 that pulls down switch; The tenth input end connects low reference voltage VGL, the tenth control end connect said first stablize electric capacity C1 the other end.
In conjunction with sequential chart referring to Fig. 3; When the Gn point is the time period of high level (being stage 3 and stage 4); This moment, the CLK1 signal also was a high level; The 9th on-off element M9 conducting; The CLK1 signal be coupled to first stablize electric capacity C1 lower end (i.e. the tenth control end of the 9th output terminal of the 9th on-off element M9 and the tenth on-off element M10) high level voltage be pulled down to low reference voltage VGL through the 9th on-off element M9, thereby the tenth on-off element M10 breaks off, the gate driving electronic circuit is normally exported the grid voltage of high level.When the Gn point is the low level time period; The 9th on-off element M9 breaks off, and when the CLK1 signal becomes high level, and stablize electric capacity C1 lower end (i.e. the tenth control end of the tenth on-off element M10) with first and is coupled and draws high; Thereby the tenth on-off element M10 conducting this moment; And the voltage of the output terminal Gn of gate driving electronic circuit is pulled down to low reference voltage VGL, and can prevent the fluctuation of gate voltage signal, improve the stability of circuit.Other circuit structure of present embodiment and the principle of work all embodiment with Fig. 2 are identical, repeat no more at this.
Embodiment six
See also Figure 10; It is the circuit diagram of the gate driving electronic circuit of the embodiment of the invention six; Comparing difference with Fig. 2 is; Saved the 6th on-off element M6 among Fig. 2, increased by second and stablized electric capacity C4, the 11 on-off element M11, twelvemo pass element M12 and the 13 on-off element M13, and the input signal of pulldown signal input end 26 has been Gn+3.Second stablize electric capacity C4 an end connect the first clock signal input end 22, the other end connects the 12 control end, the 13 control end of the 13 on-off element M13 and the 11 output terminal of the 11 on-off element M11 that twelvemo is closed element M12.The 11 on-off element M11 comprises the 11 input end, the 11 output terminal and the 11 control end; The other end of electric capacity C4 is stablized in the 11 output terminal connection second; The 11 input end connects low reference voltage VGL, and the output terminal Q that the 11 control end connects latch 21 (also promptly goes up first control end of drag switch element M1.Twelvemo is closed element M12 and is comprised the 12 input end, the 12 output terminal and the 12 control end; The 12 output terminal connects first control end of the 11 control end and last drag switch element M1; The 12 input end connects low reference voltage VGL, and the other end of electric capacity C4 is stablized in the 12 control end connection second.The 13 on-off element M13 comprises the 13 input end, the 13 output terminal and the 13 control end; The other end (also being the 12 control end that twelvemo is closed element M12) of electric capacity C4 is stablized in the 13 control end connection second; Node (being the output terminal Gn of gate driving electronic circuit) between first output terminal of the last drag switch element M1 of the 13 output terminal connection and second output terminal of the element M2 that pulls down switch, the 13 input end connects low reference voltage VGL.
In conjunction with sequential chart referring to Fig. 3; When the output terminal Q of latch 21 point is high level (1 ~ stage of stage 5); The high level that Q is ordered is controlled the 11 on-off element M11 conducting; And with second stablize electric capacity C3 lower end (also promptly twelvemo is closed the 12 control end of element M12 and the 13 control end of the 13 on-off element M13) voltage be pulled down to low reference voltage VGL, thereby twelvemo is closed element M12 and the 13 on-off element M13 breaks off.And the output terminal Q point of working as latch 21 is a low level; When the CLK1 signal of the first clock signal input end 22 becomes high level (time period before on stages 7, the back was to first, drawing the Gn-2 of signal input part 24 to uprise voltage by low-voltage once more); The 11 on-off element M1 breaks off; Second stablizes electric capacity C3 lower end (also being the 12 control end of twelvemo pass element M12 and the 13 control end of the 13 on-off element M13) level is coupled and draws high; This moment, twelvemo was closed element M12 and the 13 on-off element M13 conducting; Twelvemo is closed element M12 the Q point voltage further is pulled down to low reference voltage VGL; The 13 on-off element M13 is pulled down to low reference voltage VGL with the voltage of the output terminal Gn of gate driving electronic circuit, thereby can prevent the fluctuation of Q point voltage and gate voltage signal, has further improved the stability of circuit.Other circuit structure of present embodiment and the principle of work all embodiment with Fig. 2 are identical, repeat no more at this.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the technology contents of above-mentioned announcement capable of using is made a little change or is modified to the equivalent embodiment of equivalent variations; In every case be not break away from technical scheme content of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (13)
1. a gate driver circuit is characterized in that, comprises multistage gate driving electronic circuit, and wherein every grade of gate driving electronic circuit is used for driving respectively the gate line of a correspondence, and every grade of gate driving electronic circuit comprises:
Last drag switch element comprises first input end, first output terminal and first control end, and said first input end receives first clock signal, and said first output terminal is as the output terminal of gate driving electronic circuit;
The element that pulls down switch comprises second input end, second output terminal and second control end, and said second control end receives second clock signal, and said second input end connects a low reference voltage, and said second output terminal connects said first output terminal;
Latch, it comprises:
Draw signal input part on first, be used to receive input first on draw signal;
Draw signal input part on second, be used to receive input second on draw signal;
The latch output terminal; Connect said first control end of going up the drag switch element to output control signals to said first control end of going up the drag switch element; Said latch draws signal according to drawing on signal and said second on said first, so that the control signal of its said latch output terminal output is carried out respectively drawing on the first order and the second level.
2. gate driver circuit as claimed in claim 1 is characterized in that, every grade of gate driving electronic circuit also comprises:
On draw electric capacity, it is connected between said said first control end and said first output terminal of going up the drag switch element, is used for the control signal that said latch output terminal is exported is carried out drawing on the third level.
3. gate driver circuit as claimed in claim 2 is characterized in that, drawing electric capacity on said is the said stray capacitance that goes up the drag switch element.
4. gate driver circuit as claimed in claim 1 is characterized in that, said latch comprises:
The 3rd on-off element, it comprises the 3rd input end, the 3rd output terminal and the 3rd control end, said the 3rd input end all is connected on said first with said the 3rd control end and draws signal input part;
Coupling capacitance, one of which end connect on said second draws signal input part;
The 4th on-off element; It comprises four-input terminal, the 4th output terminal and the 4th control end; Said the 4th control end links to each other with said four-input terminal; And connect the other end of said coupling capacitance and said the 3rd output terminal of said the 3rd on-off element respectively, said the 4th output terminal as said latch output terminal to connect the said drag switch element of going up.
5. gate driver circuit as claimed in claim 4 is characterized in that, said latch also comprises:
The pulldown signal input end is used to import the pulldown signal of drop-down said latch output terminal output voltage;
The 5th on-off element; It comprises the 5th input end, the 5th output terminal and the 5th control end; Said the 5th control end connects said pulldown signal input end, and said the 5th output terminal connects the 4th output terminal of said the 4th on-off element, and said the 5th input end connects a low reference voltage.
6. gate driver circuit as claimed in claim 5 is characterized in that, said pulldown signal input end connects output terminal or the output terminal of downward partial gate driving electronic circuit of the gate driving electronic circuit of the downward third level.
7. gate driver circuit as claimed in claim 5 is characterized in that, every grade of gate driving electronic circuit also comprises:
The 6th on-off element; It comprises the 6th input end, the 6th output terminal and the 6th control end; Said the 6th input end connects said said first control end of going up the drag switch element; Node between said first output terminal of the said upward drag switch element of said the 6th output terminal connection and said second output terminal of the said element that pulls down switch, said the 6th control end connects the said said first input end of going up the drag switch element.
8. gate driver circuit as claimed in claim 5 is characterized in that, said latch also comprises:
Minion is closed element; It comprises the 7th input end, the 7th output terminal and the 7th control end; Said the 7th control end connects said pulldown signal input end, and said the 7th output terminal connects said the 3rd output terminal of said the 3rd on-off element, and said the 7th input end connects said low reference voltage.
9. gate driver circuit as claimed in claim 8 is characterized in that, every grade of gate driving electronic circuit also comprises:
Octavo is closed element; It comprises the 8th input end, the 8th output terminal and the 8th control end; Said the 8th control end connects said pulldown signal input end; Node between said first output terminal of the said upward drag switch element of said the 8th output terminal connection and said second output terminal of the said element that pulls down switch, said the 8th input end connects said low reference voltage.
10. gate driver circuit as claimed in claim 5 is characterized in that, every grade of gate driving electronic circuit also comprises:
First stablizes electric capacity, and the one of which end connects said first clock signal;
The 9th on-off element; It comprises the 9th input end, the 9th output terminal and the 9th control end; Said the 9th output terminal connect said first stablize electric capacity the other end; Said the 9th input end connects said low reference voltage, the node between said first output terminal of the said upward drag switch element of said the 9th control end connection and said second output terminal of the said element that pulls down switch;
The tenth on-off element; It comprises the tenth input end, the tenth output terminal and the tenth control end; Node between said first output terminal of the said upward drag switch element of said the tenth output terminal connection and said second output terminal of the said element that pulls down switch; Said the tenth input end connects said low reference voltage, said the tenth control end connect said first stablize electric capacity the other end.
11. gate driver circuit as claimed in claim 5 is characterized in that, every grade of gate driving electronic circuit also comprises:
Second stablizes electric capacity, and the one of which end connects said first clock signal;
The 11 on-off element; It comprises the 11 input end, the 11 output terminal and the 11 control end; Said the 11 input end connects said low reference voltage; Said the 11 output terminal connect said second stablize electric capacity the other end, said the 11 control end connects said said first control end of going up the drag switch element;
Twelvemo is closed element; It comprises the 12 input end, the 12 output terminal and the 12 control end; Said the 12 input end connects said low reference voltage; Node between said the 11 control end of said the 12 output terminal and said first control end, said the 12 control end connect said second stablize electric capacity the other end;
The 13 on-off element; It comprises the 13 input end, the 13 output terminal and the 13 control end; Said the 13 control end connect said second stablize electric capacity the other end; Said the 13 input end connects said low reference voltage, the node between said first output terminal of the said upward drag switch element of said the 13 output terminal connection and said second output terminal of the said element that pulls down switch.
12. gate driver circuit as claimed in claim 1; It is characterized in that; Said gate driver circuit comprises level Four gate driving electronic circuit at least; And import said first clock signal leading 1/4 cycle of said first clock signal of this gate driving electronic circuit, import said second clock signal leading 1/4 cycle of said second clock signal of gate driving electronic circuit at the corresponding levels than input next stage gate driving electronic circuit than input next stage gate driving electronic circuit.
13. like each described gate driver circuit in the claim 1 ~ 12; It is characterized in that, each grade gate driving electronic circuit in the said gate driver circuit after the gate driving electronic circuit of the second level first on draw signal input part connect each grade gate driving electronic circuit from first order gate driving electronic circuit after in output terminal or the said gate driver circuit of its partial gate driving electronic circuit that makes progress second on draw the output terminal of the gate driving electronic circuit of its upper level of signal input part connection.
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| CN108806611A (en) * | 2018-06-28 | 2018-11-13 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display device and driving method |
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| CN109935185A (en) * | 2018-07-18 | 2019-06-25 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN109935209A (en) * | 2018-07-18 | 2019-06-25 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display device and driving method |
| US12039949B2 (en) | 2018-07-18 | 2024-07-16 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit, gate driving circuit, display device, and driving method |
| CN111971737A (en) * | 2019-03-01 | 2020-11-20 | 京东方科技集团股份有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN113196368A (en) * | 2019-09-25 | 2021-07-30 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN113196368B (en) * | 2019-09-25 | 2023-05-23 | 京东方科技集团股份有限公司 | Shift register unit, driving method, grid driving circuit and display device |
| CN110853593A (en) * | 2019-11-27 | 2020-02-28 | 深圳市华星光电半导体显示技术有限公司 | Grid driving circuit and liquid crystal display |
| CN113178175A (en) * | 2021-04-01 | 2021-07-27 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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