CN106228927A - Shift register cell, driving method, gate driver circuit and display device - Google Patents
Shift register cell, driving method, gate driver circuit and display device Download PDFInfo
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- CN106228927A CN106228927A CN201610550989.2A CN201610550989A CN106228927A CN 106228927 A CN106228927 A CN 106228927A CN 201610550989 A CN201610550989 A CN 201610550989A CN 106228927 A CN106228927 A CN 106228927A
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- transistor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention discloses a kind of shift register cell, driving method, gate driver circuit and display device, belong to Display Technique field.This shift register cell includes: input module, reseting module, pull-up module, drop-down module and noise reduction module, wherein, input module is used for pulling up node and exports the first power supply signal, reseting module is used for pulling up node output second source signal, pull-up module is under the control at pull-up node, the first clock signal is exported to outfan, drop-down module is under the control at second clock signal and pull-up node, pull down node output the 3rd power supply signal or second clock signal, noise reduction module is under the control of pull-down node, pull up node and outfan output the 3rd power supply signal respectively.Circuit structure and the process of control of the shift register cell that the present invention provides are the most relatively simple, solve the problem that in correlation technique, shift register cell circuit structure is complicated.
Description
Technical field
The present invention relates to Display Technique field, particularly to a kind of shift register cell, driving method, raster data model electricity
Road and display device.
Background technology
Display device, when showing image, needs to utilize shift register (gate driver circuit) to sweep pixel cell
Retouching, shift register includes multiple shift register cell, and each shift register cell correspondence one-row pixels unit, by multiple
Shift register cell realizes the progressive scan of each row pixel cell to display device and drives, to show image.
In order to improve the display motility of display device, correlation technique there is a kind of displacement being capable of bilateral scanning post
Storage, this shift register is capable of forward scan and anti-phase scanning, this displacement of each row pixel cell to display device
In depositor, each shift register cell generally controls the height of the current potential of output signal by multiple transistors and capacitor
Low.
But, this has in the shift register of bilateral scanning function, the transistor that each shift register cell comprises
Number is more, and circuit structure is complex, and the power consumption of shift register is higher.
Summary of the invention
Complicated in order to solve shift register cell circuit structure in correlation technique, the problem that power consumption is higher, the present invention carries
A kind of shift register cell, driving method, gate driver circuit and display device are supplied.Described technical scheme is as follows:
On the one hand, it is provided that a kind of shift register cell, described shift register cell includes:
Input module, reseting module, pull-up module, drop-down module and noise reduction module；
Described input module is connected with the first power supply signal end, input signal end and pull-up node respectively, described input mould
Block is under the control of the input signal from described input signal end, to the output of described pull-up node from described first electricity
First power supply signal of source signal end；
Described reseting module is connected with second source signal end, reset signal end and described pull-up node respectively, described multiple
Position module is under the control of the reset signal from described reset signal end, to the output of described pull-up node from described the
The second source signal of two power supply signal ends；
Described pull-up module is connected with the first clock signal terminal, described pull-up node and outfan respectively, for described
Under the control of pull-up node, export the first clock signal from described first clock signal terminal to described outfan；
Described drop-down module respectively with second clock signal end, the 3rd power supply signal end, described pull-up node and drop-down joint
Point connects, under the control from the second clock signal of described second clock signal end and described pull-up node, to institute
State pull-down node and export the 3rd power supply signal from described 3rd power supply signal end or described second clock signal；
Described noise reduction module respectively with described pull-down node, described pull-up node, the 3rd power supply signal end and described output
End connects, and under the control of described pull-down node, exports the described 3rd to described pull-up node and described outfan respectively
Power supply signal.
Optionally, described input module, including: the first transistor；Described reseting module, including: transistor seconds；
First pole of described the first transistor is connected with described first power supply signal end, the second pole of described the first transistor
Being connected with described pull-up node, the grid of described the first transistor is connected with described input signal end；
First pole of described transistor seconds is connected with described second source signal end, the second pole of described transistor seconds
Being connected with described pull-up node, the grid of described transistor seconds is connected with described reset signal end.
Optionally, described input module, including: transistor seconds；Described reseting module, including: the first transistor；
First pole of described transistor seconds is connected with described first power supply signal end, the second pole of described transistor seconds
Being connected with described pull-up node, the grid of described transistor seconds is connected with described input signal end；
First pole of described the first transistor is connected with described second source signal end, the second pole of described the first transistor
Being connected with described pull-up node, the grid of described the first transistor is connected with described reset signal end.
Optionally, described pull-up module, including: third transistor and the first capacitor；
First pole of described third transistor is connected with described first clock signal terminal, the second pole of described third transistor
Being connected with described outfan, the grid of described third transistor is connected with described pull-up node；
One end of described first capacitor is connected with described pull-up node, and the other end of described first capacitor is defeated with described
Go out end to connect.
Optionally, described drop-down module includes: the 4th transistor, the 5th transistor and the second capacitor；
First pole and the grid of described 4th transistor are connected with described second clock signal end, described 4th transistor
Second pole is connected with described pull-down node；
First pole of described 5th transistor is connected with described 3rd power supply signal end, the second pole of described 5th transistor
Being connected with described pull-down node, the grid of described 5th transistor is connected with described pull-up node；
One end of described second capacitor is connected with described 3rd power supply signal end, the other end of described second capacitor with
Described pull-down node connects.
Optionally, described noise reduction module includes: the 6th transistor and the 7th transistor；
First pole of described 6th transistor is connected with described 3rd power supply signal end, the second pole of described 6th transistor
Being connected with described pull-up node, the grid of described 6th transistor is connected with described pull-down node；
First pole of described 7th transistor is connected with described 3rd power supply signal end, the second pole of described 7th transistor
Being connected with described outfan, the grid of described 7th transistor is connected with described pull-down node.
Optionally, described transistor is N-type transistor.
Second aspect, it is provided that the driving method of a kind of shift register cell, described shift register cell includes: defeated
Entering module, reseting module, pull-up module, drop-down module and noise reduction module, described driving method includes:
Input phase: the first power supply signal of the first power supply signal end input is the first current potential, the input of input signal end
Input signal is the first current potential, and it is the first current potential that described input module controls the current potential of pull-up node；
In the output stage: described pull-up node keeps the first current potential, the first clock signal of the first clock signal terminal input is
First current potential, described pull-up module, under the control of described pull-up node, exports described first clock signal to outfan；
Reseting stage: the reset signal of reset signal end input is the first current potential, the second of second source signal end input
Power supply signal is the second current potential, and it is the second current potential that described reseting module controls the current potential of described pull-up node；
The holding stage: described first clock signal is the first current potential, the second clock signal of second clock signal end input
Being the second current potential, described pull-up node keeps the second current potential；
The noise reduction stage: described second clock signal is the first current potential, the 3rd power supply signal of the 3rd power supply signal end input
Being the second current potential, it is the first current potential that described drop-down module controls described pull-down node, and described noise reduction module is in described pull-down node
Control under, export described 3rd power supply signal to described pull-up node and described outfan respectively.
Optionally, when forward scan, described input module includes: the first transistor；Described reseting module includes: second
Transistor；Described pull-up module includes: third transistor and the first capacitor；Described drop-down module includes: the 4th transistor,
Five transistors and the second capacitor；Described noise reduction module includes: the 6th transistor and the 7th transistor；
In described input phase, the described input signal of described input signal end input is the first current potential, and described first is brilliant
Body pipe is opened, and described first power supply signal end exports described first power supply signal to described pull-up node；
In the described output stage, described pull-up node keeps the first current potential, described third transistor and described 5th crystal
Pipe is opened, and described first clock signal terminal exports described first clock signal, described 3rd power supply signal end to described outfan
Export described 3rd power supply signal, described 6th transistor and described 7th transistor to described pull-down node to turn off；
In described reseting stage, the reset signal of described reset signal end input is the first current potential, described transistor seconds
Opening, described second source signal end exports described second source signal to described pull-up node；
In the described holding stage, described first clock signal is the first current potential, and described second clock signal is the second current potential,
Described 4th transistor turns off, and described pull-up node keeps the second current potential, and described third transistor turns off；
In the described noise reduction stage, described second clock signal is the first current potential, and described 3rd power supply signal is the second current potential,
Described 4th transistor is opened, and described second clock signal end exports described second clock signal to described pull-down node, described
6th transistor and described 7th transistor are opened, and described 3rd power supply signal end is respectively to described pull-up node and described output
End exports described 3rd power supply signal.
Optionally, when reverse scan, described input module includes: transistor seconds；Described reseting module includes: first
Transistor；Described pull-up module includes: third transistor and the first capacitor；Described drop-down module includes: the 4th transistor,
Five transistors and the second capacitor；Described noise reduction module includes: the 6th transistor and the 7th transistor；
In described input phase, the described input signal of described input signal end input is the first current potential, and described second is brilliant
Body pipe is opened, and described first power supply signal end exports described first power supply signal to described pull-up node；
In the described output stage, described pull-up node keeps the first current potential, described third transistor and described 5th crystal
Pipe is opened, and described first clock signal terminal exports described first clock signal, described 3rd power supply signal end to described outfan
Export described 3rd power supply signal, described 6th transistor and described 7th transistor to described pull-down node to turn off；
In described reseting stage, the reset signal of described reset signal end input is the first current potential, described the first transistor
Opening, described second source signal end exports described second source signal to described pull-up node；
In the described holding stage, described first clock signal is the first current potential, and described second clock signal is the second current potential,
Described 4th transistor turns off, and described pull-up node keeps the second current potential, and described third transistor turns off；
In the described noise reduction stage, described second clock signal is the first current potential, and described 3rd power supply signal is the second current potential,
Described 4th transistor is opened, and described second clock signal end exports described second clock signal to described pull-down node, described
6th transistor and described 7th transistor are opened, and described 3rd power supply signal end is respectively to described pull-up node and described output
End exports described 3rd power supply signal.
Optionally, described transistor is N-type transistor, and described first current potential is high electricity relative to described second current potential
Position.
The third aspect, it is provided that a kind of gate driver circuit, described gate driver circuit include that at least two cascades as
Shift register cell described in first aspect.
Fourth aspect, it is provided that a kind of display device, described display device includes the raster data model as described in the third aspect
Circuit.
The technical scheme that the present invention provides has the benefit that
The invention provides a kind of shift register cell, driving method, gate driver circuit and display device.This displacement
Register cell includes: input module, reseting module, pull-up module, drop-down module and noise reduction module, and wherein, input module is used
Exporting the first power supply signal in pulling up node, reseting module is used for pulling up node output second source signal, pulls up module
Under the control at pull-up node, export the first clock signal to outfan, drop-down module at second clock signal and
Under the control of pull-up node, pulling down node output the 3rd power supply signal or second clock signal, noise reduction module is for drop-down
Under the control of node, pull up node and outfan output the 3rd power supply signal respectively.The shift register list that the present invention provides
Circuit structure and the process of control of unit are the most relatively simple, reduce the power consumption of shift register, solve in correlation technique and shift
The problem that register cell circuit structure is complicated.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below required for make
Accompanying drawing be briefly described, it should be apparent that, below describe in accompanying drawing be only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is the structural representation of a kind of shift register cell that the embodiment of the present invention provides；
Fig. 2-1 is the structural representation of the another kind of shift register cell that the embodiment of the present invention provides；
Fig. 2-2 is the structural representation of another shift register cell that the embodiment of the present invention provides；
Fig. 3-1 is the flow chart of the driving method of a kind of shift register cell that the embodiment of the present invention provides；
Fig. 3-2 is the sequential chart of the forward scan of a kind of shift register cell that the embodiment of the present invention provides；
Fig. 3-3 is the sequential chart of the reverse scan of a kind of shift register cell that the embodiment of the present invention provides；
Fig. 4 is the structural representation of a kind of gate driver circuit that the embodiment of the present invention provides.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
The transistor used in all embodiments of the invention can be all thin film transistor (TFT) or field effect transistor or other characteristics
Identical device, is mainly switching transistor according to the transistor that effect embodiments of the invention in circuit are used.By
In the switching transistor used here source electrode, drain electrode be symmetrical, so its source electrode, drain electrode can exchange.At this
In bright embodiment, for distinguishing transistor the two poles of the earth in addition to grid, wherein will be referred to as the first pole by source electrode, drain electrode is referred to as the second pole,
Therefore, the grid of transistor is referred to as the 3rd pole.The intermediate ends specifying transistor by the form in accompanying drawing is grid, signal
Input is that source electrode, signal output part are for draining.The switching transistor that the embodiment of the present invention is used is N-type switching transistor, N
Type switching transistor, for turning on when grid is high potential, is ended when grid is electronegative potential.In embodiments of the present invention, first
Current potential is high potential, and the second current potential is electronegative potential.Additionally, the multiple signals in each embodiment of the present invention are all to there being the first electricity
Position and the second current potential.First current potential and the second current potential only represent the current potential of this signal 2 quantity of states, does not represent in full first
Current potential or the second current potential have specific numerical value.
Fig. 1 is the structural representation of a kind of shift register cell that the embodiment of the present invention provides, as it is shown in figure 1, this shifting
Bit register unit may include that input module 10, reseting module 20, pull-up module 30, drop-down module 40 and noise reduction module 50.
This input module 10 is connected with the first power supply signal end VDD, input signal end INPUT and pull-up node PU respectively,
This input module 10, under the control of the input signal from this input signal end INPUT, exports to this pull-up node PU
The first power supply signal from this first power supply signal end VDD.
This reseting module 20 is connected with second source signal end VSS, reset signal end RST and this pull-up node PU respectively,
This reseting module 20, under the control of the reset signal from this reset signal end RST, comes to this pull-up node PU output
Second source signal from this second source signal end VSS.
This pull-up module 30 is connected with the first clock signal terminal CLK, this pull-up node PU and outfan OUTPUT respectively, uses
Under the control at this pull-up node PU, to this outfan OUTPUT output from this first clock signal terminal CLK first time
Clock signal.
This drop-down module 40 respectively with second clock signal end CLKB, the 3rd power supply signal end VGL, this pull-up node PU and
Pull-down node PD connects, in the control from the second clock signal of this second clock signal end CLKB and this pull-up node PU
Under system, export the 3rd power supply signal from the 3rd power supply signal end VGL or this second clock signal to this pull-down node PD.
This noise reduction module 50 respectively with this pull-down node PD, this pull-up node PU, the 3rd power supply signal end VGL and this output
End OUTPUT connects, under the control of this pull-down node PD, defeated to this pull-up node PU and this outfan OUTPUT respectively
Go out the 3rd power supply signal.
In sum, embodiments providing a kind of shift register cell, this shift register cell includes: defeated
Entering module, reseting module, pull-up module, drop-down module and noise reduction module, this shift register cell is capable of display dress
The bilateral scanning of each row pixel cell in putting, and the most more letter of the circuit structure of this shift register cell and the process of control
Single, not only reduce the power consumption of shift register, and reduce pull-up node in shift register cell by noise reduction module
With the noise of outfan, improve the output effect of shift register cell.
Fig. 2-1 is the structural representation of the another kind of shift register cell that the embodiment of the present invention provides, such as Fig. 2-1 institute
Showing, this input module 10 may include that the first transistor M1；This reseting module 20 may include that transistor seconds M2.
First pole of this first transistor M1 is connected with this first power supply signal end VDD, the second of this first transistor M1
Pole is connected with this pull-up node PU, and the grid of this first transistor M1 is connected with this input signal end INPUT.
First pole of this transistor seconds M2 is connected with this second source signal end VSS, the second of this transistor seconds M2
Pole is connected with this pull-up node PU, and the grid of this transistor seconds M2 is connected with this reset signal end RST.
Fig. 2-2 is the structural representation of the another kind of shift register cell that the embodiment of the present invention provides, such as Fig. 2-2 institute
Showing, this input module 10 may include that transistor seconds M2；This reseting module 20 may include that the first transistor M1.
First pole of this transistor seconds M2 is connected with this first power supply signal end VDD, the second of this transistor seconds M2
Pole is connected with this pull-up node PU, and the grid of this transistor seconds M2 is connected with this input signal end INPUT.
First pole of this first transistor M1 is connected with this second source signal end VSS, the second of this first transistor M1
Pole is connected with this pull-up node PU, and the grid of this first transistor M1 is connected with this reset signal end RST.
Optionally, with reference to Fig. 2-1 and Fig. 2-2, this pull-up module 30 may include that third transistor M3 and the first electric capacity
Device C1.
First pole of this third transistor M3 is connected with this first clock signal terminal CLK, the second of this third transistor M3
Pole is connected with this outfan OUTPUT, and the grid of this third transistor M3 is connected with this pull-up node PU.
One end of this first capacitor C1 is connected with this pull-up node PU, the other end of this first capacitor C1 and this output
End OUTPUT connects.
Optionally, this drop-down module 40 includes: the 4th transistor M4, the 5th transistor M5 and the second capacitor C2.
First pole and the grid of the 4th transistor M4 are connected with this second clock signal end CLKB, the 4th transistor M4
The second pole be connected with this pull-down node PD.
First pole of the 5th transistor M5 is connected with the 3rd power supply signal end VGL, the second of the 5th transistor M5
Pole is connected with this pull-down node PD, and the grid of the 5th transistor M5 is connected with this pull-up node PU；
One end of this second capacitor C2 is connected with the 3rd power supply signal end VGL, the other end of this second capacitor C2
It is connected with this pull-down node PD.
Optionally, this noise reduction module 50 includes: the 6th transistor M6 and the 7th transistor M7.
First pole of the 6th transistor M6 is connected with the 3rd power supply signal end VGL, the second of the 6th transistor M6
Pole is connected with this pull-up node PU, and the grid of the 6th transistor M6 is connected with this pull-down node PD；
First pole of the 7th transistor M7 is connected with the 3rd power supply signal end VGL, the second of the 7th transistor M7
Pole is connected with this outfan OUTPUT, and the grid of the 7th transistor M7 is connected with this pull-down node PD.
In sum, embodiments providing a kind of shift register cell, this shift register cell includes: defeated
Entering module, reseting module, pull-up module, drop-down module and noise reduction module, this shift register cell is capable of display dress
The bilateral scanning of each row pixel cell in putting, and this shift register cell only includes seven transistors and two electric capacity
Device, the circuit structure of this shift register cell and the process of control are the most relatively simple, not only reduce the power consumption of shift register,
And can be reduced by noise reduction module and shift register cell pulls up node and the noise of outfan, improve shift LD
The output effect of device unit.
Fig. 3-1 is the flow chart of the driving method of a kind of shift register cell that the embodiment of the present invention provides, such as Fig. 1 institute
Showing, this shift register cell may include that input module 10, reseting module 20, pull-up module 30, drop-down module 40 and noise reduction
Module 50, with reference to Fig. 3-1, this driving method may include that
Step 301, input phase: the first power supply signal of the first power supply signal end VDD input is the first current potential, input letter
Number end INPUT input input signal be the first current potential, this input module 10 control pull-up node PU current potential be the first current potential.
Step 302, output stage: this pull-up node PU keeps the first current potential, the first of the first clock signal terminal CLK input
Clock signal is the first current potential, this pull-up module 30 under the control of this pull-up node PU, to outfan OUTPUT export this
One clock signal.
Step 303, reseting stage: the reset signal of reset signal end RST input is the first current potential, second source signal end
The second source signal of VSS input is the second current potential, and it is the second current potential that this reseting module 20 controls the current potential of this pull-up node PU.
Step 304, keep the stage: this first clock signal is the first current potential, the of second clock signal end CLKB input
Two clock signals are the second current potential, and this pull-up node PU keeps the second current potential.
Step 305, noise reduction stage: this second clock signal is the first current potential, the 3rd of the 3rd power supply signal end VGL input
Power supply signal is the second current potential, and it is the first current potential that this drop-down module 40 controls this pull-down node PD, and this noise reduction module 50 is under this
Draw under the control of node PD, export the 3rd power supply signal to this pull-up node PU and this outfan OUTPUT respectively.
In sum, embodiments provide the driving method of a kind of shift register cell, this shift register
Unit includes: input module, reseting module, pull-up module, drop-down module and noise reduction module, and this shift register cell can be real
The now bilateral scanning to row pixel cell each in display device, and the circuit structure of this shift register cell and the process of control
The most relatively simple.
Fig. 3-2 is the sequential chart of the forward scan of a kind of shift register cell that the embodiment of the present invention provides, with reference to figure
2-1, when forward scan, this input module 10 may include that the first transistor M1；This reseting module 20 may include that second
Transistor M2；This pull-up module 30 may include that third transistor M3 and the first capacitor C1；This drop-down module 40 can be wrapped
Include: the 4th transistor M4, the 5th transistor M5 and the second capacitor C2；This noise reduction module 50 may include that the 6th transistor M6
With the 7th transistor M7.With reference to Fig. 3-2, the method may include that
As a example by n-th grade of shift register cell, in above-mentioned steps 301, T1 in this input phase, this n-th grade displacement
This input signal (i.e. output letter of (n-1)th grade of shift register cell of the input signal end INPUT input of register cell
Number) be the first current potential, this first transistor M1 open, this first power supply signal end VDD to this pull-up node PU export this first
Power supply signal, this first power supply signal can give the first capacitor C1 charging, so that the current potential of this pull-up node PU is drawn
High.Simultaneously as in this input phase T1, the second clock signal of second clock signal end CLKB input is the second current potential, the
Four transistor M4 turn off, and the high potential of this pull-up node PU makes the 5th transistor M5 open, and the 3rd power supply signal end VGL is downward
Drawing node PD and the second capacitor C2 to export the 3rd power supply signal, the 3rd power supply signal is the second current potential, now the 6th crystal
Pipe M6 and the 7th transistor M7 turns off, thus ensure that the stable output of signal.
In above-mentioned steps 302, in this output stage T2, the voltage of this pull-up node PU due to bootstrap effect (English:
Bootstrapping) being further magnified, this third transistor M3 and the 5th transistor M5 open, this first clock signal terminal
CLK is to this outfan OUTPUT output drive signal, and this driving signal is this first clock signal, now this first clock letter
Number it is the first current potential；3rd power supply signal end VGL exports the 3rd power supply letter to this pull-down node PD and the second capacitor C2
Number, the 3rd power supply signal is the second current potential, thus realizes this pull-down node PD and the electric discharge of the second capacitor C2, now should
6th transistor M6 and the 7th transistor M7 turns off, and thereby may be ensured that this first clock of output stable for outfan OUTPUT
Signal.
In above-mentioned steps 303, in this reseting stage T3, the reset signal (i.e. (n+1)th of this reset signal end RST input
The output signal of level shift register cell) it is the first current potential, this transistor seconds M2 opens, this second source signal end VSS
Exporting this second source signal to this pull-up node PU, this second source signal is the second current potential, now third transistor M3 and
5th transistor M5 turns off.
In above-mentioned steps 304, in this holding stage T4, this first clock signal is the first current potential, second clock signal
The second clock signal of end CLKB input is the second current potential, and the 4th transistor M4 turns off, thus without to this pull-down node PD
With the second capacitor C2 charging, this pull-up node PU keeps the second current potential, and this third transistor M3 turns off, thus ensures outfan
The low pressure output of OUTPUT, it is ensured that the stability of signal output.
In above-mentioned steps 305, in this noise reduction stage T5, this second clock signal is the first current potential, the 4th transistor
M4 opens, and this second clock signal end CLKB exports this second clock signal, now this pull-down node PD to this pull-down node PD
Current potential be the first current potential, the 6th transistor M6 and the 7th transistor M7 open, the 3rd power supply signal end VGL respectively to
This pull-up node PU, this outfan OUTPUT export the 3rd power supply signal, owing to the 3rd power supply signal is the second current potential, because of
This pull-up node PU point and outfan OUTPUT can be put and make an uproar by this so that this outfan OUTPUT is by the first clock signal
The coupling that end CLK produces is (English: Coupling) noise voltage is eliminated, thus ensures that the low pressure of outfan OUTPUT is defeated
Go out, it is ensured that the stability of signal output.
It should be noted that before next frame scanning starts, this shift register cell can repeat noise reduction rank always
Section T5, in this noise reduction stage T5, this pull-up node PU is always maintained at the second current potential, and this pull-down node PD is always maintained at the first electricity
Position, therefore the 6th transistor M6 and the 7th transistor M7 is always maintained at opening, constantly to pull-up node PU and outfan
OUTPUT carries out noise reduction.After next frame scanning starts, when the output signal of (n-1)th grade of shift register cell output is the first electricity
During position, this n-th grade of shift register cell can perform this input phase T1 again.
With reference to Fig. 2-2, when reverse scan, this input module 10 may include that transistor seconds M2；This reseting module 20
May include that the first transistor M1；This pull-up module 30 may include that third transistor M3 and the first capacitor C1；This is drop-down
Module 40 may include that the 4th transistor M4, the 5th transistor M5 and the second capacitor C2；This noise reduction module 50 may include that
6th transistor M6 and the 7th transistor M7, the method may include that
As a example by n-th grade of shift register cell, in above-mentioned steps 301, in this input phase T1, this n-th grade displacement
This input signal (i.e. output letter of (n+1)th grade of shift register cell of the input signal end INPUT input of register cell
Number) be the first current potential, this transistor seconds M2 open, this first power supply signal end VDD to this pull-up node PU export this first
Power supply signal.
In above-mentioned steps 302, in this output stage T2, this pull-up node PU keeps the first current potential, this third transistor
M3 and the 5th transistor M5 opens, and this first clock signal terminal CLK exports this first clock signal to this outfan OUTPUT, should
3rd power supply signal end VGL inputs the 3rd power supply signal to this pull-down node PD, the 6th transistor M6 and the 7th crystal
Pipe M7 turns off.
In above-mentioned steps 303, in this reseting stage T3, the reset signal (i.e. (n-1)th of this reset signal end RST input
The output signal of level shift register cell) it is the first current potential, this first transistor M1 opens, this second source signal end VSS
This second source signal is exported to this pull-up node PU.
In above-mentioned steps 304, in this holding stage T4, this first clock signal is the first current potential, second clock signal
The second clock signal of end CLKB input is the second current potential, and the 4th transistor M4 turns off, and this pull-up node PU keeps the second electricity
Position, this third transistor M3 turns off；
In above-mentioned steps 305, in this noise reduction stage T5, this second clock signal is the first current potential, the 3rd power supply signal
3rd power supply signal of end VGL input is the second current potential, and the 4th transistor M4 opens, and this second clock signal end CLKB is to this
Pull-down node PD exports this second clock signal, the 6th transistor M6 and the 7th transistor M7 and opens, the 3rd power supply letter
Number end VGL export the 3rd power supply signal to this pull-up node PU, this outfan OUTPUT respectively.
It should be noted that before next frame scanning starts, this n-th grade of shift register cell can repeat fall always
Make an uproar stage T5, and in this noise reduction stage T5, this pull-up node PU is always maintained at the second current potential, and this pull-down node PD is always maintained at
One current potential, therefore the 6th transistor M6 and the 7th transistor M7 is always maintained at opening, constantly to pull-up node PU and defeated
Go out to hold OUTPUT to carry out noise reduction.After next frame scanning starts, when the output signal of (n+1)th grade of shift register cell output is the
During one current potential, this n-th grade of shift register cell can start to perform this input phase T1.
The concrete driving process of above-mentioned reverse scan is referred to the driving flow process of forward scan, and the embodiment of the present invention is to this
Repeat no more.
It should be noted that when reverse scan, first pole of this first transistor M1 can also continue to and this first electricity
Source signal end VSS is connected, and the first of this transistor seconds M2 extremely can continue to be connected with this second source signal end VDD, and should
The first of third transistor M3 extremely can be connected with this second clock signal end CLKB, and the first of the 4th transistor M4 is the most permissible
It is connected with this first clock signal terminal CLK, then during reverse scan, with reference to Fig. 3-2, this first power supply signal end VSS
First power supply signal of input can be the second current potential, and the second source signal of this second source signal end VDD input is first
Current potential.That is to say, when this shift register switches between forward scan and reverse scan, each displacement can not be changed and post
Annexation between storage unit and each power supply signal end, it is only necessary to the level adjusting each power supply signal end input signal is high
Low, therefore improve motility when this shift register drives.
Also, it should be noted in the above-described embodiments, it is all with the first transistor M1, transistor seconds M2, trimorphism
Body pipe M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6 and the 7th transistor M7 are N-type transistor, and first
Current potential is high potential, and the second current potential is the explanation carried out as a example by electronegative potential.Certainly, this first to the 7th transistor can also use
P-type transistor, when this first to the tenth transistor uses P-type transistor, this first current potential is electronegative potential, and this second current potential is
High potential, and the potential change of this first clock signal terminal CLK and second clock signal end CLKB can be with Fig. 3-2 or Fig. 3-3
Shown potential change is contrary (i.e. the phase contrast of the two is 180 degree).
In sum, embodiments provide the driving method of a kind of shift register cell, this shift register
Unit includes: input module, reseting module, pull-up module, drop-down module and noise reduction module, and this shift register cell can be real
The now bilateral scanning to row pixel cell each in display device, and this shift register cell only includes seven transistors
The most relatively simple with two capacitors, circuit structure and the process of control, not only reduce the power consumption of shift register, and noise reduction
During can be reduced by noise reduction module this shift register cell pulls up node and the noise of outfan, improve displacement
The output effect of register cell.
Fig. 4 is the structural representation of a kind of gate driver circuit that the embodiment of the present invention provides, as shown in Figure 4, this grid
Drive circuit can include at least two cascaded shift registers unit, the most each shift register cell can be as Fig. 1,
Shift register cell shown in Fig. 2-1 or Fig. 2-2.Figure 4, it is seen that the input letter of every one-level shift register cell
Number end INPUT input the outfan OUTPUT that input signal is upper level shift register cell output output signal；Often
The outfan that reset signal is next stage shift register cell of the reset signal end RST input of one-level shift register cell
The output signal of OUTPUT output.Additionally, the clock signal terminal that the pull-up module working as n-th grade of shift register cell is connected is
During the first clock signal terminal CLK, the clock signal that the pull-up module of the shift register cell of (n-1)th grade and n-th grade is connected
End can be second clock signal end CLKB.Therefore, when shift register needs to switch to reverse scan from forward scan, can
With by each shift register cell of change pulls up the clock signal terminal that module is connected, and change the first power supply signal
End and the level of second source signal end, it is achieved the switching of this shift register bilateral scanning.
It addition, the embodiment of the present invention also provides for a kind of display device, this display device can include grid as shown in Figure 4
Drive circuit, this gate driver circuit can include the shift LD shown in-1 or Fig. 2-2 as shown in Figure 1, Figure 2 that at least two cascades
Device unit.This display device can be: liquid crystal panel, Electronic Paper, oled panel, AMOLED panel, mobile phone, panel computer, electricity
Depending on any product with display function or parts such as machine, display, notebook computer, DPF, navigators.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (13)
1. a shift register cell, it is characterised in that described shift register cell includes:
Input module, reseting module, pull-up module, drop-down module and noise reduction module；
Described input module is connected with the first power supply signal end, input signal end and pull-up node respectively, and described input module is used
Under the control in the input signal from described input signal end, to the output of described pull-up node from described first power supply letter
Number end the first power supply signal；
Described reseting module is connected with second source signal end, reset signal end and described pull-up node respectively, described reset mould
Block is under the control of the reset signal from described reset signal end, to the output of described pull-up node from described second electricity
The second source signal of source signal end；
Described pull-up module is connected with the first clock signal terminal, described pull-up node and outfan respectively, in described pull-up
Under the control of node, export the first clock signal from described first clock signal terminal to described outfan；
Described drop-down module is respectively with second clock signal end, the 3rd power supply signal end, described pull-up node and pull-down node even
Connect, under the control from the second clock signal of described second clock signal end and described pull-up node, under described
Node is drawn to export the 3rd power supply signal from described 3rd power supply signal end or described second clock signal；
Described noise reduction module is respectively with described pull-down node, described pull-up node, the 3rd power supply signal end and described outfan even
Connect, under the control of described pull-down node, export described 3rd power supply to described pull-up node and described outfan respectively
Signal.
Shift register cell the most according to claim 1, it is characterised in that described input module, including: first crystal
Pipe；Described reseting module, including: transistor seconds；
First pole of described the first transistor is connected with described first power supply signal end, the second pole of described the first transistor and institute
Stating pull-up node to connect, the grid of described the first transistor is connected with described input signal end；
First pole of described transistor seconds is connected with described second source signal end, the second pole of described transistor seconds and institute
Stating pull-up node to connect, the grid of described transistor seconds is connected with described reset signal end.
Shift register cell the most according to claim 1, it is characterised in that described input module, including: the second crystal
Pipe；Described reseting module, including: the first transistor；
First pole of described transistor seconds is connected with described first power supply signal end, the second pole of described transistor seconds and institute
Stating pull-up node to connect, the grid of described transistor seconds is connected with described input signal end；
First pole of described the first transistor is connected with described second source signal end, the second pole of described the first transistor and institute
Stating pull-up node to connect, the grid of described the first transistor is connected with described reset signal end.
Shift register cell the most according to claim 1, it is characterised in that described pull-up module, including: the 3rd crystal
Pipe and the first capacitor；
First pole of described third transistor is connected with described first clock signal terminal, the second pole of described third transistor and institute
Stating outfan to connect, the grid of described third transistor is connected with described pull-up node；
One end of described first capacitor is connected with described pull-up node, the other end of described first capacitor and described outfan
Connect.
Shift register cell the most according to claim 1, it is characterised in that described drop-down module includes: the 4th crystal
Pipe, the 5th transistor and the second capacitor；
First pole and the grid of described 4th transistor are connected with described second clock signal end, the second of described 4th transistor
Pole is connected with described pull-down node；
First pole of described 5th transistor is connected with described 3rd power supply signal end, the second pole of described 5th transistor and institute
Stating pull-down node to connect, the grid of described 5th transistor is connected with described pull-up node；
One end of described second capacitor is connected with described 3rd power supply signal end, and the other end of described second capacitor is with described
Pull-down node connects.
Shift register cell the most according to claim 1, it is characterised in that described noise reduction module includes: the 6th crystal
Pipe and the 7th transistor；
First pole of described 6th transistor is connected with described 3rd power supply signal end, the second pole of described 6th transistor and institute
Stating pull-up node to connect, the grid of described 6th transistor is connected with described pull-down node；
First pole of described 7th transistor is connected with described 3rd power supply signal end, the second pole of described 7th transistor and institute
Stating outfan to connect, the grid of described 7th transistor is connected with described pull-down node.
7. according to the arbitrary described shift register cell of claim 2 to 6, it is characterised in that
Described transistor is N-type transistor.
8. the driving method of a shift register cell, it is characterised in that described shift register cell includes: input mould
Block, reseting module, pull-up module, drop-down module and noise reduction module, described driving method includes:
Input phase: the first power supply signal of the first power supply signal end input is the first current potential, the input of input signal end input
Signal is the first current potential, and it is the first current potential that described input module controls the current potential of pull-up node；
The output stage: described pull-up node keeps the first current potential, and the first clock signal of the first clock signal terminal input is first
Current potential, described pull-up module, under the control of described pull-up node, exports described first clock signal to outfan；
Reseting stage: the reset signal of reset signal end input is the first current potential, the second source of second source signal end input
Signal is the second current potential, and it is the second current potential that described reseting module controls the current potential of described pull-up node；
In the holding stage: described first clock signal is the first current potential, the second clock signal of second clock signal end input is the
Two current potentials, described pull-up node keeps the second current potential；
In the noise reduction stage: described second clock signal is the first current potential, the 3rd power supply signal of the 3rd power supply signal end input is the
Two current potentials, it is the first current potential that described drop-down module controls described pull-down node, and described noise reduction module is in the control of described pull-down node
Under system, export described 3rd power supply signal to described pull-up node and described outfan respectively.
Method the most according to claim 8, it is characterised in that when forward scan, described input module includes: first is brilliant
Body pipe；Described reseting module includes: transistor seconds；Described pull-up module includes: third transistor and the first capacitor；Described
Drop-down module includes: the 4th transistor, the 5th transistor and the second capacitor；Described noise reduction module includes: the 6th transistor and
7th transistor；
In described input phase, the described input signal of described input signal end input is the first current potential, described the first transistor
Opening, described first power supply signal end exports described first power supply signal to described pull-up node；
In the described output stage, described pull-up node keeps the first current potential, described third transistor and described 5th transistor to open
Opening, described first clock signal terminal exports described first clock signal to described outfan, and described 3rd power supply signal end is to institute
State pull-down node and export described 3rd power supply signal, described 6th transistor and described 7th transistor shutoff；
In described reseting stage, the reset signal of described reset signal end input is the first current potential, and described transistor seconds is opened,
Described second source signal end exports described second source signal to described pull-up node；
In the described holding stage, described first clock signal is the first current potential, and described second clock signal is the second current potential, described
4th transistor turns off, and described pull-up node keeps the second current potential, and described third transistor turns off；
In the described noise reduction stage, described second clock signal is the first current potential, and described 3rd power supply signal is the second current potential, described
4th transistor open, described second clock signal end to described pull-down node export described second clock signal, the described 6th
Transistor and described 7th transistor are opened, and described 3rd power supply signal end is defeated to described pull-up node and described outfan respectively
Go out described 3rd power supply signal.
Method the most according to claim 8, it is characterised in that when reverse scan, described input module includes: second
Transistor；Described reseting module includes: the first transistor；Described pull-up module includes: third transistor and the first capacitor；Institute
State drop-down module to include: the 4th transistor, the 5th transistor and the second capacitor；Described noise reduction module includes: the 6th transistor
With the 7th transistor；
In described input phase, the described input signal of described input signal end input is the first current potential, described transistor seconds
Opening, described first power supply signal end exports described first power supply signal to described pull-up node；
In the described output stage, described pull-up node keeps the first current potential, described third transistor and described 5th transistor to open
Opening, described first clock signal terminal exports described first clock signal to described outfan, and described 3rd power supply signal end is to institute
State pull-down node and export described 3rd power supply signal, described 6th transistor and described 7th transistor shutoff；
In described reseting stage, the reset signal of described reset signal end input is the first current potential, and described the first transistor is opened,
Described second source signal end exports described second source signal to described pull-up node；
In the described holding stage, described first clock signal is the first current potential, and described second clock signal is the second current potential, described
4th transistor turns off, and described pull-up node keeps the second current potential, and described third transistor turns off；
In the described noise reduction stage, described second clock signal is the first current potential, and described 3rd power supply signal is the second current potential, described
4th transistor open, described second clock signal end to described pull-down node export described second clock signal, the described 6th
Transistor and described 7th transistor are opened, and described 3rd power supply signal end is defeated to described pull-up node and described outfan respectively
Go out described 3rd power supply signal.
11. according to the method described in claim 9 or 10, it is characterised in that
Described transistor is N-type transistor, and described first current potential is high potential relative to described second current potential.
12. 1 kinds of gate driver circuits, it is characterised in that what described gate driver circuit included that at least two cascades wants such as right
Seek 1 to 7 arbitrary described shift register cell.
13. 1 kinds of display devices, it is characterised in that described display device includes the gate driver circuit described in claim 12.
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| US11263943B2 (en) | 2018-06-11 | 2022-03-01 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register and driving method therefor, gate drive circuit, and display device |
| CN108470535A (en) * | 2018-06-11 | 2018-08-31 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method and gate driving circuit, display device |
| CN108962148A (en) * | 2018-08-16 | 2018-12-07 | 北京华镁钛科技有限公司 | For the drive element of the grid of antenna or display panel, driving method and driving circuit |
| CN110648638A (en) * | 2019-09-25 | 2020-01-03 | 合肥京东方卓印科技有限公司 | Gate drive circuit, pixel circuit, display panel and display device |
| US11200861B2 (en) | 2019-09-25 | 2021-12-14 | Hefei Boe Joint Technology Co., Ltd. | Shift register unit, gate drive circuit, display panel and display device |
| CN113990378A (en) * | 2021-10-29 | 2022-01-28 | 福州京东方光电科技有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
| CN113990378B (en) * | 2021-10-29 | 2022-09-09 | 福州京东方光电科技有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
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