CN106057116B - Shift register cell, driving method, gate driving circuit and display device - Google Patents
Shift register cell, driving method, gate driving circuit and display device Download PDFInfo
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- CN106057116B CN106057116B CN201610445665.2A CN201610445665A CN106057116B CN 106057116 B CN106057116 B CN 106057116B CN 201610445665 A CN201610445665 A CN 201610445665A CN 106057116 B CN106057116 B CN 106057116B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Physics & Mathematics (AREA)
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of shift register cell, driving method, gate driving circuit and display devices, belong to field of display technology.The shift register cell includes: control module, output module and top rake module；The control module is connect with input signal end, reset signal end, control signal end, the first clock signal terminal, pull-up node and output end respectively, for controlling the current potential of the pull-up node and output end；The output module is connect with second clock signal end, the pull-up node and output end respectively, for exporting the second clock signal from the second clock signal end to the output end；The top rake module is connect with the output end and third clock signal terminal respectively, for exporting the third clock signal to the output end, to drag down current potential of the output end in the second output stage output signal of the shift register cell, to slow down the amplitude of grid voltage variation, display picture is avoided phenomena such as flashing and image retention occur.The present invention is for showing image.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of shift register cell, driving method, gate driving electricity
Road and display device.
Background technique
Display device when displaying an image, needs to sweep pixel unit using shift register (gate driving circuit)
It retouches, shift register includes multiple cascaded shift registers units, and each shift register cell corresponds to one-row pixels unit, and
The grid output scanning pulse signal of thin film transistor (TFT) in the row pixel unit can be realized by multiple shift register cells
Progressive scan driving to the pixel unit of display device, to show image.
The relevant technologies have a kind of shift register cell, it is usually by multiple transistors and capacitor come control output end
The height of the current potential of output signal.But usually there is parasitism between the grid and source electrode of the thin film transistor (TFT) in display device
Capacitor, so when the level that shift register is applied to the scanning pulse signal of the grid of thin film transistor (TFT) changes, than
Low level is such as changed to by high level, grid potential can generate it is huge fall, and influenced by parasitic capacitance, source potential can also produce
Life is huge to be fallen, and logical (feed through) phenomenon of bursting is generated, so that phenomena such as causing display picture appearance flashing and image retention, shows
The display effect of showing device is poor.
Summary of the invention
Display effect in order to solve the problems, such as display device in the related technology is poor, and the present invention provides a kind of displacements to post
Storage unit, driving method, gate driving circuit and display device.The technical solution is as follows:
In a first aspect, providing a kind of shift register cell, the shift register cell includes:
Control module, output module and top rake module；
The control module respectively with input signal end, reset signal end, control signal end, the first clock signal terminal, on
Node is drawn to connect with output end, in the input signal from the input signal end, answering from the reset signal end
Position signal, the control signal from the control signal end and the first clock signal from first clock signal terminal
Under control, the current potential of the pull-up node and the output end is controlled；
The output module is connect with second clock signal end, the pull-up node and the output end respectively, is used for
Under the control of the pull-up node, Xiang Suoshu output end exports the second clock signal from the second clock signal end；
The top rake module is connect with the output end and third clock signal terminal respectively, for when coming from the third
Under the control of the third clock signal of clock signal end, Xiang Suoshu output end exports the third clock signal.
Optionally, the control module includes: input submodule, resets submodule and noise reduction submodule；
The input submodule is connect with input signal end and pull-up node respectively, for coming from the input signal end
Input signal control under, control the current potential of the pull-up node；
The reset submodule respectively with reset signal end, control signal end, the pull-up node, pull-down node and described
Output end connection, for controlling the pull-up under the control of the reset signal, the control signal and the pull-down node
The current potential of node and the output end；
The noise reduction submodule respectively with the first clock signal terminal, the pull-up node, the control signal end, it is described under
Node is drawn to connect with the output end, for the control in first clock signal, the control signal and the pull-up node
Under system, noise reduction is carried out to the pull-down node and the output end.
Optionally, the top rake module, comprising: the first transistor；
First pole of the first transistor is connect with the third clock signal terminal, the grid of the first transistor and
Second pole is connect with the output end.
Optionally, the output module, comprising: second transistor and capacitor；
The grid of the second transistor is connect with the pull-up node, and the first order and the second clock signal end connect
It connects, third pole is connect with the output end；
One end of the capacitor is connect with the pull-up node, and the other end is connect with the output end.
Optionally, the input submodule includes: third transistor；
The grid of the third transistor is connect with the input signal end, and the first pole is connect with the input signal end,
Second pole is connect with the pull-up node；
The reset submodule includes: the 4th transistor, the 5th transistor and the 6th transistor；
The grid of 4th transistor is connect with the reset signal end, and the first pole is connect with the control signal end,
Second pole is connect with the pull-up node；
The grid of 5th transistor is connect with the pull-down node, and the first pole is connect with the control signal end, the
Two poles are connect with the pull-up node；
The grid of 6th transistor is connect with the reset signal end, and the first pole is connect with the control signal end,
Second pole is connect with the output end；
The noise reduction submodule includes: the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, the 11st
Transistor, the tenth two-transistor and the 13rd transistor；
The grid of 7th transistor is connect with first clock signal terminal, and the first pole and the input signal end connect
It connects, the second pole is connect with the pull-up node；
The grid of 8th transistor is connect with first clock signal terminal, the first pole and first clock signal
End connection, the second pole is connect with the grid of the 9th transistor；
The grid of 9th transistor respectively with the second pole of the 8th transistor and the tenth transistor
The connection of second pole, the first pole of the 9th transistor connect with first clock signal terminal, and the of the 9th transistor
Two poles are connect with the pull-down node；
The grid of tenth transistor is connect with the pull-up node, and the first pole is connect with the control signal end, the
Two poles are connect with the grid of the 9th transistor；
The grid of 11st transistor is connect with the pull-up node, and the first pole is connect with the control signal end,
Second pole is connect with the pull-down node；
The grid of tenth two-transistor is connect with first clock signal terminal, the first pole and the control signal end
Connection, the second pole is connect with the output end；
The grid of 13rd transistor is connect with the pull-down node, and the first pole is connect with the control signal end,
Second pole is connect with the output end.
Optionally, the transistor is N-type transistor.
Second aspect provides a kind of driving method of shift register cell, posts for displacement described in first aspect
Storage unit, the shift register cell include: control module, output module and top rake module, which comprises
Input phase, the input signal of input signal end input are the first current potential, and the control module controls the pull-up
The current potential of node is the first current potential；
First output stage, the second clock signal of second clock signal end input are the first current potential, the pull-up node
The first current potential is kept, the control module exports the second clock signal from the second clock signal end to output end；
Second output stage, the third clock signal of third clock signal terminal input are third current potential, the second clock
Signal keeps the first current potential, and first current potential is higher than the third current potential, and the control module continues defeated to the output end
The second clock signal out, the top rake module exports the third clock signal to the output end, so that the output
It holds the current potential of output signal to be higher than the third current potential and is lower than first current potential；
Reseting stage, the first clock signal of the first clock signal terminal input are the first current potential, the input of reset signal end
Reset signal is the first current potential, and the control signal of control signal end input is the second current potential, and the control module is respectively to described
Pull-up node and the output end export the control signal.
Optionally, the control module includes: input submodule, resets submodule and noise reduction submodule；
In the input phase, the input signal is the first current potential, and the input submodule controls the pull-up node
Current potential be the first current potential；
In the reseting stage, first clock signal is the first current potential, and the noise reduction submodule controls the drop-down
The current potential of node is the first current potential, and the reset signal is the first current potential, and the control signal is the second current potential, reset
Module exports the control signal to the pull-up node and the output end respectively.
Optionally, first current potential is high potential relative to second current potential；
The third current potential is high potential relative to second current potential.
Optionally, the pulse period of the third clock signal is the half of the pulse period of the second clock signal.
Optionally, the duty ratio of the second clock signal is half, and the duty ratio of the third clock signal is big
In or equal to 3/4ths.
The third aspect, provides a kind of gate driving circuit, the gate driving circuit include at least two it is cascade such as
Shift register cell described in first aspect.
Fourth aspect, provides a kind of display device, and the display device includes the gate driving as described in the third aspect
Circuit.
Technical solution provided by the invention has the benefit that
The present invention provides a kind of shift register cell, driving method, gate driving circuit and display device, the displacements
Top rake module in register cell can export third clock signal to output end, due at this in the second output stage
In second output stage, the signal of output end output is the composite signal of second clock signal and third clock signal, and
In second output stage, second clock signal is the first current potential, and third clock signal is third current potential, so that output end exports
The current potential of signal is located between two current potentials, to realize the effect to the output end output signal top rake, avoids this defeated
Signal directly drops to the second current potential of reseting stage from the first current potential of the first output stage out, to slow down grid voltage
The amplitude of variation avoids display picture from phenomena such as flashing and image retention occur, improves the display effect of display device.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 4 is a kind of flow chart of shift register cell driving method provided in an embodiment of the present invention；
Fig. 5 is a kind of timing diagram of the driving process of shift register cell provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 7 is a kind of timing diagram of gate driving circuit output end provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The transistor used in all embodiments of the invention all can be thin film transistor (TFT) or field-effect tube or other characteristics
Identical device is mainly switching transistor according to transistor used by effect the embodiment of the present invention in circuit.By
It is symmetrical in the source electrode of the switching transistor used here, drain electrode, so its source electrode, drain electrode can be interchanged.In this hair
In bright embodiment, wherein it will be known as the first order by source electrode, drain electrode is known as the second level.The centre of transistor is provided by the form in attached drawing
End is grid, signal input part is source electrode, signal output end is drain electrode.In addition, switch crystal used by the embodiment of the present invention
Pipe includes p-type switching transistor and two kinds of N-type switching transistor, wherein p-type switching transistor is led when grid is low level
It is logical, end when grid is high level, N-type switching transistor is the conducting when grid is high level, when grid is low level
Cut-off.In addition, multiple signals in each embodiment of the present invention are all corresponding with the first current potential and the second current potential.First current potential and
The current potential that two current potentials only represent the signal has 2 quantity of states.Not representing the first current potential or the second current potential in full text has specifically
Numerical value.First control signal and second control signal can be low-potential signal.
Fig. 1 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention, as shown in Figure 1, the shifting
Bit register unit may include: control module 10, output module 20 and top rake module 30.
The control module 10 respectively with input signal end INPUT, reset signal end RST, control signal end VSS, first when
Clock signal end CLK1, pull-up node PU are connected with output end Output, in the input letter from input signal end INPUT
Number, the reset signal from reset signal end RST, control signal from control signal end VSS and from this first
Under the control of the first clock signal of clock signal terminal CLK1, the current potential of pull-up node PU He output end Output are controlled；
The output module 20 is connect with second clock signal end CLK2, pull-up node PU and output end Output respectively,
For exporting second from second clock signal end CLK2 to output end Output under the control of pull-up node PU
Clock signal；
The top rake module 30 is connect with output end Output and third clock signal terminal CLK3 respectively, for from this
Under the control of the third clock signal of third clock signal terminal CLK3, the third clock signal is exported to output end Output.
In conclusion the embodiment of the invention provides a kind of shift register cell, cutting in the shift register cell
Corner Block List Representation can export third clock signal to output end in the second output stage, defeated due in second output stage
The signal of outlet output is the composite signal of second clock signal and third clock signal, and in second output stage,
Second clock signal is the first current potential, and third clock signal is third current potential, is somebody's turn to do so that the current potential of output end output signal is located at
Between two current potentials, to realize the effect to the output end output signal top rake, avoid the output signal directly from first
First current potential of output stage drops to the second current potential of reseting stage, to slow down the amplitude of grid voltage variation, avoids
It shows that phenomena such as flashing and image retention occurs in picture, improves the display effect of display device.
Fig. 2 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention, with reference to Fig. 2, the control
Molding block 10 may include: input submodule 101, reset submodule 102 and noise reduction submodule 103.
The input submodule 101 is connect with input signal end INPUT and pull-up node PU respectively, for coming from the input
Under the control of the input signal of signal end INPUT, the current potential of pull-up node PU is controlled.
The reset submodule 102 is saved with reset signal end RST, control signal end VSS, pull-up node PU, drop-down respectively
Point PD is connected with output end Output, for controlling under the control of the reset signal, the control signal and pull-down node PD
Make the current potential of pull-up node PU He output end Output.
The noise reduction submodule 103 respectively with the first clock signal terminal CLK1, pull-up node PU, control signal end VSS,
Pull-down node PD is connected with output end Output, in first clock signal, the control signal and the pull-up node
Under the control of PU, noise reduction is carried out to pull-down node PD and output end Output.
Fig. 3 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention, and with reference to Fig. 3, this is cut
Corner Block List Representation 30 may include: the first transistor M1；
The first pole of the first transistor M1 is connect with third clock signal terminal CLK3, the grid of the first transistor M1
It is connect with the second pole with output end Output.
The output module 20, comprising: second transistor M2 and capacitor；
The grid of second transistor M2 is connect with pull-up node PU, and the first order and the second clock signal end CLK2 connect
It connects, third pole is connect with output end Output；
One end of the capacitor is connect with pull-up node PU, and the other end is connect with output end Output.
The input submodule 101 includes: third transistor M3；
The grid of third transistor M3 is connect with input signal end INPUT, the first pole and input signal end INPUT
Connection, the second pole is connect with pull-up node PU；
The reset submodule 102 includes: the 4th transistor M4, the 5th transistor M5 and the 6th transistor M6；
The grid of 4th transistor M4 is connect with reset signal end RST, and the first pole and control signal end VSS connect
It connects, the second pole is connect with pull-up node PU；
The grid of 5th transistor M5 is connect with pull-down node PD, and the first pole is connect with control signal end VSS, the
Two poles are connect with pull-up node PU；
The grid of 6th transistor M6 is connect with reset signal end RST, and the first pole and control signal end VSS connect
It connects, the second pole is connect with output end Output；
The noise reduction submodule 103 includes: the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor
M10, the 11st transistor M11, the tenth two-transistor M12 and the 13rd transistor M13；
The grid of 7th transistor M7 is connect with first clock signal terminal CLK1, the first pole and the input signal end
INPUT connection, the second pole are connect with pull-up node PU；
The grid of 8th transistor M8 is connect with first clock signal terminal CLK1, the first pole and first clock signal
CLK1 connection is held, the second pole is connect with the grid of the 9th transistor M9；
The grid of 9th transistor M9 respectively with the second pole of the 8th transistor M8 and the tenth transistor M10
The connection of second pole, the first pole of the 9th transistor M9 are connect with first clock signal terminal CLK1, the 9th transistor M9's
Second pole is connect with pull-down node PD；
The grid of tenth transistor M10 is connect with pull-up node PU, and the first pole is connect with control signal end VSS,
Second pole is connect with the grid of the 9th transistor M9；
The grid of 11st transistor M11 is connect with pull-up node PU, and the first pole and control signal end VSS connect
It connects, the second pole is connect with pull-down node PD；
The grid of tenth two-transistor M12 is connect with first clock signal terminal CLK1, the first pole and the control signal
VSS connection is held, the second pole is connect with output end Output；
The grid of 13rd transistor M13 is connect with pull-down node PD, and the first pole and control signal end VSS connect
It connects, the second pole is connect with output end Output.
With reference to Fig. 3 it is found that in embodiments of the present invention, each shift register cell may include 13 transistors and 1
A capacitor, external circuit signals input include control signal, reset signal, 3 clock signals, input signal and reset letter
Number, wherein the input signal of each shift register cell can be the output signal of upper level shift register cell, each
The reset signal of shift register cell can be the output signal of next stage shift register cell, and control signal end VSS is defeated
The control signal entered is direct current low level signal.It should be noted that in practical applications, in each shift register cell
Transistor number and the number of capacitor can be increased and decreased according to the actual situation, and it is not limited in the embodiment of the present invention.
In conclusion the embodiment of the invention provides a kind of shift register cell, cutting in the shift register cell
Corner Block List Representation can export third clock signal to output end in the second output stage, defeated due in second output stage
The signal of outlet output is the composite signal of second clock signal and third clock signal, and in second output stage,
Second clock signal is the first current potential, and third clock signal is third current potential, is somebody's turn to do so that the current potential of output end output signal is located at
Between two current potentials, to realize the effect to the output end output signal top rake, avoid the output signal directly from first
First current potential of output stage drops to the second current potential of reseting stage, to slow down the amplitude of grid voltage variation, avoids
It shows that phenomena such as flashing and image retention occurs in picture, improves the display effect of display device.
Fig. 4 is a kind of flow chart of shift register cell driving method provided in an embodiment of the present invention, and this method can be with
For drive as Fig. 1 to Fig. 3 it is any shown in shift register cell, with reference to Fig. 1, which may include:
Control module 10, output module 20 and top rake module 30, this method may include:
Step 401, input phase, the input signal of input signal end INPUT input are the first current potential, the control module 10
The current potential for controlling pull-up node PU is the first current potential.
Step 402, the first output stage, the second clock signal of second clock signal end CLK2 input are the first current potential,
Pull-up node PU keeps the first current potential, which comes from the second clock signal end to output end Output output
The second clock signal of CLK2.
Step 403, the second output stage, the third clock signal of third clock signal terminal CLK3 input are third current potential,
The second clock signal keeps the first current potential, which is higher than the third current potential, which continues to the output
End Output exports the second clock signal, which exports the third clock signal to output end Output, makes
The current potential for obtaining output end Output output signal is higher than the third current potential and is lower than first current potential.
Step 404, reseting stage, the first clock signal of the first clock signal terminal CLK1 input are the first current potential, are resetted
The reset signal of signal end RST input is the first current potential, and the control signal of control signal end VSS input is the second current potential, the control
Molding block 10 exports the control signal to pull-up node PU and output end Output respectively.
In conclusion the embodiment of the invention provides a kind of driving method of shift register cell, in the driving method
Including the first output stage and the second output stage, wherein in the first output stage, the output of shift register cell output end
Signal is the second clock signal in the first current potential, in second output stage, when the signal of output end output is second
The composite signal of clock signal and third clock signal, since in second output stage, second clock signal is the first current potential,
Third clock signal is third current potential, so that the current potential of output end output signal is located between first current potential and third current potential,
To realize the effect to the output end output signal top rake, avoid the output signal directly from the first of the first output stage
Current potential drops to the second current potential of reseting stage, to slow down the amplitude of grid voltage variation, display picture is avoided to dodge
Phenomena such as bright and image retention, improve the display effect of display device.
Optionally, with reference to Fig. 2 it is found that the control module 10 may include: input submodule 101, reset 102 and of submodule
Noise reduction submodule 103.
In above-mentioned steps 401, in the input phase, which is the first current potential, the input submodule 101 control
The current potential of pull-up node PU is the first current potential.
In above-mentioned steps 403, in the reseting stage, which is the first current potential, the noise reduction submodule 103
The current potential for controlling pull-down node PD is the first current potential, which is the first current potential, which is direct current low level
Signal, and the current potential of the control signal can be the second current potential, the reset submodule 102 is defeated with this to pull-up node PU respectively
Outlet Output exports the control signal.
Fig. 5 is a kind of timing diagram of shift register cell driving process provided in an embodiment of the present invention, can with reference to Fig. 5
Know, in embodiments of the present invention, the height of the clock signal of the first clock signal terminal CLK1 and second clock signal end CLK2 input
Current potential is the first current potential vgh, and low potential is the second current potential vgl, and the high potential of the third clock signal is the first current potential vgh, low
Current potential is third current potential vgh'.
In input phase T1, the input signal of input signal end INPUT input is the first current potential vgh, at this time in Fig. 3
Third transistor M3 is opened, and third transistor M3 exports the input signal to pull-up node PU, thus by pull-up node PU
Current potential pull-up be the first current potential vgh.
In the first output stage T2, the second clock signal of second clock signal end CLK2 input is the first current potential vgh,
The third clock signal of third clock signal terminal CLK3 input is the first current potential vgh, and the current potential of pull-up node PU is due to capacitor C
Coupling continue to increase, the first transistor M1 and second transistor M2 is open state, the first transistor M1 at this time
Export the third clock signal to output end Output, second transistor M2 to output end Output export this second when
Clock signal can be with from Fig. 5 since the current potential of second clock signal and third clock signal at this time is the first current potential vgh
Find out, the current potential of output end Output output signal is also the first current potential vgh at this time.
In the second output stage T3, which keeps the first current potential vgh, and third clock signal terminal CLK3 is defeated
The third clock signal entered is third current potential vgh', which is higher than third current potential vgh', due to the third current potential
Vgh' is high potential relative to the second current potential vgl, and the first transistor M1 and second transistor M2 is still kept it turning at this time
State, second transistor M2 continues to export the second clock signal to output end Output at this time, third transistor M3 to this
Output end Output exports the third clock signal, so that output end Output output signal is the second clock signal and the
The composite signal of three clock signals, with reference to Fig. 5, in second output stage T3, the current potential of output end Output output signal
Vgh " is higher than the third current potential vgh' and is lower than first current potential vgh, believes it is possible thereby to realize and export to output end Output
Number carry out top rake purpose.Wherein the current potential vgh " of second output stage T3 output end Output output signal be by this first
What current potential vgh and the third current potential vgh' collective effect generated, and current potential vgh " specific value is by the first transistor M1 and the
The breadth length ratio W/L of two-transistor M2 is determined.
In reseting stage T4, the first clock signal of the first clock signal terminal CLK1 input is the first current potential vgh, control
The control signal of signal end VSS input is the second current potential vgl, the 7th transistor M7 and the 8th transistor M8 unlatching, the 7th crystal
Pipe M7 exports the input signal to pull-up node PU, can should since the input signal at this time is the second current potential vgl
The current potential of pull-up node PU drags down, while the 8th transistor M8 exports first clock signal to the grid of the 9th transistor M9,
9th transistor M9 is opened, and first clock signal is exported to pull-down node PD, so that the 5th transistor M5 and the 13rd
Transistor M13 is opened, the 5th transistor M5 and the 13rd transistor M13 pulls up node PU respectively and output end Output is defeated
Signal is controlled out, which is the second current potential vgl；Meanwhile in reseting stage T4, RST input in reset signal end is answered
Position signal is the first current potential vgh, the 4th transistor M4 and the 6th transistor M6 unlatching, the 4th transistor M4 and the 6th crystal
Pipe M6 is in the control signal of the second current potential vgl to pull-up node PU and output end Output output respectively.
From figure 5 it can be seen that when shift register cell unit is transitioned into reseting stage T4 from the second output stage T3
When, since in second output stage T3, the current potential vgh " of output end Output output signal is lower than first current potential vgh,
To realize the effect to the output end output signal top rake, the potential change of the output signal is exported from first
The first current potential vgh of stage T1 is changed to the vgh " of the second output stage T3, then is changed to the of reseting stage T4 from the vgh "
Two current potential vgl, therefore can directly be dropped to from the first current potential vgh of the first output stage T2 to avoid the output signal and reset rank
The second current potential vgl of section T4, slows down the amplitude of grid voltage variation, and display picture is avoided phenomena such as flashing and image retention occur,
Improve the display effect of display device.
It should be noted that with reference to Fig. 5 it is found that the first clock signal is identical with the pulse period of second clock signal, and
Duty ratio is identical, such as can be half, and the pulse period of third clock signal is the pulse week of second clock signal
The half of phase, when guaranteeing that the second clock signal is jumped from low level into high level, the third clock signal is also by low level
It jumps to high level.Further, from figure 5 it can be seen that the duration (i.e. top rake time) of second output stage T3
It is equal in the duration of third current potential within the pulse period with the third clock signal, therefore the third clock signal accounts for
Empty ratio can determine according to the top rake time required by shift register cell, due to the top rake time be generally less than this second
The a quarter of duration of the clock signal within each pulse period in high level, that is to say: the duration of T3≤(1/4)
× (T2 duration duration+T3), therefore when the duty ratio of the second clock signal is half, the third clock
The duty ratio of signal can be greater than or equal to 3/4ths, should when the duty ratio of the second clock signal is less than half
The duty ratio of third clock signal can be greater than 3/4ths, so that third clock signal is in third within each pulse period
The duration of current potential, less than or equal in second clock signal each pulse period be in the first current potential duration four/
One.If the shift register cell exist precharge the case where, relative to without precharge the case where, the third clock signal
Duty ratio can be set smaller, i.e., the duty ratio of the third clock signal can be according to the precharge feelings of shift register cell
Condition and top rake time codetermine.
It is and the first current potential using each transistor as N-type transistor it should also be noted that, in the above embodiments
It is high potential with third current potential, the second current potential is the explanation that carries out for low potential.Certainly, which can also use
P-type transistor, when each transistor is all made of P-type transistor, first current potential and third current potential can be low potential, this second
Current potential can be high potential, and the potential change of the signal of each signal end input can be opposite with potential change shown in fig. 5
(i.e. the phase difference 180 degree of the two).
In conclusion the embodiment of the invention provides a kind of driving method of shift register cell, in the driving method
Including the first output stage and the second output stage, wherein in the first output stage, the output of shift register cell output end
Signal is the second clock signal in the first current potential, in second output stage, when the signal of output end output is second
The composite signal of clock signal and third clock signal, since in second output stage, second clock signal is the first current potential,
Third clock signal is third current potential, so that the current potential of output end output signal is located between first current potential and third current potential,
To realize the effect to the output end output signal top rake, avoid the output signal directly from the first of the first output stage
Current potential drops to the second current potential of reseting stage, to slow down the amplitude of grid voltage variation, display picture is avoided to dodge
Phenomena such as bright and image retention, improve the display effect of display device.
Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention, which can
With include at least two it is cascade as Fig. 1 to 3 it is any shown in shift register cell 00, from Fig. 6 kind as can be seen that N grades
The reset signal end RST of shift register cell GOA N is connect with the output end of N+1 grades of shift register cell GOA N+1,
The output of the input signal end INPUT and N-1 grades of shift register cell GOA N-1 of N grades of shift register cell GOA N
End connection, wherein the input signal end INPUT of first order shift register cell is connect with frame open signal end STV.The grid
The timing diagram of each output end can be as shown in fig. 7, in order to guarantee that each output end moves in the gate driving circuit in driving circuit
Position output drive signal, the clock signal terminal that output module and control module in adjacent two-stage shift register cell are connected
It is not identical, for example, if when the clock signal terminal that the output module in N grades of shift register cell GOA N is connected is second
Clock signal end CLK2, the clock signal terminal of control module connection are the first clock signal terminal CLK1, then N+1 grades of shift registers
The clock signal terminal that output module in unit GOA N+1 is connected is the first clock signal terminal CLK1, control module connection
Clock signal terminal is second clock signal end CLK2.
The embodiment of the present invention provides a kind of display device, which may include gate driving electricity as shown in FIG. 6
Road.The display device can be with are as follows: liquid crystal display panel, Electronic Paper, oled panel, AMOLED panel, mobile phone, tablet computer, television set,
Any products or components having a display function such as display, laptop, Digital Frame, navigator.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (13)
1. a kind of shift register cell, which is characterized in that the shift register cell includes:
Control module, output module and top rake module；
The control module is saved with input signal end, reset signal end, control signal end, the first clock signal terminal, pull-up respectively
Point is connected with output end, when the input signal for inputting at the input signal end is the first current potential, controls the pull-up section
The current potential of point is the first current potential, and reset signal and first clock signal terminal for inputting at the reset signal end
When first clock signal of input is the first current potential, Xiang Suoshu pull-up node and output end output are believed from the control
Number end control signal, it is described control signal current potential be the second current potential；
The output module is connect with second clock signal end, the pull-up node and the output end respectively, for described
When the current potential of pull-up node is the first current potential, second clock letter of the Xiang Suoshu output end output from the second clock signal end
Number；
The top rake module is connect with the output end and third clock signal terminal respectively, in the third clock signal terminal
The third clock signal of input is third current potential, and the second clock signal is the first current potential, and the output module is to described
When output end exports the second clock signal, Xiang Suoshu output end exports the third clock signal；
Wherein, first current potential is higher than the third current potential, and the third current potential is higher than second current potential.
2. shift register cell according to claim 1, which is characterized in that the control module includes: input submodule
Block resets submodule and noise reduction submodule；
The input submodule is connect with the input signal end and the pull-up node respectively, for believing from the input
Number control under, control the current potential of the pull-up node；
The reset submodule respectively with the reset signal end, the control signal end, the pull-up node, pull-down node and
Output end connection, under the control of the reset signal, the control signal and the pull-down node, described in control
The current potential of pull-up node and the output end；
The noise reduction submodule respectively with first clock signal terminal, the pull-up node, the control signal end, it is described under
Node is drawn to connect with the output end, for the control in first clock signal, the control signal and the pull-up node
Under system, noise reduction is carried out to the pull-down node and the output end.
3. shift register cell according to claim 1, which is characterized in that the top rake module, comprising: first crystal
Pipe；
First pole of the first transistor is connect with the third clock signal terminal, the grid of the first transistor and second
Pole is connect with the output end.
4. shift register cell according to claim 1, which is characterized in that the output module, comprising: the second crystal
Pipe and capacitor；
The grid of the second transistor is connect with the pull-up node, and the first order is connect with the second clock signal end, the
Three poles are connect with the output end；
One end of the capacitor is connect with the pull-up node, and the other end is connect with the output end.
5. shift register cell according to claim 2, which is characterized in that
The input submodule includes: third transistor；
The grid of the third transistor is connect with the input signal end, and the first pole is connect with the input signal end, and second
Pole is connect with the pull-up node；
The reset submodule includes: the 4th transistor, the 5th transistor and the 6th transistor；
The grid of 4th transistor is connect with the reset signal end, and the first pole is connect with the control signal end, and second
Pole is connect with the pull-up node；
The grid of 5th transistor is connect with the pull-down node, and the first pole is connect with the control signal end, the second pole
It is connect with the pull-up node；
The grid of 6th transistor is connect with the reset signal end, and the first pole is connect with the control signal end, and second
Pole is connect with the output end；
The noise reduction submodule includes: the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, the 11st crystal
Pipe, the tenth two-transistor and the 13rd transistor；
The grid of 7th transistor is connect with first clock signal terminal, and the first pole is connect with the input signal end,
Second pole is connect with the pull-up node；
The grid of 8th transistor is connect with first clock signal terminal, and the first pole and first clock signal terminal connect
It connects, the second pole is connect with the grid of the 9th transistor；
The grid of 9th transistor respectively with the second pole of the 8th transistor and the tenth transistor second
Pole connection, the first pole of the 9th transistor are connect with first clock signal terminal, the second pole of the 9th transistor
It is connect with the pull-down node；
The grid of tenth transistor is connect with the pull-up node, and the first pole is connect with the control signal end, the second pole
It is connect with the grid of the 9th transistor；
The grid of 11st transistor is connect with the pull-up node, and the first pole is connect with the control signal end, and second
Pole is connect with the pull-down node；
The grid of tenth two-transistor is connect with first clock signal terminal, and the first pole and the control signal end connect
It connects, the second pole is connect with the output end；
The grid of 13rd transistor is connect with the pull-down node, and the first pole is connect with the control signal end, and second
Pole is connect with the output end.
6. according to any shift register cell of claim 3 to 5, which is characterized in that
The transistor is N-type transistor.
7. a kind of driving method of shift register cell, for driving any shift register list of claim 1 to 6
Member, which is characterized in that the shift register cell includes: control module, output module and top rake module, the method packet
It includes:
Input phase, the input signal of input signal end input are the first current potential, and the control module controls the pull-up node
Current potential be the first current potential；
First output stage, the second clock signal of second clock signal end input are the first current potential, and the pull-up node is kept
First current potential, the output module export the second clock signal from the second clock signal end to output end；
Second output stage, the third clock signal of third clock signal terminal input are third current potential, the second clock signal
The first current potential is kept, first current potential is higher than the third current potential, and the output module continues to export institute to the output end
Second clock signal is stated, the top rake module exports the third clock signal to the output end, so that the output end is defeated
The current potential of signal is higher than the third current potential and is lower than first current potential out；
Reseting stage, the first clock signal of the first clock signal terminal input are the first current potential, the reset of reset signal end input
Signal is the first current potential, and the control signal of control signal end input is the second current potential, and the control module is respectively to the pull-up
Node and the output end export the control signal.
8. the method according to the description of claim 7 is characterized in that the control module includes: input submodule, resets submodule
Block and noise reduction submodule；
The input submodule is connect with the input signal end and the pull-up node respectively, the reset submodule respectively with
The reset signal end, the control signal end, the pull-up node, pull-down node are connected with the output end, the noise reduction
Submodule respectively with first clock signal terminal, the pull-up node, the control signal end, the pull-down node and described
Output end connection；
In the input phase, the input signal is the first current potential, and the input submodule controls the electricity of the pull-up node
Position is the first current potential；
In the reseting stage, first clock signal is the first current potential, and the noise reduction submodule controls the pull-down node
Current potential be the first current potential, the reset signal be the first current potential, the control signal be the second current potential, the reset submodule
The control signal is exported to the pull-up node and the output end respectively.
9. method according to claim 7 or 8, which is characterized in that
First current potential is high potential relative to second current potential；
The third current potential is high potential relative to second current potential.
10. method according to claim 7 or 8, which is characterized in that
The pulse period of the third clock signal is the half of the pulse period of the second clock signal.
11. according to the method described in claim 10, it is characterized in that,
The duty ratio of the second clock signal is half, and the duty ratio of the third clock signal is greater than or equal to four points
Three.
12. a kind of gate driving circuit, which is characterized in that the gate driving circuit includes at least two cascade as right is wanted
Seek 1 to 6 any shift register cell.
13. a kind of display device, which is characterized in that the display device includes gate driving electricity as claimed in claim 12
Road.
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| CN106683630B (en) * | 2016-12-29 | 2018-06-12 | 惠科股份有限公司 | A kind of pixel charging method and circuit |
| CN106710510A (en) * | 2017-02-23 | 2017-05-24 | 合肥京东方光电科技有限公司 | Grid driving unit and driving method, grid driving circuit and display device |
| CN109389924B (en) * | 2017-08-07 | 2020-08-18 | 京东方科技集团股份有限公司 | Driving circuit for display panel, driving method thereof and display panel |
| CN109389926B (en) * | 2017-08-11 | 2022-02-25 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and array substrate |
| CN107342038B (en) | 2017-09-13 | 2021-04-02 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof, grid driving circuit and display device |
| CN109036310A (en) * | 2018-08-03 | 2018-12-18 | 深圳市华星光电半导体显示技术有限公司 | GOA unit and its driving method |
| CN109147704B (en) * | 2018-09-28 | 2021-02-26 | 合肥鑫晟光电科技有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN112863449B (en) * | 2021-01-12 | 2022-06-07 | 京东方科技集团股份有限公司 | Light-emitting control circuit, driving method thereof, display panel and display device |
| CN113823213B (en) * | 2021-10-26 | 2024-01-26 | 京东方科技集团股份有限公司 | Gate driving circuit, display substrate and display device |
| CN114038387B (en) | 2021-12-07 | 2023-08-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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