CN105788555B

CN105788555B - Shift register cell and its driving method, gate driving circuit, display device

Info

Publication number: CN105788555B
Application number: CN201610339380.0A
Authority: CN
Inventors: 米磊; 王世君; 薛艳娜
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2016-05-19
Filing date: 2016-05-19
Publication date: 2018-04-10
Anticipated expiration: 2036-05-19
Also published as: CN105788555A

Abstract

The present invention provides a kind of shift register cell and its driving method, gate driving circuit, display device.It is related to display technology field, for simplifying gate driving circuit.The shift register cell includes：First control module, input module, the second control module, the first output module, the second output module, the 3rd output module, the 4th output module and output control module；First control module is used to control first node voltage, and input module is used for the voltage for controlling section point, and the second control module is used for the voltage for controlling first node, section point, fourth node and the 5th node；First to fourth output module is respectively used to export the clock signal of first to fourth clock signal terminal, and output control module is used for the voltage for controlling the 4th output module output fourth node.Embodiments of the invention are used for the manufacture of display device.

Description

Shift register cell and its driving method, gate driving circuit, display device

Technical field

The present invention relates to display technology field, more particularly to a kind of shift register cell and its driving method, grid to drive Dynamic circuit, display device.

Background technology

Integrated raster data model (English：Gate Drive On Array, referred to as:GOA), it is to utilize thin film transistor (TFT) (English Text：Thin film transistor, referred to as：TFT) LCD (Liquid Crystal Display) array (Array) processing procedure makes gate driving circuit On thin-film transistor array base-plate, to realize the type of drive of progressive scan.

Gate driving circuit design is all the key problem that those skilled in the art constantly study all the time.Utilize Gate driving circuit is integrated on the array base palte of display panel by integrated gate driver technology, can be saved gate switch and be integrated Circuit part, so as to reduce product cost in terms of material cost and manufacture craft two.Existing gate driving circuit generally by Multiple shift register cell compositions, a grid line of the signal output part connection display panel of any shift register cell, Grid line for being connected to it provides gate drive signal, and each shift register cell includes a precharge mould Block, a drop-down module, a stable module and an output module, each module include multiple TFT again.However, with The continuous improvement of display panel resolution ratio, the quantity of grid line is also continuously increased in display panel, so needing to design more Shift register cell forms gate driving circuit and provides gate drive signal for display panel, due to existing shift register list Meta structure is complex, and each shift register cell only can provide gate drive signal to a grid line, so existing There is gate driving circuit to be unfavorable for simplifying the technique of display panel and reduce the generation cost of display panel.In addition, narrow frame Technology has enjoyed consumers always since appearance.Narrow frame technology must be to reduce the area of gate driving circuit before Carry, and grid electrode drive circuit structure is complicated in the prior art, it is difficult to reduce the area of gate driving circuit, therefore be also unfavorable for narrow The realization of frame technology.

To sum up, how to simplify gate driving circuit is those skilled in the art's technical problem urgently to be resolved hurrily.

The content of the invention

Embodiments of the invention provide a kind of shift register cell and its driving method, gate driving circuit, display dress Put, for simplifying gate driving circuit.

To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：

First aspect, there is provided a kind of shift register cell, including：First control module, input module, the second control mould Block, the first output module, the second output module, the 3rd output module, the 4th output module and output control module；

First control module connects the first scanning signal end, the second scanning signal end, the first signal input part, second Signal input part and first node, for believing under the control of first scanning signal at the first scanning signal end by described first By described under the control source first node of number input, or the control of the second scanning signal at the second scanning signal end The control source first node of binary signal input；

Input module connection section point, the secondary signal input and the first node, in institute State section point described in the control source of the secondary signal input under the control of the voltage of first node；

Second control module connect the first level terminal, second electrical level end, the 3rd node, fourth node, the 5th node, The first node and the section point, under the control of the voltage of the first node by first level terminal Control source described in the 3rd node and the voltage in the 3rd node control under by the voltage at the second electrical level end Input the first node, section point, fourth node and the 5th node；

First output module connects the first signal output part, the first clock signal terminal, first level terminal, described Section point, the 3rd node, the fourth node and the 5th node, for the voltage in the section point The first clock signal of first clock signal terminal is exported in first signal output part under control, or described The voltage of the fourth node is exported in first signal output part under the control of the voltage of three nodes；

It is second output module connection secondary signal output end, second clock signal end, first level terminal, described Section point, the 3rd node, the fourth node and the 5th node, for the voltage in the section point The second clock signal of the second clock signal end is exported in the secondary signal output end under control, or described The voltage of the fourth node is exported in the secondary signal output end under the control of the voltage of three nodes；

3rd output module connects the 3rd signal output part, the 3rd clock signal terminal, first level terminal, described Section point, the 3rd node, the fourth node and the 5th node, for the voltage in the section point The 3rd clock signal of the 3rd clock signal terminal is exported in the 3rd signal output part under control, or described The voltage of the fourth node is exported in the 3rd signal output part under the control of the voltage of three nodes；

4th output module connects the 4th signal output part, the 4th clock signal terminal, first level terminal, described Section point, the 3rd node, the fourth node and the 5th node, for the voltage in the section point The 4th clock signal of the 4th clock signal terminal is exported in the 4th signal output part under control, or described The voltage of the fourth node is exported in the 4th signal output part under the control of the voltage of three nodes；

The output control module connects the first scanning signal end, the 4th signal output part and described second Level terminal, for the voltage at the second electrical level end to exist under the control of first scanning signal at the first scanning signal end The 4th signal output part output.

Optionally, first control module includes：The first transistor and second transistor；

First pole of the first transistor connects first signal input part, and the second pole of the first transistor connects Connect the first node；The grid of the first transistor connects the first scanning signal end；

First pole of the second transistor connects the secondary signal input, and the second pole of the second transistor connects Connect the first node；The grid of the second transistor connects the second scanning signal end.

Optionally, the input module includes：Third transistor；

First pole of the third transistor connects the secondary signal input, and the second pole of the third transistor connects The section point is connect, the grid of the third transistor connects the first node.

Optionally, second control module includes：4th transistor, the 5th transistor, the 6th transistor, the 7th crystal Pipe, the 8th transistor and the 9th transistor；

First pole of the 4th transistor connects first level terminal, the second pole connection institute of the 4th transistor The 3rd node is stated, the grid of the 4th transistor connects first level terminal；

First pole of the 5th transistor connects the 3rd node, described in the second pole connection of the 5th transistor Second electrical level end, the grid of the 5th transistor connect the first node；

First pole of the 6th transistor connects the first node, described in the second pole connection of the 6th transistor Second electrical level end, the grid of the 6th transistor connect the 3rd node；

First pole of the 7th transistor connects the section point, described in the second pole connection of the 7th transistor Second electrical level end, the grid of the 7th transistor connect the 3rd node；

First pole of the 8th transistor connects the second electrical level end, the second pole connection institute of the 8th transistor The 5th node is stated, the grid of the 8th transistor connects the 3rd node；

First pole of the 9th transistor connects the second electrical level end, the second pole connection institute of the 9th transistor Fourth node is stated, the grid of the 9th transistor connects the 3rd node.

Optionally, first output module includes：Tenth transistor, the 11st transistor, the tenth two-transistor, the tenth Three transistors and the first electric capacity；

First pole of the tenth transistor connects the section point, described in the second pole connection of the tenth transistor First pole of the first electric capacity, the grid of the tenth transistor connect first level terminal；

The first pole connection first clock signal terminal of 11st transistor, the second of the 11st transistor Pole connects first signal output part, and the grid of the 11st transistor connects the first pole of first electric capacity；

First pole of the tenth two-transistor connects the first pole of first electric capacity, and the of the tenth two-transistor Two poles connect the 5th node, and the grid of the tenth two-transistor connects three node；

The first pole connection first signal output part of 13rd transistor, the second of the 13rd transistor Pole connects the fourth node, and the grid of the 13rd transistor connects three node；

Second pole of first electric capacity connects first signal output part.

Optionally, second output module includes：14th transistor, the 15th transistor, the 16th transistor, 17 transistors and the second electric capacity；

First pole of the 14th transistor connects the section point, the second pole connection of the 14th transistor First pole of second electric capacity, the grid of the 14th transistor connect first level terminal；

The first pole connection second clock signal end of 15th transistor, the second of the 15th transistor Pole connects the secondary signal output end, and the grid of the 15th transistor connects the first pole of second electric capacity；

First pole of the 16th transistor connects the first pole of second electric capacity, and the of the 16th transistor Two poles connect the 5th node, and the grid of the 16th transistor connects three node；

The first pole connection secondary signal output end of 17th transistor, the second of the 17th transistor Pole connects the fourth node, and the grid of the 17th transistor connects three node；

Second pole of second electric capacity connects the secondary signal output end.

Optionally, the 3rd output module includes：18th transistor, the 19th transistor, the 20th transistor, 21 transistors and the 3rd electric capacity；

First pole of the 18th transistor connects the section point, the second pole connection of the 18th transistor First pole of the 3rd electric capacity, the grid of the 18th transistor connect first level terminal；

The first pole connection the 3rd clock signal terminal of 19th transistor, the second of the 19th transistor Pole connects the 3rd signal output part, and the grid of the 19th transistor connects the first pole of the 3rd electric capacity；

First pole of the 20th transistor connects the first pole of the 3rd electric capacity, and the of the 20th transistor Two poles connect the 5th node, and the grid of the 20th transistor connects three node；

First pole of the 21st transistor connects the 3rd signal output part, the 21st transistor Second pole connects the 5th node, and the grid of the 21st transistor connects four node；

Second pole of the 3rd electric capacity connects the 3rd signal output part.

Optionally, the 4th output module includes：20th two-transistor, the 23rd transistor, the 24th crystalline substance Body pipe, the 25th transistor and the 4th electric capacity；

First pole of the 20th two-transistor connects the section point, the second pole of the 20th two-transistor The first pole of the 4th electric capacity is connected, the grid of the 20th two-transistor connects first level terminal；

First pole of the 23rd transistor connects the 4th clock signal terminal, the 23rd transistor Second pole connects the 4th signal output part, and the grid of the 23rd transistor connects the first of the 4th electric capacity Pole；

First pole of the 24th transistor connects the first pole of the 4th electric capacity, the 24th transistor The second pole connect the 5th node, the grid of the 24th transistor connects three node；

First pole of the 25th transistor connects the 4th signal output part, the 25th transistor Second pole connects the fourth node, and the grid of the 25th transistor connects three node；

Second pole of the 4th electric capacity connects the 4th signal output part.

Optionally, the output control module includes：26th transistor；

First pole of the 26th transistor connects the 4th signal output part, the 26th transistor Second pole connects the second electrical level end, and the grid of the 26th transistor connects the first scanning signal end.

Optionally, the first clock signal of first clock signal terminal, the second clock of the second clock signal end 4th clock signal of signal, the 3rd clock signal of the 3rd clock signal terminal and the 4th clock signal terminal is successively Differ 1/4 clock cycle, and the first clock signal of first clock signal terminal, the second of the second clock signal end 4th clock signal of clock signal, the 3rd clock signal of the 3rd clock signal terminal and the 4th clock signal terminal Dutycycle be 25%.

Optionally, it is characterised in that each transistor is N-type transistor；Or each transistor is P-type crystal Pipe.

Second aspect, there is provided a kind of driving method of shift register cell, for driving described in any one of first aspect Shift register cell；Methods described includes：

First stage, the first control module is under the control of first scanning signal at the first scanning signal end by the first signal The control source first node of input；Input module is under the control of the voltage of first node by the electricity of secondary signal input Pressure input section point；Output control module is under the control of first scanning signal at the first scanning signal end by second electrical level end Voltage signal output part export；

Second stage, the first control module is under the control of second scanning signal at the second scanning signal end by secondary signal The control source first node of input；Input module is under the control of the voltage of first node by the electricity of secondary signal input Pressure input section point；First output module is under the control of the voltage of section point by the first clock of the first clock signal terminal Signal exports in the first signal output part；

Phase III, the first control module is under the control of second scanning signal at the second scanning signal end by secondary signal The control source first node of input；Input module is under the control of the voltage of first node by the electricity of secondary signal input Pressure input section point；Second output module is under the control of the voltage of section point by the second clock of second clock signal end Signal exports in secondary signal output end；

Fourth stage, the first control module is under the control of second scanning signal at the second scanning signal end by secondary signal The control source first node of input；Input module is under the control of the voltage of first node by the electricity of secondary signal input Pressure input section point；3rd output module is under the control of the voltage of section point by the 3rd clock of the 3rd clock signal terminal Signal exports in the 3rd signal output part；

In 5th stage, the first control module is under the control of second scanning signal at the second scanning signal end by secondary signal The control source first node of input；Input module is under the control of the voltage of first node by the electricity of secondary signal input Pressure input section point；4th output module is under the control of the voltage of section point by the 4th of the 4th clock signal terminal the Clock signal exports in the 4th signal output part；

In 6th stage, the second control module is under the control of the second scanning signal by the control source the 3rd of the first level terminal By the control source first node at second electrical level end, section point, the 4th under the control of node and voltage in the 3rd node Node and the 5th node；First output module, the second output module, the 3rd output module and the 4th output module exist Respectively in the first signal output part, secondary signal output end, the 3rd signal output part under the control of the voltage of 3rd node And the 4th signal output part output fourth node voltage；

7th stage, control module under the control of first node by the node of control source the 3rd of the first level terminal and Under the control of the voltage of the 3rd node by the control source first node at second electrical level end, section point, fourth node and 5th node.

The third aspect, there is provided a kind of gate driving circuit, including displacement described at least one any one of first aspect are posted Storage unit.

Fourth aspect, there is provided a kind of display device, including the gate driving circuit described in the third aspect.

Shift register cell provided in an embodiment of the present invention includes：First control module, input module, the second control mould Block, the first output module, the second output module, the 3rd output module, the 4th output module and output control module, wherein the One control module can be by secondary signal input by the control source first node of secondary signal input, input module Control source section point, the second control module is capable of the node of control source the 3rd of the first level terminal and by second electrical level Control source first node, section point, fourth node and the 5th node at end, the first output module can be by the first clocks First clock signal of signal end exports in the first signal output part, or by the voltage of fourth node in the first signal output part Output, the second output module can export the second clock signal of second clock signal end in secondary signal output end, or The voltage of fourth node is exported in secondary signal output end, when the 3rd output module can be by the 3rd of the 3rd clock signal terminal the Clock signal is exported in the 3rd signal output part, or the voltage of fourth node is exported in the 3rd signal output part, the 4th output Module can export the 4th clock signal of the 4th clock signal terminal in the 4th signal output part, or the electricity by fourth node The output of the 4th signal output part is pressed in, output control module can be defeated in the 4th signal output part by the voltage at second electrical level end Go out, i.e., share the first control module, input module and the second control by four signal output modules in the embodiment of the present invention Module, so as to which respectively gate drive signal can be provided to a grid line, compared to each shift register in the prior art Between unit gate drive signal, shift register provided in an embodiment of the present invention are provided without common part and only to a grid line Unit shares the first control module, input module and the second control module by four signal output modules, so as to which difference can It is public equivalent to by the partial function in level Four shift register cell to provide gate drive signal to a grid line, so The embodiment of the present invention can reduce the device in shift register cell, and then simplify gate driving circuit.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these accompanying drawings.

Fig. 1 is the schematic diagram for the shift register cell that embodiments of the invention provide；

Fig. 2 is the circuit diagram for the shift register cell that embodiments of the invention provide；

Fig. 3 is the step flow chart of the driving method for the shift register cell that embodiments of the invention provide；

Fig. 4 is the timing diagram of each signal in the shift register cell that embodiments of the invention provide；

Fig. 5 is the schematic diagram for the gate driving circuit that embodiments of the invention provide.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

The transistor used in all embodiments of the invention can be thin film transistor (TFT) or FET or other characteristics Identical device, it is mainly switching transistor according to transistor used by effect embodiments of the invention in circuit.By Source electrode, drain electrode in the switching transistor used here are symmetrical, so its source electrode, drain electrode can exchange.In this hair In bright embodiment, to distinguish the two poles of the earth of transistor in addition to grid, wherein it will be referred to as the first pole by source electrode, drain electrode is referred to as the second pole. Provide that the intermediate ends of transistor are grid, signal input part is source electrode, signal output part is drain electrode by the form in accompanying drawing.In addition Switching transistor includes two kinds of p-type switching transistor and N-type switching transistor used by the embodiment of the present invention, wherein, p-type is opened Close transistor to turn on when grid be low level, end when grid be high level, it in grid is that height is electric that N-type switching transistor, which is, Conducts, end when grid is low level.

It should be noted that the printed words such as " first ", " second " in the application be used for the purpose of it is basic to function and effect Identical identical entry or similar item make a distinction, and the printed words such as " first ", " second " are not to quantity and execution order progress Limit, such as " the first transistor ", " second transistor ", " the 4th transistor " are likely to occur in the same embodiment without occurring " third transistor ", then " first ", " second ", " the 4th " only can be understood as the differentiation to different crystal pipe, without being understood that Also to include " third transistor " in the embodiment.

The embodiment of the present invention provides a kind of shift register cell, and shown in reference picture 1, the shift register cell includes： First control module 11, input module 12, the second control module 13, the first output module 14, the second output module the 15, the 3rd are defeated Go out module 16, the 4th output module 17 and output control module 18.

Wherein, the first control module 11 connects the first scanning signal end S1, the second scanning signal end S2, the input of the first signal Input1, secondary signal input Input2 and first node a are held, for the first scanning letter in the first scanning signal end S1 Number control under by the first signal input part Input1 control source first node a, or the second scanning signal end S2's By secondary signal input Input2 control source first node a under the control of second scanning signal.

Input module 12 connects section point b, secondary signal input Input2 and first node a, for first By secondary signal input Input2 control source section point b under the control of node a voltage.

Second control module 13 connects the first level terminal V1, second electrical level end V2, the 3rd node c, fourth node d, the 5th Node e, first node a and section point b, under the control of first node a voltage by the first level terminal V1 electricity By second electrical level end V2 control source first node under the control of pressure the 3rd node c of input and the voltage in the 3rd node c A, section point b, fourth node d and the 5th node e.

First output module 14 connects the first signal output part Output1, the first clock signal terminal CLK1, the first level terminal V1, section point b, the 3rd node c, fourth node d and the 5th node e, for being incited somebody to action under the control of section point b voltage First clock signal terminal CLK1 the first clock signal exports in the first signal output part Output1, or the 3rd node c's Under the control of voltage by fourth node d voltage the first signal output part Output1 output.

Second output module 15 connection secondary signal output end Output2, second clock signal end CLK2, the first level terminal V1, section point b, the 3rd node c, fourth node d and the 5th node e, for being incited somebody to action under the control of section point b voltage Second clock signal end CLK2 second clock signal exports in secondary signal output end Output2, or the 3rd node c's Fourth node d voltage is exported in secondary signal output end Output2 under the control of voltage.

3rd output module 16 connects the 3rd signal output part Output3, the 3rd clock signal terminal CLK3, the first level terminal V1, section point b, the 3rd node c, fourth node d and the 5th node e, for being incited somebody to action under the control of section point b voltage 3rd clock signal terminal CLK3 the 3rd clock signal exports in the 3rd signal output part Output3, or the 3rd node c's Fourth node d voltage is exported in the 3rd signal output part Output3 under the control of voltage.

4th output module 17 connects the 4th signal output part Output4, the 4th clock signal terminal CLK4, the first level terminal V1, section point b, the 3rd node c, fourth node d and the 5th node e, for being incited somebody to action under the control of section point b voltage 4th clock signal terminal CLK4 the 4th clock signal exports in the 4th signal output part Output4, or the 3rd node c's Fourth node d voltage is exported in the 4th signal output part Output4 under the control of voltage.

The output control module 18 connects the first scanning signal end S1, the 4th signal output part Output4 And the second electrical level end V2, for electric by second under the control of the first scanning signal of the first scanning signal end S1 Flush end V2 voltage exports in the 4th signal output part Output4.

Further, shown in reference picture 2, the first control module 11 includes：The first transistor T1 and second transistor T2；

The first transistor T1 the first pole connects the first signal input part Input1, the first transistor T1 the second pole connection First node a；The first transistor T1 grid connects the first scanning signal end S1；

Second transistor T2 the first pole connection secondary signal input Input2, second transistor T2 the second pole connection First node a；Second transistor T2 grid connects the second scanning signal end S2.

Input module 12 includes：Third transistor T3；

Third transistor T3 the first pole connection secondary signal input Input2, third transistor T3 the second pole connection Section point b, third transistor T3 grid connection first node a.

Second control module 13 includes：4th transistor T4, the 5th transistor T5, the 6th transistor T6, the 7th transistor T7, the 8th transistor T8 and the 9th transistor T9；

4th transistor T4 the first pole connects the first level terminal V1, and the 4th transistor T4 the second pole connects the 3rd node C, the 4th transistor T4 grid connect the first level terminal V1；

5th transistor T5 the first pole connects the 3rd node c, the 5th transistor T5 the second pole connection second electrical level end V2, the 5th transistor T5 grid connection first node a；

6th transistor the T6 connection of the first pole first node a, the 6th transistor T6 the second pole connection second electrical level end V2, the grid of the 6th transistor connect the 3rd node c；

7th transistor the T7 connection of the first pole section point b, the 7th transistor T7 the second pole connection second electrical level end V2, the 7th transistor T7 grid connect the 3rd node c；

8th transistor T8 the first pole connection second electrical level end V2, the 8th transistor T8 the second pole connect the 5th node E, the 8th transistor T8 grid connect the 3rd node c；

9th transistor T9 the first pole connection second electrical level end V2, the 9th transistor T9 the second pole connection fourth node D, the 9th transistor T9 grid connect the 3rd node c.

First output module 14 includes：Tenth transistor T10, the 11st transistor T11, the tenth two-transistor T12, the tenth Three transistor T13 and the first electric capacity C1；

Tenth transistor the T10 connection of the first pole section point b, the tenth transistor T10 the second pole connect the first electric capacity C1 the first pole, the tenth transistor T10 grid connect the first level terminal V1；

11st transistor T11 the first pole connects the first clock signal terminal CLK1, the 11st transistor T11 the second pole The grid for connecting the first signal output part Output1, the 11st transistor T11 connects the first electric capacity C1 the first pole；

Tenth two-transistor T12 the first pole connects the first electric capacity C1 the first pole, the tenth two-transistor T12 the second pole The 5th node e is connected, the tenth two-transistor T12 grid connects three node c；

13rd transistor T13 the first pole connects the first signal output part Output1, and the of the 13rd transistor T13 Two poles connection fourth node d, the 13rd transistor T13 grid connect three node c；

First electric capacity C1 the second pole connects the first signal output part Output1.

Second output module 15 includes：14th transistor T14, the 15th transistor T15, the 16th transistor T16, 17 transistor T17 and the second electric capacity C2；

14th transistor the T14 connection of the first pole section point b, the 14th transistor T14 the second pole connection second Electric capacity C2 the first pole, the 14th transistor T14 grid connect the first level terminal V1；

15th transistor T15 the first pole connection second clock signal end CLK2, the 15th transistor T15 the second pole The grid for connecting secondary signal output end Output2, the 15th transistor T15 connects the second electric capacity C2 the first pole；

16th transistor T16 the first pole connects the second electric capacity C2 the first pole, the 16th transistor T16 the second pole The 5th node e is connected, the 16th transistor T16 grid connects three node c；

The of 17th transistor the T17 connection of the first pole secondary signal output end Output2, the 17th transistor T17 Two poles connection fourth node d, the 17th transistor T17 grid connect three node c；

Second electric capacity C2 the second pole connection secondary signal output end Output2.

3rd output module includes：18th transistor T18, the 19th transistor T19, the 20th transistor T20, second 11 transistor T21 and the 3rd electric capacity C3；

18th transistor the T18 connection of the first pole section point b, the 18th transistor T18 the second pole connection the 3rd Electric capacity C3 the first pole, the 18th transistor T18 grid connect the first level terminal V1；

19th transistor T19 the first pole connects the 3rd clock signal terminal CLK3, the 19th transistor T19 the second pole The 3rd signal output part Output3 is connected, the 19th transistor T19 grid connects the 3rd electric capacity C3 the first pole；

20th transistor T20 the first pole connects the 3rd electric capacity C3 the first pole, the 20th transistor T20 the second pole The 5th node e is connected, the 20th transistor T20 grid connects three node c；

The 21st transistor T21 connection of the first pole the 3rd signal output part Output3, the 21st transistor T21 The second pole connection fourth node d, the 21st transistor T21 grid connect three node c；

3rd electric capacity C3 the second pole connects the 3rd signal output part Output3.

4th output module 17 includes：20th two-transistor T22, the 23rd transistor T23, the 24th transistor T24, the 25th transistor T25 and the 4th electric capacity C4；

20th two-transistor the T22 connection of the first pole section point b, the 20th two-transistor T22 the second pole connection 4th electric capacity C4 the first pole, the 20th two-transistor T22 grid connect the first level terminal V1；

23rd transistor T23 the first pole connects the 4th clock signal terminal CLK4, and the of the 23rd transistor T23 Two poles connect the 4th signal output part Output4, and the 23rd transistor T23 grid connects the 4th electric capacity C4 the first pole；

24th transistor T24 the first pole connects the 4th electric capacity C4 the first pole, and the of the 24th transistor T24 Two poles connect the 5th node e, and the 24th transistor T24 grid connects three node c；

The 25th transistor T25 connection of the first pole the 4th signal output part Output4, the 25th transistor T25 The second pole connection fourth node d, the 25th transistor T25 grid connect three node c；

4th electric capacity C4 the second pole connects the 4th signal output part Output4.

The output control module 18 includes：26th transistor T26；

The first pole of the 26th transistor T26 connects the 4th signal output part Output4, and the described 20th Six transistor T26 the second pole connects the second electrical level end V2, the grid connection of the 26th transistor T26 described the Scan signal end S1.

Yet another embodiment of the invention provides a kind of driving method of shift register cell, and the driving method is used to drive The shift register cell of any embodiment offer is provided.Specifically, shown in reference picture 3, the volume driving of the shift register cell Method comprises the following steps：

S31, first stage, the first control module is under the control of first scanning signal at the first scanning signal end by first The control source first node of signal input part；Input module is under the control of the voltage of first node by secondary signal input Control source section point；Output control module is under the control of first scanning signal at the first scanning signal end by the second electricity The voltage of flush end exports in signal output part.

S32, second stage, the first control module is under the control of second scanning signal at the second scanning signal end by second The control source first node of signal input part；Input module is under the control of the voltage of first node by secondary signal input Control source section point；First output module is under the control of the voltage of section point by the first of the first clock signal terminal Clock signal exports in the first signal output part.

S33, phase III, the first control module is under the control of second scanning signal at the second scanning signal end by second The control source first node of signal input part；Input module is under the control of the voltage of first node by secondary signal input Control source section point；Second output module is under the control of the voltage of section point by the second of second clock signal end Clock signal exports in secondary signal output end.

S34, fourth stage, the first control module is under the control of second scanning signal at the second scanning signal end by second The control source first node of signal input part；Input module is under the control of the voltage of first node by secondary signal input Control source section point；3rd output module is under the control of the voltage of section point by the 3rd of the 3rd clock signal terminal the Clock signal exports in the 3rd signal output part.

S35, the 5th stage, the first control module is under the control of second scanning signal at the second scanning signal end by second The control source first node of signal input part；Input module is under the control of the voltage of first node by secondary signal input Control source section point；4th output module is under the control of the voltage of section point by the 4th of the 4th clock signal terminal the Clock signal exports in the 4th signal output part.

S36, the 6th stage, the second control module is under the control of the second scanning signal by the control source of the first level terminal Under the control of 3rd node and the voltage in the 3rd node by the control source first node at second electrical level end, section point, Fourth node and the 5th node；First output module, the second output module, the 3rd output module and the 4th output module exist Under the control of the voltage of 3rd node respectively the first signal output part, secondary signal output end, the 3rd signal output part and 4th signal output part exports the voltage of fourth node.

S37, the 7th stage, control module is under the control of first node by the node of control source the 3rd of the first level terminal And by the control source first node, section point, fourth node at second electrical level end under the control of the voltage in the 3rd node And the 5th node.

Shift register cell driving method provided in an embodiment of the present invention is in the first stage by the first signal input part Control source first node, by the control source section point of secondary signal input and by the voltage at second electrical level end Four signal output parts export, and divide in second stage into the 5th stage by the first clock signal of the first clock signal terminal, second The 4th of the second clock signal of clock signal terminal, the 3rd clock signal of the 3rd clock signal terminal and the 4th clock signal terminal Clock signal exports in the first signal output part, secondary signal output end, the 3rd signal output part and the 4th signal output part, The 6th stage by the voltage output first node at second electrical level end, section point, fourth node and the 5th node and First signal output part, secondary signal output end, the 3rd signal output part and the 4th signal output part export fourth node Voltage, so shift register cell driving method provided in an embodiment of the present invention can drive the grid in above-described embodiment to drive Dynamic circuit output gate drive signal, and in the embodiment of the present invention by four signal output modules share the first control module, Input module and the second control module, so as to which respectively gate drive signal can be provided to a grid line, compared to existing skill Gate drive signal is provided without common part and only to a grid line between each shift register cell in art, the present invention is real The shift register cell for applying example offer shares the first control module, input module and second by four signal output modules Control module, so as to which respectively gate drive signal can be provided to a grid line, equivalent to by level Four shift register cell Partial function it is public, so the embodiment of the present invention can reduce the device in shift register cell, and then simplify grid and drive Dynamic circuit.

Hereinafter, the time sequence status schematic diagram shown in reference picture 4, to shown in the shift register cell and Fig. 3 shown in Fig. 2 The operation principle of the driving method of shift register cell illustrates, wherein, high level VGH is provided with the first level terminal V1, Second electrical level end V2 provides low level VGL, and is led in shift register cell shown in Fig. 2 during the equal grid high level of all transistors Illustrated exemplified by logical N-type transistor.Exemplary, second electrical level end V2 can be earth terminal.It should also be noted that, work as During the N-type transistor turned in shift register cell shown in Fig. 2 during the equal grid high level of all transistors, the 4th transistor T4, the tenth transistor T10, the 14th transistor T14, the 18th transistor T18 and the 20th two-transistor T22 grids are all the time It is connected with the first level terminal V1 for providing high level, so the tenth transistor T10, the 14th transistor T14, the 18th transistor T18 and the 20th two-transistor T22 is normally on transistors.

Shown in Fig. 4 the first clock signal terminal CLK1 the first clock signal, the second of second clock signal end CLK2 Clock signal, the 3rd clock signal terminal CLK3 the 3rd clock signal, the 4th clock signal terminal CLK4 the 4th clock signal, One signal input part Input1 input signal, secondary signal input Input2 input signal, the first scanning signal end S1 The first scanning signal and the second scanning signal end the second scanning signal timing diagram.Wherein the first clock signal, second The cycle of clock signal, the 3rd clock signal and the 4th clock signal is 4T, dutycycle 25%.First signal input part The cycle of Input1 input signal and secondary signal input Input2 input signal is 8T, and dutycycle 5/8, first believes The initial time of number input Input1 input signal high level shifts to an earlier date 5T than the initial time of CLK1 output high level, and second The initial time of signal input part Input2 input signal output high level shifts to an earlier date than the initial time of CLK1 output high level T.First scanning signal and the second scanning signal show that the time of high level is 5T, and the first scanning signal exports high level Initial time shift to an earlier date 5T than the initial time of CLK1 output high level, the initial time of the second scanning signal output high level with CLK1 output high level initial time it is identical, wherein the cycle of the first scanning signal and the second scanning signal can according to including The scan frequency determination of the display surface gate driving circuit of the shift register cell, exemplary, scan frequency 60HZ, then The cycle of first scanning signal and the second scanning signal is 16.67ms.As shown in Figure 4, there is provided the time sequence status in seven stages, its In, first stage t1；Second stage is t2；Phase III is t3；Fourth stage is t4；5th stage was t5；6th stage For t6；7th stage was t7.

T1 stages, Input1 high level, the first transistor T1, the 26th transistor T26 conducting, and because the high electricity of S1 It is flat, therefore first node a level is driven high, the third transistor T3 and the 5th transistor T5 that grid is connected with first node a are led It is logical.Because T5 is turned on, the 3rd node c passes through T5 connection second electrical levels end V2, the 3rd node c low levels.Because T3 is turned on And Input2 high level, so Input2 by third transistor T3 simultaneously to the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 chargings, T11, T15, T19, T23 conducting, but because CLK1, CLK2, CLK3 are low electricity in this stage It is flat, so the first output module, the second output module and the 3rd output module export low voltage level in this stage.And because T26 is turned on, so Output output points point is put down.This stage is to the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and the Four electric capacity C4 charge, therefore the t1 stages are referred to as pre-charging stage.

In the t2 stages, Input1 and S1 is low level in this stage, and T1 cut-offs, Input2 and S2 are high level, therefore T2 is turned on, and Input2 draws high first node a voltage, T3, T5 conducting by T2, and Input2 draws high section point b's by T3 Voltage, T11 are still turned on.Again because this node CLK1 starts to export high level, t2 stages, Output1 output high level. In addition, the high level of Output1 outputs acts on the first electric capacity C1 the second pole, so bootstrap effect occurs for the first electric capacity C1, The voltage of the first poles of lifting the first electric capacity C1, and then it is more stable T11 is turned on more abundant, Output1 output signal. CLK2, CLK3, CLK4 are low level, so Output2, Output3, Output4 export low level.This rank first exports Module 14 is exported, therefore the t2 stages were referred to as the first output stage.

In the t3 stages, each signal condition is similar with the t2 stages in this stage, and difference is height of the CLK1 by the t2 stages Level is changed into low level, and CLK2 is changed into high level, therefore Output2 output high level from the low level in t2 stages.Equally, The high level of Output2 outputs acts on the second electric capacity C2 the second pole, so bootstrap effect occurs for the second electric capacity C2, lifting the The voltage of two the first poles of electric capacity C2, and then it is more stable T15 is turned on more abundant, Output2 output signal.CLK1、 CLK3, CLK4 are low level, so Output1, Output3, Output4 export low level.This stage second exports mould Block 15 is exported, therefore the t3 stages were referred to as the second output stage.

In the t4 stages, each signal condition is similar with the t3 stages in this stage, and difference is height of the CLK2 by the t3 stages Level is changed into low level, and CLK3 is changed into high level, therefore Output3 output high level from the low level in t3 stages.Equally, The high level of Output3 outputs acts on the 3rd electric capacity C3 the second pole, so bootstrap effect occurs for the 3rd electric capacity C3, lifting the The voltage of three the first poles of electric capacity C3, and then it is more stable T19 is turned on more abundant, Output3 output signal.CLK1、 CLK2, CLK4 are low level, so Output1, Output2, Output4 export low level.This stage the 3rd exports mould Block 16 is exported, therefore the t4 stages were referred to as the 3rd output stage.

In the t5 stages, each signal condition is similar with the t4 stages in this stage, and difference is height of the CLK3 by the t4 stages Level is changed into low level, and CLK4 is changed into high level, therefore Output4 output high level from the low level in t4 stages.Equally, The high level of Output4 outputs acts on the 4th electric capacity C4 the second pole, so bootstrap effect occurs for the 4th electric capacity C4, lifting the The voltage of four the first poles of electric capacity C4, and then it is more stable T23 is turned on more abundant, Output4 output signal.CLK1、 CLK2, CLK3 are low level, so Output1, Output2, Output3 export low level.This stage the 4th exports mould Block 16 is exported, therefore the t5 stages were referred to as the 4th output stage.

In the t6 stages, this stage S2 high level, so T2 is turned on, Input2 low levels, Input2 is by T2 by first node a Draw as low level, T3, T5 cut-off.Because T5 ends, it is high level that V1, which is drawn the 3rd node c by T4, T6, T7, T8, T9, T12, T13, T16, T17, T20, T21, T24 and T25 are turned on.V2 passes through the low electricity of T8 connections the 5th node e, the 5th node e Flat, V2 passes through T9 connection fourth node d, fourth node d low levels.First electric capacity C1 the first pole passes through Section five of T12 connections Point e, the first electric capacity C1 are discharged, and Output1 is discharged output low level by T13 connection fourth nodes d, Ouput1.Similarly, C2 the first pole is discharged by the node e of T16 connections the 5th, C2, and Output2 passes through T13 connection fourth node d, Ouput2 quilts Electric discharge, export low level；C3 the first pole is discharged by the node e of T20 connections the 5th, C3, and Output3 passes through T21 connections Four node d, Ouput3 are discharged, and export low level；C4 the first pole is discharged by the node e of T24 connections the 5th, C4, Output4 is discharged by T25 connection fourth nodes d, Ouput4, exports low level.This stage discharges each output end, Therefore the t6 stages are referred to as discharge regime.

T7 stages, S1, S2 are level, therefore V1 draws high the 3rd node c voltage by T4, C1, C2, C3, C4, Output1, Output2, Output3, Output4 continue to discharge, and Output1, Output2, Output3, Output4 are exported Low level.This stage still discharges each output end, therefore the t7 stages are referred to as the stabilization sub stage.

It should be noted that above-mentioned shift register cell may include some stages after the t7 stages, this be by What the cycle of the first scanning signal and the second scanning signal was determined, but in S1 before secondary output high level, shift LD The 3rd node c in device unit keeps high level Output1, Output2, Output3, Output4 to export low level

Further, all transistors can also be low level conducting in the shift register cell in above-described embodiment P-type transistor, if all transistors are P-type transistor, only need to readjust each input of shift register cell The time sequence status of signal, such as：Adjust the first level terminal V1 and low level is provided, adjust t1-t5 stages Input2 in Fig. 4 and adjust Whole is low level, and adjustment t6-t7 stages Input2 are high level, and other signals are also adjusted to the clock signal of opposite in phase.

Further, N-type transistor and P-type transistor can also be used in above-mentioned shift register cell simultaneously, this When need to ensure in shift register cell to need to use identical class by same clock signal or voltage-controlled transistor Type, certainly this reasonable work-around solution that to be all those skilled in the art can make according to embodiments of the invention, therefore Protection scope of the present invention is should be, but in view of the making technology of transistor, due to the active layer of different types of transistor Dopant material differs, therefore is more beneficial for shift register cell using the transistor of uniform type in shift register cell Making technology.

One embodiment of the invention provides a kind of gate driving circuit, including the shift LD at least one above-described embodiment Device unit.

Specifically, shown in reference picture 5, the gate driving circuit includes the shift register cell of several cascades, wherein, First signal output part Output1 connections grid line G1 of the 1st grade of shift register cell, the of the 1st grade of shift register cell Binary signal output end Output2 connections grid line G2, the 3rd signal output part Output3 connections of the 1st grade of shift register cell Grid line G3, the 4th signal output part Output4 connection grid lines G4 of the 1st grade of shift register cell；2nd grade of shift register list First signal output part Output1 connections grid line G5 of member, the secondary signal output end of the 2nd grade of shift register cell Output2 connections grid line G6, the 3rd signal output part Output3 connection grid line G7 of the 2nd grade of shift register cell, the 2nd grade 4th signal output part Output4 connection grid lines G8 of shift register cell；First signal of n-th grade of shift register cell Output end Output1 connection grid lines G4n-3, the secondary signal output end Output2 connection grid lines of n-th grade of shift register cell G4n-2, the 3rd signal output part Output3 connections grid line G4n-1 of n-th grade of shift register cell, n-th grade of shift register 4th signal output part Output4 connection grid lines G4n of unit.

In addition, each shift register cell has a first clock signal terminal CLK1, a second clock signal end CLK2, the 3rd clock signal terminal CLK3, a 4th clock signal terminal CLK4 and two signal input parts；The institute of reference picture 5 Show, connected by clock signal clock1, clock2, clock3 and clock4 of four systemses to each shift register cell Four clock signal terminals connect provide clock signal, CLK1 the inputs clock1, CLK2 of each of which level shift register cell Input clock2, CLK3 input clock3, CLK4 inputs clock4.By two input signal INPUT1 and INPUT2 to each First signal input part Input1 and Input2 of shift register cell connection provides input signal；Wherein, the 1st grade of displacement is posted The first signal input part Input1 inputs INPUT1, the secondary signal input of the 1st grade of shift register cell of storage unit Input2 inputs INPUT2；The first signal input part Input1 inputs INPUT2 of 2nd grade of shift register cell, the 2nd grade of shifting The secondary signal input Input2 inputs INPUT1 of bit register unit；For n-th grade of shift register cell, when n is strange During number, each signal input part input of n-th grade of shift register cell is defeated with each signal of the 1st grade of shift register cell Enter end input identical input signal；When n is even number, each signal input part input of n-th grade of shift register cell with Each signal input part input identical clock signal of 2nd grade of shift register cell；Carried out in Fig. 5 so that n is odd number as an example Explanation.

Wherein, the first clock signal terminal CLK1 the first clock signal, second in the time sequence status reference picture 4 of system clock Clock signal terminal CLK2 second clock signal, the 3rd clock signal terminal CLK3 the 3rd clock signal, the 4th clock signal terminal CLK4 the 4th clock signal；Wherein, clock1, clock2, clock3, clock4 phase differ 1/4 clock cycle successively, Clock1, clock2, clock3, clock4 are the clock signal that dutycycle is 25%.

Further, two level terminals and two scanning signal ends are also included per one-level shift register cell, wherein, First level terminal of each shift register cell can provide voltage by same level terminal, can also use one respectively Individual independent level terminal, the second electrical level end of each same shift register cell can provide electricity by same level terminal Pressure, an independent level terminal can also be used respectively, scanning signal end is not shared between each shift register cell.

Yet another embodiment of the invention provides a kind of display device, including any gate driving circuit in above-described embodiment.

In addition, display device can be：Electronic Paper, mobile phone, tablet personal computer, television set, display, notebook computer, number Any product or part with display function such as code-phase frame, navigator.

The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any Those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in, all should It is included within the scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.

Claims

A kind of 1. shift register cell, it is characterised in that including：First control module, input module, the second control module, First output module, the second output module, the 3rd output module, the 4th output module and output control module；

First control module connects the first scanning signal end, the second scanning signal end, the first signal input part, secondary signal Input and first node, under the control of first scanning signal at the first scanning signal end that first signal is defeated Enter the control source first node at end, or believe under the control of the second scanning signal at the second scanning signal end by described second The control source first node of number input；

Input module connection section point, the secondary signal input and the first node, for described the By section point described in the control source of the secondary signal input under the control of the voltage of one node；

Second control module connects the first level terminal, second electrical level end, the 3rd node, fourth node, the 5th node, described First node and the section point, under the control of the voltage of the first node by the electricity of first level terminal By the control source at the second electrical level end under the control of pressure input the 3rd node and the voltage in the 3rd node The first node, section point, fourth node and the 5th node；

First output module connects the first signal output part, the first clock signal terminal, first level terminal, described second Node, the 3rd node, the fourth node and the 5th node, the control for the voltage in the section point Lower the first clock signal by first clock signal terminal exports in first signal output part, or at described Section three The voltage of the fourth node is exported in first signal output part under the control of the voltage of point；

The second output module connection secondary signal output end, second clock signal end, first level terminal, described second Node, the 3rd node, the fourth node and the 5th node, the control for the voltage in the section point The lower second clock signal by the second clock signal end exports in the secondary signal output end, or at described Section three The voltage of the fourth node is exported in the secondary signal output end under the control of the voltage of point；

3rd output module connects the 3rd signal output part, the 3rd clock signal terminal, first level terminal, described second Node, the 3rd node, the fourth node and the 5th node, the control for the voltage in the section point Lower the 3rd clock signal by the 3rd clock signal terminal exports in the 3rd signal output part, or at described Section three The voltage of the fourth node is exported in the 3rd signal output part under the control of the voltage of point；

4th output module connects the 4th signal output part, the 4th clock signal terminal, first level terminal, described second Node, the 3rd node, the fourth node and the 5th node, the control for the voltage in the section point Lower the 4th clock signal by the 4th clock signal terminal exports in the 4th signal output part, or at described Section three The voltage of the fourth node is exported in the 4th signal output part under the control of the voltage of point；

The output control module connects the first scanning signal end, the 4th signal output part and the second electrical level End, under the control of first scanning signal at the first scanning signal end by the voltage at the second electrical level end described 4th signal output part exports.
2. shift register cell according to claim 1, it is characterised in that first control module includes：First Transistor and second transistor；

First pole of the first transistor connects first signal input part, the second pole connection institute of the first transistor State first node；The grid of the first transistor connects the first scanning signal end；

First pole of the second transistor connects the secondary signal input, the second pole connection institute of the second transistor State first node；The grid of the second transistor connects the second scanning signal end.
3. shift register cell according to claim 1, it is characterised in that the input module includes：3rd crystal Pipe；

First pole of the third transistor connects the secondary signal input, the second pole connection institute of the third transistor Section point is stated, the grid of the third transistor connects the first node.
4. shift register cell according to claim 1, it is characterised in that second control module includes：4th Transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor；

First pole of the 4th transistor connects first level terminal, the second pole connection of the 4th transistor described the Three nodes, the grid of the 4th transistor connect first level terminal；

First pole of the 5th transistor connects the 3rd node, the second pole connection described second of the 5th transistor Level terminal, the grid of the 5th transistor connect the first node；

First pole of the 6th transistor connects the first node, the second pole connection described second of the 6th transistor Level terminal, the grid of the 6th transistor connect the 3rd node；

First pole of the 7th transistor connects the section point, the second pole connection described second of the 7th transistor Level terminal, the grid of the 7th transistor connect the 3rd node；

First pole of the 8th transistor connects the second electrical level end, the second pole connection of the 8th transistor described the Five nodes, the grid of the 8th transistor connect the 3rd node；

First pole of the 9th transistor connects the second electrical level end, the second pole connection of the 9th transistor described the Four nodes, the grid of the 9th transistor connect the 3rd node.
5. shift register cell according to claim 1, it is characterised in that first output module includes：Tenth Transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor and the first electric capacity；

First pole of the tenth transistor connects the section point, the second pole connection described first of the tenth transistor First pole of electric capacity, the grid of the tenth transistor connect first level terminal；

First pole of the 11st transistor connects first clock signal terminal, and the second pole of the 11st transistor connects First signal output part is connect, the grid of the 11st transistor connects the first pole of first electric capacity；

First pole of the tenth two-transistor connects the first pole of first electric capacity, the second pole of the tenth two-transistor The 5th node is connected, the grid of the tenth two-transistor connects the 3rd node；

First pole of the 13rd transistor connects first signal output part, and the second pole of the 13rd transistor connects The fourth node is connect, the grid of the 13rd transistor connects the 3rd node；

Second pole of first electric capacity connects first signal output part.
6. shift register cell according to claim 1, it is characterised in that second output module includes：Tenth Four transistors, the 15th transistor, the 16th transistor, the 17th transistor and the second electric capacity；

First pole of the 14th transistor connects the section point, described in the second pole connection of the 14th transistor First pole of the second electric capacity, the grid of the 14th transistor connect first level terminal；

First pole of the 15th transistor connects the second clock signal end, and the second pole of the 15th transistor connects The secondary signal output end is connect, the grid of the 15th transistor connects the first pole of second electric capacity；

First pole of the 16th transistor connects the first pole of second electric capacity, the second pole of the 16th transistor The 5th node is connected, the grid of the 16th transistor connects the 3rd node；

First pole of the 17th transistor connects the secondary signal output end, and the second pole of the 17th transistor connects The fourth node is connect, the grid of the 17th transistor connects the 3rd node；

Second pole of second electric capacity connects the secondary signal output end.
7. shift register cell according to claim 1, it is characterised in that the 3rd output module includes：Tenth Eight transistors, the 19th transistor, the 20th transistor, the 21st transistor and the 3rd electric capacity；

First pole of the 18th transistor connects the section point, described in the second pole connection of the 18th transistor First pole of the 3rd electric capacity, the grid of the 18th transistor connect first level terminal；

First pole of the 19th transistor connects the 3rd clock signal terminal, and the second pole of the 19th transistor connects The 3rd signal output part is connect, the grid of the 19th transistor connects the first pole of the 3rd electric capacity；

First pole of the 20th transistor connects the first pole of the 3rd electric capacity, the second pole of the 20th transistor The 5th node is connected, the grid of the 20th transistor connects the 3rd node；

The first pole connection the 3rd signal output part of 21st transistor, the second of the 21st transistor Pole connects the 5th node, and the grid of the 21st transistor connects the fourth node；

Second pole of the 3rd electric capacity connects the 3rd signal output part.
8. shift register cell according to claim 1, it is characterised in that the 4th output module includes：Second Ten two-transistors, the 23rd transistor, the 24th transistor, the 25th transistor and the 4th electric capacity；

First pole of the 20th two-transistor connects the section point, the second pole connection of the 20th two-transistor First pole of the 4th electric capacity, the grid of the 20th two-transistor connect first level terminal；

The first pole connection the 4th clock signal terminal of 23rd transistor, the second of the 23rd transistor Pole connects the 4th signal output part, and the grid of the 23rd transistor connects the first pole of the 4th electric capacity；

First pole of the 24th transistor connects the first pole of the 4th electric capacity, and the of the 24th transistor Two poles connect the 5th node, and the grid of the 24th transistor connects the 3rd node；

The first pole connection the 4th signal output part of 25th transistor, the second of the 25th transistor Pole connects the fourth node, and the grid of the 25th transistor connects the 3rd node；

Second pole of the 4th electric capacity connects the 4th signal output part.
9. shift register cell according to claim 1, it is characterised in that the output control module includes：Second 16 transistors；

The first pole connection the 4th signal output part of 26th transistor, the second of the 26th transistor Pole connects the second electrical level end, and the grid of the 26th transistor connects the first scanning signal end.
10. according to the shift register cell described in claim any one of 1-9, it is characterised in that first clock signal First clock signal at end, the second clock signal of the second clock signal end, the 3rd clock signal terminal the 3rd when 4th clock signal of clock signal and the 4th clock signal terminal differs 1/4 clock cycle successively, and it is described first when First clock signal of clock signal end, the second clock signal of the second clock signal end, the 3rd clock signal terminal The dutycycle of 3rd clock signal and the 4th clock signal of the 4th clock signal terminal is 25%.
11. according to the shift register cell described in claim any one of 2-9, it is characterised in that each transistor is N-type Transistor；Or each transistor is P-type transistor.
12. a kind of driving method of shift register cell, it is characterised in that for driving described in claim any one of 1-11 Shift register cell；Methods described includes：

First stage, the first control module input the first signal under the control of first scanning signal at the first scanning signal end The control source first node at end；Input module is defeated by the voltage of secondary signal input under the control of the voltage of first node Enter section point；Output control module is under the control of first scanning signal at the first scanning signal end by the electricity at second electrical level end It is pressed in signal output part output；

Second stage, the first control module input secondary signal under the control of second scanning signal at the second scanning signal end The control source first node at end；Input module is defeated by the voltage of secondary signal input under the control of the voltage of first node Enter section point；First output module is under the control of the voltage of section point by the first clock signal of the first clock signal terminal Exported in the first signal output part；

Phase III, the first control module input secondary signal under the control of second scanning signal at the second scanning signal end The control source first node at end；Input module is defeated by the voltage of secondary signal input under the control of the voltage of first node Enter section point；Second output module is under the control of the voltage of section point by the second clock signal of second clock signal end Exported in secondary signal output end；

Fourth stage, the first control module input secondary signal under the control of second scanning signal at the second scanning signal end The control source first node at end；Input module is defeated by the voltage of secondary signal input under the control of the voltage of first node Enter section point；3rd output module is under the control of the voltage of section point by the 3rd clock signal of the 3rd clock signal terminal Exported in the 3rd signal output part；

5th stage, the first control module input secondary signal under the control of second scanning signal at the second scanning signal end The control source first node at end；Input module is defeated by the voltage of secondary signal input under the control of the voltage of first node Enter section point；4th output module is under the control of the voltage of section point by the 4th clock signal of the 4th clock signal terminal Exported in the 4th signal output part；

In 6th stage, the second control module is under the control of the second scanning signal by the node of control source the 3rd of the first level terminal And by the control source first node, section point, fourth node at second electrical level end under the control of the voltage in the 3rd node And the 5th node；First output module, the second output module, the 3rd output module and the 4th output module are in the 3rd node Voltage control under respectively in the first signal output part, secondary signal output end, the 3rd signal output part and the 4th signal Output end exports the voltage of fourth node；

In 7th stage, control module is under the control of first node by the node of the control source of the first level terminal the 3rd and By the control source first node, section point, fourth node and the 5th at second electrical level end under the control of the voltage of three nodes Node.
13. a kind of gate driving circuit, it is characterised in that posted including the displacement described at least one any one of claim 1-11 Storage unit.
14. a kind of display device, it is characterised in that including the gate driving circuit described in claim 13.