CN108932933B

CN108932933B - Shift register, grid drive circuit and display device

Info

Publication number: CN108932933B
Application number: CN201710390668.5A
Authority: CN
Inventors: 古宏刚; 陈俊生; 邵贤杰; 宋洁; 姚利利
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2017-05-27
Filing date: 2017-05-27
Publication date: 2020-01-21
Anticipated expiration: 2037-05-27
Also published as: US10891913B2; US20200243034A1; CN108932933A; WO2018218886A1; EP3633664A4; EP3633664A1

Abstract

The invention provides a shift register, a gate drive circuit and a display device, belongs to the technical field of display, and can solve the problems that the conventional shift register is large in power consumption and the narrow frame design of the display device is not easy to realize. The shift register of the present invention includes: the shift register comprises a first shift register unit, a second shift register unit, a pull-down control module and a pull-down module; wherein, the first shift register unit includes: the device comprises a first input module, a first output module, a first reset module and a first noise reduction module; the second shift register unit includes: the device comprises a second input module, a second output module, a second reset module and a second noise reduction module.

Description

Shift register, grid drive circuit and display device

Technical Field

The invention belongs to the technical field of display, and particularly relates to a shift register, a grid drive circuit and a display device.

Background

With the continuous development of liquid crystal display, high resolution and narrow frame become the development trend of liquid crystal display, and the application of the gate shift register in the panel is one of the important methods for realizing narrow frame and high resolution.

The working principle of the liquid crystal display is as follows: a liquid crystal is a special substance between a solid and a liquid, which is an organic compound, normally in a liquid state, but its molecular arrangement is very regular as a solid crystal, and therefore, a liquid crystal is named, and another special property thereof is that if an electric field is applied to the liquid crystal, its molecular arrangement is changed, and at this time, if a polarizing plate is fitted thereto, it has a function of blocking light from passing therethrough (light can pass smoothly without applying an electric field), and if a color filter is fitted thereto, the magnitude of a voltage applied to the liquid crystal is changed, and the amount of light transmission of a certain color can be changed, and it can also be said that the transmittance thereof can be changed by changing the voltage applied across the liquid crystal (but in practice, this must be fitted to a polarizing plate).

The loss of power refers to the difference between the input power and the output power of the device, apparatus, etc. Loss of power. The circuit generally refers to the heat energy dissipated on the element and the device. Sometimes also the power of the power supply required by the complete machine or equipment. Power consumption is also an index of all electrical devices, and refers to the amount of energy consumed in a unit of time, which is expressed in W.

The driver of the TFT-LCD mainly includes a data driver and a gate driver, the gate driving circuit may be disposed in the display panel in a COF or COG packaging manner, or an integrated circuit unit formed in the display panel by TFTs, and the gate driving circuit generally is a shift register in which one electrode is butted with one gate line and signals are input through the gate driving circuit, thereby implementing the line-by-line scanning of pixels. Different from the conventional COF or COG design, the GOA design of the gate driver can lower the cost of the lcd panel, and simultaneously reduce one process to improve the yield. With the development of flat panel display, high resolution and narrow frame are becoming the trend of development, and the integration of gate driving circuits on a panel is the most important solution to realize high resolution and narrow frame display.

Disclosure of Invention

The present invention is directed to at least one of the technical problems in the prior art, and provides a shift register, a gate driving circuit, and a display device with low power consumption and simple structure.

The technical scheme adopted for solving the technical problem of the invention is a shift register, which comprises: the shift register comprises a first shift register unit, a second shift register unit, a pull-down control module and a pull-down module; wherein the first shift register unit includes: the device comprises a first input module, a first output module, a first reset module and a first noise reduction module; the second shift register unit includes: the second input module, the second output module, the second reset module and the second noise reduction module;

the first input module is used for pre-charging a first pull-up node under the control of a first input signal; the first pull-up node is a connecting node among the first input module, the first output module, the pull-down module, the first reset module and the first noise reduction module;

the first output module is used for outputting a first clock signal through a first signal output end under the control of the potential of the first pull-up node;

the first reset module is used for resetting the potentials of the first pull-up node and the first signal output end through a non-working level signal under the control of a first reset signal;

the second input module is used for pre-charging a second pull-up node under the control of a second input signal; the second pull-up node is a connecting node among the second input module, the second output module and the pull-down module;

the second output module is configured to output a second clock signal through a second signal output end under the control of the potential of the second pull-up node;

the second reset module is configured to reset the potentials of the second pull-up node and the second signal output terminal through the non-operating level signal under the control of a second reset signal;

the pull-down control module is used for controlling the potential of a pull-down node under the control of the first clock signal or the second clock signal; the pull-down node is a connection node among the pull-down control module, the pull-down module, the first noise reduction module and the second noise reduction module;

the pull-down module is configured to pull down the potential of the pull-down node through the non-operating level signal under control of the potential of the first pull-up node and the potential of the second pull-up node; the first noise reduction module is configured to reduce, under control of the pull-down node, output noise of the first pull-up node and the first signal output terminal through the non-operating level signal;

and the second noise reduction module is used for reducing the output noise of the second pull-up node and the second signal output end through the non-working level signal under the control of the pull-down node.

Preferably, the shift register further includes a storage module, and the storage module is configured to maintain the potential of the pull-down node.

Preferably, the first input block includes a first transistor; wherein,

and the first pole and the control pole of the first transistor are both connected with a first input signal end, and the second pole of the first transistor is connected with the first pull-up node.

Preferably, the first output module includes a third transistor and a first storage capacitor; wherein,

a first pole of the third transistor is connected with a first clock signal end, a second pole of the third transistor is connected with a first signal output end, and a control pole of the third transistor is connected with the first pull-up node;

the first end of the first storage capacitor is connected with the first pull-up node, and the second end of the first storage capacitor is connected with the first signal output end.

Preferably, the first reset module includes: a second transistor and a thirteenth transistor; wherein,

a first pole of the second transistor is connected with the first pull-up node, a second pole of the second transistor is connected with a non-working level signal end, and a control pole of the second transistor is connected with a first reset signal end;

and a first pole of the thirteenth transistor is connected with the first signal output end, a second pole of the thirteenth transistor is connected with a non-working level signal end, and a control pole of the thirteenth transistor is connected with a second clock signal end.

and a first pole of the thirteenth transistor is connected with the first signal output end, a second pole of the thirteenth transistor is connected with a non-working level signal end, and a control pole of the thirteenth transistor is connected with a first reset signal end.

Preferably, the first noise reduction module includes a fourth transistor and a fifteenth transistor; wherein,

a first pole of the fourth transistor is connected with the first signal output end, a second pole of the fourth transistor is connected with a non-working level signal end, and a control pole of the fourth transistor is connected with the pull-down node;

and a first pole of the fifteenth transistor is connected with the first pull-up node, a second pole of the fifteenth transistor is connected with a non-working level signal end, and a control pole of the fifteenth transistor is connected with the pull-down node.

Preferably, the second input block includes a fifth transistor; wherein,

and a first pole and a control pole of the fifth transistor are both connected with a second input signal end, and a second pole is connected with the second pull-up node.

Preferably, the second output module includes a seventh transistor and a second storage capacitor; wherein,

a first pole of the seventh transistor is connected with a second clock signal end, a second pole of the seventh transistor is connected with the second signal output end, and a control pole of the seventh transistor is connected with the second pull-up node;

and the first end of the second storage capacitor is connected with the second pull-up node, and the second end of the second storage capacitor is connected with the second signal output end.

Preferably, the second reset module includes a sixth transistor and a fourteenth transistor; wherein,

a first pole of the sixth transistor is connected with the second pull-up node, a second pole of the sixth transistor is connected with a non-working level signal end, and a control pole of the sixth transistor is connected with a second reset signal end;

and a first pole of the fourteenth transistor is connected with the second signal output end, a second pole of the fourteenth transistor is connected with a non-working level signal end, and a control pole of the fourteenth transistor is connected with the first clock signal end.

and a first pole of the fourteenth transistor is connected with the second signal output end, a second pole of the fourteenth transistor is connected with a non-working level signal end, and a control pole of the fourteenth transistor is connected with a second reset signal end.

Preferably, the second noise reduction module includes an eighth transistor and a sixteenth transistor; wherein,

a first pole of the eighth transistor is connected with the second signal output end, a second pole of the eighth transistor is connected with a non-working level signal end, and a control pole of the eighth transistor is connected with the pull-down node;

and the sixteenth transistor is connected with the second pull-up node in a first connection mode, a second pole of the sixteenth transistor is connected with a non-working level signal end, and a control pole of the sixteenth transistor is connected with the pull-down node.

Preferably, the pull-down module comprises a ninth transistor, a tenth transistor, and a twelfth transistor; wherein,

a first electrode and a control electrode of the ninth transistor are both connected with the first pull-up node, and a second electrode of the ninth transistor is connected with a control electrode of the twelfth transistor;

a first electrode and a control electrode of the tenth transistor are both connected with the second pull-up node, and a second electrode of the tenth transistor is connected with a control electrode of the twelfth transistor;

a first pole of the twelfth transistor is connected to the pull-down node, a second pole of the twelfth transistor is connected to the non-operating level signal terminal, and a control pole of the twelfth transistor is connected to the second pole of the ninth transistor and the second pole of the tenth transistor.

Preferably, the pull-down control module includes an eleventh transistor; wherein,

and a first pole and a control pole of the eleventh transistor are both connected with a second clock signal end, and a second pole is connected with the pull-down node.

and a first pole and a control pole of the eleventh transistor are both connected with a first clock signal end, and a second pole of the eleventh transistor is connected with the pull-down node.

Preferably, the storage module comprises a third storage capacitor; wherein,

and the first end of the third storage capacitor is connected with the pull-down node, and the second end of the third storage capacitor is connected with a non-working level signal end.

The technical scheme adopted for solving the technical problem of the invention is a gate drive circuit which comprises the shift register.

Preferably, a first input signal terminal of a first shift register unit in each stage of the shift register is connected to a second signal output terminal of a second shift register unit in the previous stage of the shift register;

the first reset signal end of the first shift register unit in each stage of the shift register is connected, and the second signal output end of the second shift register unit in the shift register of the stage is connected with the first reset signal end of the second shift register unit;

the first signal output end of a first shift register unit in each stage of the shift register is connected with the second signal input end of a second shift register unit in the shift register of the stage;

the second signal output end of the second shift register unit in each stage of the shift register is connected with the first signal input end of the first shift register unit in the next stage of the shift register;

and the second reset signal end of the second shift register unit in the shift register of each stage is connected with the first signal output end of the first shift register unit in the shift register of the next stage.

The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the grid drive circuit.

The invention has the following beneficial effects:

the shift register comprises two shift register units which provide signals for grid lines of different rows, namely a first shift register unit and a second shift register unit, the two shift register units share one pull-down module and one pull-down control module, namely the first shift register unit and the second shift register unit are connected with the same pull-down node, and a storage module is added to maintain the potential of the pull-down node, so that after the two shift register units are reset, the pull-down node continuously discharges for the pull-up node and two signal output ends, the problem of noise and voltage caused by clock signals is solved, and the yield is improved. Meanwhile, two shift register units share one pull-down node, so that compared with the conventional shift register, the number of transistors is reduced, and the power consumption is effectively reduced.

Drawings

Fig. 1 to 3 are schematic diagrams of shift registers of embodiments 1 and 2 of the present invention;

FIG. 4 is a timing chart of operation corresponding to the shift register of FIG. 1 in embodiment 2 of the present invention;

FIG. 5 is a timing chart of operation corresponding to the shift register of FIG. 3 in embodiment 2 of the present invention;

fig. 6 is a cascade connection schematic diagram of a gate driving circuit according to embodiment 3 of the present invention.

Wherein the reference numerals are: 11. a first input unit; 12. a first output unit; 131. a first pull-up node reset unit; 132. the first signal output end resets the module; 14. a first noise reduction module; 21. a second input unit; 22. a second output unit; 231. a second pull-up node reset unit; 232. a second signal output end resetting module; 24. a second noise reduction module; 20. a pull-down control module; 30. a pull-down module; 40. and a storage module.

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

The transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics, and since the source and the drain of the transistors used may be interchanged under certain conditions, the source and the drain are not different from the description of the connection relationship. In the embodiment of the present invention, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. Further, the transistors can be classified into N-type and P-type according to their characteristics, and the following embodiments will be described with reference to the transistors as N-type transistors. When an N-type transistor is adopted, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, when the grid electrode inputs a high level, the source electrode and the drain electrode are conducted, and the P type is opposite. It is contemplated that implementing a transistor as a P-type transistor will be readily apparent to one skilled in the art without inventive effort and is therefore within the scope of the embodiments of the present invention.

Since the thin film transistor is described as an N-type transistor in this embodiment, the below-described non-operating level signal is a low level signal, and the non-operating level signal terminal is a low level signal terminal. It should be understood that if the thin film transistor is a P-type transistor, the non-operating level signal is a high level signal, and the non-operating level signal terminal is a high level signal terminal.

Example 1:

as shown in fig. 1 to 3, the present embodiment provides a shift register, including: a first shift register unit, a second shift register unit, a pull-down control module 20, and a pull-down module 30; wherein, the first shift register unit includes: the device comprises a first input module 11, a first output module 12, a first reset module and a first noise reduction module 14; the second shift register unit includes: a second input module 21, a second output module 22, a second reset module, and a second noise reduction module 24.

Specifically, the first input module 11 is configured to precharge a first pull-up node pu (n) under the control of a first input signal; the first pull-up node pu (n) is a connection node between the first input module 11, the first output module 12, the pull-down module 30, the first reset module, and the first noise reduction module 14; the first output module 12 is configured to output a first clock signal through a first signal output terminal output (n) under the control of the potential of the first pull-up node pu (n); the first reset module is used for resetting the potentials of the first pull-up node pu (n) and the first signal output end (n) through a low-level signal under the control of a first reset signal; the second input module 21 is configured to precharge the second pull-up node PU (N +1) under the control of the second input signal; the second pull-up node PU (N +1) is a connection node between the second input module 21, the second output module 22, and the pull-down module 30; the second Output module 22 is configured to Output a second clock signal through a second signal Output end Output (N +1) under the control of the potential of the second pull-up node PU (N + 1); the second reset module is used for resetting the potentials of the second pull-up node PU (N +1) and the second signal Output end Output (N +1) through a low-level signal under the control of a second reset signal; the pull-down control module 20 is configured to control a potential of the pull-down node PD under the control of the first clock signal or the second clock signal; the pull-down module 30 is configured to pull down the potential of the pull-down node PD by a low level signal under the control of the potential of the first pull-up node PU (N) and the potential of the second pull-up node PU (N + 1); the pull-down node PD is a connection node between the pull-down module 30, the pull-down control module 20, the first reset noise reduction module, and the second reset noise reduction module; the first noise reduction module 14 is configured to reduce, under the control of the pull-down node PD, output noise of the first pull-up node pu (n) and the first signal output terminal output (n) through a low level signal; the second noise reduction module 24 is configured to reduce Output noise of the second pull-up node PU (N +1) and the second signal Output terminal Output (N +1) through a low level signal under the control of the pull-down node PD.

Since the shift register in this embodiment includes two shift register units, i.e., a first shift register unit and a second shift register unit, which provide signals for different rows of gate lines, and the two shift register units share one pull-down module 30 and one pull-down control module 20, that is, the first shift register unit and the second shift register unit are connected to the same pull-down node PD, i.e., share one pull-down node PD, compared with the existing shift register, the number of transistors is reduced, thereby effectively reducing power consumption. Preferably, a storage module can be additionally arranged for maintaining the potential of the pull-down node, so that the pull-down node PD continuously discharges to the pull-up node and the two signal output ends after the two shift register units are reset, the problem of noise and voltage caused by clock signals is solved, and the yield is improved.

Example 2:

as shown in fig. 1 to 3, the present embodiment provides a shift register, including: the shift register comprises a first shift register unit, a second shift register unit, a pull-down control module 20, a pull-down module 30 and a storage capacitor; wherein, the first shift register unit includes: the device comprises a first input module 11, a first output module 12, a first reset module and a first noise reduction module 14; the second shift register unit includes: a second input module 21, a second output module 22, a second reset module, and a second noise reduction module 24.

The structure of the first shift register unit is specifically described as follows:

the first input module 11 is connected to the first input signal terminal input (n) and the first pull-up node pu (n), and is configured to pre-charge the first pull-up node pu (n) according to a first input signal input by the first input signal terminal input (n).

In particular, the first input module 11 preferably comprises a first transistor M1; the first pole and the control pole of the first transistor M1 are both connected to the first input signal terminal input (n), and the second pole is connected to the first pull-up node pu (n).

In the precharge stage of the first shift register unit, when the first input signal inputted from the first input signal terminal input (n) is at a high level, the first transistor M1 is turned on, and the high level signal can be precharged to the first pull-up node pu (n) through the first transistor M1.

The first output module 12 is connected to the first clock signal terminal CLK, the first pull-up node pu (n), and the first signal output terminal output (n), and configured to output the first clock signal input by the first clock signal terminal CLK through the first signal output terminal output (n) under the control of the potential of the first pull-up node pu (n).

Specifically, the first output module 12 preferably includes a third transistor M3 and a first storage capacitor C1; a first pole of the third transistor M3 is connected to the first clock signal terminal CLK, a second pole is connected to the first signal output terminal output (n), and a control pole is connected to the first pull-up node pu (n); a first end of the first storage capacitor C1 is connected to the first pull-up node pu (n), and a second end is connected to the first signal output terminal output (n).

In the output stage of the first shift register unit, since the first pull-up node pu (n) is pulled up to the high level in the precharge stage, the third transistor M3 is turned on; the first clock signal inputted by the first clock signal terminal CLK is a high level signal, so that the first signal output terminal output (n) outputs a high-level signal; meanwhile, the potential of the first pull-up node pu (n) further rises due to the bootstrap effect of the first storage capacitor C1.

The first pull-up node reset unit 131 in the first reset module is connected to the first reset signal terminal reset (n), the first pull-up node pu (n), and the low-level signal terminal VGL, and configured to pull down the potential of the first pull-up node by the low-level signal input by the low-level signal terminal VGL under the control of the first reset signal input by the first reset signal terminal reset (n), so as to complete the reset of the first pull-up node pu (n); the first signal output terminal output (n) in the first reset module is connected to the second clock signal terminal CLKB, the first signal output terminal output (n), and the low level signal terminal VGL, and is configured to pull down the potential of the first signal output terminal output (n) through a low level signal input by the low level signal terminal VGL under the control of the second clock signal input by the second clock signal terminal CLKB, so as to complete the reset of the first signal output terminal output (n).

Specifically, the first pull-up node pu (n) reset unit 131 preferably includes a second transistor M2; a first pole of the second transistor M2 is connected to the first pull-up node pu (n), a second pole is connected to the low level signal terminal VGL, and a control pole is connected to the first reset signal terminal reset (n); the first signal output terminal output (n) reset unit 132 preferably includes a thirteenth transistor M13; a first pole of the thirteenth transistor M13 is connected to the first signal output terminal output (n), a second pole is connected to the low level signal terminal VGL, and a control pole is connected to the second clock signal terminal CLKB.

In the reset stage of the first shift register unit, the first reset signal input by the first reset signal terminal reset (n) is a high level signal, the second transistor M2 is turned on, and the potential of the first pull-up node pu (n) is pulled down by the low level signal input by the low level signal terminal VGL to complete the reset of the first pull-up node pu (n); meanwhile, the second clock signal input by the second clock signal terminal CLKB is a high level signal, the thirteenth transistor M13 is turned on, and the potential of the first signal output terminal output (n) is pulled down by the low level signal input by the low level signal terminal VGL, so as to complete the reset of the first signal output terminal output (n).

Of course, the first signal output terminal output (n) of the first reset module and the reset unit 132 may be connected to the first reset signal terminal reset (n), the first signal output terminal output (n) and the low level signal terminal VGL without connecting the second clock signal terminal CLKB. At this time, the first electrode of the thirteenth transistor M13 included in the first signal output terminal output (n) reset unit 132 is connected to the first signal output terminal output (n), the second electrode is connected to the low-level signal terminal VGL, and the control electrode is connected to the first reset signal terminal reset (n). In the reset stage of the first shift register unit, the first reset signal input by the first reset signal terminal reset (n) is a high level signal, the second transistor M2 and the thirteenth transistor M13 are both turned on, and the potentials of the first pull-up node pu (n) and the first signal output terminal output (n) are pulled down by the low level signal input by the low level signal terminal VGL, so as to complete the reset of the first pull-up node pu (n) and the first signal output terminal output (n).

The first noise reduction module 14 is connected to the first pull-up node pu (n), the first signal output terminal output (n), the pull-down node PD, and the low level signal terminal VGL, and configured to reduce output noise of the first pull-up node pu (n) and the first signal output terminal output (n) through a low level signal input by the low level signal terminal VGL under control of a potential of the pull-down node PD.

Specifically, the first noise reduction module 14 includes a fourth transistor M4 and a fifteenth transistor M15; a first pole of the fourth transistor M4 is connected to the first signal output terminal (n), a second pole is connected to the low-level signal terminal VGL, and a control pole is connected to the pull-down node PD; a first pole of the fifteenth transistor M15 is connected to the first pull-up node pu (n), a second pole is connected to the low-level signal terminal VGL, and a control pole is connected to the pull-down node PD.

In the noise reduction stage of the first shift register unit, the pull-down node PD is pulled up to a high level, and the memory module 40 is charged, at this time, the fifteenth transistor M15 is turned on to reduce the output noise of the first pull-up node pu (n); the fourth transistor M4 is turned on to reduce noise at the first signal output terminal output (n).

The structure of the second shift register unit is specifically described as follows:

the second Input module 21 is connected to the second Input signal terminal Input (N +1) and the second pull-up node PU (N +1), and configured to pre-charge the second pull-up node PU (N +1) through a second Input signal Input by the second Input signal terminal Input (N + 1).

In particular, the second input module 21 preferably includes a fifth transistor M5; the first pole and the control pole of the fifth transistor M5 are both connected to the second Input signal terminal Input (N +1), and the second pole is connected to the second pull-up node PU (N + 1).

In the precharge stage of the second shift register unit, the second Input signal terminal Input (N +1) is inputted with a high level signal, and the second pull-up node PU (N +1) is precharged by the high level signal.

The second Output module 22 is connected to the second clock signal terminal CLKB, the second pull-up node PU (N +1), and the second signal Output terminal Output (N + 1); and the Output circuit is used for controlling a second clock signal input by a second clock signal terminal CLKB to be Output through a second signal Output terminal Output (N +1) under the control of the potential of the second pull-up node PU (N + 1).

Specifically, the second output module 22 preferably includes a seventh transistor M7 and a second storage capacitor C2; a first pole of the seventh transistor M7 is connected to the second clock signal terminal CLKB, a second pole is connected to the second signal Output terminal Output (N +1), and a control pole is connected to the second pull-up node PU (N + 1); a first end of the second storage capacitor C2 is connected to the second pull-up node PU (N +1), and a second end thereof is connected to the second signal Output terminal Output (N + 1).

In the output stage of the second shift register unit, since the second pull-up node PU (N +1) is pulled up to the high level in the precharge stage, the fifth transistor M5 is turned on; the first clock signal input by the second clock signal terminal CLKB is a high level signal, so the second signal Output terminal Output (N +1) outputs a high-level signal; meanwhile, the potential of the second pull-up node PU (N +1) further rises due to the bootstrap effect of the second storage capacitor C2.

The second pull-up node RESET unit 231 in the second RESET module is connected to the second RESET signal terminal RESET (N +1), the second pull-up node PU (N +1), and the low level signal terminal VGL, and is configured to pull down the potential of the second pull-up node PU (N +1) through the low level signal input by the low level signal terminal VGL under the control of the second RESET signal input by the second RESET signal terminal RESET (N +1), so as to complete the RESET of the second pull-up node PU (N + 1); the second signal Output end Output (N +1) reset unit 232 in the second reset module is connected to the first clock signal end CLK, the low level signal end VGL, and the second signal Output end Output (N +1), and configured to pull down the potential of the second signal Output end Output (N +1) through the low level signal input by the low level signal end VGL under the control of the first clock signal input by the first clock signal end CLK, so as to complete the reset of the second signal Output end Output (N + 1).

Specifically, the second pull-up node PU (N +1) reset unit 231 preferably includes a sixth transistor M6; the second signal Output terminal Output (N +1) reset unit 232 preferably includes a fourteenth transistor M14; a first pole of the sixth transistor M6 is connected to the second pull-up node PU (N +1), a second pole is connected to the low-level signal terminal VGL, and a control pole is connected to the second RESET signal terminal RESET (N + 1); a first pole of the fourteenth transistor M14 is connected to the second signal Output terminal Output (N +1), a second pole thereof is connected to the low level signal terminal VGL, and a control pole thereof is connected to the first clock signal terminal CLK.

In the RESET stage of the second shift register unit, the RESET signal input to the second RESET signal terminal RESET (N +1) is a high level signal, the sixth transistor M6, and the second pull-up node PU (N +1) is pulled down to a low level, that is, the RESET of the second pull-up node PU (N +1) is completed; the signal written into the first clock signal terminal CLK is a high level signal, the fourteenth transistor M14 is turned on, and the second signal Output terminal Output (N +1) is pulled down to a low level, that is, the reset of the second signal Output terminal Output (N +1) is completed.

Of course, the second signal Output end Output (N +1) RESET unit 232 in the second RESET module may not be connected to the first clock signal end CLK, but may be connected to the second RESET signal end RESET (N +1), the second signal Output end Output (N +1), and the low level signal end VGL. At this time, a first pole of the fourteenth transistor M14 included in the second signal Output terminal Output (N +1) RESET unit 232 is connected to the second signal Output terminal Output (N +1), a second pole thereof is connected to the low-level signal terminal VGL, and a control pole thereof is connected to the second RESET signal terminal RESET (N + 1). In a RESET stage of the second shift register unit, the second RESET signal input by the second RESET signal terminal RESET (N +1) is a high level signal, the sixth transistor M6 and the fourteenth transistor M14 are both turned on, and the low level signal input by the low level signal terminal VGL pulls down potentials of the second pull-up node PU (N +1) and the second signal Output terminal Output (N +1), so as to complete resetting of the second pull-up node PU (N +1) and the second signal Output terminal Output (N + 1).

The second noise reduction module 24 is connected to the second pull-up node PU (N +1), the second signal Output terminal Output (N +1), the pull-down node PD, and the low level signal terminal VGL, and configured to reduce Output noise of the second pull-up node PU (N +1) and the second signal Output terminal Output (N +1) through a low level signal input by the low level signal terminal VGL under control of a potential of the pull-down node PD.

Specifically, the second noise reduction module 24 includes an eighth transistor M8 and a sixteenth transistor M16; a first pole of the eighth transistor M8 is connected to the second signal Output terminal Output (N +1), a second pole is connected to the low-level signal terminal VGL, and a control pole is connected to the pull-down node PD; a first pole of the sixteenth transistor M16 is connected to the second pull-up node PU (N +1), a second pole thereof is connected to the low level signal terminal VGL, and a control pole thereof is connected to the pull-down node PD.

In the noise reduction stage of the second shift register unit, the pull-down node PD is pulled up to a high level, and the memory module 40 is charged, at this time, the sixteenth transistor M16 is turned on to reduce the output noise of the second pull-up node PU (N + 1); the eighth transistor M8 is turned on to reduce noise of the second signal Output terminal Output (N + 1).

The above is an introduction to the first shift register unit and the second shift register unit in the shift register in the present embodiment; next, specific structures of the memory module 40, the pull-down module 30, and the pull-down control module 20 in the present embodiment will be described:

the memory module 40 in the shift register of the present embodiment includes a third storage capacitor C3; a first end of the third storage capacitor C3 is connected to the pull-down node PD, and a second end is connected to the low-level signal terminal VGL; the third storage capacitor C3 is used to maintain the potential of the pull-down node PD.

The pull-down control module 20 is connected to the second clock signal input end and the pull-down node PD, and configured to charge the pull-down node PD under control of a second clock signal input by the second clock signal input end, that is, charge the third storage capacitor C3, so that after the first shift register unit and the second shift register unit are both completed, the third storage capacitor C3 maintains the pull-down node PD at a high potential, so that the first noise reduction module 14 and the second noise reduction module 24 can continuously reduce noise of signals Output by the first pull-up node PU (N), the second pull-up node PU (N +1), the first signal Output end Output (Output) (N), and the second signal Output end Output (Output + 1).

Specifically, the pull-down control module 20 preferably includes an eleventh transistor M11; a first pole and a control pole of the eleventh transistor M11 are both connected to the second clock signal terminal CLKB, and a second pole is connected to the pull-down node PD.

In the noise reduction stage of the first shift register unit and the second shift register unit, the second clock signal written in the second clock signal terminal CLKB is a high level signal, the eleventh transistor M11 is turned on, the pull-down node PD is pulled up to a high level, and the storage capacitor C3 is charged.

Certainly, the pull-down control module 20 may also be connected to the first clock signal input end and the pull-down node PD, and is configured to charge the pull-down node PD under the control of the first clock signal input by the first clock signal input end, that is, charge the third storage capacitor C3, so that the third storage capacitor C3 maintains the pull-down node PD at a high potential after the first shift register unit and the second shift register unit are both completed, so that the first noise reduction module 14 and the second noise reduction module 24 can continuously reduce noise of signals Output by the first pull-up node PU (N), (N +1), the second pull-up node PU (N +1), the first signal Output end Output (Output) (N), and the second signal Output end Output (N + 1).

Specifically, the pull-down control module 20 preferably includes an eleventh transistor M11; a first electrode and a control electrode of the eleventh transistor M11 are both connected to the first clock signal terminal CLK, and a second electrode is connected to the pull-down node PD.

In the noise reduction stage of the first and second shift register units, the first clock signal written to the first clock signal terminal CLK is a high level signal, the eleventh transistor M11 is turned on, and the pull-down node PD is pulled up to a high level while charging the storage capacitor C3.

The pull-down module 30 is connected to the first pull-up node PU (N), the second pull-up node PU (N +1), the low level signal terminal VGL, and the pull-down node PD; and is used for pulling down the potential of the pull-down node PD by a low level signal input from the low level signal terminal VGL under the control of the potentials of the first pull-up node PU (N) and the second pull-up node PU (N + 1).

Specifically, the pull-down module 30 preferably includes a ninth transistor M9, a tenth transistor M10, a twelfth transistor M12; a first pole and a control pole of the ninth transistor M9 are both connected to the first pull-up node pu (n), and a second pole is connected to the control pole of the twelfth transistor M12; the first pole and the control pole of the tenth transistor M10 are both connected to the second pull-up node PU (N +1), and the second pole is connected to the control pole of the twelfth transistor M12; the twelfth transistor M12 has a first electrode connected to the pull-down node PD, a second electrode connected to the low-level signal terminal VGL, and a control electrode connected to the second electrode of the ninth transistor M9 and the second electrode of the tenth transistor M10.

Since the ninth transistor M9 and the tenth transistor M10 are turned on and off by the potentials of the first pull-up node PU (N) and the second pull-up node PU (N +1), respectively, and the twelfth transistor M12 is controlled by the potential of the first pull-up node PU (N) output by the ninth transistor M9 and the potential of the second pull-up node PU (N +1) output by the tenth transistor M10, the twelfth transistor M12 is turned on as long as the potential of one of the first pull-up node PU (N) and the second pull-up node PU (N +1) is a high level signal, and the potential of the pull-down node PD is pulled down by a low level signal input by the low level signal terminal VGL.

The operation principle of the shift register in the present embodiment will be described below with reference to fig. 1 and 4.

First stage (precharge stage of first shift register unit): the first input signal written into the first input signal terminal input (n) is a high level signal, the first transistor M1 is turned on, and the first input signal charges the first storage capacitor C1 through the first transistor M1, so that the potential of the first pull-up node pu (n) is pulled high; since the first pull-up node pu (n) is at a high level at this time, the ninth transistor M9 and the twelfth transistor M12 are turned on, the storage capacitor C3 is discharged, and the potential of the pull-down node PD is pulled down to a low level; at this time, the potential of the pull-down node PD is at a low level, so the fourth transistor M4 and the fifteenth transistor M15 are turned off, and at the same time, the first clock signal is at a low level, thereby ensuring that the first signal output terminal output (n) outputs a stable low-level signal.

Second stage (output stage of the first shift register unit, and precharge stage of the second shift register unit): the first input signal written into the first input signal terminal input (n) is a low level signal, the first transistor M1 is turned off, the first pull-up node pu (n) continues to keep high level, the third transistor M3 keeps on state, at this time, the first clock signal inputted into the first clock signal terminal CLK is a high level signal, and the first pull-up node pu (n) further pulls up the potential of the first pull-up node pu (n) due to bootstrap of the first storage capacitor C1, so that the first signal output terminal output (n) outputs a high level signal; since the first pull-up node pu (n) is at a high level, the ninth transistor M9 and the twelfth transistor M12 are in an on state, so the pull-down node PD is a low level signal, the fourth transistor M4 and the fifteenth transistor M15 continue to be turned off, the second clock signal written into the second clock signal terminal CLKB is a low level signal, and the thirteenth transistor M13 is in an off state, so as to ensure the stability of the output signal of the first signal output terminal output (n).

Preferably, the high level signal Output by the first signal Output terminal Output (N) in the first shift register unit can be used as the second Input signal written by the second Input signal terminal Input (N +1) in the second shift register unit in the shift register of this stage, at this time, the fifth transistor M5 is turned on, the second pull-up node PU (N +1) is pulled up, and the second storage capacitor C2 is charged, and since the second clock signal written by the second clock signal terminal CLKB is a low level signal at this time, the low level signal Output by the second signal Output terminal Output (N +1) is Output. Meanwhile, the second pull-up node PU (N +1) is pulled high, so that the tenth transistor M10 and the twelfth transistor M12 are turned on, the pull-down node PD is at a low level, and the eighth transistor M8 and the sixteenth transistor M16 are turned off, thereby ensuring that the second signal Output terminal Output (N +1) outputs a stable low level signal.

Third stage (reset stage of the first shift register unit, and output stage of the second shift register unit): the first reset signal terminal reset (n) is written with the reset signal at a high level, the second clock signal terminal CLKB is written with the second clock signal at a high level, at this time, the second transistor M2 and the fifteenth transistor M15 are turned on, and the first pull-up node pu (n) is pulled down to a low level, that is, the reset of the first pull-down node PD is completed; the thirteenth transistor M13 is turned on, and the first signal output terminal output (n) is pulled down to a low level, at which time the reset of the first signal output terminal output (n) is completed.

Meanwhile, since the signal Output by the first signal Output terminal Output (N) in the first shift register unit is Input to the second Input signal terminal Input (N +1) in the second shift register unit, the fifth transistor M5 is turned off, the second storage capacitor C2 is discharged, the potential of the second pull-up node PU (N +1) is amplified due to the bootstrap effect of the second storage capacitor C2, the second clock signal is at a high level, and the seventh transistor M7 is turned on, so the second signal Output terminal Output (N +1) outputs a high level signal. It should be noted here that since the second pull-up node PU (N +1) is at a high level and the tenth transistor M10 and the twelfth transistor M12 are turned on at this time, the pull-down node PD is pulled low, and although the second clock signal is at a high level and the eleventh transistor M11 is turned on, the pull-down node PD is not pulled high. This is so because the width-to-length ratio of the eleventh transistor M11 is selected to be smaller than that of the tenth transistor M10 and the twelfth transistor M12.

It should be noted that, since the input signal of the first reset signal terminal reset (N) is a high level signal at this stage, and the signal Output by the second signal Output terminal Output (N +1) is just a high level signal at this stage, the reset signal can be provided to the first reset signal terminal reset (N) from the second signal Output terminal Output (N + 1).

Fourth stage (reset stage of second shift register unit): the RESET signal written into the second RESET signal terminal RESET (N +1) is a high level signal, the sixth transistor M6, and the second pull-up node PU (N +1) is pulled down to a low level, that is, the RESET of the second pull-up node PU (N +1) is completed; the first clock signal written into the first clock signal terminal CLK is also a high level signal, the fourteenth transistor M14 is turned on, and the second signal Output terminal Output (N +1) is pulled down to a low level, that is, the reset of the second signal Output terminal Output (N +1) is completed.

Fifth stage (noise reduction stage of first shift register unit and second shift register unit): the second clock signal written in the second clock signal terminal CLKB is a high level signal, the eleventh transistor M11 is turned on, the pull-down node PD is pulled up to a high level, and the third storage capacitor C3 is charged at the same time, at this time, the fifteenth transistor M15 is turned on to reduce the output noise of the first pull-up node pu (n); the fourth transistor M4 is turned on to reduce noise at the first signal output terminal output (n); the sixth transistor M6 is turned on to reduce the output noise of the second pull-up node PU (N + 1); the eighth transistor M8 is turned on to reduce noise of the second signal Output terminal Output (N + 1); of course, the thirteenth transistor M13 is controlled by the second clock signal and is also turned on to stably reduce the noise at the first signal output terminal output (n). After that, although the second clock signal changes to the low level at certain time intervals, the third storage capacitor C3 can maintain the high level of the pull-down node PD, so as to continue to perform pull-down noise reduction on the first pull-up node PU (N), the second pull-up node PU (N +1), the first signal Output terminal Output (N), and the second signal Output terminal Output (N + 1). When the second clock signal is at a low level, the first clock signal written into the first clock signal terminal CLK is at a high level, and the fourteenth transistor M14 is turned on to stably reduce noise at the second signal Output terminal Output (N + 1).

And after that, repeating the step five until the next frame arrives.

It should be noted here that, when the first pole and the control pole of the eleventh transistor M11 of the pull-down control module 20 in the employed shift register unit are both connected to the first clock signal terminal CLK, and the second pole is connected to the pull-down node PD, the driving method of the shift register is similar to the above method, and the difference is only that the fourth stage (the reset stage of the second shift register unit) and the fifth stage (the noise reduction stage of the first shift register unit and the second shift register unit), as shown in fig. 3 and 5, the fourth stage and the fifth stage specifically include:

fourth stage (reset stage of second shift register unit): the RESET signal written into the second RESET signal terminal RESET (N +1) is a high level signal, the sixth transistor M6, and the second pull-up node PU (N +1) is pulled down to a low level, that is, the RESET of the second pull-up node PU (N +1) is completed; the first clock signal written into the first clock signal terminal CLK is also a high level signal, the fourteenth transistor M14 is turned on, and the second signal Output terminal Output (N +1) is pulled down to a low level, that is, the reset of the second signal Output terminal Output (N +1) is completed. Meanwhile, since the first clock signal written to the first clock signal terminal CLK is a high signal, the eleventh transistor M11 is also turned on, and the pull-down node PD is pulled up to a high level to charge the third storage capacitor C3.

Fifth stage (noise reduction stage of first shift register unit and second shift register unit): since the third storage capacitor C3 is charged in the fourth stage, the high voltage of the pull-down node PD can be maintained through the third storage capacitor C3, and the fifteenth transistor M15 is turned on to reduce the output noise of the first pull-up node pu (n); the fourth transistor M4 is turned on to reduce noise at the first signal output terminal output (n); the sixth transistor M6 is turned on to reduce the output noise of the second pull-up node PU (N + 1); the eighth transistor M8 is turned on to reduce noise of the second signal Output terminal Output (N + 1); of course, the thirteenth transistor M13 is controlled by the second clock signal, and is also turned on at this time, so as to stably reduce the noise at the first signal output terminal output (n). After that, although the first clock signal changes to the low level at certain time intervals, the third storage capacitor C3 may maintain the high level of the pull-down node PD, so as to continue to perform pull-down noise reduction on the first pull-up node PU (N), the second pull-up node PU (N +1), the first signal Output terminal Output (N), and the second signal Output terminal Output (N + 1). When the first clock signal is at a low level, the first clock signal written into the first clock signal terminal CLK is at a high level, and the fourteenth transistor M14 is turned on to stably reduce noise at the second signal Output terminal Output (N + 1).

Example 3:

as shown in fig. 6, the present embodiment provides a gate driving circuit, which includes the shift registers of embodiments 1 or 2, wherein the first input signal terminal input (N) of the first shift register unit in each stage of the shift register is connected, and the second signal Output terminal Output (N +1) of the second shift register unit in the previous stage of the shift register is connected; a first reset signal end RESET (N) of a first shift register unit in each stage of shift register is connected, and a second signal Output end Output (N +1) of a second shift register unit in the shift register of the stage is connected; the first signal output end output (N) of the first shift register unit in each stage of shift register is connected, and the second signal Input end (N +1) of the second shift register unit in the shift register of the current stage is connected; the second signal Output end Output (N +1) of the second shift register unit in each stage of shift register is connected with the first signal input end of the first shift register unit in the next stage of shift register; and a second RESET signal end RESET (N +1) of a second shift register unit in each stage of shift register is connected with a first signal output end of a first shift register unit in the next stage of shift register.

Since the gate driver circuit in this embodiment includes the shift register described in embodiment 1 or 2, power consumption is small and cost is low.

Correspondingly, the embodiment also discloses a display device which comprises the gate driving circuit. The gate driving circuit can realize narrow-edge design due to the inclusion of the gate driving circuit.

The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Of course, other conventional structures, such as a power supply unit, a display driving unit, and the like, may also be included in the display device of the present embodiment.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A shift register, comprising: the shift register comprises a first shift register unit, a second shift register unit, a pull-down control module and a pull-down module; wherein the first shift register unit includes: the device comprises a first input module, a first output module, a first reset module and a first noise reduction module; the second shift register unit includes: the second input module, the second output module, the second reset module and the second noise reduction module;

the second noise reduction module is configured to reduce, under control of the pull-down node, output noise of the second pull-up node and the second signal output terminal through the non-operating level signal;

the pull-down module comprises a ninth transistor, a tenth transistor and a twelfth transistor; wherein,

2. The shift register of claim 1, further comprising a storage module for maintaining the potential of the pull-down node.

3. The shift register of claim 1, wherein the first input block comprises a first transistor; wherein,

4. The shift register according to claim 1, wherein the first output module includes a third transistor and a first storage capacitor; wherein,

5. The shift register of claim 1, wherein the first reset module comprises: a second transistor and a thirteenth transistor; wherein,

6. The shift register of claim 1, wherein the first reset module comprises: a second transistor and a thirteenth transistor; wherein,

7. The shift register of claim 1, wherein the first noise reduction module comprises a fourth transistor and a fifteenth transistor; wherein,

8. The shift register of claim 1, wherein the second input block comprises a fifth transistor; wherein,

9. The shift register according to claim 1, wherein the second output block includes a seventh transistor and a second storage capacitor; wherein,

10. The shift register according to claim 1, wherein the second reset module includes a sixth transistor and a fourteenth transistor; wherein,

11. The shift register according to claim 1, wherein the second reset module includes a sixth transistor and a fourteenth transistor; wherein,

12. The shift register of claim 1, wherein the second noise reduction module comprises an eighth transistor and a sixteenth transistor; wherein,

13. The shift register of claim 1, wherein the pull-down control module comprises an eleventh transistor; wherein,

14. The shift register of claim 1, wherein the pull-down control module comprises an eleventh transistor; wherein,

15. The shift register of claim 2, wherein the storage module comprises a third storage capacitor; wherein,

16. A gate driver circuit comprising the shift register of any one of claims 1 to 15.

17. A gate driving circuit as claimed in claim 16, wherein the first input signal terminal of the first shift register unit in each stage of the shift register is connected to the second signal output terminal of the second shift register unit in the next stage of the shift register;

a first reset signal end of a first shift register unit in each stage of the shift register is connected with a second signal output end of a second shift register unit in the shift register of the stage;

a first signal output end of a first shift register unit in each stage of the shift register is connected with a second signal input end of a second shift register unit in the shift register of the stage;

a second signal output end of a second shift register unit in each stage of the shift register is connected with a first signal input end of a first shift register unit in the next stage of the shift register;

and the second reset signal end of the second shift register unit in each stage of the shift register is connected with the first signal output end of the first shift register unit in the next stage of the shift register.

18. A display device comprising the gate driver circuit according to claim 16 or 17.