CN113450861B

CN113450861B - Shift register unit, circuit, driving method, display panel and display device

Info

Publication number: CN113450861B
Application number: CN202110722019.7A
Authority: CN
Inventors: 金慧俊; 秦丹丹
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2024-03-12
Anticipated expiration: 2041-06-28
Also published as: CN113450861A

Abstract

The invention discloses a shift register unit, a circuit, a driving method, a display panel and a display device, which comprise two shift register modules; each shift register module comprises an input unit, a pull-up unit, a pull-down unit, a pull-up control unit, a pull-down control unit, a signal input end, a signal output end, a clock signal end, a first level signal end, a first node and a second node; the pull-down units of the two shift register modules are controlled by the same second node, and/or the pull-down control units of the two shift register modules are controlled by the same first node; when the ambient temperature is in the signal output stage of the first preset range, the signal output ends of the two shift register modules simultaneously output the enabling level of the same scanning signal to the same scanning signal line; when the ambient temperature is in the signal output stage of the second preset range, the signal output end of one shift register module of the two shift register modules outputs the enabling level of the scanning signal to the scanning signal line.

Description

Shift register unit, circuit, driving method, display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a shift register unit, a circuit, a driving method, a display panel and a display device.

Background

With the continuous development of display technology, the application of display panels is also becoming more and more widespread, for example, the display panels are applied to products such as mobile phones, computers, tablet computers, electronic books, information inquiry machines, and the like, and in addition, the display panels can be applied to instrument displays (for example, vehicle-mounted displays), control panels of smart home, and the like.

In the conventional display panel, scanning signal lines are provided to each row of pixels by a scanning circuit to scan each row of pixels line by line, thereby displaying a screen. The scanning circuit comprises a plurality of cascaded shift registers, and each shift register consists of a plurality of thin film transistors and other passive elements. The on-current of a thin film transistor is generally proportional or inversely proportional to the gate voltage thereof, and the turn-on speed of the thin film transistor varies with the ambient temperature. When the temperature of the environment where the display panel is located is low, the scanning signals output by the shift register units in the shift register cannot scan pixels of corresponding lines, so that the pixels in the display panel cannot be displayed normally; on the contrary, when the temperature of the environment where the display panel is located is higher, the scanning signals output by the shift register unit can cause the plurality of rows of pixels to be turned on together, and the display panel can not normally display, and meanwhile, the low power consumption of the display panel is also not facilitated.

Disclosure of Invention

The invention provides a shift register unit, a circuit, a driving method, a display panel and a device, which can realize display when the environmental problems are different, and can ensure that the shift register unit outputs stable and accurate scanning signals on the premise of reducing power consumption when the environmental temperature is higher.

In a first aspect, an embodiment of the present invention provides a shift register unit, including: two shift register modules; each shift register module comprises an input unit, a pull-up unit, a pull-down unit, a pull-up control unit, a pull-down control unit, a signal input end, a signal output end, a clock signal end, a first level signal end, a first node and a second node;

in the same shift register module:

the input unit is respectively and electrically connected with the signal input end and the first node; the input unit is used for charging the first node under the control of an input signal of the signal input end;

the pull-up unit is electrically connected with the clock signal end and the first node respectively; in the signal output stage, the pull-up unit is used for transmitting the clock signal of the clock signal end to the signal output end under the control of the potential of the first node;

The pull-down control unit is respectively and electrically connected with the first node, the first level signal end and the second node; the pull-down control unit is used for transmitting a first level signal of the first level signal end to the second node under the control of the potential of the first node;

the pull-down unit is respectively and electrically connected with the second node, the first level signal end and the signal output end; the pull-down unit is used for pulling down the potential of the signal output end to the first level signal under the control of the potential of the second node;

the pull-down units of the two shift register modules are controlled by the same second node, and/or the pull-down control units of the two shift register modules are controlled by the same first node;

when the ambient temperature is in the signal output stage of the first preset range, the signal output ends of the two shift register modules simultaneously output the enabling level of the same scanning signal to the same scanning signal line; when the ambient temperature is in a signal output stage of a second preset range, the signal output end of one of the two shift register modules outputs the enabling level of the scanning signal to the scanning signal line;

Wherein the temperature in the first preset range is less than the temperature in the second preset range.

In a second aspect, an embodiment of the present invention further provides a shift register circuit, including: cascaded multistage shift register units; the shift register unit is the shift register unit.

In a third aspect, an embodiment of the present invention further provides a driving method of a shift register circuit, for driving the shift register circuit provided in the second aspect, including:

acquiring the current ambient temperature;

when the ambient temperature is in a first preset range, controlling the enabling level of the scanning signals sequentially output by each level of the shift register units, and simultaneously outputting the same scanning signals by two shift register modules of each level of the shift register units;

when the ambient temperature is in a second preset range, one shift register module in each stage of shift register unit is controlled to sequentially output the enabling level of the scanning signal, and the other shift register module in each stage of shift register unit outputs the non-enabling level of the scanning signal.

In a fourth aspect, an embodiment of the present invention further provides a display panel, including: a display region and a non-display region surrounding the display region;

The non-display area comprises the shift register circuit;

the display area comprises a plurality of pixels arranged in an array and a plurality of scanning signal lines extending along a first direction and arranged along a second direction; the pixels located in the same row share the scanning signal line;

each stage of shift register unit of the shift register circuit is electrically connected with each scanning signal line in a one-to-one correspondence manner.

In a fifth aspect, an embodiment of the present invention further provides a display apparatus, including: the display panel.

According to the shift register unit provided by the embodiment of the invention, by arranging the two shift register modules, the two shift register modules are controlled to output scanning signals simultaneously in a low-temperature environment, so that the shift register unit is ensured to have higher driving capability in the low-temperature environment without increasing the amplitude and/or duty ratio of a clock signal at a clock signal end, and only one shift register module is enabled to work in the high-temperature environment, and the shift register unit is ensured to still output normal scanning sequences, so that the power consumption is reduced on the premise of ensuring normal display; in addition, by controlling the pull-down units of the two shift register modules to the same second node and/or controlling the pull-down control units of the two shift register modules to the same first node, the scan signals output by the shift register modules which are in the non-working state and influence the working signals output by the shift register modules can be ensured under the high-temperature environment, so that the reliability of the shift register units can be improved, and further, when the shift register units are applied to a display panel, the display effect of the display panel can be improved.

Drawings

Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another shift register unit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a shift register unit according to another embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a shift register unit according to an embodiment of the present invention;

fig. 5 is a driving timing chart of a shift register unit corresponding to fig. 4;

FIG. 6 is a timing diagram of driving another shift register unit corresponding to FIG. 4;

FIG. 7 is a schematic diagram of a specific circuit structure of a shift register unit according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a specific circuit structure of a shift register unit according to another embodiment of the present invention;

FIG. 9 is a schematic diagram of a specific circuit structure of a shift register unit according to another embodiment of the present invention;

fig. 10 is a driving timing chart of a shift register unit corresponding to fig. 9;

FIG. 11 is a schematic diagram of a shift register circuit according to an embodiment of the present invention;

fig. 12 is a driving timing chart of a shift register circuit corresponding to fig. 11;

FIG. 13 is a flowchart of a driving method of a shift register circuit according to an embodiment of the present invention;

Fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 16 is a schematic view of a display panel according to another embodiment of the present invention;

FIG. 17 is a schematic view of a display panel according to another embodiment of the present invention;

FIG. 18 is a schematic view of a display panel according to another embodiment of the present invention;

fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

As described in the background art, each shift register unit in the shift register circuit is composed of a plurality of thin film transistors and other passive elements, and in a low temperature environment, the turn-on speed of the thin film transistors is slow, so that the driving capability of the scanning signals output by the shift register unit is weak, and in a high temperature environment, the turn-on speed of the thin film transistors is fast, so that the driving capability of the scanning signals output by the shift register unit is strong. If the shift register can normally output the scanning signal only in a high-temperature environment, the shift register cannot meet the requirement of the low-temperature scanning signal although the power consumption is smaller; if the shift register circuit is suitable for various temperature environments, a clock signal with a larger amplitude or duty ratio needs to be provided for the shift register unit, which is disadvantageous for low power consumption of the display panel; alternatively, increasing the size of the thin film transistor in the display panel would be disadvantageous for a narrow bezel of the display panel, while a larger size thin film transistor requires a larger driving voltage, which is also disadvantageous for low power consumption of the display panel.

To solve the above technical problems, an embodiment of the present invention provides a shift register unit, including: two shift register modules; each shift register module comprises an input unit, a pull-up unit, a pull-down unit, a pull-up control unit, a pull-down control unit, a signal input end, a signal output end, a clock signal end, a first level signal end, a first node and a second node; in the same shift register module: the input unit is electrically connected with the signal input end and the first node respectively; the input unit is used for charging the first node under the control of an input signal of the signal input end; the pull-up unit is electrically connected with the clock signal end and the first node respectively; in the signal output stage, the pull-up unit is used for transmitting a clock signal of the clock signal end to the signal output end under the control of the potential of the first node; the pull-down control unit is respectively and electrically connected with the first node, the first level signal end and the second node; the pull-down control unit is used for transmitting a first level signal of the first level signal end to the second node under the control of the potential of the first node; the pull-down unit is respectively and electrically connected with the second node, the first level signal end and the signal output end; the pull-down unit is used for pulling down the potential of the signal output end to a first level signal under the control of the potential of the second node; the pull-down units of the two shift register modules are controlled by the same second node, and/or the pull-down control units of the two shift register modules are controlled by the same first node; when the ambient temperature is in the signal output stage of the first preset range, the signal output ends of the two shift register modules simultaneously output the enabling level of the same scanning signal to the same scanning signal line; when the ambient temperature is in the signal output stage of the second preset range, the signal output end of one shift register module in the two shift register modules outputs the enabling level of the scanning signal to the scanning signal line; wherein the temperature in the first preset range is less than the temperature in the second preset range.

By adopting the technical scheme, when the low-temperature environment is adopted, the two shift register modules can be controlled to output scanning signals simultaneously, on the premise that the shift register unit has higher driving capability in the low-temperature environment, the amplitude and/or the duty ratio of the clock signal at the clock signal end are not required to be improved, and only one shift register module is enabled to work in the high-temperature environment, so that the shift register unit can still output normal scanning sequences, and the power consumption is reduced on the premise that normal display is ensured; in addition, by controlling the pull-down units of the two shift register modules to the same second node and/or controlling the pull-down control units of the two shift register modules to the same first node, the scan signals output by the shift register modules which are in the non-working state and influence the working signals output by the shift register modules can be ensured under the high-temperature environment, so that the reliability of the shift register units can be improved, and further, when the shift register units are applied to a display panel, the display effect of the display panel can be improved.

The above is the core idea of the invention, and based on the embodiments of the invention, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention, where, as shown in fig. 1, the shift register unit includes two shift register modules 00; each shift register module 00 includes an input unit 10, a pull-up unit 20, a pull-down unit 30, a pull-up control unit 40, a pull-down control unit 50, a signal input terminal INF, a signal output terminal GOUT, a clock signal terminal CKB, a first level signal terminal VGL, a first node P, and a second node Q; the same shift register module 00: the input unit 10 is electrically connected with the signal input terminal INF and the first node P, respectively; the input unit 10 is configured to charge the first node P under the control of an input signal of the signal input terminal INF; the pull-up unit 20 is electrically connected to the clock signal terminal CKB and the first node P, respectively; in the signal output stage, the pull-up unit 20 is configured to transmit the clock signal of the clock signal terminal CKB to the signal output terminal GOUT under the control of the potential of the first node P; the pull-down control unit 50 is electrically connected to the first node P, the first level signal terminal VGL, and the second node Q, respectively; the pull-down control unit 50 is configured to transmit a first level signal of the first level signal terminal VGL to the second node Q under the control of the potential of the first node P; the pull-down unit 30 is electrically connected with the second node Q, the first level signal terminal VGL and the signal output terminal GOUT, respectively; the pull-down unit 30 is configured to pull down the potential of the signal output terminal GOUT to the first level signal VGL under the control of the potential of the second node Q; when the ambient temperature is in the signal output stage of the first preset range, the signal output ends GOUT of the two shift register modules 00 simultaneously output the enabling level of the same scanning signal to the same scanning signal line SCAN; when the ambient temperature is in the signal output stage of the second preset range, the signal output end GOUT of one shift register module 00 in the two shift register modules 00 outputs the enabling level of the scanning signal to the scanning signal line SCAN; wherein the temperature in the first preset range is less than the temperature in the second preset range.

For example, when the ambient temperature is in the first preset range, that is, the shift register unit works in a low temperature environment, in order to ensure that the scan signal output by the shift register unit has a higher driving capability, the two shift register modules 00 of the shift register unit work simultaneously and are in the same working state. For example, the signal input terminals INF of the two shift register modules 00 receive the same input signal, the clock signal terminals CKB receive the same clock signal, and the first level signal terminals VGL receive the same first level signal, so that, according to the same input signal, the input units 10 of the two shift register modules 00 can charge the respective first nodes P according to the input signal, so that the potentials of the first nodes P of the two shift register modules 00 are in the state of the enabling level; at this time, the pull-down control unit 50 of the two shift register modules 00 may control the first level signal of the first level signal end VGL to be transmitted to the second node Q corresponding to each according to the potential of the first node P corresponding to each other, so that the second nodes Q of the two shift register modules 00 are in a state of non-enabling level, and thus the first level signal of the first level signal end VGL of the two shift register modules 00 is not transmitted to the signal output end GOUT through the pull-down unit 30; the pull-up units 20 of the two shift register modules 00 can both transmit the clock signal provided by each clock signal terminal CKB to the signal output terminal GOUT under the control of the corresponding first node P, when the clock signal provided by the clock signal terminal CKB is the enabling level, the enabling level can be transmitted to the SCAN signal line SCAN commonly connected with the signal output terminals GOUT of the two shift register modules 00 through the signal output terminals GOUT of the two shift register modules 00, compared with the case that only one signal output terminal of the shift register module 00 provides the enabling level for the SCAN signal line SCAN, the signal output terminals GOUT of the two shift register modules 00 simultaneously provide the enabling level for the same SCAN signal line SCAN, so that the current flowing through the SCAN signal line SCAN is the sum of the currents of the output signals of the signal output terminals GOUT of the two shift register modules 00, and the current flowing through the SCAN signal line SCAN can be increased, and further the charging time of the SCAN signal line SCAN can be shortened, the driving capability of the shift register units is improved, the driving requirement of low-temperature environment is met, and the display panel can be ensured to be still in normal display environment when the shift register units are applied to the display panel. Meanwhile, because the power consumption of the shift register unit is positively correlated with the amplitude, the frequency and the like of the signals provided to each signal end of the shift register unit, compared with the mode of increasing the amplitude and/or the frequency of the clock signals provided to the shift register unit to improve the driving capability of the shift register unit, the two shift register modules 00 can output the enabling level to the scanning signal line SCAN at the same time by keeping the amplitude and the frequency of the clock signals unchanged, so that the shift register unit has higher driving capability and is beneficial to the low power consumption of the shift register unit.

Similarly, when the clock signals received by the clock signal terminals CKB of the two shift register modules 00 are both at the non-enable level and the first node P is kept at the enable level, the pull-up units 20 of the two shift register modules 00 can simultaneously transmit the non-enable level of the respective clock signal terminals CKB to the respective signal output terminals GOUT so as to simultaneously provide the non-enable level for the same SCAN signal line SCAN, so as to ensure that the display panel displays normally when the driving requirement of the low-temperature environment is satisfied; or, when the potential of the first node P of the two shift register modules 00 becomes the non-enabling level and the potential of the second node Q becomes the enabling level, the pull-down units 30 of the two shift register modules 00 can simultaneously transmit the first level signals of the respective first level signal terminals VGL to the respective signal output terminals GOUT so as to simultaneously provide the non-enabling level for the same SCAN signal line SCAN, so as to ensure that the display panel displays normally when the driving requirement of the low temperature environment is satisfied.

When the ambient temperature is in the second preset range, that is, the shift register unit works in a high-temperature environment, one shift register module 00 can be in a normal working state, the other shift register module 00 is in a non-working state, for example, the shift register module 01 is in a normal working state, and the shift register module 02 is in a non-working state; the working process of the shift register module 01 in the working state is similar to the working process of the two shift register modules 00 when the environmental temperature is higher, and is not repeated here; each signal end of the shift register module 02 in the non-working state may not receive a corresponding signal, so that it may not provide an enabling level for the SCAN signal line SCAN; at this time, in the output stage of the enabling level, only the shift register module 01 provides the enabling level for the SCAN signal line SCAN, so that the current flowing through the SCAN signal line SCAN is smaller to meet the high-temperature driving requirement; meanwhile, each signal end of the shift register module 02 which does not work can not receive a corresponding signal, so that the shift register module 02 can have lower power consumption, a shift register unit can be kept low in power consumption, and the shift register unit can be beneficial to low power consumption of a display panel when being applied to the display panel.

Therefore, the working states of the two shift register modules are controlled according to the ambient temperature, so that the two shift register modules can be in the working states in a low-temperature environment, the two shift register modules are controlled to output scanning signals simultaneously, the amplitude and/or the duty ratio of a clock signal at a clock signal end are not required to be improved on the premise that the shift register unit has higher driving capability in the low-temperature environment, only one shift register module is enabled to work in the high-temperature environment, the shift register unit is ensured to still output normal scanning signals, and therefore the power consumption is reduced on the premise that normal display is ensured.

With continued reference to fig. 1, the pull-down units 30 of the two shift register modules 00 are controlled by the same second node Q, for example, the pull-down units 30 of the two shift register modules 00 are controlled by the second node Q of the shift register module 01 which is in an operating state under all temperature environments. When the temperature of the environment is high, i.e. the temperature of the environment is within the second temperature range, the pull-down unit 30 of the shift register module 02 in the non-working state is controlled by the potential of the second node Q of the shift register module 01, i.e. when the potential of the second node Q in the shift register module 01 is at the enabling level, the shift register module 01 and the pull-down unit 30 of the shift register module 02 can simultaneously transmit the non-enabling signal provided by the respective first level signal terminal VGL to the respective signal output terminal GOUT; when the potential of the second node Q in the shift register module 01 is at the disable level, the pull-down modules 30 of the shift register module 01 and the shift register module 02 will not transmit the disable signal provided by the respective first level signal terminals VGL to the respective signal output terminals GOUT; in order to prevent the signal output end GOUT of the shift register module 02 in the non-working state from outputting an abnormal signal to the SCAN signal line SCAN, and affecting the SCAN signal provided to the SCAN signal line SCAN, the reliability of the shift register unit can be improved, and when the shift register unit is applied to the display panel, the display effect of the display panel can be improved.

It should be noted that, in fig. 1, only two pull-down control units 50 of the shift register modules 00 are exemplarily shown and controlled by the same second node Q; in the embodiment of the present invention, the pull-down units 30 of the two shift register modules 00 may be controlled by the same first node P, or the pull-down units 30 of the two shift register modules 00 may be controlled by the same second node Q and the pull-down control units 50 of the two shift register modules 00 may be controlled by the same first node P. The following is an exemplary description of the various cases.

Fig. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and fig. 2 is the same as fig. 1 in that reference is made to the description of fig. 2, and only differences between fig. 2 and fig. 1 are exemplarily described herein. As shown in fig. 2, the pull-down control units 50 of the two shift register modules 00 are controlled by the same first node P, for example, the pull-down control units 50 of the two shift register modules 00 are controlled by the first node P of the shift register module 01 in an operating state under all temperature environments. In this way, when the temperature of the environment is higher, i.e. the temperature of the environment is within the second temperature range, the pull-down control unit 50 of the shift register module 02 in the inactive state is controlled by the potential of the first node P of the shift register module 01, i.e. when the potential of the first node P of the shift register module 01 is in the enabled level state, the pull-down control unit 50 of the shift register module 01 and the pull-down control unit 50 of the shift register module 02 can simultaneously transmit the first level signal provided by the respective first level signal terminal VGL to the respective second node Q, so that the potential of the second node Q is the disabled level, and therefore, the pull-down modules 30 of the shift register module 01 and the shift register module 02 cannot transmit the disabled signal provided by the respective first level signal terminal VGL to the respective signal output terminal GOUT under the potential control of the respective second node Q; when the potential of the first node P is in the disable level state, the pull-down control unit 50 of the shift register module 01 and the shift register module 02 cannot transmit the first level signal provided by the respective one-level signal terminal VGL to the respective second node Q, and at this time, the potential of the second node Q is synchronous with the clock signal received by the respective clock signal terminal CKB, and when the clock signal is at the enable level, the pull-down control unit 30 of the shift register module 01 and the shift register module 02 can simultaneously transmit the disable signal provided by the respective first level signal terminal VGL to the respective signal output terminal GOUT, and when the clock signal is at the enable level, the respective signal output terminal GOUT of the shift register module 01 and the shift register module 02 outputs the signal received by the respective signal input terminal INF; by the arrangement, the signal output end GOUT of the shift register module 02 in the non-working state can be prevented from outputting abnormal signals to the scanning lines SCAN, and the scanning signals provided to the scanning lines SCAN are influenced, so that the reliability of the shift register unit can be improved, and the display effect of the display panel can be improved when the shift register unit is applied to the display panel.

Fig. 3 is a schematic structural diagram of a shift register unit according to another embodiment of the present invention, and fig. 3 is the same as fig. 1 and 2, and reference may be made to the above description of fig. 1 and 2, where only differences between fig. 3 and fig. 1 and 2 are exemplarily described. As shown in fig. 3, in the same shift register unit, the pull-down units 30 of two shift register modules 00 are controlled by the same second node Q, and the pull-down control units 50 of two shift register modules 00 are controlled by the same first node P. For example, the pull-down units 30 of the two shift register modules 00 are controlled by the second node Q in the shift register module 01 that is in an operating state under various temperature environments, the pull-down control units 50 of the two shift register modules 00 are controlled by the first node P in the shift register module 01 that is in an operating state under various temperature environments, so that the pull-down control units 50 of the two shift register modules 00 pull down the electric potentials of the respective signal output ends GOUT to the first level signal under the electric potential control of the first node P in the shift register module 01, or the pull-down units 30 of the two shift register modules 00 pull down the electric potentials of the respective signal output ends GOUT to the first level signal under the electric potential control of the second node Q in the shift register module 01, so that the reliability of the shift register units can be further improved, and when the shift register units are applied to a display panel, the display effect of the display panel can be improved.

For convenience of description, in the embodiment of the present invention, two shift register modules are controlled by the same second node, and the technical solution of the embodiment of the present invention is illustrated by way of example.

According to the shift register unit provided by the embodiment of the invention, by arranging the two shift register modules, when the shift register unit is in a low-temperature environment, the two shift register modules are controlled to output scanning signals simultaneously, so that on the premise that the shift register unit has higher driving capability when in the low-temperature environment, the amplitude and/or the duty ratio of a clock signal at a clock signal end are not required to be improved, and only one shift register module is enabled to work in the high-temperature environment, the shift register unit is ensured to still output normal scanning signals, and therefore, the power consumption is reduced on the premise that normal display is ensured; in addition, by controlling the pull-down units of the two shift register modules to the same second node and/or controlling the pull-down control units of the two shift register modules to the same first node, the signal output by the shift register in the non-working state can be ensured not to influence the scanning signal output by the shift register module in the working state in a high-temperature environment, so that the reliability of the shift register units can be improved, and further, when the shift register units are applied to a display panel, the display effect of the display panel can be improved.

Optionally, with continued reference to fig. 3, the two shift register modules are a first shift register module 01 and a second shift register module 02, respectively; the clock signal end of the first shift register module 01 is a first clock signal end CKB1, the clock signal end of the second shift register module 02 is a second clock signal end CKB2, and when the ambient temperature is in a first preset range, the first clock signal received by the first clock signal end CKB1 is the same as the second clock signal received by the second clock signal end CKB 2; when the ambient temperature is in a second preset range, the first clock signal received by the first clock signal end comprises an enabling level and a non-enabling level; the second clock signal received by the second clock signal terminal includes a disable level.

In this way, by providing different clock signals to the two shift register modules (01 and 02) respectively, when the environmental temperature is low, the two shift register modules (01 and 02) can work simultaneously, and simultaneously transmit the enabling level of the first clock signal and the enabling level of the second clock signal to the same scanning signal line SCAN, so that the shift register unit has higher driving capability; when the temperature of the environment is higher, only the first shift register module 01 transmits the enabling level of the first clock signal to the scanning signal line SCAN, and the second shift register module 02 does not provide the enabling level for the scanning signal line SCAN so as to meet the normal display; and because the power consumption of the shift register unit is positively correlated with the clock signal received by the shift register unit, the frequency of the clock signal and the parasitic capacitance of the shift register unit, when the second clock signal keeps the non-enabled level, the frequency of the second clock signal is lower, which is equivalent to the frequency of the second clock signal provided to the second clock signal end CKB2, so that the power consumption of the shift register unit can be reduced, and the power consumption of the display panel can be reduced when the shift register unit is applied to the display panel.

It should be noted that, the input unit 10, the pull-up unit 20, the pull-down unit 30, the pull-up control unit 40, and the pull-down control unit 50 in the shift register module 00 may be all composed of active and/or passive devices, and when the active devices include active devices, the active devices may include thin film transistors, and the channel types of the thin film transistors may be N-type or P-type; for a thin film transistor with an N-type channel, the corresponding enabling level is high level, and the non-enabling level is low level, namely, the thin film transistor is turned on when a signal received by a grid electrode of the N-type thin film transistor is a high level signal, and is turned off when the signal received by the grid electrode of the N-type thin film transistor is a low level signal; for a thin film transistor with a P-type channel, the corresponding enabling level is low, and the non-enabling level is high, namely, the thin film transistor is turned on when the signal received by the grid electrode of the P-type thin film transistor is low, and turned off when the signal received by the grid electrode of the P-type thin film transistor is high; the high and low levels are described herein as relative high and low relationships.

Fig. 4 is a schematic diagram of a specific circuit structure of a shift register unit according to an embodiment of the present invention, as shown in fig. 4, a signal output end of a first shift register module 01 is a first signal output end GOUT1, a signal output end of a second shift register module 02 is a second signal output end GOUT2, and the first signal output end GOUT1 and the second signal output end GOUT2 are electrically connected with the same scanning signal line; the first level signal end VGL of the first shift register module 01 and the first level signal end VGL of the second shift register module 02 receive the same first level signal; the signal input end of the first shift register module 01 comprises a first signal input end Gn-1 and a second signal input end Gn+1, the signal output end of the second shift register module 02 comprises a first signal input end Gn-1 and a second signal input end Gn+1, the first signal input ends Gn-1 of the two shift register modules (01 and 02) are electrically connected with the signal output ends (GOUT 1 and GOUT 2) of the previous stage shift register unit, and the second signal input end Gn-1 is electrically connected with the signal output ends (GOUT 1 and GOUT 2) of the next stage shift register unit; thus, when the shift register unit according to the embodiment of the present invention is applied to the shift register circuit, the shift register circuit may respectively implement forward scanning and backward scanning, that is, when the first shift register module 01 and the second shift register module 02 each charge the first node P according to the signal received by the first signal input terminal Gn-1 thereof, the shift register unit performs the forward scanning process, and when the first shift register module 01 and the second shift register module 02 each charge the first node P according to the signal received by the second signal input terminal gn+1 thereof, the shift register unit performs the backward scanning process, thereby enabling flexible control of the shift register unit, so that the shift register unit may be applied to different scan scenarios.

Here, the first shift register module 01 and the second shift register module 02 have substantially the same configuration, and thus the first shift register module 01 will be described as an example. The input unit 10 includes a first transistor T1 and a second transistor T2, at this time, the first shift register module 01 further includes a first potential control terminal FW and a second potential control terminal BW, wherein, in the forward scanning phase, the first potential control signal received by the first potential control terminal FW is kept at an enable level, and the second potential control signal received by the second potential control terminal BW is kept at a disable level; in contrast, in the reverse scan phase, the first potential control signal received by the first potential control terminal FW is maintained at a non-enable level, and the second potential control signal received by the second potential control terminal BW is maintained at an enable level; the gate of the first transistor T1 is electrically connected to the first signal input terminal Gn-1, the gate of the second transistor T2 is electrically connected to the second signal input terminal gn+1, the first pole of the first transistor T1 is electrically connected to the first potential control terminal FW, the second pole of the first transistor T1 is electrically connected to the second pole of the second transistor T2 at the first node P, and the first pole of the second transistor T2 is electrically connected to the second potential control terminal BW. The pull-up control unit 40 includes a third transistor T3, a second electrode of the third transistor T3 is electrically connected to the first node P, a first electrode of the third transistor T3 is electrically connected to the first level signal terminal VGL, and a gate of the third transistor T3 is electrically connected to the second node Q; the pull-down control unit 50 includes a fourth transistor T4, a gate of the fourth transistor T4 is electrically connected to the first node P, a first pole of the fourth transistor T4 is electrically connected to the first level signal terminal VGL, and a second pole of the fourth transistor T4 is electrically connected to the second node Q; the pull-down unit 30 includes a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected to the second node Q, a first pole of the fifth transistor T5 is electrically connected to the first level signal terminal VGL, and a second pole of the fifth transistor T5 is electrically connected to the first signal output terminal GOUT 1; the pull-up unit 20 includes a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the first node, a first pole of the sixth transistor T6 is electrically connected to the first clock signal terminal CKB1, and a second pole of the sixth transistor T6 is electrically connected to the signal output terminal.

Fig. 5 is a driving timing diagram of a shift register unit corresponding to fig. 4, as shown in fig. 5, when the ambient temperature is at a first preset temperature, the first clock signal received by the first clock signal terminal CKB1 is the same as the second clock signal received by the second clock signal terminal CKB 2. Taking forward scanning as an example, in the stage T1, the first input signal Gn-1 received by the first signal input terminal Gn-1 is an enabling level, the first clock signal CKB1 of the first clock signal terminal CKB1 and the second clock signal CKB2 of the second clock signal terminal CKB2 are both at a non-enabling level, the first transistors T1 of the two shift register modules 00 are both in a conducting state, so that the enabling level of the first control potential terminal FW is transmitted to the first node P, the first node P is charged, so that the potential of the first node P is in a state of enabling level, the fourth transistors T4 of the two shift register modules 00 transmit the first level signal of the first level signal terminal VGL to the second node Q under the control of the potential of the first node P, so that the potential of the second node Q is in a state of non-enabling level, and the fifth transistors T5 of the second shift register modules 02 are controlled by the second node Q of the first shift register modules 01, so that the first shift register modules 01 and the third transistors T02 of the second shift register modules 02 are not in a state of being in which the respective switching-off state when the first level signals of the second transistors T1 and the second transistors T02 of the second shift register modules are not in the respective switching-off state (the first transistors of the second transistors T1 are not being turned off); since the first clock signal CKB1 received by the first clock signal terminal CKB1 is the same as the second clock signal CKB2 received by the second clock signal terminal CKB2, the sixth transistors T6 of the two shift register modules 00 transmit the same clock signal to the SCAN signal lines SCAN connected in common under the control of the potential of the first node P.

In the T2 stage, the first input signal Gn-1 received by the first signal input terminal Gn-1 and the second input signal gn+1 received by the second signal input terminal gn+1 are both at a non-enable level, the first clock signal CKB1 of the first clock signal terminal CKB1 and the second clock signal CKB2 of the second clock signal terminal CKB2 are at an enable level, the enable level in the T1 stage is still maintained because the first node P has no input of the non-enable level, the fourth transistor T4 and the sixth transistor T6 are turned on, the first level signal provided by the first level signal terminal VGL is transmitted to the second node Q through the turned-on fourth transistor T4, the sixth transistors T6 of the two shift register modules 00 transmit the enable levels of the respective clock signal terminals (CKB 1 and CKB 2) to the respective signal output terminals (GOUT 1 and GOUT 2) under the potential control of the first node P, that is, the first signal output terminal GOUT1 and the second signal output terminal GOUT2 output the enable levels at the same time, that is, the signal output terminals (GOUT 1 and GOUT 2) of the two shift register modules 00 simultaneously supply the enable levels of the SCAN signals (GOUT 1 and GOUT 2) to the SCAN signal lines SCAN commonly connected therewith, so as to increase the current flowing through the SCAN signal lines SCAN, shorten the charging time of the SCAN signal lines SCAN, and improve the driving capability of the shift register units, thereby ensuring normal display in a low temperature environment.

In the stage T3, the second input signal gn+1 received by the second signal input terminal gn+1 is at an enabling level, the first clock signal CKB1 of the first clock signal terminal CKB1 and the second clock signal CKB2 of the second clock signal terminal CKB2 are both at a non-enabling level, the second transistors T2 of the two shift register modules 00 are both in an on state, so that the non-enabling level of the second control potential terminal BW is transmitted to the first node P, the potential of the first node P becomes a non-enabling level, the fourth transistors T4 and the sixth transistors T6 of the two shift register modules 00 are both in an off state under the control of the potential of the first node P, the potential of the second nodes Q of the two shift register modules 00 are both kept at the non-enabling level under the control of the non-enabling level of the first clock signal CKB1 and the second clock signal CKB2, and the fifth transistors T5 of the second shift register modules 02 are controlled by the second node Q of the first shift register module 01, so that the potential of the second transistors T01 and the second transistors T2 of the second shift register modules are both in the off state under the control of the non-enabling level of the first clock signal CKB1 and the second clock signal CKB2, and the potential of the second clock signal CKB2 are both in the off state under the control of the non-enabling level of the first clock signal of the second transistors T1.

In the stage T4, the first input signal Gn-1 received by the first signal input terminal Gn-1 and the second input signal gn+1 received by the second signal input terminal gn+1 are both at a non-enable level, the first clock signal CKB1 of the first clock signal terminal CKB1 and the second clock signal CKB2 of the second clock signal terminal CKB2 are both at an enable level, the potentials of the second nodes Q of the two shift register modules 00 are respectively changed from the non-enable level to the enable level at the control lines of the first clock signal CKB1 and the second clock signal CKB2, and the fifth transistor T5 of the second shift register module 02 is controlled by the second node Q of the first shift register module 01, so that the third transistors T3 of the first shift register module 01 and the second shift register module 02 are both on, the non-enable level of the first level signal terminal VGL is transmitted to the first node P through the third transistors T3 which are on under the potential control of the respective second node Q, and the non-enable level of the first node P is kept at the non-enable level at the first node P state; meanwhile, the non-enable level of the first level signal terminal VGL is further transmitted to the first signal output terminal GOUT1 and the second signal output terminal GOUT2 respectively corresponding to the first level signal terminal GOUT1 and the second level signal output terminal GOUT2 through the two turned-on fifth transistors T5, and at this time, the scan signal GOUT1 output by the first signal output terminal GOUT1 and the scan signal GOUT2 output by the second signal output terminal GOUT2 are both non-enable levels at the first level signal terminal VGL.

After the t4 stage, since the first input signal Gn-1 received by the first signal input terminal Gn-1 and the second input signal gn+1 received by the second signal input terminal gn+1 are always at the disable level, the first node P will always be kept at the disable level state, and the potentials of the second nodes Q of the two shift register modules 00 are synchronized with the first clock signal ckb1 and the second clock signal ckb2, respectively, and the scan signal GOUT1 output by the first signal output terminal GOUT1 and the scan signal GOUT2 output by the second signal output terminal GOUT2 are both kept at the disable level.

Fig. 6 is a driving timing chart of another shift register unit corresponding to fig. 4, and the same points in fig. 6 as those in fig. 5 are referred to the above description of fig. 5, and only the differences in fig. 6 from fig. 5 are exemplarily described herein. As shown in fig. 4 and fig. 6, when the ambient temperature is at the second preset temperature, the first clock signal CKB1 received by the first clock signal terminal CKB1 includes an enable level and a disable level; the second clock signal CKB2 received by the second clock signal terminal CKB2 includes only the disable level. In the stage T2, the sixth transistor T6 of the first shift register module 01 is turned on, so that the enabling level of the first clock signal CKB1 of the first clock signal end CKB1 is transmitted from the first signal output end Gout1 to the SCAN signal line SCAN, and at this time, although the sixth transistor T6 of the second shift register module 02 is also turned on, the driving capability of the SCAN signal outputted from the shift register unit to the SCAN signal line SCAN is relatively weak due to the second clock signal CKB2 of the second clock signal end CKB2 being the non-enabling level, so as to ensure the normal display function at the high temperature; meanwhile, since the second clock signal CKB2 of the second clock signal terminal CKB2 in the second shift register 02 is kept at the non-enable level, i.e., the frequency of the second clock signal CKB2 is low, the power consumption of the shift register unit can be reduced.

Optionally, with continued reference to fig. 4 and 6, the pull-down unit of the second shift register module 02 is electrically connected to the second node Q of the first shift register module 01; the pull-down unit 30 of the second shift register module 02 is configured to transmit a second clock signal to the signal output terminal GOUT under the potential control of the second node Q of the first shift register module 01; in this way, in the period T1 and the period T2 when the temperature of the environment is higher, if the potential of the second node Q of the first shift register module 01 is in the non-enabled level state, the fifth transistor T5 of the first shift register module 01 and the fifth transistor T5 of the second shift register module 02 can be simultaneously controlled to be in the off state, so as to prevent the fifth transistor T5 of the second shift register module 02 from being turned on to affect the signal output by the signal output terminal GOUT when the second shift register module 02 does not work, thereby improving the accuracy and reliability of the signal output by the shift register unit.

It should be noted that, in fig. 5, the pull-down unit of the second shift register module 02 is exemplarily shown to be electrically connected to the second node Q of the first shift register module 01, and the node multiplexing manner may also be other cases, and the following is an exemplary description for different cases.

Fig. 7 is a schematic circuit diagram of another embodiment of a shift register unit according to the present invention, where fig. 7 is the same as fig. 4, reference may be made to the description of fig. 4, and only differences between fig. 7 and fig. 4 are exemplarily described herein. As shown in fig. 7, the pull-down control unit 50 of the second shift register module 02 is electrically connected to the first node P of the first shift register module 01, and the pull-down control unit 50 of the second shift register module 02 transmits the first level signal of the first level signal terminal VGL to the second node Q of the second shift register module 02 under the control of the potential of the first node P of the first shift register module 01; so set up, when the temperature of the environment that is located is higher, if first node P of first shift register module 01 is in the state of non-enabling level, can control the fourth transistor T4 of first shift register module 01 and the fourth transistor T4 of second shift register module 02 simultaneously and be in the state of closing to prevent second shift register module 02 when not working, the fourth transistor T4 of second shift register module 02 switches on and influences the signal that signal output terminal GOUT exports, can improve the accuracy and the reliability of shift register unit output signal this moment equally.

Fig. 8 is a schematic diagram of a specific circuit structure of a shift register unit according to another embodiment of the present invention, and fig. 8 is the same as fig. 7 and 4, and reference may be made to the above description of fig. 7 and 4, and only the differences between fig. 8 and fig. 7 and 4 will be exemplarily described. As shown in fig. 8, the pull-down unit 30 of the second shift register module 02 is electrically connected to the second node Q of the first shift register module 01, and the pull-down control unit 50 of the second shift register module 02 is electrically connected to the first node P of the first shift register module 01; at this time, the pull-down unit 30 of the second shift register module 02 is configured to transmit the second clock signal to the signal output terminal GOUT2 under the control of the potential of the second node Q of the first shift register module 01, and at the same time, the pull-down control unit 50 of the second shift register module 02 transmits the first level signal of the first level signal terminal VGL to the second node Q of the second shift register module 02 under the control of the potential of the first node P of the second shift register module 02; therefore, the effect of improving the accuracy and the reliability of the output signal of the shift register unit can be achieved through the combined action of the first node P and the second node Q of the first shift register module 01.

Optionally, fig. 9 is a schematic diagram of a specific circuit structure of another shift register unit according to an embodiment of the present invention, as shown in fig. 9, each shift register module 00 further includes a reset unit 60 and a reset control terminal CK; in the same shift register module, the reset unit 60 is electrically connected with the reset control end CK, the first level signal end VGL and the signal output end GOUT respectively; the reset unit 60 is configured to transmit a first level signal to the signal output terminal under the control of a reset control signal of the reset control terminal CK. In this way, the reset signal of the reset unit 60 and the reset control terminal CK can reset the signal output terminal Gout1/Gout2, so as to prevent the signal transmitted to the signal output terminal Gout1/Gout2 from affecting the signal transmitted to the signal output terminal Gout1/Gout2 at the next time, thereby further improving the accuracy and reliability of the output signal of the shift register unit.

It is understood that the reset unit 60 may include, but is not limited to, a seventh transistor T7; the gate of the seventh transistor T7 is electrically connected to the reset control terminal CK, the first pole of the seventh transistor T7 is electrically connected to the first level signal terminal VGL, and the second pole of the seventh transistor T7 is electrically connected to the signal output terminal.

Further, with continued reference to fig. 9, each shift register module further includes a first capacitor C1 and a second capacitor C2; in the same shift register module, a first capacitor C1 is electrically connected between a clock signal end and a second node Q; the first capacitor C1 is configured to couple a clock signal provided from the clock signal terminal to the second node Q; the second capacitor C2 is electrically connected between the signal output terminal GOUT and the first node P; the second capacitor C2 is a bootstrap capacitor, and is used for pulling up the potential of the first node P.

For example, fig. 10 is a driving timing diagram of a shift register unit corresponding to fig. 9, referring to fig. 9 and 10 in combination, when the ambient temperature is within a first preset range, the first shift register module 01 and the second shift register module 02 operate simultaneously. Taking the working process of the first shift register module 01 in the forward scanning stage as an example, in the T1 stage, the first input signal received by the first signal input terminal Gn-1 is an enabling level, the first clock signal CKB1 received by the first clock signal terminal CKB1 is a non-enabling level, the reset control signal CK of the reset control terminal CK is an enabling level, at this time, the first transistor T1 is turned on, so that the enabling level of the first control potential terminal FW is transmitted to the first node P through the turned-on first transistor T1, the first node P is charged, so that the potential VP of the first node P is in a state of enabling level, the fourth transistor T4 controls the first level signal of the first level signal terminal VGL to be transmitted to the second node Q according to the potential VP of the first node P, so that the potential VQ of the second node Q is in a state of non-enabling level, so that the third transistor T3 and the fifth transistor T5 are in a turned-off state, and the first level signal is not transmitted to the first signal output terminal GOUT1; the sixth transistor T6 transmits the disable level of the first clock signal CKB1 of the first clock signal terminal CKB1 to the first signal output terminal GOUT1 under the control of the potential VP of the first node P; similarly, since the fourth transistor T4 of the second shift register module 02 is controlled by the first node P of the first shift register module 01, the potential of the second node Q of the second shift register module 02 is also the disabling level, and the second shift register module 02 transmits the disabling level of the second clock signal CKB2 of the second clock signal end CKB2 to the second signal output end GOUT2.

In the stage T2, the first input signal Gn-1 received by the first signal input terminal Gn-1 and the second input signal gn+1 received by the second signal input terminal gn+1 are both at a non-enable level, the first clock signal CKB1 of the first clock signal terminal CKB1 is at an enable level, the reset control signal CK of the reset control terminal CK is at a non-enable level, the potential VP of the first node P still maintains the enable level in the stage T1 due to the absence of the input of the non-enable level to the first node P, the fourth transistor T4 and the sixth transistor T6 are in a conducting state, the first level signal of the first level signal terminal VGL is transmitted to the second node Q through the fourth transistor T4 that is conducting, and the sixth transistor T6 transmits the enable level of the first clock signal CKB1 of the first clock signal terminal CKB1 to the first signal output terminal GOUT1 under the control of the potential VP of the first node P, that is, and the first signal output terminal GOUT1 outputs the enable level due to the bootstrap effect of the second capacitor C2 is further high. Similarly, since the fourth transistor T4 of the second shift register module 02 is controlled by the first node P of the first shift register module 01, the potential of the second node Q of the second shift register module 02 is also the non-enabled level, and the second shift register module 02 transmits the enabled level of the second clock signal end CKB2 to the second signal output end GOUT2.

In the period T3, the second input signal gn+1 received by the second signal input terminal gn+1 is at an enable level, the first clock signal CKB1 received by the first clock signal terminal CKB1 is at a disable level, the reset control signal CK of the reset control terminal CK is at an enable level, the second transistor T2 is turned on, the first node P is written to the disable level provided by the second control potential terminal BW, the fourth transistor T4 and the sixth transistor T6 are both in an off state, since the first clock signal CKB1 of the first clock signal terminal CKB1 is at the disable level, the signal coupled to the second node Q via the first capacitor C1 is still at the disable level, the fifth transistor T5 is still in the off state, and the seventh transistor T7 transmits the first level signal to the first signal output terminal GOUT1 under the control of the reset control signal CK of the reset control terminal CK. Similarly, since the fourth transistor T4 of the second shift register module 02 is controlled by the first node P of the first shift register module 01, the potential of the second node Q of the second shift register module 02 is kept at the disable level, and the seventh transistor T7 of the second shift register module 02 transmits the first level signal to the second signal output terminal GOUT2.

In the stage T4, the first input signal Gn-1 received by the first signal input terminal Gn-1 and the second input signal gn+1 received by the second signal input terminal gn+1 are both at a non-enable level, the first clock signal CKB1 of the first clock signal terminal CKB1 and the second clock signal CKB2 of the second clock signal terminal CKB2 are at an enable level, the first clock signal CKB1 is coupled to the second node Q of the first shift register module 01, so that the potential VQ thereof is at the enable level, the third transistor T3 and the fifth transistor T5 are turned on under the control of the potential VQ of the second node Q, and at this time, the scan signal GOUT1 output by the first signal output terminal GOUT1 is at the non-enable level of the first level signal terminal VGL; accordingly, since the fourth transistor T4 of the second shift register module 02 is controlled by the first node P of the first shift register module 01, the fourth transistor T4 of the second shift register module 02 is also in the off state, and the scan signal GOUT2 output by the second signal output terminal GOUT2 is the non-enable level of the first level signal terminal VGL.

After the t4 stage, the first input signal Gn-1 received by the first signal input terminal Gn-1 and the second input signal gn+1 received by the second signal input terminal gn+1 are both at the non-enable level, the phases of the first clock signal ckb1 and the reset signal ck are opposite, at this time, the potential VP of the first node P is kept at the non-enable level, the scanning signal GOUT1 output by the first signal output terminal GOUT1 is kept at the non-enable level, the potential VP of the first node P is not bootstrapped and raised, and is kept at the non-enable level. The first clock signal CKB1 of the first clock signal terminal CKB1 is coupled to the second node Q through the first capacitor C1, when the first clock signal CKB1 is at an enable level and the reset control signal ck is at a disable level, the potential VQ of the second node Q is at an enable level, the fifth transistor T5 is turned on, the first level signal provided by the first level signal terminal VGL is transmitted to the first signal output terminal GOUT1 through the fifth transistor T5, and the seventh transistor T7 is in an off state; when the first clock signal CKB1 is at the disable level and the reset control signal ck is at the enable level, the potential of the first capacitor C1 coupled to the second node Q is at the disable level, the fifth transistor T5 is turned off, the seventh transistor T7 is turned on under the control of the reset control signal ck, the first level signal provided by the first level signal terminal VGL is transmitted to the first signal output terminal GOUT1, that is, after the period T4, the scan signal GOUT1 output by the first signal output terminal GOUT1 is kept at the disable level, the potential VP of the first node P is kept at the disable level, the potential VQ of the second node Q is synchronous with the first clock signal CKB1 of the first clock signal terminal CKB1, and the fifth transistor T5 and the seventh transistor T7 are alternately turned on to transmit the first level signal to the first signal output terminal GOUT1. Similarly, the scan signal GOUT2 outputted from the second signal output terminal GOUT2 of the second shift register module 02 is kept at the disable level.

Based on the same inventive concept, the embodiment of the invention also provides a shift register circuit, which comprises cascaded multistage shift register units; the shift register unit is provided by any one of the embodiments, so that the shift register circuit provided by the embodiment of the present invention includes the technical features of the shift register unit provided by the embodiment of the present invention, and can achieve the beneficial effects of the shift register unit provided by the embodiment of the present invention.

Optionally, the shift register circuit further includes a start signal terminal, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, and a first level signal transmission line; the signal input ends of the two shift register modules in the first stage shift register unit are electrically connected with the starting signal end; the signal input ends of the two shift register modules in each stage of shift register units from the second stage of shift register unit to the last stage of shift register unit are electrically connected with the signal output ends of the two shift register modules in the shift register unit of the upper stage; when the two shift register modules of each level of shift register unit are a first shift register module and a second shift register module respectively, the clock signal end of the first shift register module of the ith level of shift register unit is electrically connected with a first clock signal wire, and the clock signal end of the second shift register module of the ith level of shift register unit is electrically connected with a second clock signal wire; the clock signal end of the first shift register module of the (i+1) -th shift register unit is electrically connected with the third clock signal line, and the clock signal end of the second shift register module of the (i+1) -th shift register unit is electrically connected with the fourth clock signal line; the first level signal end of the first shift register module and the first level signal end of the second shift register module of each level shift register unit are electrically connected with a first level signal transmission line; wherein i is an odd number; the polarity of the clock signal transmitted by the first clock signal line is opposite to that of the clock signal transmitted by the third clock signal line; when the ambient temperature is in the first preset range, the polarity of the clock signal transmitted by the second clock signal line is opposite to the polarity of the clock signal transmitted by the fourth clock signal line.

Fig. 11 is a schematic structural diagram of a shift register circuit according to an embodiment of the present invention, and as shown in fig. 11, taking a shift register circuit including four stages of shift register units as an example, in a forward scanning stage, the shift register unit ASG1 is a first stage shift register unit, and the first signal input terminals Gn-1 of the first shift register module 01 and the second shift register module 02 are electrically connected to the start signal terminal STV; the shift register unit ASG2 is a second stage shift register unit, and the first signal input terminals Gn-1 of the first shift register module 01 and the second shift register module 02 are electrically connected with the first signal output terminal GOUT1 of the first shift register module 01 and the second signal output terminal GOUT2 of the second shift register module 02 in the shift register unit ASG 1; the shift register unit ASG3 is a third stage shift register unit, and the first signal input terminals Gn-1 of the first shift register module 01 and the second shift register module 02 are electrically connected with the first signal output terminal GOUT1 of the first shift register module 01 and the second signal output terminal GOUT2 of the second shift register module 02 in the shift register unit ASG 2; the shift register unit ASG4 is a fourth stage shift register unit, and the first signal input terminals Gn-1 of the first shift register module 01 and the second shift register module 02 are electrically connected to the first signal output terminal GOUT1 of the first shift register module 01 and the second signal output terminal GOUT2 of the second shift register module 02 in the shift register unit ASG 3.

In contrast, in the reverse scanning stage, the shift register unit ASG4 is a first-pole shift register unit, and the second signal input terminals gn+1 of the first shift register module 01 and the second shift register module 02 are electrically connected to the start signal terminal STV; the shift register unit ASG3 is a second stage shift register unit, and the second signal input terminals gn+1 of the first shift register module 01 and the second shift register module 02 are electrically connected to the first signal output terminal GOUT1 of the first shift register module 01 and the second signal output terminal GOUT2 of the second shift register module 02 in the shift register unit ASG 4; the shift register unit ASG2 is a third stage shift register unit, and the second signal input terminals gn+1 of the first shift register module 01 and the second shift register module 02 are electrically connected to the first signal output terminal GOUT1 of the first shift register module 01 and the second signal output terminal GOUT2 of the second shift register module 02 in the shift register unit ASG 3; the shift register unit ASG1 is a fourth stage shift register unit, and the second signal input terminals gn+1 of the first shift register module 01 and the second shift register module 02 are electrically connected to the first signal output terminal GOUT1 of the first shift register module 01 and the second signal output terminal GOUT2 of the second shift register module 02 in the shift register unit ASG 2.

Correspondingly, the shift register units ASG1 and ASG3 are odd-numbered shift register units, so that the first clock signal end CKB1 of the first shift register module 01 in the shift register unit ASG1 is electrically connected to the first clock signal line CK1, the second clock signal end CKB2 of the second shift register module 02 in the shift register unit ASG1 is electrically connected to the second clock signal line CK2, the first clock signal end CKB1 of the first shift register module 01 in the shift register unit ASG2 is electrically connected to the first clock signal line CK1, and the second clock signal end CKB2 of the second shift register module 02 in the shift register unit ASG2 is electrically connected to the second clock signal line CK 2; the shift register units ASG2 and ASG4 are even-numbered shift register units, such that the first clock signal end CKB1 of the first shift register module 01 in the shift register unit ASG2 is electrically connected to the third clock signal line CK3, the second clock signal end CKB2 of the second shift register module 02 in the shift register unit ASG2 is electrically connected to the fourth clock signal line CK4, the first clock signal end CKB1 of the first shift register module 01 in the shift register unit ASG4 is electrically connected to the third clock signal line CK3, and the second clock signal end CKB2 of the second shift register module 02 in the shift register unit ASG4 is electrically connected to the fourth clock signal line CK 4; meanwhile, the first level signal terminals VGL of the two shift register modules (01 and 02) of all the shift register units (ASG 1, ASG2, ASG3, and ASG 4) are electrically connected to the first level signal transmission line VL.

In fig. 12, for example, in combination with fig. 11 and 12, when the ambient temperature is in the first preset range, the clock signals (c 1 and c 2) provided by the first clock signal line CKB1 and the second clock signal line CKB2 are the same and synchronous, the clock signals (c 3 and c 4) provided by the third clock signal line CKB3 and the fourth clock signal line CKB4 are the same and synchronous, and the clock signals (c 1 and c 3) provided by the first clock signal line CKB1 and the third clock signal line CKB3 are opposite in phase, so that the shift register units (ASG 1, ASG2, ASG3 and ASG 4) sequentially provide the enabling levels of the SCAN signals (g 1, g2, g3 and g 4) to the SCAN signal lines (SCAN 1, SCAN2, SCAN3 and g 4), and the shift register units (ASG 1, ASG2, ASG3, ASG 4) of the first shift register module (01) and the shift module (g 2, g 02) of the shift register unit of the stage.

Accordingly, when the ambient temperature is within the second preset range, the first clock signal supplied from the first clock signal line CKB1 and the third clock signal line CKB3 includes an enable level and a disable level, and the clock signals supplied from the second clock signal line CKB2 and the fourth clock signal line CKB4 include only the disable level, so that the first shift register module 01 of each stage of shift register units (ASG 1, ASG2, ASG3, and ASG 4) sequentially supplies the enable level of the SCAN signals (g 1, SCAN2, SCAN3, and SCAN 4) to each of the SCAN signal lines (g 1, g2, g3, and g 4), while the second shift register module 02 of each stage of shift register units (ASG 1, ASG2, ASG3, and ASG 4) does not supply the enable level of the SCAN signals (g 1, g2, g3, and g 4) to each of the SCAN signal lines (SCAN 1, SCAN2, SCAN3, and SCAN 4).

Therefore, no matter the temperature of the environment, the shift register units at all levels can be controlled to sequentially output the enabling level of the scanning signals so as to realize progressive scanning of the scanning signal lines, and the shift register units at all levels can output stable and accurate scanning signals; meanwhile, when the shift register units at all levels have lower power consumption, the low power consumption of the shift register circuit can be facilitated, so that the low power consumption of the display panel is facilitated when the shift register circuit is applied to the display panel.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of a shift register circuit, where the driving method is used for driving the shift register circuit provided by the embodiment of the present invention, fig. 13 is a flowchart of the driving method of the shift register circuit provided by the embodiment of the present invention, and as shown in fig. 13, the driving method includes:

s110, acquiring the current ambient temperature.

S120, when the ambient temperature is in a first preset range, controlling each level of shift register units to sequentially output the enabling level of the scanning signal, and simultaneously outputting the same scanning signal by two shift register modules of each level of shift register units.

And S130, when the ambient temperature is in a second preset range, controlling one shift register module in each stage of shift register units to sequentially output the enabling level of the scanning signal, and controlling the other shift register module in each stage of shift register units to output the non-enabling level of the scanning signal.

For example, after the current ambient temperature is obtained, the range to which the current ambient temperature belongs may be determined, so as to correspondingly determine the working states of the two shift register modules in each shift register unit. Referring to fig. 11 and 12 in combination, when the ambient temperature is in the first preset range, the clock signals (c 1 and c 2) provided by the first clock signal line CKB1 and the second clock signal line CKB2 are identical and synchronized, the clock signals (c 3 and c 4) provided by the third clock signal line CKB3 and the fourth clock signal line CKB4 are identical and synchronized, and the clock signals (c 1 and c 3) provided by the first clock signal line CKB1 and the third clock signal line CKB3 are opposite in phase, so that the shift register units (ASG 1, ASG2, ASG3, and ASG 4) of each stage sequentially supply the enable levels of the SCAN signals (g 1, g2, g3, and g 4) to the respective SCAN signal lines (SCAN 1, SCAN2, SCAN3, and SCAN 4), and the first shift register module 01 and the second shift register module 02 of each stage shift register unit (ASG 1, ASG2, ASG3, ASG 4) synchronously output the identical SCAN signals (g 1, g3, g 4).

Accordingly, when the ambient temperature is within the second preset range, the clock signals provided by the first clock signal line CKB1 and the third clock signal line CKB3 include an enable level and a disable level, and the clock signals provided by the second clock signal line CKB2 and the fourth clock signal line CKB4 include only the disable level, so that the first shift register module 01 of each stage of shift register units (ASG 1, ASG2, ASG3, and ASG 4) sequentially provides the enable level of the SCAN signals (g 1, SCAN2, SCAN3, and SCAN 4) to each SCAN signal line (g 1, g2, g3, and g 4), while the second shift register module 02 of each stage of shift register units (ASG 1, ASG2, ASG3, and ASG 4) does not provide the enable level of the SCAN signals (g 1, g2, g3, and g 4) to each SCAN signal line (SCAN 1, SCAN2, SCAN3, and SCAN 4).

Based on the same inventive concept, the embodiment of the invention also provides a display panel, which comprises a display area and a non-display area surrounding the display area; the non-display area includes the shift register circuit provided by any one of the embodiments, so that the display panel provided by the embodiment of the invention includes the technical features of the shift register circuit provided by the embodiment of the invention, which can achieve the beneficial effects of the shift register circuit provided by the embodiment of the invention.

Fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 14, a display panel 200 includes a display area a and a non-display area B; the display area A comprises a plurality of pixels 03 arranged in an array manner and a plurality of scanning signal lines SCAN which extend along a first direction X and are arranged along a second direction Y; the pixels 03 in the same row share one scanning signal line SCAN; the shift register circuit 100 is provided in the non-display area B; the signal output ends (GOUT 1 and GOUT 2) of two shift register modules in each stage of shift register units of the shift register circuit are electrically connected with each scanning signal line SCAN in a one-to-one correspondence manner, so that each stage of shift register units in the shift register circuit can provide the enabling level of the scanning signal for each row of pixels 03 through each scanning signal line SCAN and sequentially control the thin film transistors in each row of pixels 03 to be conducted; when the ambient temperature of the display panel 200 is high, the first shift register module 01 in each stage of shift register units can provide the enable level of the scanning signal for each row of pixels 03 through each scanning signal line SCAN; when the ambient temperature of the display panel 200 is low, the first shift register module 01 and the second shift register module in each stage of shift register units work simultaneously, and sequentially provide the SCAN signal lines SCAN with the enable level of the SCAN signal with larger current, so as to rapidly charge to the on threshold of the thin film transistor in each pixel 03, thereby meeting the low-temperature driving requirement.

Therefore, no matter the temperature of the environment where the display panel is located, each level of shift register units of the shift register circuit can sequentially output the enabling level of the scanning signal so as to realize progressive scanning of pixels of each row, and each row of pixels can normally display and emit light, so that the display effect of the display panel is improved; meanwhile, when the shift register units at all levels have lower power consumption, the low power consumption of the shift register circuit, namely the low power consumption of the display panel, can be facilitated, so that the display panel can be applied to a display device with low power consumption requirements.

Optionally, fig. 15 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 15, a SCAN signal line electrically connected to a pixel 03 located in an odd-numbered row is a first SCAN signal line SCAN01, and a SCAN signal line electrically connected to a pixel located in an even-numbered row is a second SCAN signal line SCAN02; the shift register unit electrically connected to the first SCAN signal line SCAN01 and the shift register unit electrically connected to the second SCAN signal line SCAN02 are respectively located at opposite sides of the display area a. In this way, the non-display areas B on both sides of the display area a of the display panel 200 can be symmetrically arranged, so that the frame of the display panel 200 is uniformly distributed around the display area a, which is beneficial to the practicality and the aesthetic property of the display panel 100.

Wherein, each shift register unit comprises two shift register modules (01 and 02), and the two shift register modules of the shift register unit can be a first shift register module 01 and a second shift register module 02 respectively; when the ambient temperature is in the signal output stage of the second preset range, the signal output end of each first shift register module 01 outputs the enabling level of the scanning signal to the scanning signal line; at this time, the shift register units located on the same side may be sequentially arranged along the column direction Y of the pixels 03, and the first shift register module 01 and the second shift register module 02 of the same shift register unit are adjacent.

Specifically, since two shift register modules (01 and 02) in the same shift register unit are controlled by the same first node P and/or the same second node Q; namely, in the same shift register unit, the pull-down control unit of the second shift register module 02 is electrically connected with the first node P of the first shift register module 01, and/or the pull-down unit of the second shift register module 02 is electrically connected with the second node Q of the first shift register module 01; by making the first shift register module 01 and the second shift register module 02 of the same shift register unit adjacent, the arrangement of the signal lines electrically connecting the first shift register module 01 and the second shift register module 02 can be facilitated to be simplified, thereby facilitating the design of the display panel 200 to be simplified; meanwhile, when the first shift register module 01 and the second shift register module 02 of the same shift register unit are adjacent, the length of the signal line for electrically connecting the first shift register module 01 and the second shift register module 02 can be shortened, thereby facilitating reduction of loss of signals transmitted to the second shift register module 02 by the first node P and/or the second node Q of the first shift register module 01.

It can be understood that, as shown in fig. 15, when the shift register units located on the same side may be sequentially arranged along the column direction Y of the pixels 03 and the first shift register modules 01 and the second shift register modules 02 of the same shift register unit are adjacent, the first shift register modules 01 and the second shift register modules 02 of the shift register units located on the same side are sequentially alternately arranged along the column direction Y of the pixels 03; alternatively, as shown in fig. 16, among the shift register cells on the same side, the first shift register modules 01 of two adjacent shift register cells are adjacent, or the second shift register modules 02 of two adjacent shift register cells are adjacent.

In addition, the shift register circuit disposed in the non-display area of the display panel may be disposed in such a manner that two shift register modules of the same shift register unit are disposed on opposite sides of the display area. At this time, the specific arrangement manner of the two shift register modules of each stage of shift register unit of the shift register circuit may be various, which is not particularly limited in the embodiment of the present invention.

As shown in fig. 17, when two shift register modules of the shift register unit are the first shift register module 01 and the second shift register module 02, if the signal output end of each first shift register module outputs the enabling level of the scan signal to the scan signal line when the ambient temperature is in the signal output stage of the second preset range, the first shift register module 01 of each shift register unit may be located on the same side, and the second shift register module 02 of each shift register unit may be located on the same side.

Fig. 18 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 18 is the same as fig. 17 in that reference is made to the description of fig. 17, and details thereof are omitted herein, and only differences between fig. 18 and fig. 17 are described herein for exemplary purposes. As shown in fig. 18, the first shift register block 01 of the shift register unit electrically connected to the odd-numbered rows and the second shift register block 02 of the shift register unit electrically connected to the even-numbered rows are located on the same side; and the second shift register module 02 electrically connected with the shift register unit of the odd-numbered row and the first shift register module 01 electrically connected with the shift register unit of the even-numbered row are positioned on the same side.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 19 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and as shown in fig. 19, the display device 300 includes the display panel 200 provided in any embodiment of the present invention. The display device 300 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 13, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart wristband, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal and the like, and the embodiment of the invention is not particularly limited thereto

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A shift register unit, comprising: two shift register modules; each shift register module comprises an input unit, a pull-up unit, a pull-down unit, a pull-up control unit, a pull-down control unit, a signal input end, a signal output end, a clock signal end, a first level signal end, a first node and a second node;

in the same shift register module:

Wherein the temperature in the first preset range is less than the temperature in the second preset range;

the two shift register modules are a first shift register module and a second shift register module respectively;

the clock signal end of the first shift register module is a first clock signal end, and the clock signal end of the second shift register module is a second clock signal end;

when the ambient temperature is in the first preset range, the first clock signal received by the first clock signal end is the same as the second clock signal received by the second clock signal end;

when the ambient temperature is in the second preset range, the first clock signal received by the first clock signal terminal comprises an enabling level and a non-enabling level; the second clock signal received by the second clock signal terminal comprises a non-enabling level;

the pull-down unit of the second shift register module is electrically connected with the second node of the first shift register module; the pull-down unit of the second shift register module is used for transmitting the second clock signal to the signal output end under the potential control of the second node of the first shift register module;

and/or, the pull-down control unit of the second shift register module is electrically connected with the first node of the first shift register module; the pull-down control unit of the second shift register module transmits the first level signal of the first level signal end to the second node of the second shift register module under the control of the potential of the first node of the first shift register module.

2. The shift register unit of claim 1, wherein each of the shift register modules further comprises a reset unit and a reset control terminal;

in the same shift register module, the reset unit is electrically connected with the reset control end, the first level signal end and the signal output end respectively; the reset unit is used for transmitting the first level signal to the signal output end under the control of a reset control signal of the reset control end.

3. The shift register cell of claim 1, wherein each of the shift register modules further comprises a first capacitor;

in the same shift register module, the first capacitor is electrically connected between the clock signal terminal and the second node.

4. The shift register cell of claim 1, wherein each of the shift register modules further comprises a second capacitor;

in the same shift register module, the second capacitor is electrically connected between the signal output end and the first node.

5. A shift register circuit, comprising: cascaded multistage shift register units; the shift register unit is a shift register unit according to any one of claims 1 to 4.

6. The shift register circuit of claim 5, further comprising: a start signal terminal, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, and a first level signal transmission line;

the signal input ends of the two shift register modules in the first stage shift register unit are electrically connected with the starting signal end; the signal input ends of the two shift register modules in each stage of shift register units from the second stage of shift register unit to the last stage of shift register unit are electrically connected with the signal output ends of the two shift register modules in the shift register unit of the upper stage;

when two shift register modules of each stage of shift register unit are a first shift register module and a second shift register module respectively, a clock signal end of the first shift register module of the ith stage of shift register unit is electrically connected with the first clock signal line, and a clock signal end of the second shift register module of the ith stage of shift register unit is electrically connected with the second clock signal line; the clock signal end of the first shift register module of the (i+1) -th shift register unit is electrically connected with the third clock signal line, and the clock signal end of the second shift register module of the (i+1) -th shift register unit is electrically connected with the fourth clock signal line; the first level signal end of the first shift register module and the first level signal end of the second shift register module of each level shift register unit are electrically connected with the first level signal transmission line;

Wherein i is an odd number; the polarity of the clock signal transmitted by the first clock signal line is opposite to that of the clock signal transmitted by the third clock signal line; when the ambient temperature is in the first preset range, the polarity of the clock signal transmitted by the second clock signal line is opposite to the polarity of the clock signal transmitted by the fourth clock signal line.

7. A driving method of a shift register circuit for driving the shift register circuit according to any one of claims 5 to 6, comprising:

acquiring the current ambient temperature;

when the ambient temperature is in a first preset range, controlling each level of shift register units to sequentially output the enabling level of the scanning signals, and simultaneously outputting the same scanning signals by two shift register modules of each level of shift register units;

8. A display panel, comprising: a display region and a non-display region surrounding the display region;

The non-display region includes the shift register circuit according to any one of claims 5 to 6;

9. The display panel according to claim 8, wherein the scanning signal line electrically connected to the pixels in odd-numbered rows is a first scanning signal line, and the scanning signal line electrically connected to the pixels in even-numbered rows is a second scanning signal line;

the shift register unit electrically connected to the first scan signal line and the shift register unit electrically connected to the second scan signal line are respectively located at opposite sides of the display area.

10. The display panel according to claim 9, wherein the two shift register modules of the shift register unit are a first shift register module and a second shift register module, respectively; when the ambient temperature is in a signal output stage of a second preset range, the signal output end of each first shift register module outputs the enabling level of the scanning signal to the scanning signal line;

The shift register units positioned on the same side are sequentially arranged along the column direction of the pixels, and the first shift register module and the second shift register module of the same shift register unit are adjacent.

11. The display panel according to claim 10, wherein the first shift register modules and the second shift register modules of the shift register units located on the same side are alternately arranged in sequence in the column direction of the pixels.

12. The display panel according to claim 10, wherein in each of the shift register units located on the same side, first shift register modules of two adjacent shift register units are adjacent, or second shift register modules of two adjacent shift register units are adjacent.

13. The display panel according to claim 8, wherein two shift register modules of the same shift register unit are respectively located at two opposite sides of the display area.

14. The display panel according to claim 13, wherein the two shift register modules of the shift register unit are a first shift register module and a second shift register module, respectively; when the ambient temperature is in a signal output stage of a second preset range, the signal output end of each first shift register module outputs the enabling level of the scanning signal to the scanning signal line;

The first shift register modules of the shift register units are positioned on the same side, and the second shift register modules of the shift register units are positioned on the same side;

or the first shift register module of the shift register unit electrically connected with the odd-numbered rows and the second shift register module of the shift register unit electrically connected with the even-numbered rows are positioned on the same side; and the second shift register module of the shift register unit electrically connected with the odd-numbered rows and the first shift register module of the shift register unit electrically connected with the even-numbered rows are located at the same side.

15. A display device, comprising: the display panel of any one of claims 8 to 14.