CN113763859B

CN113763859B - Shift register and driving method thereof, grid driving circuit, panel and device

Info

Publication number: CN113763859B
Application number: CN202111017317.2A
Authority: CN
Inventors: 李东华; 魏晓丽; 赖国昌; 李俊谊
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2024-02-23
Anticipated expiration: 2041-08-31
Also published as: CN113763859A

Abstract

The embodiment of the application provides a shift register, a driving method thereof, a grid driving circuit, a panel and a device, wherein the shift register comprises: the control end of the first output module is electrically connected with the first node, the first end of the first output module is electrically connected with the first power supply voltage signal end, and the second end of the first output module is electrically connected with the output end of the shift register; the control end of the second output module is electrically connected with the second node, the first end of the second output module is electrically connected with the first clock signal end, and the second end of the second output module is electrically connected with the output end of the shift register; the first node control module is electrically connected with the level control end, the second clock signal end and the first node and is used for transmitting a second clock signal of the second clock signal end to the first node under the control of the level control end; the second node control module is electrically connected with the third clock signal end, the first input signal end, the first scanning control signal end and the second node and used for controlling the potential of the second node. According to the embodiment of the application, the driving capability of the shift register can be improved.

Description

Shift register and driving method thereof, grid driving circuit, panel and device

Technical Field

The application belongs to the technical field of display, and particularly relates to a shift register, a driving method thereof, a grid driving circuit, a panel and a device.

Background

The display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines. For driving the gate lines, a gate driving circuit composed of a plurality of cascaded shift registers may be used to provide scan driving signals for the plurality of rows of gate lines, so as to control the plurality of rows of gate lines to be sequentially opened.

However, the inventors of the present application found that the voltage value of the scan driving signal output from the shift register in the related art cannot reach the expected voltage value, and the driving capability of the shift register is poor.

Disclosure of Invention

The embodiment of the application provides a shift register, a driving method thereof, a grid driving circuit, a panel and a device, which can enable the voltage value of a scanning driving signal output by the shift register to reach an expected voltage value and improve the driving capability of the shift register.

In a first aspect, embodiments of the present application provide a shift register, including:

the control end of the first output module is electrically connected with the first node, the first end of the first output module is electrically connected with the first power supply voltage signal end, and the second end of the first output module is electrically connected with the output end of the shift register;

The control end of the second output module is electrically connected with the second node, the first end of the second output module is electrically connected with the first clock signal end, and the second end of the second output module is electrically connected with the output end of the shift register;

the control end of the first node control module is electrically connected with the level control end, the first end of the first node control module is electrically connected with the second clock signal end, and the second end of the first node control module is electrically connected with the first node and is used for responding to the conduction level of the level control end and transmitting the second clock signal of the second clock signal end to the first node;

the second node control module is electrically connected to the third clock signal end, the first input signal end, the first scanning control signal end and the second node and is used for responding to the conduction level of the third clock signal end and the first scanning control signal end and transmitting the first input signal of the first input signal end to the second node.

In a second aspect, an embodiment of the present application provides a driving method of a shift register, where the shift register includes the shift register provided in the first aspect, and the driving method includes:

In the level output stage, the level control end is at a conduction level, and the first node control module is conducted in response to the conduction level of the level control end and transmits a second clock signal of the second clock signal end to the first node; the third clock signal end and the first scanning control signal end are in a conducting level, and the second node control module responds to the conducting level of the third clock signal end and the conducting level of the first scanning control signal end to conduct, and transmits a first input signal of the first input signal end to the second node.

In a third aspect, embodiments of the present application provide a gate driving circuit, which includes a plurality of cascaded shift registers as provided in the first aspect.

In a fourth aspect, embodiments of the present application provide a display panel, where the gate driving circuit includes a plurality of cascaded shift registers as provided in the first aspect.

In a fifth aspect, embodiments of the present application provide a display device including a display panel as provided in the fourth aspect.

The shift register, the driving method thereof, the grid driving circuit, the panel and the device of the embodiment of the application comprise the following steps: the control end of the first output module is electrically connected with the first node, the first end of the first output module is electrically connected with the first power supply voltage signal end, and the second end of the first output module is electrically connected with the output end of the shift register; the control end of the second output module is electrically connected with the second node, the first end of the second output module is electrically connected with the first clock signal end, and the second end of the second output module is electrically connected with the output end of the shift register; the control end of the first node control module is electrically connected with the level control end, the first end of the first node control module is electrically connected with the second clock signal end, and the second end of the first node control module is electrically connected with the first node and is used for responding to the conduction level of the level control end and transmitting the second clock signal of the second clock signal end to the first node; the second node control module is electrically connected to the third clock signal end, the first input signal end, the first scanning control signal end and the second node and is used for responding to the conduction level of the third clock signal end and the first scanning control signal end and transmitting the first input signal of the first input signal end to the second node. Compared with the prior art in which a transistor is arranged between the first node, the second node and the first power voltage signal terminal VGL, the potential of the first node is indirectly controlled by the second node, in this embodiment of the present application, since the potential of the first node can be controlled by the second clock signal input by the first node control module, that is, the potential of the first node is not indirectly controlled by the second node, the transistor is prevented from being arranged between the second node and the first power voltage signal terminal VGL, and the second node is prevented from leaking to the first power voltage signal terminal VGL through the transistor, thereby maintaining the potential of the control terminal (the second node) of the second output module, further ensuring that the voltage value of the scan driving signal output by the second output module can reach the expected voltage value, and improving the driving capability of the shift register.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

FIG. 1 is a schematic diagram of a shift register in the related art;

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a driving timing diagram of the shift register shown in FIG. 2;

FIG. 4 is a schematic diagram of another structure of a shift register according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a driving timing of the shift register shown in FIG. 4;

FIG. 6 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of another embodiment of a shift register according to the present disclosure;

FIG. 10 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram showing a driving timing of the shift register shown in FIG. 12;

FIG. 14 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram showing a driving timing of the shift register shown in FIG. 14;

FIG. 16 is a schematic flow chart of a driving method of a shift register according to an embodiment of the present disclosure;

FIG. 17 is a schematic flow chart of another method for driving a shift register according to an embodiment of the present disclosure;

fig. 18 is a schematic flow chart of a driving method of a shift register according to an embodiment of the present disclosure;

fig. 19 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 20 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The transistor in the embodiment of the present application is described by taking an N-type transistor as an example, but the transistor is not limited to an N-type transistor, and may be replaced by a P-type transistor. For an N-type transistor, the on level is high and the off level is low. That is, the gate of the N-type transistor is on between the first and second poles when the gate is high, and is off between the first and second poles when the gate is low. For a P-type transistor, the on level is low and the off level is high. That is, when the control of the P-type transistor is at a very low level, the first pole and the second pole are turned on, and when the control of the P-type transistor is at a high level, the first pole and the second pole are turned off. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.

In the embodiments herein, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience in describing the circuit structure, and the first node, the second node, and the third node are not one actual circuit unit.

In the embodiment of the application, the power supply voltage signal output by the first power supply voltage signal end VGL is a negative voltage signal, and the voltage value is as 7V; the power voltage signal output by the second power voltage signal terminal VGH is a positive voltage signal, and the voltage value is +7v.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes a problem existing in the prior art:

The inventor of the present application found that the voltage value of the scan driving signal output by the shift register in the related art cannot reach the expected voltage value, and the driving capability of the shift register is poor. In order to solve the problems that the voltage value of the scanning driving signal output by the shift register cannot reach the expected voltage value and the driving capability of the shift register is poor, the inventor of the application firstly researches and analyzes the root cause of the technical problems, and the specific research and analysis process is as follows:

the inventors of the present application found that, as shown in fig. 1, the control method adopted in the related art is a method in which the first node N1 and the second node N2 are indirectly controlled by each other, that is, if the potential of the second node N2 changes, the change of the potential of the first node N1 is necessarily caused. Specifically, the first node N1 is configured to control on or off of the transistor M1, and when the potential of the first node N1 is at a high level, the transistor M1 is turned on, and the signal of the first power voltage signal terminal VGL is transmitted to the second node N2, so that the potential of the second node N2 is at a low level. The second node N2 is configured to control on or off of the transistor M2, and when the potential of the second node N2 is at a high level, the transistor M2 is turned on, and the signal of the first power voltage signal terminal VGL is transmitted to the first node N1, so that the potential of the first node N1 is at a low level. In general, the potential of the first node N1 and the potential of the second node N2 are always opposite. When the potential of the first node N1 is at a high level and the potential of the second node N2 is at a low level, the transistor M3 is turned on and the transistor M4 is turned off, and the signal of the first power voltage signal terminal VGL is transmitted to the output terminal Gout of the shift register through the transistor M3. When the potential of the first node N1 is at a low level and the potential of the second node N2 is at a high level, the transistor M3 is turned off and the transistor M4 is turned on, and the signal of the clock signal terminal OUT' is transmitted to the output terminal Gout of the shift register through the transistor M4.

However, the transistor M1 cannot be completely turned off due to the characteristics of the transistor itself, and there is a leakage current. When the potential of the second node N2 is at the high level, the potential of the second node N2 is reduced due to the leakage current of the second node N2 to the first power voltage signal terminal VGL through the transistor M1 because the potential of the first power voltage signal terminal VGL is lower than the potential of the second node N2. As the potential of the second node N2 decreases, the switching degree of the transistor M4 decreases, so that the current/voltage of the scan driving signal transmitted by the transistor M4 decreases, and the voltage value of the scan driving signal output by the transistor M4 cannot reach the expected voltage value, thereby making the driving capability of the shift register worse.

In view of the above-mentioned research of the inventor, the embodiment of the application provides a shift register, a driving method thereof, a gate driving circuit, a panel and a device, which can solve the technical problems that the voltage value of a scanning driving signal output by the shift register cannot reach an expected voltage value and the driving capability of the shift register is poor in the related art.

The technical conception of the embodiment of the application is as follows: compared with the prior art in which the transistor M1 is disposed between the first node N1, the second node N2 and the first power voltage signal terminal VGL, in the embodiment of the present application, the potential of the first node N1 is controlled by the second clock signal input by the first node control module in a manner that the second node N2 indirectly controls the potential of the first node N1, that is, the second node N2 does not indirectly control the potential of the first node N1 any more, so that the transistor M1 is prevented from being disposed between the second node N2 and the first power voltage signal terminal VGL, and the second node N2 is prevented from leaking current to the first power voltage signal terminal VGL through the transistor M1, thereby maintaining the potential of the second node N2, and further ensuring that the voltage value of the scan driving signal output by the transistor M4 can reach the expected voltage value, and improving the driving capability of the shift register.

The shift register provided in the embodiment of the present application will be first described below.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present application. As shown in fig. 2, the shift register 20 provided in an embodiment of the present application may include a first output module 201, a second output module 202, a first node control module 203, and a second node control module 204.

The control terminal of the first output module 201 is electrically connected to the first node N1, the first terminal of the first output module 201 is electrically connected to the first power voltage signal terminal VGL, and the second terminal of the first output module 201 is electrically connected to the output terminal Gout of the shift register 20. The control terminal of the second output module 202 is electrically connected to the second node N2, the first terminal of the second output module 202 is electrically connected to the first clock signal terminal OUT, and the second terminal of the second output module 202 is electrically connected to the output terminal Gout of the shift register 20. The control end of the first node control module 203 is electrically connected to the level control end S1, the first end of the first node control module 203 is electrically connected to the second clock signal end Set1, and the second end of the first node control module 203 is electrically connected to the first node N1, for transmitting the second clock signal of the second clock signal end Set1 to the first node N1 in response to the on level of the level control end S1. The second node control module 204 is electrically connected to the third clock signal terminal Set2, the first input signal terminal IN, the first scan control signal terminal S2, and the second node N2, and is configured to transmit the first input signal of the first input signal terminal IN to the second node N2 IN response to the conduction levels of the third clock signal terminal Set2 and the first scan control signal terminal S2.

In this way, the potential of the first node N1 is controlled by the first node control module 203, and the potential of the second node N2 is controlled by the second node control module 204. The potential of the first node N1 and the potential of the second node N2 are controlled independently, that is, the potential of the first node N1 is not controlled indirectly through the second node N2, so that a transistor is prevented from being arranged between the second node N2 and the first power voltage signal terminal VGL, leakage current of the second node N2 to the first power voltage signal terminal VGL through the transistor is prevented, the potential of the second node N2 is maintained, the voltage value of the scanning driving signal output by the second output module 202 is further ensured to reach an expected voltage value, and the driving capability of the shift register is improved.

For ease of understanding, the control procedure of the first node control module 203 and the second node control module 204 is illustrated below in connection with fig. 3.

As shown in fig. 3, optionally, according to some embodiments of the present application, the driving timing of the shift register 20 of an embodiment of the present application includes: a first low level output stage t1, a second low level output stage t2, and a high level output stage t3.

For example, in the first low level output stage t1, the level control terminal S1 is at a conductive level, the first node control module 203 is turned on in response to the conductive level of the level control terminal S1, the conductive level of the second clock signal terminal Set1 is transmitted to the first node N1, the first output module 201 is turned on in response to the conductive level of the first node N1, and the low level output by the first power voltage signal terminal VGL is transmitted to the output terminal Gout of the shift register 20. The third clock signal terminal Set2 and the first scan control signal terminal S2 are at an on level, the second node control module 204 is turned on IN response to the on level of the third clock signal terminal Set2 and the first scan control signal terminal S2, and transmits the off level of the first input signal terminal IN to the second node N2, and the second output module 202 is turned off IN response to the off level of the second node N2.

For example, in the second low level output stage t2, the level control terminal S1 is at the on level, the first node control module 203 is turned on in response to the on level of the level control terminal S1, the on level of the second clock signal terminal Set1 is transmitted to the first node N1, the first output module 201 is turned on in response to the on level of the first node N1, and the low level output by the first power voltage signal terminal VGL is transmitted to the output terminal Gout of the shift register 20. The third clock signal terminal Set2 and the first scan control signal terminal S2 are at a conductive level, the second node control module 204 is turned on IN response to the third clock signal terminal Set2 and the first scan control signal terminal S2 being at a conductive level, the conductive level of the first input signal terminal IN is transmitted to the second node N2, the second output module 202 is turned on IN response to the conductive level of the second node N2, and the low level output from the first clock signal terminal OUT is transmitted to the output terminal Gout of the shift register 20.

For example, in the high level output stage t3, the level control terminal S1 is at an on level, the first node control module 203 is turned on in response to the on level of the level control terminal S1, the off level of the second clock signal terminal Set1 is transmitted to the first node N1, and the first output module 201 is turned off in response to the off level of the first node N1. The second node N2 maintains a turn-on level, and the second output module 202 is turned on in response to the turn-on level of the second node N2, and transmits the high level output from the first clock signal terminal OUT to the output terminal Gout of the shift register 20.

As shown in fig. 4, according to some embodiments of the present application, the level control terminal S1 may optionally include a second node N2, that is, the on/off of the first node control module 203 is controlled by the second node N2.

In this way, since the level control terminal S1 multiplexes the second node N2, it is not necessary to additionally add a control signal line/terminal to control on/off of the first node control module 203, thereby reducing the number of wirings, saving the wiring space, and reducing the production cost.

With continued reference to fig. 4, accordingly, the shift register 20 provided in an embodiment of the present application may further include a first reset module 205, where a control end of the first reset module 205 is electrically connected to the reset signal end Set3, a first end of the first reset module 205 is electrically connected to the second power voltage signal end VGH, and a second end of the first reset module 205 is electrically connected to the first node N1. As shown in fig. 5, unlike the driving timing shown in fig. 3, in the first low level output stage t1, the potential of the first node N1 is controlled by the first reset module 205. Specifically, in the case where the level control terminal S1 multiplexes the second node N2, since the second node N2 in the first low level output stage t1 is at the off level, the first node control module 203 is in the off state under the control of the off level of the second node N2, and cannot transmit the on level of the second clock signal terminal Set1 to the first node N1, the on level may be transmitted to the first node N1 by the first reset module 205, so that the potential of the first node N1 is the on level. That is, in the embodiment shown in fig. 5, in the first low level output stage t1, the first reset module 205 is turned on in response to the on level of the reset signal terminal Set3, and transmits the on level of the second power voltage signal terminal VGH to the first node N1 so that the potential of the first node N1 is the on level.

At other times except for the first low level output stage t1, the first reset module 205 may also be turned on in response to the on level of the reset signal terminal Set3 to transmit the second power voltage signal of the second power voltage signal terminal VGH to the first node N1 to reset the first node N1. Optionally, a reset phase may also be included after the high level output phase t 3. In the reset phase, the first reset module 205 is turned on in response to the on level of the reset signal terminal Set3, and transmits the second power voltage signal of the second power voltage signal terminal VGH to the first node N1 to reset the first node N1. By resetting the first node N1, the first node N1 can be prevented from being in a negative bias state for a long time, and the first node N1 can be ensured to be able to normally write an expected potential.

It should be noted that, the specific process of the second low-level output stage t2 and the high-level output stage t3 in the embodiment shown in fig. 5 is the same as the specific process of the second low-level output stage t2 and the high-level output stage t3 in the embodiment shown in fig. 3, and will not be described herein.

As shown in fig. 6, at least two of the reset signal terminal Set3, the second clock signal terminal Set1, and the third clock signal terminal Set2 may optionally be multiplexed according to some embodiments of the present application. That is, any two of the reset signal terminal Set3, the second clock signal terminal Set1, and the third clock signal terminal Set2 may be multiplexed, or three of the reset signal terminal Set3, the second clock signal terminal Set1, and the third clock signal terminal Set2 may be multiplexed. When the reset signal terminal Set3 and the third clock signal terminal Set2 both multiplex the second clock signal terminal Set1, the second clock signal terminal Set1 may output an on level in both the first low level output stage t1 and the second low level output stage t2, and output an off level in the high level output stage t 3.

In this way, since at least two of the reset signal terminal Set3, the second clock signal terminal Set1, and the third clock signal terminal Set2 are multiplexed, the number of wirings can be reduced, the wiring space can be saved, and the production cost can be reduced.

As shown in fig. 7, optionally, according to some embodiments of the present application, the shift register 20 provided in an embodiment of the present application may further include a first coupling module 206, a first end of the first coupling module 206 is electrically connected to the second node N2, and a second end of the first coupling module 206 is electrically connected to the output terminal Gout of the shift register 20.

In the high level output stage t3, the output terminal Gout of the shift register 20 transitions from the low level output stage t2 to the high level output, i.e. the potential of the second terminal of the first coupling module 206 transitions. The first coupling module 206 is coupled under the influence of the potential jump at one end, so that the potential at the first end (the second node N2) of the first coupling module 206 is pulled up from a higher voltage value to a higher voltage value, so that the second output module 202 is turned on more thoroughly, and the second output module 202 can output a high-level signal with a higher voltage value, and the stability of the second output module 202 outputting the high-level signal is maintained.

With continued reference to fig. 7, the shift register 20 provided in an embodiment of the present application may optionally further include a third node N3 and a first switch module 207 according to some embodiments of the present application. The third node N3 is located between the second node N2 and the output terminal Gout of the shift register 20, and the first terminal of the first coupling module 206 and the control terminal of the second output module 202 are electrically connected to the third node N3. The control terminal of the first switch module 207 is electrically connected to the second power voltage signal terminal VGH, the first terminal of the first switch module 207 is electrically connected to the second node N2, and the second terminal of the first switch module 207 is electrically connected to the third node N3, and is configured to be turned off when the output terminal Gout of the shift register 20 outputs a high level, so as to disconnect the electrical connection between the second node N2 and the third node N3.

Specifically, in the high-level output stage t3, the first coupling module 206 is coupled to pull up the potential of the first end (the third node N3) of the first coupling module 206 from a higher voltage value to a higher voltage value. When the difference between the voltage value Vg of the control terminal of the first switch module 207 and the voltage value Vs of the second terminal of the first switch module 207 is smaller than or equal to the absolute value |V of the threshold voltage of the first switch module 207, which is influenced by the switching characteristics of the transistor itself _th When I, i.e. V _g -V _s ≤|V _th When the first switch module 207 is turned off, the electrical connection between the second node N2 and the third node N3 is disconnected. On the one hand, since the electrical connection between the second node N2 and the third node N3 is disconnected, the third node N3 can maintain a higher potential, so that the second output module 202 is turned on more thoroughly, and the second output module 202 is ensured to be capable of stabilizing a high level signal. On the other hand, since the electrical connection between the second node N2 and the third node N3 is disconnected, the potential of the second node N2 is not continuously pulled up, so that the voltage difference between the gate drain or the gate source of each transistor (such as the first node control module 203) connected to the second node N2 can be reduced, and the circuit stability can be improved.

The following describes each of the above modules in detail with reference to a schematic circuit diagram of a shift register according to an embodiment of the present application shown in fig. 8.

As shown in fig. 8, according to some embodiments of the present application, optionally, the first output module 201 may include a first transistor T1, a gate of the first transistor T1 is electrically connected to the first node N1, a first pole of the first transistor T1 is electrically connected to the first power voltage signal terminal VGL, and a second pole of the first transistor T1 is electrically connected to the output terminal Gout of the shift register 20. The first transistor T1 is turned on/off under the control of the on/off level of the first node N1. When the first node N1 is on, the first transistor T1 is turned on, and transmits the low level output from the first power voltage signal terminal VGL to the output terminal Gout of the shift register 20.

The second output module 202 may include a second transistor T2, a gate of the second transistor T2 is electrically connected to the second node N2, a first pole of the second transistor T2 is electrically connected to the first clock signal terminal OUT, and a second pole of the second transistor T2 is electrically connected to the output terminal Gout of the shift register 20. The second transistor T2 is turned on/off under the control of the on/off level of the second node N2. When the second node N2 is on, the second transistor T2 is turned on, and transmits the low level or the high level output from the first clock signal terminal OUT to the output terminal Gout of the shift register 20.

The first node control module 203 may include a third transistor T3, a gate of the third transistor T3 is electrically connected to the level control terminal S1, a first pole of the third transistor T3 is electrically connected to the second clock signal terminal Set1, and a second pole of the third transistor T3 is electrically connected to the first node N1. The third transistor T3 is turned on/off under the control of the on/off level output from the level control terminal S1. When the level control terminal S1 outputs the on level, the third transistor T3 is turned on, and the on level or the off level of the second clock signal terminal Set1 is transmitted to the first node N1 to control the potential of the first node N1.

The second node control module 204 may include a fourth transistor T4 and a fifth transistor T5, wherein a gate of the fourth transistor T4 is electrically connected to the first scan control signal terminal S2, and a first pole of the fourth transistor T4 is electrically connected to the first input signal terminal IN. The gate of the fifth transistor T5 is electrically connected to the third clock signal terminal Set2, the first pole of the fifth transistor T5 is electrically connected to the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5 is electrically connected to the second node N2. The fourth transistor T4 is turned on/off under the control of the on/off level outputted from the first scan control signal terminal S2. The fifth transistor T5 is turned on/off under the control of the on/off level output from the third clock signal terminal Set 2. When the first scan control signal terminal S2 outputs an on level and the third clock signal terminal Set2 outputs an off level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the on level or the off level output from the first input signal terminal IN is transmitted to the second node N2 to control the potential of the second node N2.

In this way, the potential of the first node N1 is controlled by the third transistor T3, and the potential of the second node N2 is controlled by the fourth transistor T4 and the fifth transistor T5. The potential of the first node N1 and the potential of the second node N2 are controlled independently, that is, the potential of the first node N1 is not controlled indirectly through the second node N2, so that a transistor is prevented from being arranged between the second node N2 and the first power voltage signal terminal VGL, leakage current of the second node N2 to the first power voltage signal terminal VGL through the transistor is prevented, the potential of the second node N2 is maintained, the voltage value of the scanning driving signal output by the second output module 202 is further ensured to reach an expected voltage value, and the driving capability of the shift register is improved.

With continued reference to fig. 8, according to some embodiments of the present application, optionally, the first reset module 205 may include a sixth transistor T6, where a gate of the sixth transistor T6 is electrically connected to the reset signal terminal Set3, a first pole of the sixth transistor T6 is electrically connected to the second power voltage signal terminal VGH, and a second terminal of the sixth transistor T6 is electrically connected to the first node N1. The sixth transistor T6 is turned on/off under the control of the on/off level output from the reset signal terminal Set 3. When the reset signal terminal Set3 outputs the on level, the sixth transistor T6 is turned on, and the on level of the second power voltage signal terminal VGH is transmitted to the first node N1, which may be used to reset the first node N1. By resetting the first node N1, the first node N1 can be prevented from being in a negative bias state for a long time, and the first node N1 can be ensured to be able to normally write an expected potential.

With continued reference to fig. 8, in accordance with some embodiments of the present application, the first coupling module 206 may optionally include a first coupling capacitor C1, a first plate of the first coupling capacitor C1 is electrically connected to the second node N2, and a second plate of the first coupling capacitor C1 is electrically connected to the output Gout of the shift register 20. The first coupling capacitor C1 may be used to maintain the potential of the second node N2, such as in the high-level output phase t3, and the first coupling capacitor C1 may maintain the potential of the second node N2 at the on-level. In the high-level output stage T3, the first coupling capacitor C1 is coupled, so that the second transistor T2 is turned on more thoroughly, and the second transistor T2 can output a high-level signal with a higher voltage value, and the stability of the second transistor T2 outputting the high-level signal is maintained.

As shown in fig. 9, the shift register 20 provided in an embodiment of the present application may further include a third node N3 and a first switch module 207 according to some embodiments of the present application. The third node N3 is located between the second node N2 and the output terminal Gout of the shift register 20, and the first plate of the first coupling capacitor C1 and the gate of the second transistor T2 are electrically connected to the third node N3. In the embodiment shown in fig. 9, the second transistor T2 is turned on/off under the control of the on/off level of the third node N3. When the third node N3 is on, the second transistor T2 is turned on, and transmits the low level or the high level output from the first clock signal terminal OUT to the output terminal Gout of the shift register 20.

With continued reference to fig. 9, the first switching module 207 may include a seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the second power voltage signal terminal VGH, a first pole of the seventh transistor T7 is electrically connected to the second node N2, and a second pole of the seventh transistor T7 is electrically connected to the third node N3. In the first low-level output stage T1 and the second low-level output stage T2, the seventh transistor T7 is in an on state. In the high level output stage t3, the first coupling capacitor C1 is coupled to pull up the potential of the first plate (the third node N3) of the first coupling capacitor C1 from a higher voltage value to a higher voltage value. Under the influence of the switching characteristics of the transistors, when the voltage Vg of the gate of the seventh transistor T7 is different from the voltage Vs of the source of the seventh transistor T7 An absolute value |v smaller than or equal to the threshold voltage of the seventh transistor T7 _th When I, i.e. V _g -V _s ≤|V _th When i, the seventh transistor T7 is turned off, thereby disconnecting the electrical connection between the second node N2 and the third node N3. On the one hand, since the electrical connection between the second node N2 and the third node N3 is disconnected, the third node N3 can maintain a higher potential, so that the second transistor T2 is turned on more thoroughly, and the second transistor T2 is ensured to be capable of stabilizing a high-level signal. On the other hand, since the electrical connection between the second node N2 and the third node N3 is disconnected, the potential of the second node N2 is not continuously pulled up, and the voltage difference between the gate drain or the gate source of each transistor (e.g., the third transistor T3) connected to the second node N2 can be reduced, thereby improving the circuit stability.

With continued reference to fig. 9, the shift register 20 provided in an embodiment of the present application may further include a storage capacitor C2, where a first plate of the storage capacitor C2 may be electrically connected to the first node N1, and a second plate of the storage capacitor C2 may be electrically connected to the first power voltage signal terminal VGL for maintaining the potential of the first node N1.

As shown in fig. 10, the shift register 20 provided in an embodiment of the present application may optionally further include a discharging module 208 according to some embodiments of the present application. The discharge module 208 may include: an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The gate of the eighth transistor T8, the gate of the ninth transistor T9, and the gate of the tenth transistor T10 are all electrically connected to the discharge control terminal GAS. The first pole of the eighth transistor T8 is electrically connected to the first power voltage signal terminal VGL, and the second pole of the eighth transistor T8 is electrically connected to the first node N1. A first pole of the ninth transistor T9 is electrically connected to the first power voltage signal terminal VGL, and a second pole of the ninth transistor T9 is electrically connected to the second node N2. The first pole of the tenth transistor T10 is electrically connected to the second power voltage signal terminal VGH, and the second pole of the tenth transistor T10 is electrically connected to the output terminal Gout of the shift register 20.

In the embodiment shown in fig. 10, the discharge control terminal GAS is used to simultaneously control on or off of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 to reduce the number of control signal lines/terminals, save wiring space, and reduce production costs. When the eighth transistor T8 is turned on, the signal of the first power voltage signal terminal VGL may be transmitted to the first node N1 to discharge the first node N1. When the ninth transistor T9 is turned on, the signal of the first power voltage signal terminal VGL may be transmitted to the second node N2 to discharge the second node N2. When the tenth transistor T10 is turned on, a signal of the second power voltage signal terminal VGH may be transmitted to the output terminal Gout of the shift register 20 to discharge the output terminal Gout of the shift register 20.

As shown in fig. 11, the shift register 20 provided in an embodiment of the present application may optionally further include a second reset module 209 according to some embodiments of the present application. The second reset module 209 may include an eleventh transistor T11, a gate of the eleventh transistor T11 may be electrically connected to the reset terminal Greset, a first pole of the eleventh transistor T11 may be electrically connected to the first power voltage signal terminal VGL, and a second pole of the eleventh transistor T11 may be electrically connected to the output terminal Gout of the shift register 20 for being turned on in response to an on level of the reset terminal Greset, and transmitting a signal of the first power voltage signal terminal VGL to the output terminal Gout of the shift register 20 to reset the output terminal Gout of the shift register 20. In practical applications, the second reset module 209 may reset the output terminal Gout of the shift register 20 when the display device applied by the shift register 20 is powered down and powered up, so as to pull the potential of the output terminal Gout of the shift register 20 to be low, and avoid the power up display disorder phenomenon.

As shown IN fig. 12, the first input signal terminal IN may optionally include a normal scan input signal terminal INF and a reverse scan input signal terminal INB, and the first scan control signal terminal S2 may include a forward scan control signal terminal U2D and a reverse scan control signal terminal D2U, according to some embodiments of the present application. Accordingly, the fourth transistor T4 may include a first sub-transistor T41 and a second sub-transistor T42. The gate of the first sub-transistor T41 is electrically connected to the forward scan control signal terminal U2D, the first pole of the first sub-transistor T41 is electrically connected to the forward scan input signal terminal INF, and the second pole of the first sub-transistor T41 is electrically connected to the first pole of the fifth transistor T5. The gate of the second sub-transistor T42 is electrically connected to the inverse scan control signal terminal D2U, the first pole of the second sub-transistor T42 is electrically connected to the inverse scan input signal terminal INB, and the second pole of the second sub-transistor T42 is electrically connected to the first pole of the fifth transistor T5.

In the forward scanning, the potential of the second node N2 is controlled by the first sub-transistor T41 and the fifth transistor T5. At the time of the reverse scanning, the potential of the second node N2 is controlled by the second sub-transistor T42 and the fifth transistor T5.

Specifically, during the forward scanning, the second sub-transistor T42 is in an off state, and the first sub-transistor T41 is turned on/off under the control of the on/off level output from the forward scanning control signal terminal U2D. The fifth transistor T5 is turned on/off under the control of the on/off level output from the third clock signal terminal Set 2. When the forward scan control signal terminal U2D outputs the on level and the third clock signal terminal Set2 outputs the on level, the first sub-transistor T41 and the fifth transistor T5 are turned on, and the on level or the off level output from the forward scan input signal terminal INF is transmitted to the second node N2, so as to control the potential of the second node N2. At the time of the reverse scan, the first sub-transistor T41 is in an off state, and the second sub-transistor T42 is turned on/off under the control of the on/off level output from the reverse scan control signal terminal D2U. The fifth transistor T5 is turned on/off under the control of the on/off level output from the third clock signal terminal Set 2. When the reverse scan control signal terminal D2U outputs the on level and the third clock signal terminal Set2 outputs the on level, the second sub-transistor T42 and the fifth transistor T5 are turned on, and the on level or the off level output from the reverse scan input signal terminal INB is transmitted to the second node N2 to control the potential of the second node N2.

Fig. 13 is a timing diagram of driving the circuit shown in fig. 12. The following describes the operation principle of the shift register 20 according to an embodiment of the present application with reference to fig. 12 and 13 by taking forward scanning as an example.

As shown in fig. 12 and 13, in the first low level output stage T1, the level control terminal S1 outputs a turn-on level, the third transistor T3 is turned on in response to the turn-on level of the level control terminal S1, the turn-on level of the second clock signal terminal Set1 is transmitted to the first node N1, the first transistor T1 is turned on in response to the turn-on level of the first node N1, and the low level output from the first power voltage signal terminal VGL is transmitted to the output terminal Gout of the shift register 20. The forward scan control signal terminal U2D outputs a turn-on level, the first sub-transistor T41 is turned on in response to the turn-on level of the forward scan control signal terminal U2D, and the fifth transistor T5 is turned on in response to the turn-on level of the second clock signal terminal Set 1. The off level output by the normal scan input signal terminal INF is transmitted to the second node N2 through the first sub-transistor T41 and the fifth transistor T5, and is transmitted to the third node N3 through the turned-on seventh transistor T7, and both the second node N2 and the third node N3 are off levels. The second transistor T2 is turned off in response to the off level of the third node N3.

In the second low level output stage T2, the level control terminal S1 outputs a turn-on level, the third transistor T3 is turned on in response to the turn-on level of the level control terminal S1, the turn-on level of the second clock signal terminal Set1 is transmitted to the first node N1, the first transistor T1 is turned on in response to the turn-on level of the first node N1, and the low level output from the first power voltage signal terminal VGL is transmitted to the output terminal Gout of the shift register 20. The forward scan control signal terminal U2D outputs a turn-on level, the first sub-transistor T41 is turned on in response to the turn-on level of the forward scan control signal terminal U2D, and the fifth transistor T5 is turned on in response to the turn-on level of the second clock signal terminal Set 1. The turn-on level of the normal scan input signal INF is transmitted to the second node N2 through the first sub-transistor T41 and the fifth transistor T5, and is transmitted to the third node N3 through the turned-on seventh transistor T7, where the second node N2 and the third node N3 are both turned-on levels. The second transistor T2 is turned on in response to the turn-on level of the third node N3, and transmits the low level output from the first clock signal terminal OUT to the output terminal Gout of the shift register 20.

In the high level output stage T3, the level control terminal S1 outputs an on level, the third transistor T3 is turned on in response to the on level of the level control terminal S1, the off level of the second clock signal terminal Set1 is transmitted to the first node N1, and the first transistor T1 is turned off in response to the off level of the first node N1. The second node N2 and the third node N3 maintain the turn-on level by the first coupling capacitor C1, and the second transistor T2 is turned on in response to the turn-on level of the third node N3, and transmits the high level output from the first clock signal terminal OUT to the output terminal Gout of the shift register 20.

In the high-level output stage T3, the first coupling capacitor C1 is coupled, so that the potential of the first polar plate (the third node N3) of the first coupling capacitor C1 is pulled up from a higher voltage value to a higher voltage value, so that the second transistor T2 is turned on more thoroughly, and further the second transistor T2 can output a high-level signal with a higher voltage value, and the stability of the second transistor T2 outputting the high-level signal is maintained. When the difference between the voltage Vg of the gate of the seventh transistor T7 and the voltage Vs of the source of the seventh transistor T7 is smaller than or equal to the absolute value |V of the threshold voltage of the seventh transistor T7, due to the switching characteristics of the transistor _th When I, i.e. V _g -V _s ≤|V _th When i, the seventh transistor T7 is turned off, thereby disconnecting the electrical connection between the second node N2 and the third node N3. On the one hand, since the electrical connection between the second node N2 and the third node N3 is disconnected, the third node N3 can maintain a higher potential, so that the second transistor T2 is turned on more thoroughly, and the second transistor T2 is ensured to be capable of stabilizing a high-level signal. On the other hand, since the electrical connection between the second node N2 and the third node N3 is disconnected, the potential of the second node N2 is not continuously pulled high, and a voltage difference between the gate drain or the gate source of each transistor (e.g., the third transistor T3) connected to the second node N2 can be reduced.

Fig. 14 is a schematic circuit diagram of a shift register according to an embodiment of the present application. Fig. 15 is a driving timing diagram of the circuit shown in fig. 14. As shown in fig. 14, unlike the embodiment shown in fig. 12, in the embodiment shown in fig. 14, the level control terminal S1 multiplexes the second node N2. Accordingly, as shown in fig. 15, in the first low level output stage T1, the forward scan control signal terminal U2D outputs a turn-on level, the first sub-transistor T41 is turned on in response to the turn-on level output from the forward scan control signal terminal U2D, and the fifth transistor T5 is turned on in response to the turn-on level output from the second clock signal terminal Set 1. The off level output by the normal scan input signal terminal INF is transmitted to the second node N2 through the first sub-transistor T41 and the fifth transistor T5, and is transmitted to the third node N3 through the turned-on seventh transistor T7, and both the second node N2 and the third node N3 are off levels. The second transistor T2 is turned off in response to the off level of the third node N3. Since the second node N2 is at the off level, the third transistor T3 is turned off. The sixth transistor T6 is turned on in response to the on level output from the second clock signal terminal Set1, transmits the on level of the second power voltage signal terminal VGH to the first node N1, and the first transistor T1 is turned on in response to the on level of the first node N1, and transmits the low level output from the first power voltage signal terminal VGL to the output terminal Gout of the shift register 20.

It should be noted that, the specific processes of the second low level output stage t2 and the high level output stage t3 in the embodiment shown in fig. 15 are the same as or similar to the specific processes of the second low level output stage t2 and the high level output stage t3 in the embodiment shown in fig. 13, and are not described herein.

Based on the shift register provided in the foregoing embodiment, correspondingly, the present application further provides a specific implementation manner of a driving method of the shift register. Please refer to the following examples.

As shown in fig. 16, the driving method of the shift register provided in the embodiment of the present application includes the following steps:

s101, in a level output stage, a level control end is in a conduction level, a first node control module is conducted in response to the conduction level of the level control end, and a second clock signal of a second clock signal end is transmitted to a first node; the third clock signal end and the first scanning control signal end are in a conducting level, and the second node control module responds to the conducting level of the third clock signal end and the conducting level of the first scanning control signal end to conduct, and transmits a first input signal of the first input signal end to the second node.

Thus, the potential of the first node is controlled by the first node control module and the potential of the second node is controlled by the second node control module. The potential of the first node and the potential of the second node are independently controlled, namely the potential of the first node is not indirectly controlled through the second node, so that a transistor is prevented from being arranged between the second node and the first power supply voltage signal end, leakage current of the second node to the first power supply voltage signal end through the transistor is prevented, the potential of the second node is maintained, the voltage value of a scanning driving signal output by the second output module is further ensured to reach an expected voltage value, and the driving capability of the shift register is improved.

As shown in fig. 17, S101 may optionally include step S1011 according to some embodiments of the present application: the first low-level output stage, the level control end is in the conductive level, the first node control module is conductive in response to the conductive level of the level control end, the conductive level of the second clock signal end is transmitted to the first node, the first output module is conductive in response to the conductive level of the first node, and the low level output by the first power supply voltage signal end is transmitted to the output end of the shift register; the third clock signal end and the first scanning control signal end are in on level, the second node control module is conducted in response to the on level of the third clock signal end and the first scanning control signal end, the cut-off level of the first input signal end is transmitted to the second node, and the second output module is cut-off in response to the cut-off level of the second node.

As shown in fig. 17, optionally, after S1011, S101 may further include step S1012: the second low level output stage, the level control end is in the conductive level, so that the first node control module transmits the conductive level of the second clock signal end to the first node, the first output module responds to the conductive level of the first node to conduct, and the low level output by the first power supply voltage signal end is transmitted to the output end of the shift register; the second node control module is in conduction with the first scanning control signal end in response to the conduction level of the third clock signal end and the first scanning control signal end, the conduction level of the first input signal end is transmitted to the second node, the second output module is in conduction with the conduction level of the second node, and the low level output by the first clock signal end is transmitted to the output end of the shift register.

As shown in fig. 17, optionally, after S1012, S101 may further include step S1013: a high level output stage, wherein the level control end is in an on level so that the first node control module transmits the cut-off level of the second clock signal end to the first node, and the first output module is cut-off in response to the cut-off level of the first node; the second node keeps the conducting level, and the second output module is conducted in response to the conducting level of the second node and transmits the high level output by the first clock signal end to the output end of the shift register.

As shown in fig. 18, according to other embodiments of the present application, the level control terminal optionally multiplexes the second node. Accordingly, in the embodiment shown in fig. 18, S101 may include steps S1012 'and S1013', step S1012 'being the same as the specific process of step S1012 described above, and step S1013' being the same as the specific process of step S1013 described above. In addition, before S101, the driving method of the shift register provided in the embodiment of the present application may further include step S100: a first low level output stage, in which the reset signal terminal outputs a conduction level, the first reset module is conducted in response to the conduction level of the reset signal terminal, the conduction level of the second power supply voltage signal terminal is transmitted to the first node, the first output module is conducted in response to the conduction level of the first node, and the low level output by the first power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third clock signal end and the first scanning control signal end are in on level, the second node control module is conducted in response to the on level of the third clock signal end and the first scanning control signal end, the cut-off level of the first input signal end is transmitted to the second node, and the second output module is cut-off in response to the cut-off level of the second node.

The steps in the driving method of the shift register shown in fig. 16 to 18 have been described in detail when the shift register is introduced, and are not described herein for brevity.

Based on the shift register 20 provided in the above embodiment, correspondingly, the embodiment of the application further provides a gate driving circuit. As shown in fig. 19, the gate driving circuit 100 provided in the embodiment of the present application includes a plurality of cascaded shift registers 20. The output terminal Gout of the shift register 20 may be electrically connected to the scan signal line S in the display panel to supply the scan driving signal to the sub-pixel connected to the scan signal line S.

Note that, the gate driving circuit 100 may be located on one side of the display panel or may be located on two sides of the display panel. That is, the display panel to which the gate driving circuit 100 is applied may adopt a single-side scanning (or referred to as single-side driving) method, may adopt a double-side scanning (or referred to as double-side driving) method, and may also adopt a cross-scanning method, which is not limited in the embodiment of the present application.

Based on the shift register 20 provided in the above embodiment, correspondingly, the embodiment of the application also provides a display panel. As shown in fig. 20, the display panel 1000 provided in the embodiment of the present application includes a plurality of cascaded shift registers 20. The display panel 1000 may further include scan signal lines S sequentially arranged in a column direction. The output terminal Gout of the shift register 20 may be electrically connected to the scan signal line S to supply a scan driving signal to the sub-pixels connected to the scan signal line S.

Based on the shift register 20 and the display panel 1000 provided in the foregoing embodiments, correspondingly, the embodiment of the present application further provides a display device 200, as shown in fig. 21, where the display device 200 may include a device body 2000 and the display panel 1000 in the foregoing embodiments, and the display panel 1000 is covered on the device body 2000. Various devices, such as a sensing device, a processing device, etc., may be provided in the apparatus body 2000, which is not limited herein. The display device 200 may be a device having a display function, such as a mobile phone, a computer, a tablet computer, a digital camera, a television, and an electronic paper, and is not limited thereto.

It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. For the display panel embodiment and the display device embodiment, reference may be made to the description of the pixel driving circuit embodiment and the array substrate embodiment. The present application is not limited to the specific constructions described above and shown in the drawings. Various changes, modifications and additions may be made by those skilled in the art after appreciating the spirit of the present application. Also, a detailed description of known techniques is omitted herein for the sake of brevity.

Those skilled in the art will appreciate that the above-described embodiments are exemplary and not limiting. The different technical features presented in the different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in view of the drawings, the description, and the claims. In the claims, the term "comprising" does not exclude other structures; the amounts refer to "a" and do not exclude a plurality; the terms "first," "second," and the like, are used for designating a name and not for indicating any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The presence of certain features in different dependent claims does not imply that these features cannot be combined to advantage.

Claims

1. A shift register, comprising:

the second node control module is electrically connected to a third clock signal end, a first input signal end, a first scanning control signal end and the second node, and is used for responding to the conduction level of the third clock signal end and the first scanning control signal end and transmitting a first input signal of the first input signal end to the second node.

2. The shift register of claim 1, wherein said level control terminal comprises said second node.

3. The shift register of claim 1, further comprising:

the first reset module, the control end and the reset signal end of first reset module are connected, the first end and the second power voltage signal end of first reset module are connected, the second end of first reset module with first node electricity is connected for responding to reset signal end's turn on level and switch on, will the second power voltage signal of second power voltage signal end is transmitted to first node to reset the first node.

4. A shift register as claimed in claim 3, in which at least two of the reset signal terminal, the second clock signal terminal and the third clock signal terminal are multiplexed.

5. The shift register of claim 1, further comprising:

and the first end of the first coupling module is electrically connected with the second node, and the second end of the first coupling module is electrically connected with the output end of the shift register.

6. The shift register of claim 5, further comprising:

the third node is positioned between the second node and the output end of the shift register, and the first end of the first coupling module and the control end of the second output module are electrically connected with the third node;

The control end of the first switch module is electrically connected with the second power supply voltage signal end, the first end of the first switch module is electrically connected with the second node, and the second end of the first switch module is electrically connected with the third node and is used for being turned off when the output end of the shift register outputs high level so as to disconnect the electrical connection between the second node and the third node.

7. The shift register as claimed in claim 1, wherein,

the first output module includes:

a first transistor, a gate of which is electrically connected to the first node, a first pole of which is electrically connected to the first power voltage signal terminal, and a second pole of which is electrically connected to the output terminal of the shift register;

the second output module includes:

a second transistor, a gate of which is electrically connected to the second node, a first electrode of which is electrically connected to the first clock signal terminal, and a second electrode of which is electrically connected to an output terminal of the shift register;

the first node control module includes:

A third transistor, a gate of which is electrically connected to the level control terminal, a first pole of which is electrically connected to the second clock signal terminal, and a second pole of which is electrically connected to the first node;

the second node control module includes:

a gate of the fourth transistor is electrically connected with the first scanning control signal end, and a first pole of the fourth transistor is electrically connected with the first input signal end;

and a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the third clock signal terminal, a first pole of the fifth transistor is electrically connected to a second pole of the fourth transistor, and a second pole of the fifth transistor is electrically connected to the second node.

8. The shift register of claim 1, further comprising a first reset module, the first reset module comprising:

and a sixth transistor, wherein the gate of the sixth transistor is electrically connected to the reset signal terminal, the first electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal, and the second terminal of the sixth transistor is electrically connected to the first node.

9. The shift register of claim 1, further comprising a first coupling module, the first coupling module comprising:

and the first polar plate of the first coupling capacitor is electrically connected with the second node, and the second polar plate of the first coupling capacitor is electrically connected with the output end of the shift register.

10. The shift register of claim 9, further comprising a third node and a first switch module;

the first switch module includes:

and a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the second power supply voltage signal terminal, a first pole of the seventh transistor is electrically connected to the second node, and a second pole of the seventh transistor is electrically connected to the third node.

11. A driving method of a shift register, characterized in that the shift register includes the shift register according to any one of claims 1 to 10, the driving method comprising:

A level output stage, wherein the level control end is at a conduction level, and the first node control module is conducted in response to the conduction level of the level control end and transmits a second clock signal of the second clock signal end to the first node; the third clock signal terminal and the first scan control signal terminal are at a conductive level, and the second node control module is conductive in response to the conductive levels of the third clock signal terminal and the first scan control signal terminal, and transmits a first input signal of the first input signal terminal to the second node.

12. The driving method according to claim 11, wherein the level output stage specifically comprises:

a first low level output stage, in which the level control terminal is at a conduction level, the first node control module is turned on in response to the conduction level of the level control terminal, the conduction level of the second clock signal terminal is transmitted to the first node, the first output module is turned on in response to the conduction level of the first node, and the low level output by the first power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third clock signal end and the first scanning control signal end are in a conducting level, the second node control module is conducted in response to the conducting level of the third clock signal end and the conducting level of the first scanning control signal end, the cut-off level of the first input signal end is transmitted to the second node, and the second output module is cut-off in response to the cut-off level of the second node.

13. The driving method according to claim 11, wherein the level control terminal includes the second node;

the shift register further comprises a first reset module, wherein the control end of the first reset module is electrically connected with a reset signal end, the first end of the first reset module is electrically connected with a second power supply voltage signal end, and the second end of the first reset module is electrically connected with the first node;

the driving method further includes:

a first low level output stage, in which the reset signal terminal outputs a conduction level, the first reset module is turned on in response to the conduction level of the reset signal terminal, the conduction level of the second power supply voltage signal terminal is transmitted to the first node, the first output module is turned on in response to the conduction level of the first node, and the low level output by the first power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third clock signal end and the first scanning control signal end are in a conducting level, the second node control module is conducted in response to the conducting level of the third clock signal end and the conducting level of the first scanning control signal end, the cut-off level of the first input signal end is transmitted to the second node, and the second output module is cut-off in response to the cut-off level of the second node.

14. The driving method according to claim 12 or 13, wherein after the first low level output phase, the level output phase specifically further comprises:

a second low level output stage, in which the level control terminal is at a conduction level, so that the first node control module transmits the conduction level of the second clock signal terminal to the first node, and the first output module is turned on in response to the conduction level of the first node, and transmits the low level output by the first power supply voltage signal terminal to the output terminal of the shift register; the third clock signal end and the first scanning control signal end are in a conduction level, the second node control module is conducted in response to the conduction level of the third clock signal end and the first scanning control signal end, the conduction level of the first input signal end is transmitted to the second node, the second output module is conducted in response to the conduction level of the second node, and the low level output by the first clock signal end is transmitted to the output end of the shift register.

15. The driving method according to claim 14, wherein after the second low level output stage, the level output stage specifically further comprises:

A high level output stage, wherein the level control terminal is in an on level so that the first node control module transmits the cut-off level of the second clock signal terminal to the first node, and the first output module is cut-off in response to the cut-off level of the first node; the second node keeps on level, and the second output module is conducted in response to the on level of the second node and transmits the high level output by the first clock signal end to the output end of the shift register.

16. A gate drive circuit comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 10.

17. A display panel comprising a plurality of cascaded shift registers according to any of claims 1-10.

18. A display device comprising the display panel of claim 17.