CN108172163B

CN108172163B - Shift register unit, shift register circuit and display panel thereof

Info

Publication number: CN108172163B
Application number: CN201810002740.7A
Authority: CN
Inventors: 高雪岭; 商广良; 王志冲
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2018-01-02
Filing date: 2018-01-02
Publication date: 2021-01-26
Anticipated expiration: 2038-01-02
Also published as: CN108172163A

Abstract

The disclosure relates to a shift register unit, a shift register circuit and a display panel thereof. The shift register unit includes: the input module is used for transmitting the input signal to a pull-up node and transmitting a first power supply signal to the pull-down node under the control of the input signal; a pull-up module for transmitting a clock signal to a signal output terminal and transmitting the first power signal to the pull-down node under control of a voltage signal of the pull-up node; the control module is used for transmitting the first power supply signal and/or the second power supply signal to a pull-down node under the control of the input signal and the voltage signal of the signal output end; and the pull-down module is used for transmitting the first power supply signal to the pull-up node and the signal output end under the control of a voltage signal of the pull-down node. The display device and the display method can avoid poor display caused by overlarge leakage current.

Description

Shift register unit, shift register circuit and display panel thereof

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, and a display panel thereof.

Background

With the development of optical technology and semiconductor technology, flat panel displays represented by Liquid Crystal Displays (LCDs) and Organic Light Emitting Diode (OLED) displays have the characteristics of lightness, thinness, low energy consumption, fast response speed, good color purity, high contrast ratio and the like, and have a leading position in the Display field.

Display devices have been developed to have high integration and low cost in recent years. Taking a Gate Driver on Array (GOA) technology as a representative example, the Gate driving circuit is integrated in a peripheral region of the Array substrate by using the GOA technology, so that the integration of the display device is effectively improved and the manufacturing cost thereof is reduced while the narrow frame design is realized. The output end of each stage of shift register unit in the GOA circuit is connected with a corresponding grid line and used for outputting a grid scanning signal to the grid line so as to realize the function of scanning line by line. However, since a Thin Film Transistor (TFT) is generally used as a switching element of a shift register unit, and the TFT itself has characteristics of a leakage current and a parasitic capacitance, various defects often occur in a shift register circuit, thereby causing a display abnormality.

Referring to the shift register unit in the related art shown in fig. 1 and the timing diagram shown in fig. 2, when the transistors M4, M5, and M6 are turned on, the leakage current is large and lasts for a while, so that the transistors M4, M5, and M6 generate heat due to over-high temperature, which causes the transistors to fail, affects the stability of the GOA circuit, and causes abnormal display.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a shift register unit, a shift register circuit and a display panel thereof, which overcome one or more of the problems due to the limitations and disadvantages of the related art, at least to some extent.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a shift register unit including:

the input module is used for transmitting the input signal to a pull-up node and transmitting a first power supply signal to the pull-down node under the control of the input signal;

a pull-up module for transmitting a clock signal to a signal output terminal and transmitting the first power signal to the pull-down node under control of a voltage signal of the pull-up node;

the control module is used for transmitting the first power supply signal and/or the second power supply signal to a pull-down node under the control of the input signal and the voltage signal of the signal output end;

and the pull-down module is used for transmitting the first power supply signal to the pull-up node and the signal output end under the control of a voltage signal of the pull-down node.

In an exemplary embodiment of the present disclosure, the control module includes:

a first control unit for transmitting the first power signal and/or the second power signal to the pull-down node under control of the input signal;

a second control unit for transmitting the first power signal and/or the second power signal to the pull-down node under control of the voltage signal of the signal output terminal.

In an exemplary embodiment of the present disclosure, the first control unit includes:

a first switch element, a control end of which receives the input signal, a first end of which receives the second power supply signal, and a second end of which is connected with a first end of a third switch element;

a second switch element, a control terminal of which receives the input signal, a first terminal of which receives the first power signal, and a second terminal of which is connected to a second terminal of the third switch element;

the second control unit includes:

the control end of the third switching element receives the voltage signal of the signal output end, the first end of the third switching element is connected with the second end of the first switching element, and the second end of the third switching element is connected with the second end of the second switching element;

and the control end of the fourth switching element receives the voltage signal of the signal output end, the first end of the fourth switching element receives the first power supply signal, and the second end of the fourth switching element is connected with the second end of the second switching element.

In an exemplary embodiment of the present disclosure, the input module includes:

a fifth switching element having a control terminal receiving the input signal, a first terminal receiving the input signal, and a second terminal connected to the pull-up node;

and a control end of the sixth switching element receives the input signal, a first end of the sixth switching element receives the first power supply signal, and a second end of the sixth switching element is connected with the pull-down node.

In an exemplary embodiment of the present disclosure, the pull-up module includes:

a seventh switching element, a control end of which is connected to the pull-up node, a first end of which receives the clock signal, and a second end of which is connected to the signal output end;

a first end of the storage capacitor is connected with the pull-up node, and a second end of the storage capacitor is connected with the signal output end;

and the control end of the eighth switching element is connected with the pull-up node, the first end of the eighth switching element receives the first power supply signal, and the second end of the eighth switching element is connected with the pull-down node.

In an exemplary embodiment of the present disclosure, the pull-down module includes:

a ninth switching element having a control terminal connected to the pull-down node, a first terminal receiving the first power signal, and a second terminal connected to the pull-up node;

a tenth switching element having a control terminal connected to the pull-down node, a first terminal receiving the first power signal, and a second terminal connected to the signal output terminal;

and an eleventh switching element having a control terminal connected to the second terminal of the third switching element, a first terminal connected to the second terminal of the third switching element, and a second terminal connected to the pull-down node.

In an exemplary embodiment of the present disclosure, further comprising:

a reset module for transmitting the first power signal to the pull-up node under control of a reset signal;

the reset module includes:

and a twelfth switching element, a control end of which is connected with a reset signal, a first end of which receives the first power supply signal, and a second end of which is connected with the pull-up node.

In an exemplary embodiment of the present disclosure, the first switching element and the third switching element are P-type MOS transistors, and the second switching element and the fourth switching element are N-type MOS transistors.

According to an aspect of the present disclosure, there is provided a shift register circuit comprising a plurality of cascaded shift register cells as described in any one of the above;

the output signal of the signal output end of the M-th stage shift register unit is the input signal of the M + 1-th stage shift register unit.

According to an aspect of the present disclosure, there is provided a display panel including a display area and a peripheral area; wherein the peripheral region is provided with any one of the shift register circuits described above.

According to the shift register unit, the shift register circuit and the display panel thereof provided by the exemplary embodiment of the disclosure, the control module is added on the basis of the traditional shift register unit structure, so that when an input signal is at a high level or a low level, no current path exists among the second power signal, the pull-down node and the first power signal, and the leakage current flowing through the transistor is reduced, thereby avoiding the heating phenomenon caused by the overhigh temperature of the transistor, improving the stability of the GOA circuit, and avoiding the poor display caused by the heating phenomenon.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 is a schematic diagram of a prior art shift register unit;

FIG. 2 is a schematic diagram showing a timing diagram of the operation of a shift register unit in the prior art;

FIG. 3 is a diagram schematically illustrating current simulation results of a shift register cell in the prior art;

FIG. 4 schematically illustrates a structural schematic diagram of a shift register cell in an exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a timing diagram of the operation of a shift register cell in an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates an equivalent circuit diagram of a shift register cell at a first stage in an exemplary embodiment of the present disclosure;

FIG. 7 schematically illustrates an equivalent circuit diagram of a shift register cell at a second stage in an exemplary embodiment of the disclosure;

fig. 8 schematically illustrates an equivalent circuit diagram of a shift register cell at a third stage in an exemplary embodiment of the present disclosure;

fig. 9 schematically illustrates an equivalent circuit diagram of a shift register unit at a fourth stage in an exemplary embodiment of the present disclosure;

FIG. 10 is a graph schematically illustrating simulation results of shift register cell currents in exemplary embodiments of the present disclosure;

fig. 11 schematically shows a cascade structure of the shift register circuit in the exemplary embodiment of the present disclosure.

Reference numerals:

M1-M12 first to twelfth transistors

C1 storage capacitor

Input signal

Output signal Output terminal

PU pull-up node

PD pull-down node

N1-N2 first and second nodes

CLK clock signal

RST reset signal

LVGL/VGL first power supply signal

VDD second power supply signal

Id leakage current

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

For example, referring to the shift register unit in the related art shown in fig. 1 and the timing diagram shown in fig. 2 thereof, when the Input signal Input is at a high level, the first transistor M1 is turned on to transmit the Input signal Input to the pull-up node PU, and the pull-up node PU is at a high level, so that the fifth transistor M5 is turned on to transmit the first power signal LVGL to the pull-down node PD, so as to pull down the level of the pull-down node PD. When the Input signal Input is at a high level, the sixth transistor M6 is turned on to transmit the first power signal LVGL to the pull-down node PD, thereby pulling the level of the pull-down node PD low. The fourth transistor M4 is turned on under the control of the second power signal VDD to transmit the second power signal VDD to the pull-down node PD, and 2 conductive paths are formed among the second power signal VDD, the PD node and the first power signal LVGL, wherein the direction of the arrow indicates the direction of the leakage current.

Referring again to the simulation result of the leakage current when the transistors M4, M5, M6 shown in fig. 3 are turned on, when the pull-up node PU discharges to the pull-down node PD, the magnitude of the leakage current flowing through the transistor M4 is above 400uA, and since the voltage amplitude of the pull-up node PU is pulled up again when the clock signal CLK is at a high level, the gate voltage acting on the M5 transistor is larger than the gate voltage acting on the M6, and according to the TFT saturation region leakage current formula Id ═ 1/2) ucox (W/L) (Vgs-Vth) ^2, the larger the Vgs-Vth value is, the larger the leakage current is, and therefore the leakage current flowing through the M4 is mostly distributed to the M5 drain terminal. Thus, the leakage current in the formed conductive path flows through the M4, M5, M6 tubes and lasts for a while, so that the M4, M5, M6 tubes generate heat due to over-high temperature, and further cause the transistor failure, which affects the stability of the GOA circuit, thereby causing the display abnormality.

The present exemplary embodiment proposes a shift register unit for providing a gate scan signal; as shown in fig. 4, the shift register unit may include:

an Input module 10, configured to transmit an Input signal Input to a pull-up node PU and transmit a first power signal LVGL to a pull-down node PD under control of the Input signal Input;

a pull-up module 20, configured to transmit a clock signal CLK to a signal Output terminal Output and transmit the first power signal LVGL to the pull-down node PD under the control of the voltage signal of the pull-up node PU;

a control module 30, configured to transmit a first power signal VGL and/or a second power signal VDD to the pull-down node PD under the control of the voltage signals of the Input signal Input and the signal Output terminal Output;

a pull-down module 40, configured to transmit the first power signal LVGL to the pull-up node PD and the signal Output terminal Output under the control of the voltage signal of the pull-down node PD.

In addition, the shift register unit may further include:

a reset module 50, configured to transmit the first power signal LVGL to the pull-up node PU under the control of a reset signal RST.

The shift register unit provided by the exemplary embodiment of the present disclosure adds a control module 30 on the basis of the structure of the conventional shift register unit, so that when the input signal is at a high level or a low level, no current path exists among the second power signal VDD, the pull-down node PD, and the first power signal LVGL, and the leakage current flowing through the transistors M11, M6, and M8 is reduced, thereby avoiding the heating phenomenon caused by the over-high temperature of the transistors, improving the stability of the GOA circuit, and avoiding the poor display caused thereby.

In this exemplary embodiment, the control module 30 may specifically include a first control unit and a second control unit; the first control unit is used for transmitting a second power supply signal VDD and/or a first power supply signal VGL to the pull-down node PD under the control of the Input signal Input; the second control unit is configured to transmit the second power signal VDD and/or the first power signal VGL to the pull-down node PD under the control of the voltage signal of the signal Output terminal Output.

It should be noted that: the control module 30 of the exemplary embodiment is configured to prevent a current path from being formed between the transistors M11, M6, and M8, and avoid a transistor heating phenomenon caused by a large leakage current, so as long as the above effects can be achieved, the control module 30 may be configured with one control unit or a plurality of control units, which is not particularly limited herein.

The shift register unit in the present exemplary embodiment is described in detail below with reference to fig. 4. As shown in fig. 4, taking the fifth to twelfth transistors as N-type transistors as an example, the control terminal may be a gate of the transistor, the first terminal may be a source of the transistor, and the second terminal may be a drain of the transistor; however, since the source and the drain of the transistor are not strictly distinguished, the first terminal may be the drain of the transistor and the second terminal may be the source of the transistor. Wherein:

the input module 10 may include: a fifth switching element having a control terminal receiving the Input signal, a first terminal receiving the Input signal, and a second terminal connected to the pull-up node PU; the input module 10 may further include: a control end of the sixth switching element receives the Input signal Input, a first end of the sixth switching element receives the first power signal LVGL, and a second end of the sixth switching element is connected to the pull-down node PD.

The drawing-up module 20 may include: a seventh switching element, a control end of which is connected to the pull-up node PU, a first end of which receives the clock signal CLK, and a second end of which is connected to the signal Output end Output; the pull-up module may further include a storage capacitor C1, a first end of which is connected to the pull-up node PU, and a second end of which is connected to the signal Output terminal Output; the drawing-up module may further include: and a control end of the eighth switching element is connected to the pull-up node PU, a first end of the eighth switching element receives the first power signal LVGL, and a second end of the eighth switching element is connected to the pull-down node PD.

The control module 30 may include a first control unit and a second control unit. Wherein the first control unit may include: a first switch element having a control terminal receiving the Input signal Input, a first terminal receiving the second power signal VDD, and a second terminal connected to the first terminal of the third switch element through a second node N2; a control terminal of the second switching element receives the Input signal Input, a first terminal of the second switching element receives the first power signal VGL, and a second terminal of the second switching element is connected to a second terminal of the third switching element through a first node N1. The second control unit may include: a third switching element having a control terminal receiving a voltage signal of the signal Output terminal Output, a first terminal connected to the second terminal of the first switching element through a second node N2, and a second terminal connected to the second terminal of the second switching element through a first node N1; and a control terminal of the fourth switching element receives the voltage signal of the signal Output terminal Output, a first terminal of the fourth switching element receives the first power signal VGL, and a second terminal of the fourth switching element is connected to the second terminal of the second switching element through a first node N1.

The pull-down module 40 may include: a ninth switching element having a control terminal connected to the pull-down node PD, a first terminal receiving the first power signal LVGL, and a second terminal connected to the pull-up node PU; a tenth switching element having a control terminal connected to the pull-down node PD, a first terminal receiving the first power signal LVGL, and a second terminal connected to the signal Output terminal Output; and an eleventh switching element having a control terminal connected to the second terminal of the third switching element through a first node N1, a first terminal connected to the second terminal of the third switching element through a first node N1, and a second terminal connected to the pull-down node PD.

In addition, the shift register unit may further include:

the reset module 50 may include: a twelfth switching element having a control terminal receiving the reset signal RST, a first terminal receiving the first power signal LVGL, and a second terminal connected to the pull-up node PU.

In the present exemplary embodiment, all the switching elements may employ MOS transistors (Metal Oxide Semiconductor field effect transistors), specifically, the fifth to twelfth switching elements, the second switching element, and the fourth switching element may each employ an N-type MOS transistor, and the first switching element and the third switching element may employ a P-type MOS transistor. In addition, the fifth to twelfth switching elements, the second switching element, and the fourth switching element may also be P-type transistors. It should be noted that: the level signals of the respective signal terminals require a corresponding adjustment change for different transistor types.

Next, the operation principle of the shift register unit in the present embodiment will be specifically described with reference to the operation timing chart shown in fig. 5 and the equivalent circuit diagrams at each stage of the operation of the control timing shown in fig. 6 to 9. The first power signals LVGL and VGL are dc low level signals, and the second power signal VDD is a high level signal.

The working process of the shift register circuit specifically comprises the following stages:

first stage t 1: when the Input signal Input is low, the first transistor M1 is turned on to transmit the second power signal VDD to the second node N2, and the second node N2 is high; the voltage signal of the signal Output terminal Output is at a low level, the third transistor M3 is turned on under the action of the low level of the signal Output terminal Output to transmit the high level of the second node N2 to the first node N1, the eleventh transistor M11 is turned on under the action of the high level of the first node N1 to transmit the high level of the first node N1 to the pull-down node PD, and the pull-down node PD is at a high level; under the action of the high level of the pull-down node PD, the ninth transistor M9 is turned on to pull down the level of the pull-up node PU by the first power signal LVGL; since the pull-up node PU is low, the eighth transistor M8 is turned off; since the Input signal Input is at a low level, the sixth transistor M6 is turned off; meanwhile, under the action of the high level of the pull-down node PD, the tenth transistor M10 is turned on to transmit the first power signal LVGL to the signal Output terminal Output, and at this time, a low level signal is Output. It can be seen that, since the eleventh transistor M11 is turned on, the sixth transistor M6 and the eighth transistor M8 are both turned off, resulting in no current path among the second power signal VDD, the pull-down node PD, and the first power signal LVGL.

Second stage t 2: when the Input signal Input is at a high level, the fifth transistor M5 is turned on to transmit the Input signal Input to the pull-up node PU to pull up the voltage of the pull-up node PU, and the storage capacitor C1 discharges to keep the pull-up node PU at the high level; the clock signal CLK is at a low level, and the seventh transistor M7 is turned on to transmit the clock signal CLK to the signal Output terminal Output, so that the voltage signal at the signal Output terminal Output is at a low level; the third transistor M3 is turned on in response to the voltage signal of the signal Output terminal Output, and the fourth transistor M4 is turned off; since the pull-up node PU is at a high level, the eighth transistor M8 is turned on to transmit the first power signal LVGL to the pull-down node PD; the Input signal Input is at a high level, and the sixth transistor M6 is turned on to transmit the first power signal LVGL to the pull-down node PD, so as to pull down the level of the pull-down node PD; the Input signal Input is high, and the first transistor M1 is turned off; the second transistor M2 is turned on in response to the Input signal Input to transmit the first power signal VGL to the first node N1, and the first node N1 is low, thereby causing the eleventh transistor M11 to be turned off. It can be seen that, since the first transistor M1 is turned off, the eleventh transistor M11 is turned off, and the sixth transistor M6 and the eighth transistor M8 are both turned on, there is no current path between the second power signal VDD, the pull-down node PD, and the first power signal LVGL.

Third stage t 3: when the Input signal Input is at a high level, the fifth transistor M5 is turned on to transmit the Input signal Input to the pull-up node PU to pull up the voltage of the pull-up node PU, and the storage capacitor C1 discharges to keep the pull-up node PU at the high level; under the action of the high level of the pull-up node PU, the seventh transistor M7 is turned on to transmit the clock signal CLK to the signal Output terminal Output, so that the voltage signal at the signal Output terminal Output is at a high level; the fourth transistor M4 is turned on in response to the voltage signal of the signal Output terminal Output, and the third transistor M3 is turned off; the Input signal Input is high, and the first transistor M1 is turned off; the second transistor M2 is turned on in response to the Input signal Input to transmit the first power signal VGL to the first node N1, and the first node N1 is low, thereby causing the eleventh transistor M11 to be turned off; since the pull-up node PU is at a high level, the eighth transistor M8 is turned on to transmit the first power signal LVGL to the pull-down node PD; the Input signal Input is high, and the sixth transistor M6 is turned on to transmit the first power signal LVGL to the pull-down node PD to pull down the level of the pull-down node PD. It can be seen that, since the eleventh transistor M11 is turned off, the eighth transistor M8 and the sixth transistor M6 are turned on, resulting in no current path among the second power signal VDD, the pull-down node PD, and the first power signal LVGL.

Fourth stage t 4: when the Input signal Input is at a low level, the second transistor M2 is turned off, the first transistor M1 is turned on to transmit the second power signal VDD to the second node N2, and the second node N2 is at a high level; under the action of the high level of the storage capacitor C1, the pull-up node PU maintains a high level, the eighth transistor M8 is turned on under the action of the pull-up node PU to transmit the first power signal LVGL to the pull-down node PD so as to maintain a low level state, and then the sixth transistor M6 is turned off; the seventh transistor M7 is turned on under the action of the pull-up node PU to transmit the clock signal CLK to the signal Output terminal Output, and the voltage signal at the signal Output terminal Output is at a high level; the third transistor M3 is turned off, and the fourth transistor M4 is turned on in response to the voltage signal at the signal Output terminal Output to transmit the first power signal VGL to the first node N1, so that the first node N1 is low, thereby causing the eleventh transistor M11 to be turned off. It can be seen that, since the third transistor M3 is turned off, the eleventh transistor M11 is turned off, the eighth transistor M8 is turned on, and the eighth transistor M6 is turned off, there is no current path among the second power signal VDD, the pull-down node PD, and the first power signal LVGL.

In order to verify whether a current path exists among the second power signal VDD, the pull-down node PD, and the first power signal LVGL, a simulation result shown in fig. 10 is described. As can be seen from the figure, only the first transistor M1 has a leakage current of 10uA and the duration of the leakage current is only 6us, and transient currents exist in the other eleventh transistor, the sixth transistor, the eighth transistor and the first to fourth transistors, but no persistent leakage current occurs.

It should be noted that: after the fourth stage t4, in a frame scanning time, the shift register units of each stage may repeat the first stage t1 and the fourth stage t4 once according to actual conditions.

Based on the above process, when the last stage of shift register unit of each frame outputs a voltage signal, the control module 30 controls the on and off states of each transistor by using the Input signal Input and the signal Output terminal Output, so that when the Input signal is at a high level or a low level, there is no current path between the second power signal VDD, the pull-down node PD, and the first power signal LVGL, and the purpose of reducing the leakage current flowing through the transistors M11, M8, and M6 is achieved, thereby avoiding the problem of poor stability of the GOA circuit caused by the heating phenomenon of the transistors due to an excessively high temperature, and avoiding the display failure caused thereby.

The present exemplary embodiment also provides a shift register circuit, which can be applied to a GOA circuit including one or more clock signals CLK as a gate driving circuit; as shown in fig. 11, the shift register circuit may include a plurality of cascaded shift register units described above; the Output signal of the signal Output end Output of the M-th stage shift register unit is the first Input signal Input of the M + 1-th stage shift register unit, and the Output signal of the signal Output end Output of the M + 1-th stage shift register unit is the reset signal RST of the M-th stage shift register unit. For example, the reset signal in the first shift register unit SR1 may be the output signal of the second shift register unit SR 2; the input signal of the first shift register unit SR1 may be a start signal STV, and the input signal of the second shift register unit SR2 may be the output signal of the first shift register unit SR 1.

On the basis, the scanning mode of the shift register circuit can comprise forward scanning or reverse scanning. When the forward direction scanning is adopted, the Input signal Input of the first stage shift register unit is a starting signal. When the reverse scanning is adopted, the Input signal Input of the last stage of shift register unit is the initial signal.

It should be noted that: the specific details of each module unit in the shift register circuit have been described in detail in the corresponding shift register unit, and are not described herein again.

The present exemplary embodiment also provides a display panel including a display region and a peripheral region, and the shift register circuit described above is provided in the peripheral region.

Therefore, in the present embodiment, the shift register circuit is integrated on the periphery of the display panel by using the GOA technology, so as to implement the design of the narrow-bezel panel and reduce the manufacturing cost of the display panel.

The Display Panel may be specifically an LCD Display Panel, an OLED Display Panel, a PLED (Polymer Light-Emitting Diode) Display Panel, a PDP (Plasma Display Panel), and the like, and the application of the Display Panel is not particularly limited herein.

The present exemplary embodiment also provides a display device including the display panel described above. The display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A shift register cell, comprising:

the control module is used for transmitting a second power supply signal to a pull-down node in a first stage and transmitting the first power supply signal to the pull-down node in a second stage, a third stage and a fourth stage under the control of the input signal and the voltage signal of the signal output end;

in the first stage, the input signal is at a low level, the voltage signal of the signal output end is at a low level, and the pull-down node is at a high level; in the second stage, the input signal is at a high level, the voltage signal of the signal output end is at a low level, and the pull-down node is at a low level; in the third stage, the input signal is at a high level, the voltage signal at the signal output end is at a high level, and the pull-down node is at a low level; in the fourth stage, the input signal is at a low level, the voltage signal of the signal output end is at a high level, and the pull-down node is at a low level; the first power supply signal is at a low level, and the second power supply signal is at a high level;

2. The shift register cell of claim 1, wherein the control module comprises:

a first control unit for transmitting a second power signal to the pull-down node in a first stage and transmitting the first power signal to the pull-down node in a second stage, a third stage and a fourth stage under the control of the input signal;

and the second control unit is used for transmitting a second power supply signal to the pull-down node in a first stage and transmitting the first power supply signal to the pull-down node in a second stage, a third stage and a fourth stage under the control of the voltage signal of the signal output end.

3. The shift register cell according to claim 2, wherein the first control unit comprises:

the second control unit includes:

4. The shift register cell of claim 1, wherein the input module comprises:

5. The shift register cell of claim 1, wherein the pull-up module comprises:

6. The shift register cell of claim 3, wherein the pull-down module comprises:

7. The shift register cell of claim 1, further comprising:

the reset module includes:

8. The shift register unit according to claim 3, wherein the first switching element and the third switching element are P-type MOS transistors, and the second switching element and the fourth switching element are N-type MOS transistors.

9. A shift register circuit comprising a plurality of cascaded shift register cells of any of claims 1-8;

10. A display panel includes a display region and a peripheral region; wherein the peripheral region is provided with the shift register circuit according to claim 9.