CN112634805B - Shift register, display panel and display device - Google Patents
Shift register, display panel and display device Download PDFInfo
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- CN112634805B CN112634805B CN202011473461.2A CN202011473461A CN112634805B CN 112634805 B CN112634805 B CN 112634805B CN 202011473461 A CN202011473461 A CN 202011473461A CN 112634805 B CN112634805 B CN 112634805B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The application discloses a shift register, a display panel and a display device. The shift register comprises an input control module, a first output control module, a second output control module, a first node control module and a second node control module; the second node control module is electrically connected to the first node, the first input signal terminal, the third clock signal terminal, the first level voltage terminal, the second level voltage terminal, and the second node, and transmits the first voltage signal to the second node in response to an on level of the first node, and transmits the second voltage signal to the second node in response to an off level of the first input signal terminal and an on level of the third clock signal terminal. According to the embodiment of the application, the stability of the shift register can be improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a shift register, a display panel and a display device.
Background
In the display field, a shift register is often required to implement a scan display or other functions. The shift register usually includes transistors, and threshold voltages of the transistors may shift due to a process or other reasons, so that when the shift register operates, voltages of internal control nodes of the shift register are unstable, and the shift register cannot stably operate.
Therefore, how to improve the stability of the shift register becomes a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the application provides a shift register, a display panel and a display device, which can improve the stability of the shift register.
In a first aspect, an embodiment of the present application provides a shift register, including an input control module, electrically connected to an input signal terminal, a first clock signal terminal, and a first node, and configured to transmit an input signal provided by the input signal terminal to the first node in response to a turn-on level of the first clock signal terminal; the first output control module is electrically connected with the first node, the second clock signal end and the output signal end and used for responding to the conduction level of the first node and transmitting a second clock signal provided by the second clock signal end to the output signal end; the second output control module is electrically connected with the second node, the first level voltage end and the output signal end and used for responding to the conduction level of the second node and transmitting the first voltage signal provided by the first level voltage end to the output signal end; the first node control module is electrically connected with the first node, the first level voltage end and the second node and used for responding to the conduction level of the second node and transmitting a first voltage signal provided by the first level voltage end to the first node; and the second node control module is electrically connected with the first node, the input signal terminal, the third clock signal terminal, the first level voltage terminal, the second level voltage terminal and the second node, transmits the first voltage signal to the second node in response to the on level of the first node, and transmits the second voltage signal to the second node in response to the off level of the first input signal terminal and the on level of the third clock signal terminal.
In one possible implementation of the first aspect, the input control module includes: and the grid electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the input signal end, and the second electrode of the first transistor is electrically connected with the first node.
In a possible implementation manner of the first aspect, the second node control module includes: a gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to the first level voltage terminal, and a second electrode of the second transistor is electrically connected to the second node; a gate of the third transistor is electrically connected to a third node, a first electrode of the third transistor is electrically connected to the second level voltage terminal, and a second electrode of the third transistor is electrically connected to the second node; a gate of the fourth transistor is electrically connected with the third clock signal terminal, a first electrode of the fourth transistor is electrically connected with the second level voltage terminal, and a second electrode of the fourth transistor is electrically connected with the third node; a gate of the fifth transistor is electrically connected with the input signal end, a first electrode of the fifth transistor is electrically connected with the third node, and a second electrode of the fifth transistor is electrically connected with the second node; and a first pole of the first capacitor is electrically connected with the first pole of the third transistor, and a second pole of the first capacitor is electrically connected with the third node.
In a possible implementation manner of the first aspect, the first node control module includes: and a gate of the sixth transistor is electrically connected to the second node, a first electrode of the sixth transistor is electrically connected to the first level voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first node.
In a possible implementation manner of the first aspect, the first output control module includes a seventh transistor, a gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the output signal terminal;
the second output control module comprises an eighth transistor, the grid electrode of the eighth transistor is electrically connected with the second node, the first electrode of the eighth transistor is electrically connected with the first level voltage end, and the second electrode of the eighth transistor is electrically connected with the output signal end;
preferably, the shift register further comprises a second capacitor, a first electrode of the second capacitor is electrically connected to the first node, and a second electrode of the second capacitor is electrically connected to the output signal terminal;
preferably, the shift register further includes a third capacitor, a first electrode of the third capacitor is electrically connected to the second node, and a second electrode of the third capacitor is electrically connected to the first electrode of the eighth transistor.
In a possible implementation manner of the first aspect, the shift register further includes a reset module, where the reset module is electrically connected to the first node, the third clock signal terminal, and the reset signal terminal, and is configured to transmit a reset signal provided by the reset signal terminal to the first node in response to a conducting level of the third clock signal terminal;
preferably, the reset module includes:
and the grid electrode of the ninth transistor is electrically connected with the third clock signal end, the first electrode of the ninth transistor is electrically connected with the reset signal end, and the second electrode of the ninth transistor is electrically connected with the first node.
In one possible implementation manner of the first aspect, the first level voltage terminal is multiplexed as a reset signal terminal.
In a possible implementation manner of the first aspect, the shift register further includes a tenth transistor, a gate of the tenth transistor is electrically connected to the second level voltage terminal, a first electrode of the tenth transistor is electrically connected to the first node, and a second electrode of the tenth transistor is electrically connected to the first node control module, the second node control module, the input control module, and the reset module.
In a second aspect, an embodiment of the present application provides a display panel, including a plurality of cascaded shift registers as described in any one of the embodiments of the first aspect;
except the shift register of the last stage, the output signal end of the shift register of the other stages is electrically connected with the input signal end of the shift register of the next stage;
preferably, the reset signal terminal of each stage of the shift register is electrically connected to the first level voltage terminal.
In a third aspect, an embodiment of the present application provides a display device, which includes the display panel according to any one of the embodiments of the second aspect.
According to the shift register, the driving method thereof, the display panel and the display device in the embodiment of the application, the first node control module and the second node control module included in the shift register form the inverter between the first node and the second node, and the second node control module can ensure that the second node has no floating connection state in the whole process, so that the shift register can be ensured to work stably. In addition, the shift register provided by the embodiment of the application can keep working stability under the conditions of high temperature and low refresh rate.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic diagram showing a structure of a shift register of an example in the related art;
FIG. 2 is a timing signal diagram of an exemplary shift register of the related art;
FIG. 3 is a schematic diagram of a shift register according to an embodiment of the present application;
FIG. 4 is a schematic diagram of timing signals provided by an embodiment of the present application;
fig. 5 is a schematic flowchart illustrating a driving method of a shift register according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a shift register according to another embodiment of the present application;
FIG. 7 is a diagram illustrating a shift register according to another embodiment of the present application;
FIG. 8 is a diagram illustrating a shift register according to another embodiment of the present application;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 10 is a schematic diagram illustrating a cascade structure of a shift register according to an embodiment of the present application;
fig. 11 illustrates a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the element, it can be directly on the other layer or region or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
Fig. 1 shows a schematic diagram of a shift register of an example in the related art. Fig. 2 shows a timing signal diagram of an exemplary shift register in the related art. As shown in fig. 1, the shift register includes seven transistors M1 to M7 and two capacitors C11 and C12. Wherein transistors M2, M3, and M4 form an inverter between node L1 and node L2. Taking the transistors M1 to M7 as P-type transistors as an example, when the output terminal S _ out of the shift register outputs a high level for a long time, the node L1 should be kept at a low level, the node L2 should be kept at a high level, and the transistor M4 should be kept at an off state. This causes the gate of the transistor M4 to operate at a positive voltage for a long time, which causes the threshold voltage Vth of the transistor M4 to be biased positively, resulting in leakage of the transistor M4. As shown in fig. 2, in the period a, the clock signal CLK1 is at a high level, the transistor M4 leaks electricity, the clock signal CLK1 leaks electricity to the node L1 through the transistor M4, the node L1 cannot maintain a low level, the transistor M3 is turned off, the high level of the level voltage terminal VGH cannot be written into the node L2, the node L2 cannot maintain a high level, no signal is transmitted to the node L2, a floating state occurs in the node L2, that is, the node L2 has an unstable potential, the potential of the node L2 becomes low, the transistor M7 is turned on, and when the clock signal CLK2 changes from a high level to a low level, the output terminal S _ out of the shift register outputs a low level of the clock signal CLK 2. That is, the transistor M4 has a leakage, which causes the potential of the node L1 to be high when the clock signal CLK1 is at a high level, and further causes the node L2 to have a low potential, thereby causing the problem that the shift register cannot stably operate. In addition, a gate driving circuit formed by cascading a plurality of shift registers as shown in fig. 1 is easy to cause a flash screen; the longer the drain time of the transistor M4, i.e., the longer the duration of the period a in fig. 2, the higher the potential of the node L1 will be, and therefore, the screen flicker is more likely to occur at a low refresh rate, e.g., 30Hz; high temperatures accelerate the resulting leakage of transistor M4 and therefore flicker is more likely to occur at high temperatures.
In order to solve the above technical problems, embodiments of a shift register, a driving method of a shift register, a display panel and a display device are provided, and embodiments of the shift register, the driving method of the shift register, the display panel and the display device will be described below with reference to the accompanying drawings.
Fig. 3 shows a schematic structural diagram of a shift register according to an embodiment of the present application. As shown in fig. 3, a shift register provided in the embodiment of the present application includes an input control module 11, a first output control module 12, a second output control module 13, a first node control module 14, and a second node control module 15.
The input control module 11 is electrically connected to the input signal terminal SIN, the first clock signal terminal CLK1, and the first node N1, and is configured to transmit an input signal provided by the input signal terminal SIN to the first node N1 in response to a turn-on level of the first clock signal terminal CLK 1. The first output control module 12 is electrically connected to the first node N1, the second clock signal terminal CLK2 and the output signal terminal S _ out, and is configured to transmit the second clock signal provided by the second clock signal terminal CLK2 to the output signal terminal S _ out in response to the on level of the first node N1. The second output control module 13 is electrically connected to the second node N2, the first level voltage terminal VGH and the output signal terminal S _ out, and is configured to transmit the first voltage signal provided by the first level voltage terminal VGH to the output signal terminal S _ out in response to the on level of the second node N2. The first node control module 14 is electrically connected to the first node N1, the first level voltage terminal VGH and the second node N2, and configured to transmit a first voltage signal provided by the first level voltage terminal VGH to the first node N1 in response to the on level of the second node N2. The second node control module 15 is electrically connected to the first node N1, the first input signal terminal SIN, the third clock signal terminal CLK3, the first level voltage terminal VGH, the second level voltage terminal VGL, and the second node N2, and is configured to transmit the first voltage signal to the second node N2 in response to an on level of the first node N1, and to transmit the second voltage signal to the second node N2 in response to an off level of the first input signal terminal SIN and an on level of the third clock signal terminal CLK 3. Under the control of the second node control module 15, a signal is provided to the second node N2 at any time, so that the second node N2 does not have a floating (floating) state, that is, the second node N2 does not have a state of unstable potential
It should be noted that, the shift register includes a switch transistor, and the on level and the off level in the embodiment of the present application are distinguished according to the type of the switch transistor, the on level refers to a level capable of controlling the switch transistor to be turned on, and the off level refers to a level capable of controlling the switch transistor to be turned off, for example, when the switch transistor is a P-type transistor, the on level is a low level, and the off level is a high level; when the switching transistor is an N-type transistor, the on level is a high level and the off level is a low level. In the embodiments of the present application, the switching transistor is described as a P-type transistor, that is, in the embodiments of the present application, the on levels are all low levels, and the off levels are all high levels.
FIG. 4 is a timing diagram according to an embodiment of the present invention.
Fig. 5 is a schematic flowchart of a control method of a shift register according to an embodiment of the present invention, for driving the shift register provided in the embodiment of the present application as described above.
In the embodiment of the present application, the first level voltage terminal VGH and the second level voltage terminal VGL are both fixed potential terminals. For example, the first level voltage terminal VGH may be a high level dc power source terminal, which provides a high level; the second level voltage terminal VGL may be a low level dc power terminal, which provides a low level.
The following describes in detail a driving method of a shift register according to an embodiment of the present application with reference to the shift register structure in fig. 3 and the timing signals in fig. 4. As shown in fig. 5, the driving method of the shift register includes steps 501 to 504.
In step 502, in the second period t2, the second clock signal terminal CLK2 and the second level voltage terminal VHL provide the on level, the first clock signal terminal CLK1, the input signal terminal SIN, the third clock signal terminal CLK3 and the first level voltage terminal VGH provide the off level, the first node N1 maintains the on level, the second node N2 maintains the off level, and the output signal terminal S _ out outputs the on level provided by the second clock signal terminal CLK 2.
In step 503, in the third period t3, the third clock signal terminal CLK3 and the second level voltage terminal VGL provide the on level, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the input signal terminal SIN and the first level voltage terminal VGH provide the off level, the second node control module 15 transmits the on level provided by the second level voltage terminal VGL to the second node N2 in response to the off level of the first input signal terminal SIN and the on level of the third clock signal terminal CLK3, the first node control module 14 transmits the off level provided by the first level voltage terminal VGH to the first node N1 in response to the on level of the second node N2, and the output signal terminal S _ out outputs the off level provided by the first level voltage terminal VGH.
In step 504, in the fourth time period t4, the first clock signal terminal CLK1 and the second level voltage terminal VGL provide the on level, the second clock signal terminal CLK2, the third clock signal terminal CLK3, the input signal terminal SIN and the first level voltage terminal VGH provide the off level, the first node N1 maintains the off level, the second node N2 maintains the on level, and the output signal terminal S _ out outputs the off level provided by the first level voltage terminal VGH.
The second node control module 15 is configured to continuously control the potential of the second node N2. That is to say, under the control of the second node control module 15, a signal is provided to the second node N2 at any time, and the second node N2 does not have a floating (floating) state, that is, the second node N2 does not have an unstable potential state, so that the operating stability of the shift register can be ensured.
It should be noted that, in the embodiment of the present application, the shift registers are used to form a scanning circuit after being cascaded, so that the scanning circuit sequentially outputs a low level, a timing signal shown in fig. 5 may be a timing sequence of a first stage shift register in the scanning circuit, an input end SIN of the first stage shift register is electrically connected to a driving chip, the driving chip provides a signal, and except for the first stage shift register, output signal ends S _ out of each other stage shift register are electrically connected to an input signal end SIN of a previous stage shift register.
In the shift register and the driving method thereof in the embodiment of the present application, the first node control module 14 and the second node control module 15 included in the shift register form an inverter between the first node N1 and the second node N2, and the second node control module 15 is used for continuously controlling the potential of the second node N2. Even if the transistor in the second node control module 15 has leakage, the second node control module 15 can continuously control the potential of the second node N2, that is, the second node control module 15 can ensure that the second node N2 has no floating state in the whole process, thereby ensuring that the shift register can stably work. In addition, the shift register provided by the embodiment of the application can keep working stability under the conditions of high temperature and low refresh rate.
Fig. 6 shows a schematic structural diagram of a shift register provided in another embodiment of the present application. As shown in fig. 6, the input control module 11, the first output control module 12, the second output control module 13, the first node control module 14, and the second node control module 15 may be composed of components. The specific structures of the input control module 11, the first output control module 12, the second output control module 13, the first node control module 14, and the second node control module 15 will be exemplified below.
In some alternative embodiments, the input control module 11 comprises a first transistor T1. A gate of the first transistor T1 is electrically connected to the first clock signal terminal CLK1, a first pole of the first transistor T1 is electrically connected to the input signal terminal SIN, and a second pole of the first transistor T1 is electrically connected to the first node N1.
In some optional embodiments, the second node control module 15 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the first capacitor C1 constitute one of inverters between the first node N1 and the second node N2.
A gate of the second transistor T2 is electrically connected to the first node N1, a first pole of the second transistor T2 is electrically connected to the first level voltage terminal VGH, and a second pole of the second transistor T2 is electrically connected to the second node N2. A gate electrode of the third transistor T3 is electrically connected to the third node N3, a first pole of the third transistor T3 is electrically connected to the second level voltage terminal VGL, and a second pole of the third transistor T3 is electrically connected to the second node N2. A gate of the fourth transistor T4 is electrically connected to the third clock signal terminal CLK3, a first pole of the fourth transistor T4 is electrically connected to the second level voltage terminal VGL, and a second pole of the fourth transistor T2 is electrically connected to the third node N3. A gate of the fifth transistor T5 is electrically connected to the input signal terminal SIN, a first pole of the fifth transistor T5 is electrically connected to the third node N3, and a second pole of the fifth transistor T5 is electrically connected to the second node N2. A first electrode of the first capacitor C1 is electrically connected to the first electrode of the third transistor T3, and a second electrode of the first capacitor C1 is electrically connected to the third node N3.
Referring to fig. 4 and fig. 6, in the first period T1, the first clock signal terminal CLK1 and the input signal terminal SIN provide a low level, the third clock signal terminal CLK3 provides a high level, the first transistor T1 and the fifth transistor T5 are turned on, the first node N1 is at a low level, the second transistor T2 is turned on, the second node N2 is pulled high by the second level voltage terminal VGH, the third node N3 is pulled high, and the third transistor T3 and the fourth transistor T4 are turned off. In the second period T2, the first clock signal terminal CLK1, the third clock signal terminal CLK3 and the input signal terminal SIN provide a high level, the first transistor T1 is turned off, the first node N1 maintains a low level at the previous stage, at this time, the CLK2 output by the output terminal S _ out is at a low level, due to the coupling effect of the second capacitor C2, the first node N1 continues to maintain the low level, at this time, the second transistor T2 is turned on, the second node N2 is pulled high by the second level voltage terminal VGH, the fourth transistor T4 and the fifth transistor T5 are turned off, the third node N3 maintains a high level at the previous stage, and the third transistor T3 is turned off. In the third period T3, the third clock signal terminal CLK3 provides a low level, the fourth transistor T4 is turned on, the potential of the third node N3 is pulled low by the first level voltage terminal VGL, the third transistor T3 is turned on, and the potential of the second node N2 becomes a low level. In the fourth period T4, due to the coupling effect of the first capacitor C1, the third node N3 maintains a low level, and the third transistor T3 is turned on, so that the second node N2 continues to maintain a low level. In the period after the fourth period T4, the input signal terminal SIN is always at the high level, the fifth transistor T5 is kept turned off, and the third node N3 is kept at the low level, i.e., the third transistor T3 is in the continuous on state, so that even if the second transistor T2 leaks electricity, the potential of the second node N2 is not affected, thereby ensuring the stability of the shift register.
In some optional embodiments, the first node control module 14 includes a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the second node N2, a first pole of the sixth transistor T6 is electrically connected to the first level voltage terminal VGH, and a gate of the sixth transistor T6 is electrically connected to the first node N1.
The sixth transistor T6 constitutes another inverter between the first node N1 and the second node N2. By simply setting a sixth transistor T6, the first node N1 can be set to a high level when the second node N2 is set to a low level, thereby ensuring the operation stability of the shift register.
In some optional embodiments, the first output control module 12 includes a seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the first node N1, a first pole of the seventh transistor T7 is electrically connected to the second clock signal terminal CLK2, and a second pole of the seventh transistor T7 is electrically connected to the output signal terminal S _ out. The second output control module 13 includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the second node N2, a first pole of the eighth transistor T8 is electrically connected to the first level voltage terminal VGH, and a second pole of the eighth transistor T8 is electrically connected to the output signal terminal S _ out.
In some optional embodiments, the shift register further includes a second capacitor C2, a first pole of the second capacitor C2 is electrically connected to the first node N1, and a second pole of the second capacitor C2 is electrically connected to the output signal terminal S _ out. By providing the second capacitor C2, the potential of the first node N1 can be better maintained, that is, the second capacitor C2 can more stably maintain the gate voltage of the seventh transistor T7.
In some optional embodiments, the shift register further includes a third capacitor C3, a first pole of the third capacitor C3 is electrically connected to the second node N2, and a second pole of the third capacitor C3 is electrically connected to the first pole of the eighth transistor T8. By providing the third capacitor C3, the potential of the second node N2 can be maintained better, that is, the gate voltage of the eighth transistor T8 can be maintained more stably by the third capacitor C3.
Fig. 7 shows a schematic structural diagram of a shift register according to yet another embodiment of the present application. In some optional embodiments, as shown in fig. 7, the shift register further includes a reset module 16, and the reset module 16 is electrically connected to the first node N1, the third clock signal terminal CLK3 and the reset signal terminal RST, and is configured to transmit the reset signal provided by the reset signal terminal RST to the first node N1 in response to the on level of the third clock signal terminal CLK 3. By providing the reset module 16, the first node N1 can be reset, i.e., the first node N1 can be better maintained at the cut-off level.
In some alternative embodiments, the reset module 16 includes a ninth transistor T9. A gate of the ninth transistor T9 is electrically connected to the third clock signal terminal CLK3, a first pole of the ninth transistor T9 is electrically connected to the reset signal terminal RST, and a second pole of the ninth transistor T9 is electrically connected to the first node N1.
In some optional embodiments, the first level voltage terminal VGH is multiplexed to the reset signal terminal RST, which can reduce the number of wires and save space.
Fig. 8 shows a schematic structural diagram of a shift register according to yet another embodiment of the present application. In some optional embodiments, as shown in fig. 8, the shift register further includes a tenth transistor T10, a gate of the tenth transistor T10 is electrically connected to the second level voltage terminal VGL, a first pole of the tenth transistor T10 is electrically connected to the first node N1, and a second pole of the tenth transistor T10 is electrically connected to the first node control module 14, the second node control module 15, the input control module 11, and the reset module 16. It is understood that the tenth transistor T10 is in a normally-on state, the second clock signal terminal CLK2 provides a low level during the second period T2, the second clock signal terminal CLK2 pulls the potential of the first node N1 lower, and due to the tenth transistor T10, the gate voltage of the second transistor T2 is prevented from being too low, which causes the threshold voltage Vth of the second transistor T2 to shift, and the first transistor T1, the sixth transistor T6 and the ninth transistor T9 are also prevented from being broken down by too low voltage.
The following further describes an embodiment of the present application with reference to a specific structure of the shift register in fig. 8 and an operation process as shown in fig. 4, wherein the description is still given by taking an example in which each transistor is a P-type transistor. Wherein, in the following periods, the tenth transistor T10 is always in a conductive state. Hereinafter, the voltage signal supplied from the first level voltage terminal VGH is referred to as VGH, and the voltage signal supplied from the second level voltage terminal VGL is referred to as VGL. Illustratively, vgh may be 7v, vgl may be-7 v, and the present application is not limited thereto.
In the first period T1, the first clock signal terminal CLK1, the input signal terminal SIN and the second level voltage terminal VGL provide a low level, the second clock signal terminal CLK2, the third clock signal terminal CLK3 and the first level voltage terminal VGH provide a high level, the first transistor T1 is turned on, the potential of the first node N1 is pulled down to a low level, the seventh transistor T7 is turned on, and the output signal terminal S _ out outputs the high level provided by the second clock signal terminal CLK 2. The second transistor T2 is turned on, the potential of the second node N2 is pulled high to a high level, the fifth transistor T5 is turned on, the potential of the third node N3 is pulled high to a high level, the third transistor T3 is turned off, and the fourth transistor T4 is turned off.
In the second period T2, the second clock signal terminal CLK2 and the second level voltage terminal VGL provide a low level, the first clock signal terminal CLK1, the input signal terminal SIN, the third clock signal terminal CLK3 and the first level voltage terminal VGH provide a high level, the first transistor T1 is turned off, the first node N1 maintains a low level, the seventh transistor T7 is turned on, the potential of the first node N1 is maintained at the low level by the coupling effect of the second capacitor C2, and the output signal terminal S _ out outputs the low level provided by the second clock signal terminal CLK 2. The second node N2 and the third node N3 maintain a high level.
In the third period T3, the third clock signal terminal CLK3 and the second level voltage terminal VGL provide a low level, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the input signal terminal SIN and the first level voltage terminal VGH provide a high level, the ninth transistor T9 is turned on, the potential of the first node N1 is pulled high, the fourth transistor T4 is turned on, the potential of the third node N3 is pulled low to a low level, the third transistor T3 is turned on, the eighth transistor T8 is turned on, and the output signal terminal S _ out outputs the high level provided by the first level voltage terminal VGH. In addition, the sixth transistor T6 is also turned on, and the high level provided by the first level voltage terminal VGH is transmitted to the first node N1 through the sixth transistor T6.
In the fourth period T4, the first clock signal terminal CLK1 and the second level voltage terminal VGL provide a low level, the second clock signal terminal CLK2, the third clock signal terminal CLK3, the input signal terminal SIN and the first level voltage terminal VGH provide a high level, the first transistor T1 is turned on, the first node N1 is pulled high, the third node N3 maintains the low level of the third period T3 due to the effect of the first capacitor C1, the third transistor T3 is turned on, the second node N2 maintains the low level, and the output signal terminal S _ out outputs the high level provided by the first level voltage terminal VGH.
In the period after the fourth period T4, even if the second transistor T2 leaks, the potential of the third node N3 is always kept at the low level due to the first capacitor C1, the third transistor T3 is turned on, so that the second node N2 is kept at the low level, the seventh transistor T7 is kept at the off state even if the second clock signal terminal CLK2 provides the low level, the eighth transistor T8 is kept at the on state, and the output signal terminal S _ out is always used for outputting the high level provided by the first level voltage terminal VGH.
Fig. 9 illustrates a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 9, the display panel 100 includes a display area AA and a non-display area NA. The display area AA includes pixel circuits (not shown) and scan lines 20. The non-display area NA includes a gate driving circuit 10, and the gate driving circuit 10 includes a plurality of cascaded shift registers according to any one of the above embodiments.
The display panel provided in the embodiment of the present application has the beneficial effects of the shift register provided in any one of the embodiments of the present application, and specific reference may be made to the specific description of the shift register in each of the embodiments above, which is not described herein again.
Fig. 10 is a schematic diagram illustrating a cascade structure of a shift register according to an embodiment of the present application. In some alternative embodiments, as shown in fig. 10, the gate driving circuit 10 includes N cascaded shift registers according to any one of the above embodiments, where N is a positive integer greater than 1. Except the last stage of shift register SR _ N, the output signal terminal of each stage of shift register is electrically connected with the input signal terminal SIN of the next stage of shift register, and the first level voltage terminal VGH is multiplexed as the reset signal terminal RST. By arranging the three clock signal ends, the next-stage shift register is not required to reset the previous-stage shift register, and the stability of the grid driving circuit is improved.
For example, the display panel may be provided with three clock signal lines clk1, clk2, clk3, which are electrically connected to the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3, respectively, and in addition, the input signal terminal SIN of the first stage shift register SR _1 is electrically connected to the start signal terminal STV.
The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 11, fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 11 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present application. The embodiment of fig. 11 is only an example of a mobile phone, and the display device 1000 is described, it should be understood that the display device provided in the embodiment of the present application may be other display devices with a display function, such as a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
Claims (14)
1. A shift register, comprising:
the input control module is electrically connected with an input signal end, a first clock signal end and a first node and used for responding to the conducting level of the first clock signal end and transmitting an input signal provided by the input signal end to the first node;
the first output control module is electrically connected with the first node, the second clock signal end and the output signal end and is used for responding to the conduction level of the first node and transmitting a second clock signal provided by the second clock signal end to the output signal end;
the second output control module is electrically connected with a second node, a first level voltage end and the output signal end and used for responding to the conduction level of the second node and transmitting a first voltage signal provided by the first level voltage end to the output signal end;
the first node control module is electrically connected with the first node, the first level voltage end and the second node and used for responding to the conduction level of the second node and transmitting a first voltage signal provided by the first level voltage end to the first node;
a second node control module electrically connected to the first node, the input signal terminal, a third clock signal terminal, the first level voltage terminal, a second level voltage terminal, and a second node, for transmitting the first voltage signal to the second node in response to an on level of the first node, and for transmitting a second voltage signal to the second node in response to an off level of the input signal terminal and an on level of the third clock signal terminal.
2. The shift register of claim 1, wherein the input control module comprises:
a gate of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the input signal terminal, and a second electrode of the first transistor is electrically connected to the first node.
3. The shift register of claim 1, wherein the second node control module comprises:
a second transistor, a gate of which is electrically connected to the first node, a first electrode of which is electrically connected to the first level voltage terminal, and a second electrode of which is electrically connected to the second node;
a third transistor, a gate of which is electrically connected to a third node, a first electrode of which is electrically connected to the second level voltage terminal, and a second electrode of which is electrically connected to the second node;
a gate of the fourth transistor is electrically connected to the third clock signal terminal, a first electrode of the fourth transistor is electrically connected to the second level voltage terminal, and a second electrode of the fourth transistor is electrically connected to the third node;
a fifth transistor, a gate of which is electrically connected to the input signal terminal, a first electrode of which is electrically connected to the third node, and a second electrode of which is electrically connected to the second node;
a first capacitor having a first electrode electrically connected to the first electrode of the third transistor and a second electrode electrically connected to the third node.
4. The shift register of claim 1, wherein the first node control module comprises:
a gate of the sixth transistor is electrically connected to the second node, a first electrode of the sixth transistor is electrically connected to the first level voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first node.
5. The shift register according to claim 1, wherein the first output control block includes a seventh transistor, a gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the output signal terminal;
the second output control module comprises an eighth transistor, the grid electrode of the eighth transistor is electrically connected with the second node, the first electrode of the eighth transistor is electrically connected with the first level voltage end, and the second electrode of the eighth transistor is electrically connected with the output signal end.
6. The shift register according to claim 5, further comprising a second capacitor, wherein a first electrode of the second capacitor is electrically connected to the first node, and a second electrode of the second capacitor is electrically connected to the output signal terminal.
7. The shift register according to claim 5, further comprising a third capacitor, wherein a first pole of the third capacitor is electrically connected to the second node, and a second pole of the third capacitor is electrically connected to the first pole of the eighth transistor.
8. The shift register according to claim 1, further comprising a reset module electrically connected to the first node, the third clock signal terminal, and a reset signal terminal, for transmitting a reset signal provided from the reset signal terminal to the first node in response to an on level of the third clock signal terminal.
9. The shift register of claim 8, wherein the reset module comprises:
a ninth transistor, a gate of which is electrically connected to the third clock signal terminal, a first electrode of which is electrically connected to the reset signal terminal, and a second electrode of which is electrically connected to the first node.
10. The shift register according to claim 8 or 9, wherein the first level voltage terminal is multiplexed as the reset signal terminal.
11. The shift register according to claim 8 or 9, further comprising a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second level voltage terminal, a first electrode of the tenth transistor is electrically connected to the first node, and a second electrode of the tenth transistor is electrically connected to the first node control module, the second node control module, the input control module, and the reset module.
12. A display panel comprising a plurality of cascaded shift registers according to any one of claims 1 to 11;
except the last stage of shift register, the output signal end of each stage of shift register is electrically connected with the input signal end of the next stage of shift register.
13. The display panel according to claim 12, wherein the reset signal terminal of each stage of the shift register is electrically connected to the first level voltage terminal.
14. A display device characterized by comprising the display panel according to claim 12 or 13.
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| EP4207150A4 (en) * | 2021-05-24 | 2023-12-06 | BOE Technology Group Co., Ltd. | Shift register and drive method therefor, and scanning drive circuit and display apparatus |
| CN113362768B (en) * | 2021-06-29 | 2023-02-28 | 京东方科技集团股份有限公司 | Display device, grid drive circuit, shift register unit and drive method thereof |
| CN113889022A (en) * | 2021-10-27 | 2022-01-04 | 合肥维信诺科技有限公司 | Shift register, display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106887217A (en) * | 2017-05-04 | 2017-06-23 | 京东方科技集团股份有限公司 | Shift register cell and its control method, gate driving circuit, display device |
| CN107093414A (en) * | 2017-07-03 | 2017-08-25 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| US10467938B1 (en) * | 2018-06-25 | 2019-11-05 | Shanghai Tianma AM-OLED Co., Ltd. | Scan driving circuit, display device and driving method |
| CN111369927A (en) * | 2020-03-23 | 2020-07-03 | 武汉天马微电子有限公司 | Shift register and control method thereof, display panel and display device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102024116B1 (en) * | 2012-03-22 | 2019-11-15 | 삼성디스플레이 주식회사 | A gate driving circuit and a display apparatus using the same |
| CN105047127B (en) * | 2015-09-21 | 2017-12-22 | 京东方科技集团股份有限公司 | Shift register cell and driving method, line-scanning drive circuit, display device |
| CN105427790B (en) * | 2016-01-05 | 2017-12-08 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| CN106448540B (en) * | 2016-11-18 | 2020-11-17 | 上海天马有机发光显示技术有限公司 | Display panel, shift register circuit and driving method |
| CN106782399A (en) * | 2017-01-11 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| CN106782337B (en) * | 2017-02-14 | 2019-01-25 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and organic electroluminescent display panel |
| CN107103870A (en) * | 2017-06-27 | 2017-08-29 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit, its driving method and display panel |
| CN107863057B (en) * | 2017-10-31 | 2020-12-18 | 上海天马微电子有限公司 | Shift register, driving method thereof, driving control circuit and related device |
| CN110364108B (en) * | 2019-06-27 | 2023-02-17 | 厦门天马微电子有限公司 | Shift register, display panel and display device |
| CN110517620B (en) * | 2019-08-30 | 2022-11-29 | 成都辰显光电有限公司 | Shift register and display panel |
| CN111583850B (en) * | 2020-05-22 | 2022-05-13 | 昆山国显光电有限公司 | Shift register, light-emitting control circuit and display panel |
-
2020
- 2020-12-15 CN CN202011473461.2A patent/CN112634805B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106887217A (en) * | 2017-05-04 | 2017-06-23 | 京东方科技集团股份有限公司 | Shift register cell and its control method, gate driving circuit, display device |
| CN107093414A (en) * | 2017-07-03 | 2017-08-25 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| US10467938B1 (en) * | 2018-06-25 | 2019-11-05 | Shanghai Tianma AM-OLED Co., Ltd. | Scan driving circuit, display device and driving method |
| CN111369927A (en) * | 2020-03-23 | 2020-07-03 | 武汉天马微电子有限公司 | Shift register and control method thereof, display panel and display device |
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|---|---|
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