CN114999557A - Shift register, driving method thereof and grid driving circuit - Google Patents

Shift register, driving method thereof and grid driving circuit Download PDF

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Publication number
CN114999557A
CN114999557A CN202210736934.6A CN202210736934A CN114999557A CN 114999557 A CN114999557 A CN 114999557A CN 202210736934 A CN202210736934 A CN 202210736934A CN 114999557 A CN114999557 A CN 114999557A
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node
output
transistor
control unit
signal output
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郑灿
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a shift register, a driving method thereof and a grid driving circuit, wherein the shift register comprises: the device comprises an input unit, an up-pull control unit, a down-pull control unit, a plurality of output control units and an output reset unit. Each output control unit is connected with the corresponding clock signal line to be output and the signal output end and is used for inputting the clock signal to be output provided by the clock signal line to be output to the corresponding signal output end under the control of the potential of the first node; each output reset unit is used for inputting a third voltage provided by a third power supply end to the signal output end under the control of the potential of the second node. The shift register provided by the invention comprises a plurality of output control units, and the plurality of output control units can drive a plurality of grid lines, so that the number of the shift registers in the grid driving circuit can be effectively reduced, the small size of the grid driving circuit is facilitated, and the narrow frame of the display panel is facilitated.

Description

Shift register, driving method thereof and grid driving circuit
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a driving method thereof and a grid driving circuit.
Background
The basic principle of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) for displaying one frame of picture is to input a square wave with a certain width to each row of pixels in sequence from top to bottom through Gate (Gate) driving, and then output signals required for driving each row of pixels from top to bottom through Source (Source).
However, each stage of shift register in the conventional gate driving circuit can only be used for driving one row of gate lines, so that the whole gate driving circuit occupies a large space, which is not favorable for realizing a narrow frame.
Therefore, how to effectively reduce the occupied space of the gate driving circuit is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The present invention provides a shift register, a driving method thereof, and a gate driving circuit, which are used for solving at least one of the technical problems in the prior art.
To achieve the above object, the present invention provides a shift register, comprising: the input unit, the pull-up control unit, the pull-down control unit and the output control units are connected to a first node, and the pull-up control unit, the pull-down control unit and the output reset units are connected to a second node;
the input unit is used for inputting an input signal provided by an input signal end to the first node under the control of a first clock signal provided by a first clock signal line;
the pull-up control unit is used for inputting a second clock signal provided by a second clock signal line to the second node under the control of the potential of the first node, or inputting a first voltage provided by a first power supply end to the second node under the control of the second clock signal provided by the second clock signal line;
the pull-down control unit is used for inputting a second voltage provided by a second power supply end to the first node under the control of the potential of a second node;
each output control unit is connected with the corresponding clock signal line to be output and the corresponding signal output end, and is used for inputting the clock signal to be output provided by the clock signal line to be output to the corresponding signal output end under the control of the potential of the first node so as to enable the signal output end to output a scanning signal;
each output reset unit is connected with a corresponding signal output end and used for inputting a third voltage provided by a third power supply end to the signal output end under the control of the potential of the second node so as to reset the signal output end.
Optionally, the input unit includes: a first transistor;
the control electrode of the first transistor is connected with the first clock signal line, the first electrode of the first transistor is connected with the input signal end, and the second electrode of the first transistor is connected with the first node.
Optionally, the pull-up control unit includes: a second transistor and a third transistor;
a control electrode of the second transistor is connected with the first node, a first electrode of the second transistor is connected with a second clock signal line, and a second electrode of the second transistor is connected with the second node;
a control electrode of the third transistor is connected to the second clock signal line, a first electrode of the third transistor is connected to the first power source terminal, and a second electrode of the third transistor is connected to the second node.
Optionally, the pull-down control unit includes: a fourth transistor;
a control electrode of the fourth transistor is connected to the second node, a first electrode of the fourth transistor is connected to a second power source terminal, and a second electrode of the fourth transistor is connected to the first node.
Optionally, the output control unit includes: a fifth transistor and a first capacitor;
a control electrode of the fifth transistor is connected with the first node, a clock signal line to be output corresponding to the first electrode of the fifth transistor is connected, and a second electrode of the fifth transistor is connected with the corresponding signal output end;
and the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the corresponding signal output end.
Optionally, the output reset unit includes: a sixth transistor and a second capacitor;
a control electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the third power supply terminal, and a second electrode of the sixth transistor is connected to the corresponding signal output terminal;
a first end of the second capacitor is connected to a second node, and a second end of the second capacitor is connected to the third power supply terminal.
Optionally, the shift register further includes: a current chopping unit between the input unit and the first node and between the pull-down control unit and the first node;
the current cut-off unit is configured to, when the output control unit inputs the clock signal to be output to a corresponding signal output end under the control of the potential of the first node, open a circuit between the input unit and the first node and open a circuit between the pull-down control unit and the first node, so as to avoid a leakage current in the input unit and the pull-down control unit from affecting the potential of the first node.
Optionally, the current chopping unit includes: a seventh transistor;
a control electrode of the seventh transistor is connected to a fourth power supply terminal, a first electrode of the seventh transistor is connected to both the input unit and the pull-down control unit, and a second electrode of the seventh transistor is connected to the first node.
Optionally, the method further comprises: the load units are in one-to-one correspondence with the signal output ends and are connected with the corresponding signal output ends, and the load units are used for limiting the current of the corresponding signal output ends;
the load unit includes: a resistor and a third capacitor;
the first end of the resistor is connected with the corresponding signal output end, the second end of the resistor is connected with the first end of the third capacitor, and the second end of the third capacitor is grounded.
In order to achieve the above object, the present invention further provides a gate driving circuit, including: the shift registers are cascaded and adopt the shift register;
the signal output end of the last scanning signal in the shift register of the previous stage is connected with the signal input end of the shift register of the next stage.
In order to achieve the above object, the present invention further provides a driving method of a shift register, where the shift register adopts the above shift register, and the driving method includes:
in an input stage, the input unit inputs an input signal provided by an input signal terminal to the first node under the control of a first clock signal provided by a first clock signal line, and the pull-up control unit inputs a second clock signal provided by a second clock signal line to the second node under the control of the potential of the first node;
in the output stage, each output control unit sends the clock signal to be output in the corresponding clock signal line to be output to the corresponding signal output end under the control of the potential of the first node, so that each signal output end sequentially outputs a scanning signal;
in a reset phase, the pull-up control unit inputs a first voltage provided by a first power supply terminal to the second node under the control of a second clock signal provided by a second clock signal line, the pull-down control unit inputs a second voltage provided by a second power supply terminal to the first node under the control of a potential of the second node to reset the first node, and the output reset unit inputs a third voltage provided by a third power supply terminal to the signal output terminal under the control of the potential of the second node to reset the signal output terminal.
The invention has the following beneficial effects:
the invention provides a shift register, a driving method thereof and a grid driving circuit, wherein the shift register comprises a plurality of output control units and a plurality of output reset units, and the plurality of output control units can drive a plurality of grid lines, so that the number of the shift registers in the grid driving circuit can be effectively reduced, the small size of the grid driving circuit is facilitated, and the narrow frame of a display panel is facilitated.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a shift register according to a second embodiment of the present invention;
FIG. 3 is a timing diagram illustrating operation of the shift register shown in FIG. 2;
fig. 4 is a schematic structural diagram of a gate driving circuit according to a third embodiment of the present invention;
fig. 5 is a flowchart of a driving method of a shift register according to a fourth embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, a shift register, a driving method thereof, and a gate driving circuit thereof provided by the present invention are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention, as shown in fig. 1, the shift register includes: the device comprises an input unit 1, an upward-pulling control unit 2, a downward-pulling control unit 3, a plurality of output control units 4 and a plurality of output reset units 5, wherein the output reset units 5 correspond to the output control units 4 one to one. The input unit 1, the pull-up control unit 2, the pull-down control unit 3 and the output control unit 4 are connected to a first node N1, and the pull-up control unit 2, the pull-down control unit 3 and the output reset unit 5 are connected to a second node N2.
The input unit 1 is used for inputting an input signal provided by an input signal terminal STV to a first node N1 under the control of a first clock signal provided by a first clock signal line CK 1.
The pull-up control unit 2 inputs the second clock signal supplied from the second clock signal line CK2 to the second node N2 under the control of the potential of the first node N1, or inputs the first voltage supplied from the first power source terminal to the second node N2 under the control of the second clock signal supplied from the second clock signal line CK 2.
The pull-down control unit 3 is used for inputting the second voltage provided by the second power source terminal to the first node N1 under the control of the potential of the second node N2.
Each OUTPUT control unit 4 is connected to the corresponding to-be-OUTPUT clock signal line CKB1/CKB2/CKB3 and the signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3, and is configured to input the to-be-OUTPUT clock signal provided by the to-be-OUTPUT clock signal line CKB1/CKB2/CKB3 to the corresponding signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3 under the control of the potential of the first node N1, so that the respective signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 OUTPUT the scan signal. The time when the clock signal to be output is at the effective potential in the clock signal lines to be output CKB1/CKB2/CKB3 connected to the output control units 4 is sequentially staggered.
Each of the OUTPUT reset units 5 is connected to a corresponding signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3, for inputting a third voltage supplied from a third power source terminal to the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 under the control of the potential of the second node N2 to reset the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT 3.
In order to facilitate understanding of the technical solutions of the present invention for those skilled in the art, the operation of the shift register shown in fig. 1 will be described in detail below. The driving process of the shift register comprises the following three stages:
in the input stage, the input unit 1 inputs the input signal provided by the input signal terminal STV to the first node N1 under the control of the first clock signal provided by the first clock signal line CK1, and the pull-up control unit 2 inputs the second clock signal provided by the second clock signal line CK2 to the second node N2 under the control of the potential of the first node N1;
in the OUTPUT stage, each OUTPUT control unit 4 sends the clock signal to be OUTPUT in the corresponding clock signal line to be OUTPUT CKB1/CKB2/CKB3 to the corresponding signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3 under the control of the potential of the first node N1. Since the times at which the clock signals to be OUTPUT are at the effective potential in the clock signal lines to be OUTPUT CKB1/CKB2/CKB3 to which the OUTPUT control units 4 are connected are sequentially staggered, the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 sequentially OUTPUT the scan signals, and the gate lines connected to the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 can be sequentially driven.
In the reset phase, the pull-up control unit 2 inputs the first voltage provided by the first power terminal to the second node N2 under the control of the second clock signal provided by the second clock signal line CK2, the pull-down control unit 3 inputs the second voltage provided by the second power terminal to the first node N1 under the control of the potential of the second node N2 to reset the first node N1, and the OUTPUT reset unit 5 inputs the third voltage provided by the third power terminal to the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 under the control of the potential of the second node N2 to reset the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT 3.
It should be noted that the case that the shift register shown in the figure includes 3 output control units 4 and 3 output reset units 5 is only for illustrative purposes, and does not limit the technical solution of the present invention. It will be understood by those skilled in the art that the number of the output control units 4 and the output reset units 5 in the shift register provided by the present invention can be adjusted according to actual needs.
In the present embodiment, since the shift register includes the plurality of OUTPUT control units 4, the plurality of OUTPUT reset units 5, and the plurality of signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3, the shift register can provide scan signals for a plurality of gate lines on the display panel, i.e., the shift register can drive a plurality of gate lines. Under the condition that the number of grid lines in the display panel is certain, compared with the prior art, the technical scheme provided by the invention can effectively reduce the number of the shift registers in the grid driving circuit, so that the space occupied by the grid driving circuit is reduced, and the realization of a narrow frame is facilitated.
Optionally, the shift register further comprises: a current chopping unit 6 and a load unit 7.
The current cut-off unit 6 is located between the input unit 1 and the first node N1 and between the pull-down control unit 3 and the first node N1, and is configured to, when the OUTPUT control unit 4 inputs the clock signal to be OUTPUT to the corresponding signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3 under the control of the potential of the first node N1 (i.e., during an OUTPUT stage), make the circuit between the input unit 1 and the first node N1 broken and the circuit between the pull-down control unit 3 and the first node N1 broken, so as to avoid the leakage current in the input unit 1 and the pull-down control unit 3 from affecting the potential of the first node N1, and further ensure the normal operation of each OUTPUT control unit 4.
The load units 7 are in one-to-one correspondence with the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3, the load units 7 are connected with the corresponding signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3, and the load units 7 are used for limiting the current magnitude of the corresponding signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 so as to prevent the current of the signals OUTPUT by the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 from being too large.
The first embodiment of the invention provides a shift register, which can drive a plurality of gate lines, so that the number of the shift registers in a gate driving circuit can be effectively reduced, the size reduction of the gate driving circuit is facilitated, and the narrow frame of a display panel is facilitated.
Example two
Fig. 2 is a circuit schematic diagram of a shift register according to a second embodiment of the present invention, and as shown in fig. 2, the circuit schematic diagram shown in fig. 2 is a concrete example of the structure schematic diagram shown in fig. 1, and in this embodiment, the number of the output control units 4'/4 "/4"' and the number of the output reset units 5'/5 "/5"' are described as an example 3.
Alternatively, the input unit 1 includes: a first transistor M1; a control electrode of the first transistor M1 is connected to the first clock signal line CK1, a first electrode of the first transistor M1 is connected to the input signal terminal STV, and a second electrode of the first transistor M1 is connected to the first node N1.
The pull-up control unit 2 includes: a second transistor M2 and a third transistor M3; a control electrode of the second transistor M2 is connected to the first node N1, a first electrode of the second transistor M2 is connected to the second clock signal line CK2, and a second electrode of the second transistor M2 is connected to the second node N2; a control electrode of the third transistor M3 is connected to the second clock signal line CK2, a first electrode of the third transistor M3 is connected to the first power source terminal, and a second electrode of the third transistor M3 is connected to the second node N2.
The pull-down control unit 3 includes: a fourth transistor M4; a control electrode of the fourth transistor M4 is connected to the second node N2, a first electrode of the fourth transistor M4 is connected to the second power source terminal, and a second electrode of the fourth transistor M4 is connected to the first node N1.
The output control unit 4'/4 "/4'" includes: a fifth transistor M5'/M5 "/M5"' and a first capacitor C1'/C1 "/C1"'; the control electrode of the fifth transistor M5'/M5 "/M5'" is connected to the first node N1, the to-be-OUTPUT clock signal line CKB1/CKB2/CKB3 corresponding to the first electrode of the fifth transistor M5'/M5 "/M5'" is connected, and the second electrode of the fifth transistor M5'/M5 "/M5'" is connected to the corresponding signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT 3; first ends of the first capacitors C1'/C1 "/C1'" are connected to a first node N1, and second ends of the first capacitors C1'/C1 "/C1'" are connected to corresponding signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT 3.
The output reset unit 5'/5 "/5'" includes: a sixth transistor M6'/M6 "/M6'" and a second capacitor C2; a control electrode of the sixth transistor M6'/M6 "/M6"' is connected to the second node N2, a first electrode of the sixth transistor M6'/M6 "/M6"' is connected to the third power supply terminal, and a second electrode of the sixth transistor M6'/M6 "/M6"' is connected to the corresponding signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT 3; a first terminal of the second capacitor C2 is connected to the second node N2, and a second terminal of the second capacitor C2 is connected to the third power supply terminal. It should be noted that, in the present embodiment, the sixth transistors M6'/M6 "/M6'" in the output reset units 5'/5 "/5'" may share a second capacitor C2.
The current chopping unit 6 includes: a seventh transistor M7; a control electrode of the seventh transistor M7 is connected to the fourth power source terminal, a first electrode of the seventh transistor M7 is connected to both the input unit 1 and the pull-down control unit 3, and a second electrode of the seventh transistor M7 is connected to the first node N1.
The load unit 7 includes: a resistor RL and a third capacitor C3; the first end of the resistor RL is connected with the corresponding signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3, the second end of the resistor RL is connected with the first end of the third capacitor C3, and the second end of the third capacitor C3 is grounded.
In order to facilitate better understanding of the technical solutions of the present invention, the operation of the shift register shown in fig. 2 will be described in detail below with reference to the accompanying drawings.
It should be noted that the transistors used in the embodiments may be thin film transistors or field effect transistors or other devices having the same and similar characteristics, and since the source and the drain of the transistors used are symmetrical, the source and the drain are indistinguishable. In an embodiment, to distinguish the source and drain of the transistor, one of the poles is called a first pole, the other pole is called a second pole, and the gate is called a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, a P-type transistor is used for explanation, when a P-type transistor is used, a first electrode is a drain electrode of the P-type transistor, a second electrode is a source electrode of the P-type transistor, and when a high level is input to a gate electrode, the P-type transistor is turned on; the situation is reversed for an N-type transistor. It is contemplated that implementing the present invention with N-type transistors is well within the scope of the present invention, as those skilled in the art can easily conceive without inventive effort.
In the case where the transistors in the shift register are all P-type transistors, the first voltage supplied from the first power supply terminal and the fourth voltage supplied from the fourth power supply terminal are both low-level voltages VGL, and the second voltage supplied from the second power supply terminal and the third voltage supplied from the third power supply terminal are both high-level voltages VGH. The voltage level corresponding to the input signal in the high level state is VH, and the voltage level corresponding to the input signal in the low level state is VL. Wherein VGL is slightly less than VL.
For convenience of description, the 3 signal OUTPUT terminals are respectively referred to as a first signal OUTPUT terminal OUTPUT1, a second signal OUTPUT terminal OUTPUT2, and a signal OUTPUT terminal OUTPUT3, the 3 OUTPUT control units 4'/4 ' ″ are respectively referred to as a first OUTPUT control unit 4', the second OUTPUT control unit 4 ″ and the third OUTPUT control unit 4 '/5' ″, the 3 OUTPUT reset units 5 '/5' ″ are respectively referred to as a first OUTPUT reset unit 5', a second OUTPUT reset unit 5 ″ and a third OUTPUT reset unit 5' ″, the first OUTPUT control unit 4 'and the first OUTPUT reset unit 5' correspond to the first signal OUTPUT terminal OUTPUT1, the second OUTPUT control unit 4 ″ and the second OUTPUT reset unit 5 ″ correspond to the second signal OUTPUT terminal OUTPUT2, and the third OUTPUT control unit 4'″ and the third OUTPUT reset unit 5' ″ correspond to the third signal OUTPUT terminal OUTPUT 3.
The clock signal lines to be output to which the first output control unit 4', the second output control unit 4 ″ and the third output control unit 4' ″ are respectively connected are referred to as a first clock signal line to be output CKB1 (providing a first clock signal to be output), a second clock signal line to be output CKB2 (providing a second clock signal to be output) and a third clock signal line to be output CKB3 (providing a third clock signal to be output).
The time of the low level potential (effective potential) in the first clock signal, the second clock signal, the first clock signal to be output, the second clock signal to be output and the third clock signal to be output is staggered in sequence, and the duty ratio of the low level potential is 20%.
It should be noted that, since the control electrode of the seventh transistor M7 is connected to the low-level power supply, the seventh transistor M7 is in the "normally open" (the voltage at the source and drain of the seventh transistor M7 is turned on) state.
Fig. 3 is a timing diagram illustrating the operation of the shift register shown in fig. 2, and as shown in fig. 3, the operation of the shift register includes the following three stages:
an input stage: the input signal provided by the input signal terminal STV is in a low level state, the first clock signal provided by the first clock signal line CK1 is in a low level state, and the second clock signal provided by the second clock signal line CK2 is in a high level state.
Since the first clock signal is in a low state, the first transistor M1 is turned on, and the input signal provided by the input signal terminal STV is written to the first node N1 through the first transistor M1 and the seventh transistor M7 in sequence.
It should be noted that, when the input signal passes through the seventh transistor M7, the gate-source voltage of the seventh transistor M7 is equal to VGL < VL (the result is less than 0), the first transistor M1 is turned on and operates in the nonlinear region, there is a threshold loss in the process of writing the input signal in the low level state into the first node N1 through the seventh transistor M7, and the voltage of the first node N1 is VL + | Vth |. Wherein Vth is a threshold voltage of each transistor in the shift register and is a negative value.
Of course, those skilled in the art should know that the magnitude of VGL may be adjusted to a lower level in advance, so that there is no threshold loss when the input signal passes through the seventh transistor M7, but the power consumption of the whole circuit is increased. The details are not described in detail.
The second transistor M2 is turned on under the control of the low-level potential of the third node N3, the second clock signal in the high-level state is written to the second node N2 through the second transistor M2, and the second node N2 is at the high-level potential. At this time, the sixth transistors M6'/M6 "/M6'" in the first, second, and third output reset units 5', 5 ", 5'" are all in the off state.
Meanwhile, since the first node N1 is at a low level potential (voltage VL + | Vth |), and the first to-be-OUTPUT clock signal provided by the first to-be-OUTPUT clock signal line CKB1, the second to-be-OUTPUT clock signal provided by the second to-be-OUTPUT clock signal line CKB 2/and the third to-be-OUTPUT clock signal provided by the third to-be-OUTPUT clock signal line CKB3 are all at a high level state, the fifth transistors M5'/M5 "/M5"' in the first OUTPUT control unit 4', the second OUTPUT control unit 4 ″ and the third OUTPUT control unit 4' "are all turned on, and the first to-be-OUTPUT clock signal, the second to-be-OUTPUT clock signal and the third to-be-OUTPUT clock signal can be written to the corresponding signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 through the corresponding fifth transistors M5 without threshold loss. Each of the signal OUTPUT terminals OUTPUT1, OUTPUT2, and OUTPUT3 OUTPUTs a high level signal.
In this embodiment, it is assumed that the voltage corresponding to each clock signal to be output in the high level state is VH 0 The voltage corresponding to the low level state is VL 0 Then, at the end of the input phase, the voltage difference between the two ends of the first capacitor C1' is VH 0 -VL-|Vth|。
An output stage: the input signal provided by the input signal terminal STV is in a high state, the first clock signal provided by the first clock signal line CK1 is in a high state, and the second clock signal provided by the second clock signal line CK2 is in a high state.
Since the first clock signal provided by the first clock signal line CK1 is in a high state, the first transistor M1 is turned off, and both the first node N1 and the third node N3 are in a floating state. The third node N3 maintains the low level state of the previous stage, the second transistor M2 is turned on continuously, the second clock signal in the high level state is written into the second node N2 through the second transistor M2, the second node N2 maintains the high level state, and the sixth transistors M6'/M6 "/M6'" in the first output resetting unit 5', the second output resetting unit 5 "and the third output resetting unit 5'" are all in the off state.
The whole output stage comprises three output sub-stages: a first output sub-phase, a second output sub-phase and a third output sub-phase.
During the first output sub-stage, the first to-be-output clock signal provided by the first to-be-output clock signal line CKB1 is in a low level state, and the second to-be-output clock signal provided by the second to-be-output clock signal line CKB2 and the third to-be-output clock signal provided by the third to-be-output clock signal line CKB3 are in a high level state. At this time, the first signal OUTPUT terminal OUTPUT1 OUTPUTs a low level signal, and the corresponding voltage level is VL 0 。
At the first output sub-stageAt the initial time of the segment, the voltage of the second end of the first capacitor C1' in the first output control unit 4' changes abruptly, so that the first capacitor C1' maintains the voltage difference (with the magnitude of VH) between the two ends 0 VL-Vth) is constant to pull down the voltage at the first end of the first capacitor C1' to a lower level, which is VL + | Vth | + VL 0 -VH 0 That is, the voltage of the first node N1 is VL + | Vth | + VL 0 -VH 0 . At this time, each output clock signal may be outputted without threshold loss through the fifth transistor M5'/M5 "/M5'" within the corresponding output control unit 4'/4 "/4'".
The first signal OUTPUT terminal OUTPUT1 OUTPUTs a low level signal, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a high level signal, and the third signal OUTPUT terminal OUTPUT3 OUTPUTs a high level signal.
The voltage at the first node N1 is VL + | Vth | + VL 0 -VH 0 At this time, since the voltage VGL of the control electrode of the seventh transistor M7 is greater than the voltage VL + | Vth | + VL of the first node N1 (the second electrode of the seventh transistor M7) 0 -VH 0 Therefore, the seventh transistor M7 is in the off state, i.e., the input unit 1 and the first node N1 and the pull-down control unit 3 and the first node N1 are both open, so as to prevent the leakage current in the input unit 1 and the pull-down control unit 3 from affecting the potential of the first node N1, thereby ensuring the normal operation of the OUTPUT control units 4'/4 "/4"', and maintaining the stable OUTPUT of the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT 3.
In addition, the resistor RL and the third capacitor C3 can be used as loads to reduce the current of the signals OUTPUT by the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3, so as to effectively avoid the problem of excessive OUTPUT current of the signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT 3.
At the end of the first OUTPUT sub-stage, the first to-be-OUTPUT clock signal provided by the first to-be-OUTPUT clock signal line CKB1 jumps to a high level state, the first signal OUTPUT terminal OUTPUT1 OUTPUTs a high level signal, and the corresponding voltage level is VH 0 The voltage of the second terminal of the first capacitor C1' in the first output control unit 4' is suddenly changed, so that the first capacitor C1' isMaintain the voltage difference between both ends (with the magnitude of VH 0 VL-Vth) is constant to pull up the voltage at the first end of the first capacitor C1', and the voltage is VL + Vth |.
During the first OUTPUT sub-phase, the gate lines on the display panel connected to the first signal OUTPUT terminal OUTPUT1 are driven.
During the second output sub-stage, the second to-be-output clock signal provided by the second to-be-output clock signal line CKB2 is in a low level state, and the first to-be-output clock signal provided by the first to-be-output clock signal line CKB1 and the third to-be-output clock signal provided by the third to-be-output clock signal line CKB3 are in a high level state. At this time, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a low level signal with a voltage VL 0 。
Similar to the first output sub-phase, at the initial time of the second output sub-phase, under the bootstrap action of the first capacitor C1 "in the second output control unit 4", the voltage of the first node N1 is pulled down to VL + | Vth | + VL 0 -VH 0 . Each output clock signal can be outputted without threshold loss through the fifth transistor M5'/M5 "/M5'" in the corresponding output control unit 4'/4 "/4'". The first signal OUTPUT terminal OUTPUT1 OUTPUTs a high level signal, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a low level signal, and the third signal OUTPUT terminal OUTPUT3 OUTPUTs a high level signal. At the end of the second OUTPUT sub-phase, the second to-be-OUTPUT clock signal provided by the second to-be-OUTPUT clock signal line CKB2 jumps to a high level state, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a high level signal, and at the same time, under the bootstrap action of the first capacitor C1 "in the second OUTPUT control unit 4", the voltage of the first node N1 is pulled up to VL + | Vth |.
During the second OUTPUT sub-phase, the gate lines on the display panel connected to the second signal OUTPUT terminal OUTPUT2 are driven.
In the third output sub-stage, the third to-be-output clock signal provided by the third to-be-output clock signal line CKB3 is at a low level state, and the first to-be-output clock signal and the second to-be-output clock signal provided by the first to-be-output clock signal line CKB1 are at a low level stateThe second clock signal to be output provided by the signal line CKB2 is in a high state. At this time, the third signal OUTPUT terminal OUTPUT3 OUTPUTs a low level signal with a voltage VL 0 。
Similar to the above process, the voltage at the first node N1 is initially pulled down to VL + | Vth | + VL by the first capacitor C1' ″ 0 -VH 0 And then is pulled up to VL + | Vth | by the first capacitor C1' ″ again at the end time. At the end of the third OUTPUT sub-phase, the third signal OUTPUT terminal OUTPUT3 OUTPUTs a high signal.
During the third OUTPUT sub-phase, the gate lines on the display panel connected to the third signal OUTPUT terminal OUTPUT3 are driven.
A reset stage: the input signal provided by the input signal terminal STV is in a high state, the first clock signal provided by the first clock signal line CK1 is in a high state, and the second clock signal provided by the second clock signal line CK2 is in a low state.
Since the second clock signal is at a low level, the third transistor M3 is turned on, and the first voltage VGL provided by the first power terminal is written into the second node N2 through the third transistor M3, and the second node N2 is at a low level. Under the control of the potential of the second node N2, the fourth transistor M4 is turned on, the second voltage VGH supplied from the second power source terminal is written to the third node N3 through the fourth transistor M4, and the second transistor M2 is turned off. Accordingly, the second voltage VGH provided by the second power source terminal is written to the first node N1 through the fourth transistor M4 and the seventh transistor M7, and when the first node N1 is at a high level, the first node N1 is reset, and the fifth transistors M5'/M5'/M5 ' ″ of the output control units 4'/4 "/4 ' ″ are all in a turned-off state.
Meanwhile, since the second node N2 is at a low level, the sixth transistors M6'/M6 "/M6'" in the first OUTPUT reset unit 5', the second OUTPUT reset unit 5 ", and the third OUTPUT reset unit 5'" are all turned on, and at this time, the third voltage VGH provided by the third power terminal is written to the corresponding signal OUTPUT terminals OUTPUT1/OUTPUT2/OUTPUT3 through the sixth transistors M6'/M6 "/M6'" in each reset unit, each signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3 OUTPUTs a high level potential, and each signal OUTPUT terminal OUTPUT1/OUTPUT2/OUTPUT3 OUTPUTs a complete reset.
It should be noted that, as those skilled in the art should easily understand, in this embodiment, a plurality of output control units and a plurality of output reset units may be provided, and a corresponding clock signal line to be output is configured for each output control unit, and the times of the clock signals to be output in the clock signal lines to be output at the effective voltage are sequentially staggered, so that one shift register can sequentially drive a plurality of gate lines.
Fig. 4 is a schematic structural diagram of a gate driving circuit according to a third embodiment of the present invention, as shown in fig. 4, the gate driving circuit includes: a plurality of shift registers SR _1/SR _2/SR _3 … … connected in series, wherein the shift registers SR _1/SR _2/SR _3 … … can be the shift registers of the first embodiment or the second embodiment, and the last signal OUTPUT terminal OUTPUT3 of each stage outputting the scan signal is connected to the signal input terminal STV of the next stage of shift register.
It should be noted that the case of driving 3 GATE lines GATE1/GATE2/GATE3 … … by one stage of shift register in the drawings only serves as an exemplary function, and does not limit the technical solution of the present invention.
The grid driving circuit can be applied to a display device to drive grid lines in the display device. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
Fig. 5 is a flowchart of a driving method of a shift register according to a fourth embodiment of the present invention, and as shown in fig. 5, the shift register adopts the shift register according to the first embodiment or the second embodiment, and the driving method of the shift register includes:
in the input stage, the input unit inputs the input signal provided by the input signal terminal to the first node under the control of the first clock signal provided by the first clock signal line, and the pull-up control unit inputs the second clock signal provided by the second clock signal line to the second node under the control of the potential of the first node in step S1.
Step S2, in the output stage, each output control unit sends the clock signal to be output in the corresponding clock signal line to be output to the corresponding signal output terminal under the control of the potential of the first node, so that each signal output terminal sequentially outputs the scan signal.
Step S3, in the reset phase, the pull-up control unit inputs the first voltage provided by the first power source terminal to the second node under the control of the second clock signal provided by the second clock signal line, the pull-down control unit inputs the second voltage provided by the second power source terminal to the first node under the control of the potential of the second node to reset the first node, and the output reset unit inputs the third voltage provided by the third power source terminal to the signal output terminal under the control of the potential of the second node to reset the signal output terminal.
For the specific description of each step, reference may be made to the corresponding contents in the foregoing first embodiment and second embodiment, which are not described herein again.
It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, and the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (14)

1. A shift register, comprising: the input unit, the pull-up control unit, the pull-down control unit and the output control unit are connected to a first node, and the pull-up control unit, the pull-down control unit and the output reset unit are connected to a second node;
the input unit is used for inputting an input signal provided by an input signal end to the first node under the control of a first clock signal provided by a first clock signal line;
the pull-up control unit is configured to input a low-level or high-level signal to the second node under control of a potential of the first node;
the pull-down control unit is used for inputting a second voltage provided by a second power supply end to the first node under the control of the potential of a second node;
the output control unit is connected with the clock signal line to be output and the signal output end and is used for inputting the high level or the low level provided by the clock signal line to be output to the signal output end under the control of the potential of the first node so as to enable the signal output end to output the scanning signal;
the output reset unit is connected with the signal output end and is used for inputting a third voltage provided by a third power supply end to the signal output end under the control of the potential of the second node so as to reset the signal output end;
the pull-up control unit comprises an N-type transistor; the output control unit includes a P-type transistor.
2. The shift register according to claim 1, wherein the output control unit includes a first output control unit and a second output control unit; the output reset unit comprises a first output reset unit and a second output reset unit; the signal output end comprises a first signal output end and a second signal output end;
the first output control unit is connected with the first clock signal line to be output and the first signal output end, and is used for inputting the high level or the low level provided by the first clock signal line to be output to the first signal output end under the control of the potential of the first node so as to enable the first signal output end to output the scanning signal;
the second output control unit is connected with a second signal line to be output and a second signal output end, and is used for inputting the high level or the low level provided by the second signal line to be output to the second signal output end under the control of the potential of the first node so as to enable the second signal output end to output a scanning signal;
the first output reset unit is connected with the first signal output end and is used for inputting a third voltage provided by a third power supply end to the first signal output end under the control of the potential of the second node so as to reset the first signal output end;
the second output reset unit is connected with the second signal output end, and inputs a third voltage provided by a third power supply end to the second signal output end so as to reset the second signal output end.
3. The shift register according to claim 1, wherein the input unit comprises: a first transistor;
the control electrode of the first transistor is connected with the first clock signal line, the first electrode of the first transistor is connected with the input signal end, and the second electrode of the first transistor is connected with the first node.
4. The shift register according to claim 1, wherein the pull-up control unit comprises: a second transistor and a third transistor;
a control electrode of the second transistor is connected to the first node, a first electrode of the second transistor is configured to input a high level or a low level to a second node, and a second electrode of the second transistor is connected to the second node;
the off-time of the third transistor is equal to the low level time of the first node in one period, the first pole of the third transistor is connected with the first power end, and the second pole of the third transistor is connected with the second node.
5. The shift register according to claim 4, wherein the third transistor is an N-type transistor.
6. The shift register according to claim 1, wherein the pull-down control unit comprises: a fourth transistor;
a control electrode of the fourth transistor is connected to the second node, a first electrode of the fourth transistor is connected to a second power source terminal, and a second electrode of the fourth transistor is connected to the first node.
7. The shift register according to claim 1, wherein the output control unit comprises: a fifth transistor and a first capacitor;
a control electrode of the fifth transistor is connected with the first node, a clock signal line to be output corresponding to the first electrode of the fifth transistor is connected, and a second electrode of the fifth transistor is connected with the corresponding signal output end;
and the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the corresponding signal output end.
8. The shift register according to claim 1, wherein the output reset unit includes: a sixth transistor;
a control electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the third power supply terminal, and a second electrode of the sixth transistor is connected to the corresponding signal output terminal.
9. The shift register of claim 1, further comprising: a current chopping unit between the input unit and the first node and between the pull-down control unit and the first node;
the current cut-off unit is configured to cause the input unit and the first node to be disconnected and the pull-down control unit and the first node to be disconnected when the output control unit inputs the high level or the low level to the signal output end under the control of the potential of the first node, so as to avoid a leakage current in the input unit and the pull-down control unit from affecting the potential of the first node.
10. The shift register according to claim 9, wherein the current chopping unit includes: a seventh transistor;
a control electrode of the seventh transistor is connected to a fourth power supply terminal, a first electrode of the seventh transistor is connected to both the input unit and the pull-down control unit, and a second electrode of the seventh transistor is connected to the first node.
11. The shift register of claim 1, further comprising: the load units are in one-to-one correspondence with the signal output ends and are connected with the corresponding signal output ends, and the load units are used for limiting the current of the corresponding signal output ends;
the load unit includes: a resistor and a third capacitor;
the first end of the resistor is connected with the corresponding signal output end, the second end of the resistor is connected with the first end of the third capacitor, and the second end of the third capacitor is grounded.
12. A gate drive circuit, comprising: a plurality of cascaded shift registers, wherein the shift registers adopt the shift register of any one of the claims 1-11;
the signal output end of the last scanning signal in the shift register of the previous stage is connected with the signal input end of the shift register of the next stage.
13. A driving method of a shift register, wherein the shift register is the shift register according to any one of claims 1 to 9, the driving method comprising:
in an input stage, the input unit inputs an input signal provided by an input signal terminal to the first node under control of a first clock signal provided by a first clock signal line, and the pull-up control unit inputs a high level or a low level to the second node under control of a potential of the first node;
in an output stage, the output control unit sends a high level or a low level to the corresponding signal output end under the control of the potential of the first node, so that the signal output end outputs a scanning signal;
in a reset phase, the pull-up control unit inputs a first voltage provided by a first power supply terminal to the second node under the control of a third node, the pull-down control unit inputs a second voltage provided by a second power supply terminal to the first node under the control of a potential of the second node to reset the first node, and the output reset unit inputs a third voltage provided by a third power supply terminal to the signal output terminal under the control of the potential of the second node to reset the signal output terminal.
14. A display substrate comprising the gate driver circuit of claim 12.
CN202210736934.6A 2017-07-20 2017-07-20 Shift register, driving method thereof and grid driving circuit Pending CN114999557A (en)

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