CN111583850B

CN111583850B - Shift register, light-emitting control circuit and display panel

Info

Publication number: CN111583850B
Application number: CN202010443540.2A
Authority: CN
Inventors: 李威龙; 卢慧玲; 张露; 胡思明
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2020-05-22
Filing date: 2020-05-22
Publication date: 2022-05-13
Anticipated expiration: 2040-05-22
Also published as: CN111583850A

Abstract

The embodiment of the invention discloses a shift register, a light-emitting control circuit and a display panel, wherein in the shift register, a second common node potential control module keeps the potential of a common node when a signal output by the shift register is a first potential signal, so that when the shift register outputs the first potential signal for a long time, the potential of the common node can be better kept, the first output control module can ensure that a signal output to a second node according to the potential signal of the common node is more accurate, the second output control module can ensure that a signal output to the first node according to the potential signal of the common node is more accurate, the conduction states of a first output module and a second output module are more accurate, namely the abnormal actions of all modules in the shift register are reduced, and the shift register can normally work when the display panel carries out low-refresh-rate display, the display effect of the display panel is ensured.

Description

Shift register, light-emitting control circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a shift register, a light-emitting control circuit and a display panel.

Background

Along with the popularization of mobile display, information required by people can be conveniently obtained through mobile phones or wearing display products, in order to obtain the information more immediately and rapidly, a mobile display needs to be not closed for a long time so that a user can see the required information at any time, and the function of continuously opening (not automatically closing) a display screen without opening and closing the display screen is a so-called AOD (always on display) display function.

In order to prevent excessive battery drain of the mobile display device, the AOD function is usually accompanied by a low refresh rate display to reduce power consumption and ensure a long service life of the mobile display device.

However, the conventional light-emitting control circuit does not support the operation of low refresh rate, and the light-emitting control circuit may have abnormal operation at low refresh rate, which may affect the display effect.

Disclosure of Invention

The invention provides a shift register, a light-emitting control circuit and a display panel, which are used for ensuring that the light-emitting control circuit can normally work under a low refreshing frequency so as to ensure the display effect.

In a first aspect, an embodiment of the present invention provides a shift register, including: the first output module, the second output module, the first output control module, the second output control module, the first common node potential control module and the second common node potential control module; the first common node potential control module is used for controlling the potential of the common node according to a signal of a first clock signal end; the second common node potential control module is electrically connected with the first node and the common node, and is used for controlling the potential of the common node according to the signal of the first clock signal end, the signal of the second clock signal end and the signal of the first node, and maintaining the potential of the common node when the shift register outputs the first potential signal; the first output control module is used for controlling the potential of a second node according to the signal of the second clock signal end and the signals of the first node and the common node; the first output module is used for transmitting a signal of the first voltage end to an output end of the shift register according to the potential of the second node; the second output control module is used for controlling the potential of the first node according to the signal of the first clock signal end, the signal of the second clock signal end and the potential of the common node; the second output module is used for transmitting a signal of a second voltage end to the output end of the shift register according to the potential of the first node.

In a second aspect, an embodiment of the present invention further provides a light emission control circuit, which is characterized by including a plurality of cascade-connected shift registers provided in the first aspect.

In a third aspect, an embodiment of the present invention further provides a display panel, including the light emission control circuit provided in the second aspect, further including a first clock signal line, a second clock signal line, a first potential signal line, and a second potential signal line, where a first voltage end of each shift register is electrically connected to the first potential signal line, and a second voltage end of each shift register is electrically connected to the second potential signal line; in the adjacent two stages of shift registers, a first clock signal end of the previous stage of shift register is electrically connected with the first clock signal line, and a second clock signal end of the previous stage of shift register is electrically connected with the second clock signal line; and the first clock signal end of the shift register of the next stage is electrically connected with the second clock signal wire, and the second clock signal end of the shift register of the next stage is electrically connected with the second clock signal wire.

In the shift register, the light emission control circuit, and the display panel provided in the embodiments of the present invention, a second common node potential control module is respectively electrically connected to the first node and the common node, and the second common node potential control module maintains the potential of the common node when a signal output by the shift register is a first potential signal (the first potential signal is a potential signal output by the shift register for a long time under a low refresh frequency of the display panel, and when the pixel circuit receives the first potential signal, the light emitting device in the pixel circuit does not emit light), so that when the shift register outputs the first potential signal for a long time, the potential of the common node can be maintained well, because the first output control module needs to control the potential of the first node according to the potential of the common node, and the second output control module needs to control the potential of the second node according to the potential of the common node, the potential of the common node is well maintained, so that the first output control module can output a signal to the second node accurately according to the potential signal of the common node, and the second output control module can output a signal to the first node accurately according to the potential signal of the common node, so that the conduction states of the first output module and the second output module are accurate, namely, the abnormal actions of all modules in the shift register are reduced, the shift register can normally work when the display panel performs low refresh rate display, and the display effect of the display panel is ensured.

Drawings

FIG. 1 is a schematic diagram of a shift register of the type commonly used in the prior art;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a simulation waveform for the output of a shift register according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a light-emitting control circuit according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional lighting control circuit does not support the operation with a low refresh rate, and the lighting control circuit may have an abnormal operation at a low refresh rate, which may affect the display effect. The inventor researches and finds that the above problems occur because the conventional light emitting control circuit generally includes a plurality of cascaded shift registers, each shift register generally includes a plurality of thin film transistors, and in order to ensure that the display panel has lower power consumption at a low refresh frequency, the shift register is generally required to output the same level signal for a long time, and the long-time output of the same level signal by the shift register can cause a certain transistor or some transistors in the shift register to be under the stress of positive voltage or the stress of negative voltage for a long time, so that the threshold voltage of the thin film transistor under the stress of positive voltage or the stress of negative voltage for a long time is subjected to positive bias or negative bias, and the positive bias or negative bias of the threshold voltage causes the leakage of the thin film transistor to increase, thereby causing abnormal operation of the shift register. Since the shift registers in the light-emitting control circuit are usually connected in cascade, the abnormal operation of one shift register may cause the abnormal operation of the whole light-emitting control circuit, and finally the display effect is affected.

Fig. 1 is a schematic structural diagram of a shift register commonly used in the prior art, and referring to fig. 1, the shift register includes a first output transistor T01, a second output transistor T02, a control transistor T03 electrically connected to a gate of the second output transistor T02, a first output control module, a second output control module, a first voltage terminal VGH, a second voltage terminal VGL, a first clock signal terminal ECK1, and a second clock signal terminal (not shown in the figure). For example, if each thin film transistor in the shift register is a P-type transistor (the gate is turned on when the signal is a low level signal), and the thin film transistor in the pixel circuit in the display panel driven by the light emission control circuit is also a P-type transistor, the shift register needs to output a high level signal for a long time, and the potential of the gate of the second output transistor T02 (i.e., the N0 node) needs to be a high potential for a long time, so that the second output transistor T02 is in an off state. However, if the potential of the N0 node is high for a long time, which may cause the control transistor T03 to be under the stress of a positive voltage for a long time, the leakage of the control transistor T03 may increase, the first output control module and the second output control module are both electrically connected to the control transistor T03, the increase of the leakage of the control transistor T03 may cause the thin film transistors in the first output control module and the second output control module to operate abnormally, the output end of the first output control module is electrically connected to the first output transistor T01, and the output end of the second output control module is electrically connected to the second output transistor T02, so the abnormal operation of the thin film transistors in the first output control module and the second output control module may cause the abnormal operation of the first output transistor T01 and the second output transistor T02, and finally, the output signal of the shift register is inaccurate, which affects the display effect.

Based on the above problem, an embodiment of the present invention provides a shift register, and fig. 2 is a schematic structural diagram of the shift register provided by the embodiment of the present invention, and referring to fig. 2, the shift register includes: a first output module 110, a second output module 120, a first output control module 130, a second output control module 140, a first common node potential control module 150, a second common node potential control module 160;

the first common node potential control module 150 is configured to control the potential of the common node a according to a signal of the first clock signal terminal ECK 1; the second common node potential control module 160 is electrically connected to the first node N1 and the common node a, and is configured to control the potential of the common node a according to the signal of the first clock signal terminal ECK1, the signal of the second clock signal terminal ECK2 and the signal of the first node N1, and to maintain the potential of the common node a when the shift register outputs the first potential signal;

the first output control module 130 is configured to control the potential of the second node N2 according to the signal of the second clock signal terminal ECK2, the signal of the first node N1 and the signal of the common node a; the first output module 110 is configured to transmit a signal of the first voltage terminal VGH to an output terminal of the shift register according to the potential of the second node N2;

the second output control module 140 is configured to control the potential of the first node N1 according to the signal of the first clock signal terminal ECK1, the signal of the second clock signal terminal ECK2 and the potential of the common node a; the second output module 120 is used for transmitting the signal of the second voltage terminal VGL to the output terminal OUT of the shift register according to the potential of the first node N1.

Specifically, the shift registers may be used in a light emission control circuit, and in the display panel, each shift register may be connected to at least one light emission control line, and each light emission control line may be connected to one row of pixel circuits. Optionally, when the output signal of the shift register is the first potential signal, the light emitting device in the pixel circuit does not emit light, and when the output signal of the shift register is the second potential signal, the light emitting device in the pixel circuit emits light. For example, when the light emission control transistor in the pixel circuit is a P-type transistor, the first potential signal is a high potential signal, and the second potential signal is a low potential signal. As described above, if the shift register outputs a signal of the same level for a long time, some or some transistors in the shift register may be under the stress of positive voltage or negative voltage for a long time, which may increase the leakage of the thin film transistor whose gate is electrically connected to the gate of the output transistor, and may cause the potential of the node electrically connected to the source or the drain of the thin film transistor to be unstable, which may cause an abnormal operation of the shift register.

In the present invention, the first node N1 is equivalent to the N0 node in the shift register shown in fig. 1. In the shift register of this embodiment, the second common node potential control module 160 is electrically connected to the first node N1 and the common node a, respectively, and the second common node potential control module 160 maintains the potential of the common node a when the signal output by the shift register is the first potential signal (the first potential signal is a potential signal output by the shift register for a long time at a low refresh frequency, and when the pixel circuit receives the first potential signal, the light emitting device in the pixel circuit does not emit light), for example, the second common node potential control module 160 may have a smaller leakage current than the control transistor T03 in the shift register shown in fig. 1, so that when the shift register outputs the first potential signal for a long time, the potential of the common node a can be maintained well, because the first output control module 130 needs to control the potential of the first node N1 according to the potential of the common node a, the second output control module 140 needs to control the potential of the second node N2 according to the potential of the common node a, and the potential of the common node a is well maintained, so that it can be ensured that the signal output from the first output control module 130 to the second node N2 according to the potential signal of the common node a is relatively accurate, and that the signal output from the second output control module 140 to the first node N1 according to the potential signal of the common node a is relatively accurate, and further, the conduction states of the first output module 110 and the second output module 120 are relatively accurate, that is, the abnormal actions of the modules in the shift register are reduced, it is ensured that the shift register can normally work when the display panel performs low refresh rate display, and the display effect of the display panel is ensured.

The above is the core idea of the present invention, and the following will clearly and completely describe the technical solution in the embodiment of the present invention with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

With continued reference to fig. 2, optionally, the first common node potential control module 150 is electrically connected to the first clock signal terminal ECK1, the second voltage terminal VGL, and the common node a, respectively; the second common node potential control module 160 is further electrically connected to the first clock signal terminal ECK1, the second clock signal terminal ECK2, the first voltage terminal VGH, and the second voltage terminal VGL, respectively; the first output control module 130 is electrically connected to the second clock signal terminal ECK2, the first voltage terminal VGH, the first node N1, and the common node a and the second node N2, respectively; the second output control module 140 is electrically connected to a signal of the first clock signal terminal ECK1, a signal of the second clock signal terminal ECK2, the common node a, the first voltage terminal VGH, the first node N1, and the start signal terminal, respectively; the first output module 110 is electrically connected to the second node N2, the first voltage terminal VGH, and the output terminal of the shift register, respectively; the second output module 120 is electrically connected to the first node N1, the second voltage terminal VGL, and the output terminal of the shift register, respectively.

Fig. 3 is a driving timing diagram of a shift register according to an embodiment of the present invention, where the driving timing diagram can be used to drive the shift register shown in fig. 1, and referring to fig. 2 and fig. 3, an operation process of the shift register shown in fig. 2 includes a first stage t1, a second stage t2, a third stage 23, a fourth stage t4, a fifth stage t5, a sixth stage t6, and a seventh stage t 7. Optionally, the signal input by the first voltage end VGH is a first potential signal, the signal input by the second voltage end VGL is a second potential signal, and optionally, the first potential signal is a high potential, and the second potential signal is a low potential. Hereinafter, a signal input to the first clock signal input terminal is referred to as a first clock signal, and a signal input to the second clock signal input terminal is referred to as a second clock signal. The following description will take the example that the first clock signal and the second clock signal are both active at low potential (i.e. the module controlled by the first clock signal is turned on when the first clock signal is at low potential, and the module controlled by the second clock signal is turned on when the second clock signal is at low potential).

In the first period t1, the start signal terminal inputs a low voltage, the first clock signal is at a low voltage, and the second clock signal is at a high voltage. The first common node potential control module 150 transmits a low potential signal of the second voltage terminal VGL to the common node a in response to a low potential of the first clock signal, so that the potential of the common node a is a low potential. The second common node potential control module 160 transmits a low potential signal of the second voltage terminal VGL to the common node a in response to the low potential of the first node N1 and the low potential of the first clock signal. The second output control module 140 is turned on between the start signal terminal and the first node N1 in response to the low level of the first clock signal, and transmits the low level signal of the start signal terminal to the first node N1, and the second output control module 120 is turned on in response to the low level of the first node N1, so that the low level signal of the second voltage terminal VGL is transmitted to the output terminal of the shift register. The first output control module 130 responds to the low voltage level of the first node N1 to enable the first voltage terminal VGH to be connected to the second node N2, so that the high voltage level of the first voltage terminal VGH is transmitted to the second node N2, and the first output control module 110 responds to the high voltage level of the second node N2 to be disconnected, so that the high voltage level of the first voltage terminal VGH cannot be transmitted to the output terminal of the shift register.

In the second phase t2, the start signal terminal inputs a low voltage, the first clock signal is at a high voltage, and the second clock signal is at a low voltage. Optionally, the second output control module 140 includes a first storage unit electrically connected to the first node N1, and the first storage unit is configured to store the potential of the first node N1, so that the potential of the first node N1 is kept at a low potential. The second output module 120 is turned on in response to the low level of the first node N1 during the second stage t2, such that the low level signal of the second voltage terminal VGL is transmitted to the output terminal of the shift register. The first output control module 130 responds to the low voltage level of the first node N1 to make the first voltage terminal VGH and the second node N2 turn on, so that the high voltage level of the first voltage terminal VGH is transmitted to the second node N2, and the first output module 110 responds to the high voltage level of the second node N2 to turn off, so that the high voltage level of the first voltage terminal VGH cannot be transmitted to the output terminal of the shift register. The second common node potential control module 160 transmits a high potential signal of the first voltage terminal VGH to the common node a in response to the low potential of the first node N1 and the low potential of the second clock signal. Therefore, in the second stage t2, the output terminal of the shift register continues to output the low signal.

In the third stage t3, the start signal terminal inputs a high voltage, the first clock signal is a low voltage, and the second clock signal is a high voltage. The first common node potential control module 150 transmits a low potential signal of the second voltage terminal VGL to the common node a in response to the first clock signal, so that the potential of the common node a is a low potential. The second output control module 140 responds to the low level of the first clock signal to turn on the start signal terminal and the first node N1, and transmits the high level signal of the start signal terminal to the first node N1, and the second output control module 120 responds to the high level of the first node N1 to turn off, so that the low level signal of the second voltage terminal VGL cannot be transmitted to the output terminal of the shift register. The first output control module 130 is responsive to the high voltage level of the first node N1 to disable the conduction between the first voltage terminal VGH and the second node N2, such that the high voltage level of the first voltage terminal VGH cannot be transmitted to the second node N2, and the first output control module 130 is responsive to the high voltage level of the second clock signal terminal ECK2 to disable the conduction between the second clock signal terminal ECK2 and the second node N2; the first output module 110 may include a second storage unit, and the second storage unit may be configured to store the potential of the second node N2, such that the second node N2 maintains the high potential of the previous stage, and the first output module 110 is also turned off. The second common node potential control module 160 is turned off according to the high potential of the first node N1. Therefore, in the third stage t3, the first output block 110 and the second output block 120 are both turned off, and the output terminal of the shift register maintains the low potential outputted from the previous stage.

In the fourth period t4, the start signal terminal inputs a high voltage, the first clock signal is a high voltage, and the second clock signal is a low voltage. Optionally, the first output control module 130 includes a third storage unit electrically connected to the common node a, and the third storage unit can be used for storing the potential of the common node a. The first output control module 130 is responsive to a low level of the common node a and a low level of the second clock signal terminal ECK2 to make the second clock signal terminal ECK2 and the second node N2 conductive, and transmit a low level signal of the second clock signal terminal ECK2 to the second node N2, and the first output module 110 is responsive to a low level of the second node N2 to be conductive, and transmit a high level signal of the first voltage terminal VGH to the output terminal of the shift register. Meanwhile, the second output control module 140 responds to the low potential of the common node a and the low potential of the second clock signal terminal ECK2, so that the first voltage terminal VGH is connected to the first node N1, the high potential signal of the first voltage terminal VGH is transmitted to the first node N1, and the second output module 120 responds to the high potential of the first node N1 and is turned off, so that the low potential signal of the second voltage terminal VGL cannot be transmitted to the output terminal of the shift register. The second common node potential control module 160 is turned off according to the high potential of the first node N1.

In the fifth phase t5, the start signal terminal inputs a high voltage, the first clock signal is a low voltage, and the second clock signal is a high voltage. The first common node potential control module 150 is turned on in response to a low potential of the first clock signal, and transmits a low potential signal of the second voltage terminal VGL to the common node a, which is a low potential. The second output control module 140 turns on the start signal terminal and the first node N1 in response to the low level of the first clock signal, transmits the high level of the start signal terminal to the first node N1, and turns off the second output module 120 in response to the high level of the first node N1. And the second output control module 140 responds to the high level of the second clock signal, such that the first voltage terminal VGH is not conducted with the first node N1. The first output control module 130 is responsive to the high signal of the second clock signal terminal ECK2 to disable the conduction between the second clock signal terminal ECK2 and the second node N2, and the first output control module 130 is responsive to the high signal of the first node N1 to disable the conduction between the first voltage terminal VGH and the second node N2. In the fifth phase t5, the second memory cell of the first output module 110 maintains the low voltage level at the second node N2, and the first output module 110 is turned on in response to the low voltage level at the second node N2 to transmit the high voltage level at the first voltage terminal VGH to the output terminal of the shift signal. The second common node potential control module 160 is turned off according to the high potential of the first node N1.

In the sixth phase t6, the start signal terminal inputs a low signal, the first clock signal is high, and the second clock signal is low. The first common node potential control module 150 is turned off in response to a high level of the first clock signal, such that the second voltage terminal VGL is not conducted with the common node a. The first memory cell maintains the high voltage level of the first node N1, and the second common node a control voltage level module is turned off in response to the high voltage level of the first node N1, such that neither the high voltage signal of the first voltage terminal VGH nor the low voltage signal of the second voltage terminal VGL can be transmitted to the common node a through the second common node control voltage module 160. The second memory cell holds a low potential for a stage on the common node a. The first output control module 130 is responsive to a low level of the common node a and a low level of the second clock signal to make the second clock signal terminal ECK2 and the second node N2 conduct, and transmit a low level of the second clock signal to the first node N1, and the first output module 110 is responsive to a low level of the first node N1 to conduct, and transmit a high level signal of the first voltage terminal VGH to the output terminal of the shift register.

In the seventh phase t7, the start signal terminal inputs a low voltage, the first clock signal is at a low voltage, and the second clock signal is at a high voltage. The first common node potential control module 150 is turned on in response to the low potential of the first clock signal, and transmits the low potential signal of the second voltage terminal VGL to the common node a, so that the potential of the common node a is a low potential. The second output control module 140 is turned on between the start signal terminal and the first node N1 in response to the low level of the first clock signal, and transmits the low level signal of the start signal terminal to the first node N1, and the second output control module 120 is turned on in response to the low level of the first node N1, so that the low level signal of the second voltage terminal VGL is transmitted to the output terminal of the shift register. The first output control module 130 responds to the low voltage level of the first node N1 to enable the first voltage terminal VGH to be connected to the second node N2, so that the high voltage level of the first voltage terminal VGH is transmitted to the second node N2, and the first output control module 110 responds to the high voltage level of the second node N2 to be disconnected, so that the high voltage level of the first voltage terminal VGH cannot be transmitted to the output terminal of the shift register.

As can be seen from the above analysis of the operation process of the shift register, in the third stage t3, the fourth stage t4, the fifth stage t5 and the sixth stage t6, the potential of the first node N1 is a first potential signal, which is a signal of the first voltage terminal VGH (in the embodiments of the present invention, the first potential signal is a high potential signal). In the shift register of this embodiment, when the signal output by the shift register is the first potential signal (the first potential signal is a potential signal output by the display panel at a low refresh frequency for a long time by the shift register, and when the pixel circuit receives the first potential signal, the light emitting device in the pixel circuit does not emit light), the potential of the common node a is maintained, for example, the second common node potential control module 160 may have a smaller leakage current than the control transistor T03 in the shift register shown in fig. 1, so that when the shift register outputs the first potential signal for a long time, the potential of the common node a may be maintained well, and it is ensured that the shift register may operate normally when the display panel performs low refresh rate display, thereby ensuring the display effect of the display panel.

Fig. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and referring to fig. 4, optionally, the second common node potential control module 160 includes a first leakage prevention unit 151 and a second leakage prevention unit 152; the first anti-creeping unit 151 includes a first input terminal electrically connected to the second voltage terminal VGL, a first output terminal electrically connected to the first node N1, a first control terminal electrically connected to the first clock signal terminal ECK1, and a second control terminal electrically connected to the common node a; the second anti-leakage unit 152 includes a second input terminal electrically connected to the first voltage terminal VGH, a second output terminal electrically connected to the first node N1, a third control terminal electrically connected to the second clock signal terminal ECK2, and a fourth control terminal electrically connected to the common node a.

Specifically, the first leakage prevention unit 151 is turned on or off according to the potential of the first node N1 and the first clock signal, and for example, when the first leakage prevention unit 151 is active at a low level, the potential of the first node N1 is at a low level, and the first clock signal is at a low level, the first leakage prevention unit 151 is turned on, and transmits the signal of the second voltage terminal VGL to the common node a. The second leakage preventing unit 152 is turned on or off according to the potential of the first node N1 and the second clock signal, and for example, when the second leakage preventing unit 152 is active low, the first node N1 is low and the second clock signal is low, the second leakage preventing unit 152 is turned on and transmits the signal of the first voltage terminal VGH to the common node a. Optionally, the first anti-leakage unit 151 and the second anti-leakage unit 152 may have a smaller leakage current than the control transistor T03 in fig. 1, so that when the shift register outputs the first potential signal for a long time, the potential of the common node a may be better maintained, and the shift register may work normally when the display panel performs low refresh rate display, thereby ensuring the display effect of the display panel.

With continued reference to fig. 4, optionally, the first anti-leakage unit 151 includes a first transistor T1 and a second transistor T2, a gate of the first transistor T1 serves as a first control terminal of the first anti-leakage unit 151, a first pole of the first transistor T1 serves as a first input terminal of the first anti-leakage unit 151, and a second pole of the first transistor T1 is electrically connected to a first pole of the second transistor T2; the gate of the second transistor T2 serves as the second control terminal of the first anti-leakage unit 151, and the second pole of the second transistor T2 serves as the first output terminal of the first anti-leakage unit 151.

Specifically, the first transistor T1 turns on or off in response to the potential of the first node N1, the second transistor T2 turns on or off in response to the first clock signal, and transmits the second potential signal of the second voltage terminal VGL to the common node a when both the first transistor T1 and the second transistor T2 are turned on, for example, when both the first transistor T1 and the second transistor T2 are P-type transistors, the first transistor T1 and the second transistor T2 are turned on when the potential of the first node N1 is low and the first clock signal is low. By providing the first anti-leakage unit 151 including the first transistor T1 and the second transistor T2, and electrically connecting the gate of the first transistor T1 as a first control terminal to the first node N1 (corresponding to the node N0 in fig. 1), so that the output terminal of the shift register outputs the first potential signal for a long time (the first potential signal is a potential signal output by the shift register for a long time at a low refresh frequency, and when the pixel circuit receives the first potential signal, the light emitting device in the pixel circuit does not emit light), for example, when the second output module 120 includes a P-type thin film transistor, and the potential of the first node N1 is a high potential signal for a long time, the first transistor T1 is still under the stress of a positive voltage for a long time, but the second transistor T2 is further included between the first transistor T1 and the common node a, and the second transistor T2 can block the leakage of the first transistor T1, compared with a control transistor T03 electrically connected with the node N0 in the prior art shown in FIG. 1, the first anti-leakage unit 151 has a smaller leakage current, so that the potential of the common node A can be well maintained, thereby reducing the abnormal operation of the shift register and ensuring the normal operation of the shift register.

Alternatively, the second transistor T2 is an oxide transistor, for example, the second transistor T2 may be an IGZO transistor. Since the leakage current of the oxide transistor is small, providing the second transistor T2 as an oxide transistor can further prevent the leakage current of the first transistor T1 from flowing to the common node a through the second transistor T2, so that the potential of the common node a can be better maintained.

Alternatively, the first transistor T1 is an oxide transistor, for example, the first transistor T1 may be an IGZO transistor. Since the leakage current of the oxide transistor is small, the first transistor T1 is an IGZO transistor, so that the leakage current of the first transistor T1 itself is small, and the potential of the common node a is further favorably maintained.

With continued reference to fig. 4, optionally, the second anti-leakage unit 152 includes a third transistor T3 and a fourth transistor T4, a gate of the third transistor T3 is used as a third control terminal of the second anti-leakage unit 152, a first pole of the third transistor T3 is used as a second input terminal of the second anti-leakage unit 152, and a second pole of the third transistor T3 is electrically connected to a first pole of the fourth transistor T4; the gate of the fourth transistor T4 serves as the fourth control terminal of the second leakage preventing unit 152, and the second pole of the fourth transistor T4 serves as the second output terminal of the second leakage preventing unit 152.

Specifically, the third transistor T3 turns on or off in response to the potential of the first node N1, the fourth transistor T4 turns on or off in response to the second clock signal, and transmits the second potential signal of the second voltage terminal VGL to the common node a when both the third transistor T3 and the fourth transistor T4 are turned on, for example, when both the third transistor T3 and the fourth transistor T4 are P-type transistors, the third transistor T3 and the fourth transistor T4 are turned on when the potential of the first node N1 is low and the second clock signal is low. By providing the first anti-leakage unit 151 including the third transistor T3 and the fourth transistor T4, and the gate of the third transistor T3 as the third control terminal is electrically connected to the first node N1 (corresponding to the N0 node in fig. 1), so that the output terminal of the shift register outputs the first potential signal for a long time (the first potential signal is the potential signal output by the shift register for a long time at a low refresh frequency, and when the pixel circuit receives the first potential signal, the light emitting device in the pixel circuit does not emit light), for example, when the second output module 120 includes a P-type thin film transistor, and the potential of the first node N1 is high for a long time, the third transistor T3 is still under the stress of a positive voltage for a long time, but the fourth transistor T4 is further included between the third transistor T3 and the common node a, and the fourth transistor T4 can cut off the leakage of the third transistor T3, compared with a control transistor T03 electrically connected to the node N0 in fig. 1 in the prior art, the second anti-leakage unit 152 has a smaller leakage current, so that the potential of the common node a can be well maintained, thereby reducing the abnormal operation of the shift register and ensuring the normal operation of the shift register.

Fig. 5 is a schematic structural diagram of another shift register according to an embodiment of the present invention, referring to fig. 5, optionally, the first output control module 130 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1, a gate of the fifth transistor T5 is electrically connected to a first node N1, a first pole of the fifth transistor T5 is electrically connected to the first voltage terminal VGH, and a second pole of the fifth transistor T5 is electrically connected to a second node N2; a gate of the sixth transistor T6 is electrically connected to the common node a, a first pole of the sixth transistor T6 is electrically connected to the second clock signal terminal ECK2, and a second pole of the sixth transistor T6 is electrically connected to the first pole of the seventh transistor T7; a gate of the seventh transistor T7 is electrically connected to the second clock signal terminal ECK2, and a second pole of the seventh transistor T7 is electrically connected to the second node N2; one end of the first capacitor C1 is electrically connected to the gate of the sixth transistor T6, and the other end of the first capacitor C1 is electrically connected to the second pole of the sixth transistor T6.

Specifically, the fifth transistor T5 turns on or off in response to the potential of the first node N1, and transmits the first potential signal of the first voltage terminal VGH to the second node N2 when turned on, for example, when the fifth transistor T5 is a P-type transistor, the fifth transistor T5 turns on when the first node N1 is at a low potential. The sixth transistor T6 is turned on or off in response to the potential of the common node a, the seventh transistor T7 is turned on or off in response to the potential of the second clock signal, and when both the sixth transistor T6 and the seventh transistor T7 are turned on, the potential of the second clock signal is transmitted to the second node N2 through the sixth transistor T6 and the seventh transistor T7, for example, when the sixth transistor T6 and the seventh transistor T7 are P-type transistors, the sixth transistor T6 is turned on when the common node a is at a low potential, and the seventh transistor T7 is turned on when the second clock signal is at a low potential. The first capacitor C1 may be used as the third storage unit in the above embodiments to store the potential of the common node a.

Fig. 6 is a schematic structural diagram of another shift register provided in the embodiment of the present invention, referring to fig. 6, optionally, the second output control module 140 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2, a gate of the eighth transistor T8 is electrically connected to the first clock signal terminal ECK1, a first electrode of the eighth transistor T8 is electrically connected to the start signal terminal, and a second electrode of the eighth transistor T8 is electrically connected to the first node N1; a gate of the ninth transistor T9 is electrically connected to the common node a, a first pole of the ninth transistor T9 is electrically connected to the first voltage terminal VGH, and a second pole of the ninth transistor T9 is electrically connected to the first pole of the tenth transistor T10; a gate of the tenth transistor T10 is electrically connected to the second clock signal terminal ECK2, and a second pole of the tenth transistor T10 is electrically connected to the first node N1; the first terminal of the second capacitor C2 is electrically connected to the second clock signal terminal ECK2, and the first terminal of the second capacitor C2 is electrically connected to the first node N1.

Specifically, the eighth transistor T8 turns on or off in response to the potential of the first clock signal, and transmits a signal of the start signal terminal to the first node N1 when turned on; the ninth transistor T9 is turned on or off in response to the potential of the common node a, the tenth transistor T10 is turned on or off in response to the potential of the second clock signal, and the first voltage signal of the first voltage terminal VGH is transmitted to the first node N1 through the ninth transistor T9 and the tenth transistor T10 when the ninth transistor T9 and the tenth transistor T10 are turned on. The second capacitor C2 may be used as the first storage unit in the above embodiments to hold the potential of the first node N1.

Fig. 7 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and referring to fig. 7, optionally, the first output module 110 includes an eleventh transistor T11 and a third capacitor C3, a gate of the eleventh transistor T11 is electrically connected to the second node N2, a first pole of the eleventh transistor T11 is electrically connected to the first voltage terminal VGH, and a second pole of the eleventh transistor T11 is electrically connected to the output terminal of the shift register; a first point of the third capacitor C3 is electrically connected to the gate of the eleventh transistor T11, and a second end of the third capacitor C3 is electrically connected to the first pole of the eleventh transistor T11; preferably, the second output module 120 includes a twelfth transistor T12, a gate of the twelfth transistor T12 is electrically connected to the first node N1, a first pole of the twelfth transistor T12 is electrically connected to the second voltage terminal VGL, and a second pole of the twelfth transistor T12 is electrically connected to the output terminal of the shift register; preferably, the first common node potential control module 150 includes a thirteenth transistor T13, a gate of the thirteenth transistor T13 is electrically connected to the first clock signal terminal ECK1, a first pole of the thirteenth transistor T13 is electrically connected to the second voltage terminal VGL, and a second pole of the thirteenth transistor T13 is electrically connected to the common node a.

Specifically, the eleventh transistor T11 turns on or off in response to the potential of the second node N2 and transmits the first potential signal of the first voltage terminal VGH to the output terminal of the shift register when turned on, and the third capacitor C3 may serve as the second storage unit in the above-described embodiment for storing the potential of the second node N2. The twelfth transistor T12 turns on or off in response to the potential of the first node N1, and transmits the potential of the second voltage terminal VGL to the output terminal of the shift register when turned on. The thirteenth transistor T13 turns on or off in response to the potential of the first clock signal, and transmits the second potential signal of the second voltage terminal VGL to the common node a when turned on.

Fig. 8 is a schematic structural diagram of another shift register provided in the embodiment of the present invention, and referring to fig. 8, optionally, the second common node potential control module 160 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; the first output control module 130 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1; the second output control module 140 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2; the first output module 110 includes an eleventh transistor T11 and a third capacitor C3; the second output module 120 includes a twelfth transistor T12; the first common node potential control block 150 includes a thirteenth transistor T13.

The driving sequence shown in fig. 2 is also applicable to driving the shift register shown in fig. 8, and referring to fig. 2 and 8, the working process of the shift register includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6 and a seventh stage t 7. Optionally, the first potential signal is a high potential, and the second potential signal is a low potential. In the following, the first clock signal and the second clock signal are active at low voltage (i.e. the transistor controlled by the first clock signal is turned on when the first clock signal is at low voltage, and the transistor controlled by the second clock signal is turned on when the second clock signal is at low voltage).

In the first period t1, the start signal terminal inputs a low voltage, the first clock signal is at a low voltage, and the second clock signal is at a high voltage. The eighth transistor T8 is turned on in response to the low level of the first clock signal, transmits the low level signal of the start signal terminal to the first node N1, and the second capacitor C2 is written with the low level. The twelfth transistor T12 is turned on in response to the low potential of the first node N1, so that a low potential signal of the second voltage terminal VGL is transmitted to the output terminal of the shift register. The fifth transistor T5 is turned on in response to the low potential of the first node N1, such that the high potential of the first voltage terminal VGH is transmitted to the second node N2, and the eleventh transistor T11 is turned off in response to the high potential of the second node N2, such that the high potential of the first voltage terminal VGH cannot be transmitted to the output terminal of the shift register. The thirteenth transistor T13 turns on in response to the low level of the first clock signal, and transmits a low level signal of the second voltage terminal VGL to the common node a; the first transistor T1 is turned on in response to the low potential of the first node N1, the second transistor T2 is turned on in response to the low potential of the first clock signal, and the low potential signal of the second voltage terminal VGL is transmitted to the common node a. Meanwhile, the first capacitor C1 is written with a low signal at the second voltage terminal VGL.

In the second phase t2, the start signal terminal inputs a low voltage, the first clock signal is at a high voltage, and the second clock signal is at a low voltage. Optionally, the second capacitor C2 stores the potential of the first node N1, so that the potential of the first node N1 is kept at a low potential. Then, in the second stage T2, the twelfth transistor T12, the fifth transistor T5, the first transistor T1 and the third transistor T3 are turned on in response to the low potential of the first node N1, and the low potential signal of the second voltage terminal VGL is transmitted to the output terminal of the shift register through the twelfth transistor T12. The high voltage of the first voltage terminal VGH is transmitted to the second node N2 through the fifth transistor T5, and the third capacitor C3 is written with the high voltage, so that the eleventh transistor T11 is turned off in response to the high voltage of the second node N2, and the high voltage of the first voltage terminal VGH cannot be transmitted to the output terminal of the shift register. The fourth transistor T4 is turned on in response to the low level of the second clock signal, and the high level signal of the first voltage terminal VGH is transmitted to the common node a through the third transistor T3 and the fourth transistor T4 while the first capacitor C1 is written with the high level.

In the third stage t3, the start signal terminal inputs a high voltage, the first clock signal is a low voltage, and the second clock signal is a high voltage. The thirteenth transistor T13 and the eighth transistor T8 are turned on in response to the low level of the first clock signal, the low level of the second voltage terminal VGL is transmitted to the common node a through the thirteenth transistor T13, such that the potential of the common node a is low, while the first capacitor C1 is written with the low level, the sixth transistor T6 is turned on in response to the low level of the common node a, but the seventh transistor T7 is turned off due to the high level of the second clock signal, such that the potential of the second clock signal terminal ECK2 cannot be transmitted to the second node N2. The high level signal of the start signal terminal is transmitted to the first node N1 through the eighth transistor T8, and the twelfth transistor T12 and the fifth transistor T5 are turned off in response to the high level of the first node N1. The third capacitor C3 keeps the high voltage at the second node N2 for a period of time, so that the eleventh transistor T11 is also turned off. Therefore, in the third stage T3, both the eleventh transistor T11 and the twelfth transistor T12 are turned off, and the output terminal of the shift register maintains the low potential outputted from the previous stage. While the first transistor T1 and the third transistor T3 are turned off in response to the high potential of the first node N1.

In the fourth period t4, the start signal terminal inputs a high voltage, the first clock signal is a high voltage, and the second clock signal is a low voltage. The first capacitor C1 stores the potential of the common node a so that the common node a remains at the low potential of the previous stage. The sixth transistor T6 is turned on in response to the low potential of the common node a, the seventh transistor T7 is turned on in response to the low potential of the second clock signal terminal ECK2, transmits the low potential signal of the second clock signal terminal ECK2 to the second node N2, and the eleventh transistor T11 is turned on in response to the low potential of the second node N2, and transmits the high potential signal of the first voltage terminal VGH to the output terminal of the shift register. Meanwhile, the ninth transistor T9 is turned on in response to the low potential of the common node a, the tenth transistor T10 is turned on in response to the low potential of the second clock signal terminal ECK2, transmits the high potential signal of the first voltage terminal VGH to the first node N1, and the twelfth transistor T12 is turned off in response to the high potential of the first node N1, such that the low potential signal of the second voltage terminal VGL cannot be transmitted to the output terminal of the shift register. While the first transistor T1 and the third transistor T3 are turned off in response to the high potential of the first node N1.

In the fifth phase t5, the start signal terminal inputs a high voltage, the first clock signal is a low voltage, and the second clock signal is a high voltage. The eighth transistor T8 is turned on in response to a low potential of the first clock signal, transmits a high potential of the start signal terminal to the first node N1, and the twelfth transistor T12, the fifth transistor T5, the first transistor T1, and the third transistor T3 are turned off in response to a high potential of the first node N1. And the high potential of the second clock signal turns off the tenth transistor T10 and the seventh transistor T7. The thirteenth transistor T13 is turned on in response to the low level of the first clock signal, and transmits a low level signal of the second voltage terminal VGL to the common node a and the first capacitor C1, and the common node a is at a low level. In the fifth stage T5, the third capacitor C3 maintains the low potential of the second node N2, and the eleventh transistor T11 is turned on in response to the low potential of the second node N2, so as to transmit the high potential of the first voltage terminal VGH to the output terminal of the shift signal.

In the sixth phase t6, the start signal terminal inputs a low signal, the first clock signal is high, and the second clock signal is low. The eighth transistor T8 and the thirteenth transistor T13 are turned off according to the high potential of the first clock signal. The first capacitor C1 holds the low potential on the common node a for the first period. The sixth transistor T6 is turned on in response to the low potential of the common node a, the seventh transistor T7 is turned on in response to the low potential of the second clock signal, transmits the low potential of the second clock signal to the first node N1, and the eleventh transistor T11 is turned on in response to the low potential of the first node N1, and transmits the high potential signal of the first voltage terminal VGH to the output terminal of the shift register. While the first transistor T1 and the third transistor T3 are turned off in response to the high potential of the first node N1.

In the seventh phase t7, the start signal terminal inputs a low voltage, the first clock signal is at a low voltage, and the second clock signal is at a high voltage. The thirteenth transistor T13 turns on in response to the low level of the first clock signal, and transmits the low level signal of the second voltage terminal VGL to the common node a, so that the potential of the common node a is low. The eighth transistor T8 is turned on in response to a low level of the first clock signal to transmit a low level signal of the start signal terminal to the first node N1, and the twelfth transistor T12 is turned on in response to a low level of the first node N1, so that a low level signal of the second voltage terminal VGL is transmitted to the output terminal of the shift register. The fifth transistor T5 is turned on in response to the low potential of the first node N1, such that the high potential of the first voltage terminal VGH is transmitted to the second node N2, and the eleventh transistor T11 is turned off in response to the high potential of the second node N2, such that the high potential of the first voltage terminal VGH cannot be transmitted to the output terminal of the shift register.

It should be noted that, in any of the embodiments of the present invention, each module in the shift register includes a transistor, and the structure and the manufacturing process of the shift register are simpler because the transistor has a simple structure and a simple manufacturing process. When the shift register is applied to a display panel, the transistors in the shift register and the transistors on the display panel can be manufactured in the same process flow, so that the process flow is saved, and the cost is reduced.

It should be noted that, in the seventh phase T7 (refer to fig. 3) of the operation process of the shift register according to any of the above embodiments of the present invention, the low potential signal output by the shift register is not completely equal to the second potential signal of the second voltage terminal VGL, and because the transistor is turned off for a certain time, in the seventh phase T7, the first output module 110 (or the eleventh transistor T11) is not completely turned off, so that the potential signal output by the shift register in this phase is higher than the potential of the second potential signal.

Fig. 9 is a schematic diagram of an output simulation waveform of a shift register according to an embodiment of the present invention, where in fig. 9, an abscissa represents time, an ordinate represents an output voltage, a first waveform 11 is an ideal output waveform, a second waveform 12 is an output waveform of the shift register in the prior art shown in fig. 1, and a third waveform 13 is an output waveform of the shift register according to the embodiment of the present invention, and it can be seen from the simulation waveform shown in fig. 9 that the output waveform of the shift register according to the embodiment of the present invention is substantially consistent with the ideal output waveform, so that the shift register can be ensured to normally operate at a low refresh frequency, and further, the influence of inaccurate waveform output of the shift register in the prior art on a display effect can be improved.

An embodiment of the present invention further provides a light-emitting control circuit, fig. 10 is a schematic structural diagram of the light-emitting control circuit provided in the embodiment of the present invention, and referring to fig. 10, the light-emitting control circuit includes a plurality of cascade-connected shift registers 100 provided in any of the above embodiments of the present invention.

Referring to fig. 11, the display panel 200 includes the light emitting control circuit of the above embodiment, and further includes a first clock signal line 210, a second clock signal line 220, a first potential signal line 230, and a second potential signal line 240, wherein a first voltage end VGH of each shift register 100 is electrically connected to the first potential signal line 230, and a second voltage end VGL of each shift register 100 is electrically connected to the second potential signal line 240; in the adjacent two stages of shift registers, the first clock signal end ECK1 of the previous stage of shift register is electrically connected with the first clock signal line 210, and the second clock signal end ECK2 of the previous stage of shift register is electrically connected with the second clock signal line 220; the first clock signal terminal ECK1 of the next shift register stage is electrically connected to the second clock signal line 220, and the second clock signal terminal ECK2 of the next shift register stage is electrically connected to the second clock signal line 220.

The display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, an electronic paper display panel, or the like. The output terminal of each stage of the shift register is electrically connected to the light emission control line 260 on the display panel, and transmits a scan signal to each light emission control line 260. Referring to fig. 11, the display panel further includes a start signal line 250, and a start signal terminal of the first stage shift register is electrically connected to the start signal line 250, and shifts a start signal on the start signal line 250 and outputs the start signal through an output terminal of the shift register. In the adjacent two stages of shift registers, the next stage shift register shifts and outputs the signal output by the previous stage shift register. Therefore, the display panel provided by the embodiment of the invention realizes the function of outputting signals (such as light-emitting control signals) line by line, and the signal stability output by each stage of shift register is good.

Fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 12, optionally, the light-emitting control circuit is disposed on two sides of the display panel. Because of the luminescence control line 260 has certain impedance and capacitive reactance, it is located display panel's both sides to set up the luminescence control circuit, and in the luminescence control circuit of both sides, the same luminescence control line 260 can be connected to the same stage shift register, provides the luminescence control signal for luminescence control line 260 from both sides promptly, and then is favorable to reducing the influence of impedance and capacitive reactance on the luminescence control line 260 to display effect for show more evenly in the display panel, improve display effect.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register, comprising: the first output module, the second output module, the first output control module, the second output control module, the first common node potential control module and the second common node potential control module;

the first common node potential control module is used for controlling the potential of the common node according to a signal of a first clock signal end; the second common node potential control module is electrically connected with the first node and the common node, and is used for controlling the potential of the common node according to the signal of the first clock signal end, the signal of the second clock signal end and the signal of the first node, and maintaining the potential of the common node when the shift register outputs the first potential signal;

the first output control module is used for controlling the potential of a second node according to the signal of the second clock signal end and the signals of the first node and the common node; the first output module is used for transmitting a signal of a first voltage end to an output end of the shift register according to the potential of the second node;

the second output control module is used for controlling the potential of the first node according to the signal of the first clock signal end, the signal of the second clock signal end and the potential of the common node; the second output module is used for transmitting a signal of a second voltage end to the output end of the shift register according to the potential of the first node.

2. The shift register according to claim 1, wherein the first common node potential control block is electrically connected to the first clock signal terminal, the second voltage terminal, and the common node, respectively;

the second common node potential control module is further electrically connected with the first clock signal terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal respectively;

the first output control module is electrically connected with the second clock signal terminal, the first voltage terminal, the first node, the common node and the second node respectively;

the second output control module is electrically connected with the first clock signal end, the second clock signal end, the common node, the first voltage end, the first node and the starting signal end respectively;

the first output module is electrically connected with the second node, the first voltage end and the output end of the shift register respectively;

the second output module is electrically connected with the first node, the second voltage end and the output end of the shift register respectively.

3. The shift register according to claim 1, wherein the second common node potential control block includes a first leakage preventing unit and a second leakage preventing unit;

the first anti-creeping unit comprises a first input end, a first output end, a first control end and a second control end, wherein the first input end is electrically connected with the second voltage end, the first control end is electrically connected with the first node, the second control end is electrically connected with the first clock signal end, and the first output end is electrically connected with the common node;

the second anti-creeping unit comprises a second input end, a second output end, a third control end and a fourth control end, the second input end is electrically connected with the first voltage end, the third control end is electrically connected with the first node, the fourth control end is electrically connected with the second clock signal end, and the second output end is electrically connected with the common node.

4. The shift register according to claim 3, wherein the first leakage preventing unit includes a first transistor and a second transistor, a gate of the first transistor serves as a first control terminal of the first leakage preventing unit, a first pole of the first transistor serves as a first input terminal of the first leakage preventing unit, and a second pole of the first transistor is electrically connected to a first pole of the second transistor;

a grid electrode of the second transistor is used as a second control end of the first anti-leakage unit, and a second pole of the second transistor is used as a first output end of the first anti-leakage unit;

preferably, the second transistor is an oxide transistor.

5. The shift register according to claim 3, wherein the second leakage preventing unit includes a third transistor and a fourth transistor, a gate of the third transistor is a third control terminal of the second leakage preventing unit, a first pole of the third transistor is a second input terminal of the second leakage preventing unit, and a second pole of the third transistor is electrically connected to a first pole of the fourth transistor;

a gate of the fourth transistor is used as a fourth control terminal of the second anti-leakage unit, and a second pole of the fourth transistor is used as a second output terminal of the second anti-leakage unit;

preferably, the fourth transistor is an oxide transistor.

6. The shift register according to claim 1 or 2, wherein the first output control module includes a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor, a gate of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node;

a gate of the sixth transistor is electrically connected to the common node, a first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor;

a gate of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the second node;

one end of the first capacitor is electrically connected with the grid electrode of the sixth transistor, and the other end of the first capacitor is electrically connected with the second pole of the sixth transistor.

7. The shift register according to claim 1 or 2, wherein the second output control module includes an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor, a gate of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to a start signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node;

a gate of the ninth transistor is electrically connected to the common node, a first electrode of the ninth transistor is electrically connected to the first voltage terminal, and a second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor;

a gate of the tenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the tenth transistor is electrically connected to the first node;

the first end of the second capacitor is electrically connected with the second clock signal end, and the second end of the second capacitor is electrically connected with the first node.

8. The shift register according to claim 1 or 2, wherein the first output module includes an eleventh transistor and a third capacitor, a gate of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the output terminal of the shift register; a first end of the third capacitor is electrically connected with the gate of the eleventh transistor, and a second end of the third capacitor is electrically connected with the first pole of the eleventh transistor;

preferably, the second output module includes a twelfth transistor, a gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the second voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the output terminal of the shift register;

preferably, the first common node potential control module includes a thirteenth transistor, a gate of the thirteenth transistor is electrically connected to a first clock signal terminal, a first electrode of the thirteenth transistor is electrically connected to the second voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the common node.

9. A light emission control circuit comprising a plurality of shift registers according to any one of claims 1 to 8 connected in cascade.

10. A display panel comprising the light emission control circuit according to claim 9, further comprising a first clock signal line, a second clock signal line, a first potential signal line, and a second potential signal line, wherein a first voltage terminal of each of the shift registers is electrically connected to the first potential signal line, and a second voltage terminal of each of the shift registers is electrically connected to the second potential signal line;

in the adjacent two stages of shift registers, a first clock signal end of the previous stage of shift register is electrically connected with the first clock signal line, and a second clock signal end of the previous stage of shift register is electrically connected with the second clock signal line; and the first clock signal end of the shift register of the next stage is electrically connected with the second clock signal line, and the second clock signal end of the shift register of the next stage is electrically connected with the first clock signal line.