CN111179812A

CN111179812A - Display panel, driving method thereof and display device

Info

Publication number: CN111179812A
Application number: CN202010182673.9A
Authority: CN
Inventors: 上官修宁
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2020-03-16
Filing date: 2020-03-16
Publication date: 2020-05-19
Anticipated expiration: 2040-03-16
Also published as: CN111179812B

Abstract

The embodiment of the invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises a grid driving circuit, a starting signal line and n clock signal lines, wherein n is more than or equal to 3; the grid driving circuit comprises a plurality of cascaded shift registers, the output end of each stage of shift register is electrically connected with at least one scanning line, wherein the first clock signal input end of the kn + i stage of shift register is electrically connected with the ith clock signal line, the second clock signal input end of the kn + i stage of shift register is electrically connected with the (i +1) th clock signal line, k is more than or equal to 0, and i is more than or equal to 1 and less than or equal to n-1; and a first clock signal input end of the mth x n-stage shift register is electrically connected with the nth clock signal line, and a second clock signal input end of the mth x n-stage shift register is electrically connected with the (m-1) n +1 clock signal line. According to the technical scheme, the data writing time of the pixel circuits in the upper area and the lower area of the display panel tends to be consistent, and the brightness difference of the upper area and the lower area of the display panel is further improved.

Description

Display panel, driving method thereof and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.

Background

With the development of display technology, a high refresh rate display screen has become a great trend.

When the existing display panel works, the refresh frequency for displaying the static picture and the dynamic game picture is usually different, specifically, the refresh frequency for displaying the static picture is usually lower, for example, usually 60Hz, and the refresh frequency for displaying the dynamic game picture is usually higher, for example, 90Hz, 120Hz or 144Hz may be used.

However, the existing display panel has the problem that the brightness of the upper and lower regions of the display panel is not consistent under the condition of higher refreshing frequency, and especially when the refreshing frequency is switched from low refreshing frequency to high refreshing frequency, the brightness difference of the upper and lower regions is more obvious.

Disclosure of Invention

The invention provides a display panel, a driving method thereof and a display device, which aim to reduce the brightness difference of upper and lower areas of the display panel when a high refresh frequency is adopted, particularly when a low refresh frequency is switched to the high refresh frequency, and improve the display effect.

In a first aspect, an embodiment of the present invention provides a display panel, including a display area and a non-display area around the display area;

a grid driving circuit, a starting signal line and n clock signal lines corresponding to the grid driving circuit are arranged in at least one non-display area on one side of the display area, wherein n is more than or equal to 3; the grid driving circuit comprises a plurality of cascaded shift registers, each shift register comprises a shift signal input end, and the shift signal input end of the first-stage shift register is electrically connected with the initial signal line;

the shift register also comprises a first clock signal input end, a second clock signal input end and an output end, wherein the output end of each stage of shift register is correspondingly and electrically connected with at least one scanning line, the first clock signal input end of the kn + i stage of shift register is electrically connected with the ith clock signal line, the second clock input end of the kn + i stage of shift register is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and is less than or equal to n-1;

the first clock signal input end of the mth x n-th stage shift register is electrically connected with the nth clock signal line, the second clock signal input end of the mth x n-th stage shift register is electrically connected with the (m-1) n +1 clock signal lines, wherein m is more than or equal to 1;

wherein m, n, k and i are integers.

Optionally, n is 4.

Optionally, adjacent two stages of shift registers are all cascaded through a switch unit, wherein in the adjacent two stages of shift registers to which the first switch unit is connected, an output end of a previous stage of shift register is electrically connected with a first end of the first switch unit, a shift signal input end of a next stage of shift register is electrically connected with a second end of the first switch unit, and the first switch unit is any one switch unit in the gate driving circuit;

optionally, the shift register is a bidirectional shift register.

Optionally, the non-display area includes a first sub non-display area and a second sub non-display area located at two opposite sides of the display area along the extending direction of the scan line,

a grid driving circuit, a starting signal line and n clock signal lines are arranged in the first sub non-display area and the second sub non-display area respectively; the output ends of the same level shift registers in the first sub non-display area and the second sub non-display area are connected with the same scanning line.

Optionally, the shift register includes: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor;

the grid electrode of the first transistor is electrically connected with the first node, the first pole of the first transistor is electrically connected with the first clock signal input end, and the second pole of the first transistor is electrically connected with the second node; the grid electrode of the second transistor is electrically connected with the first clock signal input end, the first pole of the second transistor is electrically connected with the first potential signal input end, and the second pole of the second transistor is electrically connected with the second node;

a grid electrode of the third transistor is electrically connected with the first clock signal input end, a first pole of the third transistor is electrically connected with the shift signal input end, and a second pole of the third transistor is electrically connected with the first node; the grid electrode of the fourth transistor is electrically connected with the second clock signal input end, the first electrode of the fourth transistor is electrically connected with the second electrode of the fifth transistor, and the second electrode of the fourth transistor is electrically connected with the second electrode of the third transistor; the grid electrode of the fifth transistor is electrically connected with the second node, and the first electrode of the fifth transistor is electrically connected with the second potential signal input end;

a grid electrode of the sixth transistor is electrically connected with the second node, a first electrode of the sixth transistor is electrically connected with the second potential signal input end, a second electrode of the sixth transistor is electrically connected with the output end of the shift register, and two ends of the first capacitor are respectively electrically connected with the grid electrode and the first electrode of the sixth transistor;

a grid electrode of the seventh transistor is electrically connected with the first node, a first pole of the seventh transistor is electrically connected with the second clock signal input end, and a second pole of the seventh transistor is electrically connected with the output end of the shift register;

two ends of the second capacitor are respectively and electrically connected with the grid electrode and the second electrode of the seventh transistor;

the shift register further comprises an eighth transistor, wherein the grid electrode of the eighth transistor is electrically connected with the second potential signal input end, the first pole of the eighth transistor is electrically connected with the first node, and the second pole of the eighth transistor is electrically connected with the grid electrode of the seventh transistor.

Optionally, the display area further includes a plurality of data lines and a plurality of pixel circuits;

the scanning lines extend along a first direction, and each scanning line is connected with a row of pixel circuits;

the data lines extend along a second direction, and each data line is connected with one column of pixel circuits;

the first direction intersects the second direction.

In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, for driving the display panel provided in the first aspect, where the driving method of the display panel includes:

in one frame, clock pulse signals are periodically provided for the first clock signal line to the nth clock signal line in sequence;

wherein, in a first period of supplying clock pulse signals to the first clock signal line to the nth clock signal line in sequence, a start pulse signal is supplied to the start signal line, wherein the start pulse signal is at least overlapped with the clock signal supplied to the first clock signal line.

Optionally, a rising edge of the start pulse signal coincides with a rising edge of the clock pulse signal provided to the first clock signal line, and the start pulse signal coincides with a falling edge of the clock pulse signal provided to the nth clock signal line.

Optionally, the display area further includes a plurality of data lines and a plurality of pixel circuits; the data lines extend along the second direction, and each data line is connected with one column of pixel circuits

The driving method further includes:

the data signal is supplied to the data line from a second cycle in which the clock pulse signal is sequentially supplied to the first clock signal line to the nth clock signal line.

Before the clock pulse signals are periodically supplied to the first clock signal line to the nth clock signal line, the method comprises the following steps:

a level signal opposite to the start pulse signal is supplied to the start signal line, and a level signal opposite to the clock pulse signal is supplied to the n clock signal lines.

In a second aspect, an embodiment of the present invention further provides a display device, including the display panel and the driver chip provided in the first aspect, where the driver chip includes n clock signal output ends, and the n clock signal output ends are respectively electrically connected to the n clock signal lines in a one-to-one correspondence manner.

According to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the display panel comprises n clock signal lines, wherein n is more than or equal to 3; a first clock signal input end of the kn + i-th stage shift register is electrically connected with the ith clock signal line, a second clock signal input end of the kn + i-th stage shift register is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and less than or equal to n-1; and a first clock signal input end of the mth x n-stage shift register is electrically connected with the nth clock signal line, and a second clock signal input end of the mth x n-stage shift register is electrically connected with the (m-1) n +1 clock signal line. Compared with the existing display panel comprising only two clock signal lines, the number of the shift registers connected with each clock signal line is reduced, correspondingly, the paths through which the clock signals are transmitted to the shift registers on the upper portion of the display panel and output as scanning signals are reduced, the overall RC Loading when the clock signals are transmitted to the shift registers on the upper portion of the display panel and output as the scanning signals is reduced, the time of the rising edge and the time of the falling edge of the clock signals are shortened, the overall pulse length of the clock signals is prolonged, the data writing time of pixel circuits on the upper portion of the display panel is prolonged, the data writing time of the pixel circuits on the upper portion and the lower portion of the display panel is consistent, and the brightness difference of the upper area and the lower area of the display panel is improved.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention;

FIG. 5 is a timing diagram illustrating a driving method of a display panel according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a scan circuit according to an embodiment of the present invention;

fig. 8 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

FIG. 9 is a timing diagram illustrating driving of another display panel according to the present invention;

fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional display panel has a problem that the brightness of the upper and lower regions of the display panel is inconsistent under a higher refresh frequency, and especially when the refresh frequency is switched from a low refresh frequency to a high refresh frequency, the brightness difference between the upper and lower regions is more obvious. The inventor has found that the above problem occurs because the driving chip is usually disposed at the lower portion of the display panel, the gate driving circuit is usually disposed at the left side and/or the right side of the display panel, and the display panel usually includes two clock signal lines for providing the clock signal to the gate driving circuit, and the clock signal extends from the lower driving chip to the upper portion of the display panel. The grid driving circuit comprises a plurality of cascaded shift registers, each shift register is electrically connected with two clock signal lines, the clock signals on the two clock signal lines are respectively transmitted to the output ends of the two adjacent stages of shift registers to be output to the scanning lines as scanning signals, and finally the scanning signals are transmitted to the pixel circuits through the scanning lines. Because the distances between the upper part of the display panel and the lower part of the display panel and the driving chip are different, the RC Loading (resistance-capacitance load) is generated on each scanning line which corresponds to the output of the scanning signal, so that the RC Loading (resistance-capacitance load) transmitted by the clock signal to the upper part of the display panel is larger than the RC Loading transmitted to the lower part of the display panel, the data voltage writing time of a pixel circuit on the upper part of the display panel is shorter than the data voltage writing time of a pixel circuit on the lower part of the display panel, the data writing time of the pixel circuit on the upper part of the display panel is insufficient, and the data writing is insufficient, so that the brightness difference between the upper part and the lower part of the display panel is. Especially, when the refresh frequency is high or the refresh frequency is switched from low to high, the data writing time per row of pixel circuits is short, and the data writing time is shorter due to the large RC Loading on the upper portion of the display panel, which further causes the brightness difference between the upper and lower regions of the display panel.

For the above reasons, an embodiment of the present invention provides a display panel, and fig. 1 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, and referring to fig. 1, the display panel 100 includes:

a non-display area NAA including a display area AA and a periphery of the display area AA;

at least one side of the non-display area NAA is provided with a gate drive circuit 110, and a start signal line SL and n clock signal lines corresponding to the gate drive circuit 110, wherein n is more than or equal to 3; the gate driving circuit 110 includes a plurality of cascaded shift registers 111, each shift register 111 includes a shift signal input terminal SIN, and the shift signal input terminal SIN of the first stage shift register 111 is electrically connected to the start signal line SL;

the shift register 111 further comprises a first clock signal input end C1, a second clock signal input end C2 and an output end SCAN, the output end SCAN of each stage of the shift register 111 is correspondingly and electrically connected with at least one scanning line 120, wherein the first clock signal input end C1 of the kn + i stage of the shift register 111 is electrically connected with the ith clock signal line, the second clock input end of the kn + i stage of the shift register 111 is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and less than or equal to n-1;

the first clock signal input end C1 of the mth/nth shift register 111 is electrically connected with the nth clock signal line, the second clock signal input end C2 of the mth/nth shift register 111 is electrically connected with the (m-1) nth +1 clock signal line, wherein m is more than or equal to 1;

wherein m, n, k and i are integers.

Specifically, referring to fig. 1, the display area AA further includes a plurality of data lines 130 and a plurality of pixel circuits 140; fig. 1 illustrates that each stage of the shift register 111 is electrically connected to one scan line 120, the scan lines 120 extend along the first direction x, and each scan line 120 is connected to one row of the pixel circuits 140; the data lines 130 extend along the second direction y, and each data line 130 is connected with one column of pixel circuits 140; the first direction x intersects the second direction y. The pixel circuits 140 may be arranged in an array, and the scan lines 120 are used for transmitting scan signals to the pixel circuits 140 electrically connected thereto. In the non-display area NAA, a gate driving circuit 110 is disposed, and the gate driving circuit 110 is configured to generate a SCAN signal and output the SCAN signal to the SCAN line 120, wherein the gate driving circuit 110 includes a plurality of stages of shift registers 111 connected in cascade, and an output terminal SCAN of each shift register 111 is connectable to one SCAN line 120 and outputs the SCAN signal to the SCAN line 120 electrically connected thereto through the output terminal SCAN. The shift register 111 in this embodiment may be any shift register 111 driven by two clock signals to operate in the prior art, and the specific structure of the shift register 111 is not specifically limited in this embodiment of the present invention.

Fig. 1 schematically shows a case where the gate driving circuit 110 is provided in the non-display area NAA on the display area AA side, and an example in which 4 clock signal lines are included in the display panel is shown. Specifically, referring to fig. 1, when the display panel includes four clock signal lines, that is, a first clock signal line SCK1, a first clock signal line SCK2, a first clock signal line SCK3, and a first clock signal line SCK4, where n is 4, then 1 is not less than i is not less than 3, when k is 0, and i is 1, then kn + i is 1, that is, the first clock signal input terminal C1 of the first stage shift register 111 is electrically connected to the 1(i) th clock signal line SCK1, and the second clock signal input terminal C2 of the first stage shift register 111 is electrically connected to the 2(i +1) th clock signal line SCK 2; when k is 0 and i is 2, kn + i is 2, the first clock signal input terminal C1 of the second stage shift register 111 is electrically connected to the 2(i) th clock signal line SCK2, and the second clock signal input terminal C2 of the second stage shift register 111 is electrically connected to the 3(i +1) th clock signal line SCK 3; when k is 0 and i is 3, kn + i is 3, the first clock signal input terminal C1 of the third stage shift register 111 is electrically connected to the 3(i) th clock signal line SCK3, and the second clock signal input terminal C2 of the third stage shift register 111 is electrically connected to the 4(i +1) th clock signal line SCK 4; when m is 1, m × n is 4, the first clock signal input terminal C1 of the fourth stage shift register is electrically connected to the 4(n) fourth clock signal line SCK4, and the second clock signal input terminal C2 of the fourth stage shift register 111 is electrically connected to the 1((m-1) n +1) th clock signal line SCK 1. When k takes other values and m takes other values, the connection is similar to the above-mentioned connection situation, and the description thereof is omitted. The clock signals on the first clock signal line to the nth clock signal line are clock signals which are provided in sequence, namely j is more than or equal to 1 and less than or equal to n-1 after the clock signal on the j +1 th clock signal line.

As described in the background art, since the distances between the upper portion of the display panel and the lower portion of the display panel and the driving chip are different, RC Loading exists on each scan line 120 corresponding to the output of the scan signal for the clock signal transmitted to the upper portion of the display panel, which results in that the RC Loading transmitted to the upper portion of the display panel by the clock signal is greater than the RC Loading transmitted to the lower portion of the display panel. For example, when there are only two clock signal lines in the display panel, the shift register 111 for each electrode of the gate driving circuit 110 is connected to the two clock signal lines, and the clock signals on the two clock signal lines are respectively used as an erase signal and a write signal, wherein the write signal is used as a scan signal output to the scan line 120. In the adjacent two stages of shift registers 111, if the erase signal of the previous stage of shift register 111 is the clock signal on the first clock signal line and the write signal is the clock signal on the second clock signal line, the erase signal of the next stage of shift register 111 is the clock signal on the second clock signal line and the write signal is the clock signal on the first clock signal line. For example, the shift register 111 corresponding to the odd-numbered pixel circuit 140 in the display panel uses the clock signal on the first clock signal line as the write signal, uses the clock signal on the second clock signal line as the erase signal, and the shift register 111 corresponding to the even-numbered pixel circuit 140 in the display panel uses the clock signal on the first clock signal line as the erase signal and uses the clock signal on the second clock signal line as the write signal. During the transmission of the clock signal on the first clock signal line and the second clock signal, for example, when the first clock signal is transmitted to the odd-numbered rows on the upper portion of the display panel, for example, the shift registers 111 corresponding to the pixel circuits 140 in the first row, when the first clock signal is transmitted upward, RC Loading exists on the scan lines 120 connected to the shift registers 111 corresponding to all the pixel circuits 140 in the odd-numbered rows in the display panel, so that the RC Loading of the clock signal is very large, both the rising edge and the falling edge of the clock signal in the timing sequence are oblique lines, i.e., the rising and/or falling time of the clock signal is long, the pulse duration of the clock signal is short, and the data voltage writing is insufficient. Accordingly, when the second clock signal is transmitted as the write signal to the shift register 111 corresponding to the pixel circuit 140 in the even-numbered row in the upper portion of the display panel, the data voltage is insufficiently written in the pixel circuit in the upper portion of the display panel due to the above-mentioned reason.

The display panel provided by the embodiment comprises n clock signal lines, wherein n is more than or equal to 3; the first clock signal input end C1 of the kn + i-th stage shift register 111 is electrically connected with the ith clock signal line, the second clock input end of the kn + i-th stage shift register 111 is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and less than or equal to n-1; the first clock signal input terminal C1 of the mth x n-th stage shift register 111 is electrically connected to the nth clock signal line, and the second clock signal input terminal C2 of the mth x n-th stage shift register 111 is electrically connected to the (m-1) n +1 clock signal lines. For example, for the display panel shown in fig. 1, which includes 4 clock signal lines, for example, the clock signal on the first clock signal line SCK1 is used as the write signal for the shift register 111 of the first stage, when the first row of pixel circuits 140 electrically connected to the first stage shift register 111 is scanned, the clock signal on the first clock signal line SCK1 only needs to be transmitted to the kn +1 th stage shift register 111 as a write signal, for the display panel shown in fig. 1, if n is 4, the clock signal on the first clock signal line only needs to be transmitted to the shift register 111 of the 1 st stage, the shift register 111 of the 5 th stage, and the shift register 111 … … of the 9 th stage, and the clock signal on the first clock signal line SCK1 also only has RC Loading on the scan line 120 electrically connected to the shift register 111 of the 1 st stage, the shift register 111 of the 5 th stage, and the shift register 111 … … of the 9 th stage; for example, when the clock signal on the second clock signal line SCK2 is used as the write signal for the second-stage shift register 111, when scanning the second row of pixel circuits 140 electrically connected to the second-stage shift register 111, the clock signal on the second clock signal line SCK2 only needs to be transmitted to the second-stage shift register 111, the second-stage shift register 6, and the second-stage shift register 10 111 … …, and the clock signal on the second clock signal line SCK2 only has RCLoading on the scan line 120 electrically connected to the second-stage shift register 111, the second-stage shift register 6, and the second-stage shift register 10 111 … …. The principle that the clock signal on the third clock signal line SCK3 is used as the write signal for the third stage shift register 111 and the clock signal on the fourth clock signal line SCK4 is used as the write signal for the fourth stage shift register 111 is the same as the principle of the first clock signal line SCK1 and the second clock signal line SCK2, and is not described herein again. As can be seen from the above analysis, the display panel provided in this embodiment includes at least three clock signal lines, so that, compared to the existing display panel including only two clock signal lines, the number of the shift registers 111 connected to each clock signal line is reduced, and accordingly, the paths through which the clock signals are transmitted to the shift registers 111 on the upper portion of the display panel and output as the scan signals are reduced, so that the overall RC Loading during the transmission of the clock signals is reduced, and further the clock signals are transmitted to the shift registers 111 on the upper portion of the display panel and output as the scan signals, and the time of the rising edge and the falling edge of the clock signals is shortened, so that the overall pulse length of the clock signals is increased, so that the data writing time of the pixel circuits 140 on the upper portion of the display panel is increased, and the data writing time of the pixel circuits 140 on the upper portion and the lower portion of the display panel, thereby improving the brightness difference between the upper and lower regions of the display panel.

According to the display panel provided by the embodiment of the invention, the display panel comprises n clock signal lines, wherein n is more than or equal to 3; a first clock signal input end of the kn + i-th stage shift register is electrically connected with the ith clock signal line, a second clock signal input end of the kn + i-th stage shift register is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and less than or equal to n-1; and a first clock signal input end of the mth x n-stage shift register is electrically connected with the nth clock signal line, and a second clock signal input end of the mth x n-stage shift register is electrically connected with the (m-1) n +1 clock signal line. Compared with the existing display panel comprising only two clock signal lines, the number of the shift registers connected with each clock signal line is reduced, correspondingly, the paths through which the clock signals are transmitted to the shift registers on the upper portion of the display panel and output as scanning signals are reduced, the overall RC Loading when the clock signals are transmitted to the shift registers on the upper portion of the display panel and output as the scanning signals is reduced, the time of the rising edge and the time of the falling edge of the clock signals are shortened, the overall pulse length of the clock signals is prolonged, the data writing time of pixel circuits on the upper portion of the display panel is prolonged, the data writing time of the pixel circuits on the upper portion and the lower portion of the display panel is consistent, and the brightness difference of the upper area and the lower area of the display panel is improved.

On the basis of the above technical solution, optionally, n is 4, that is, the display panel includes 4 clock signal lines. Specifically, the inventor tests and simulations that the display panel including 4 clock signal lines is significantly lower than the display panel RC Loading including 2 clock signal lines, wherein the resistance R is reduced by 7.3%, and the capacitance C is reduced by 23%, so that the charging time of the upper and lower regions of the display panel is consistent, and the brightness difference caused by insufficient data voltage writing time when the refresh frequency is high is improved.

Fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 2, optionally, n is 3, that is, the display panel includes 3 clock signal lines, which are SCK1, SCK2, and SCK3, respectively. Specifically, including 3 clock signal lines in the display panel, both can guarantee that the number of clock signal lines in the display panel is more than two in the current display panel, and then when reducing clock signal's RC Loading, guarantee that the number of clock signal lines is less, and then be favorable to the realization of narrow frame.

Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 3, optionally, two adjacent shift registers 111 are all cascaded through a switch unit 112, where in two adjacent shift registers connected to a first switch unit, an output terminal Scan of a shift register of a previous stage is electrically connected to a first terminal R1 of the first switch unit, a shift signal input terminal SIN of a shift register of a next stage is electrically connected to a second terminal of the first switch unit 112, and the first switch unit is any one switch unit 112 in the gate driving circuit 110;

the display panel 100 further includes a control signal line CL for controlling the on-state of the switch cells, and the control signal line CL is electrically connected to the control terminal R3 of each switch cell 111.

Optionally, the switching unit 111 is a transistor. The display panel of this embodiment may be a foldable display panel, and when the existing foldable display panel performs partial display, normally display is performed through a part of pixel circuit rows of the display panel, and a part of the pixel circuit rows are brushed with black, that is, a part of the pixel circuit writes in normal data voltage, and a part of the pixel circuit writes in black data voltage, and when the black data voltage is written in, the display panel may also generate a certain loss. In the display panel provided in the present embodiment, two adjacent stages of shift registers 111 are arranged in cascade via the switch units 112, so that when a part of the display is displayed, the signal transmission between the adjacent two stages of shift registers 111 at the folding position is cut off by controlling the turn-off of the switching unit 112 at the folding position of the display panel, and further controls the shift register 111 corresponding to the portion of the display panel that does not need to display to be unable to output the scan signal, the clock signal as the write signal is not transmitted to the scanning line to which the pixel circuit of the non-display required portion is connected, and the pixel circuit which does not need to display part does not write data, compared with the prior art that the pixel circuit which does not need to display part is brushed black, the RC Loading of the clock signal on the scanning line of the display part is not needed, and the overall power consumption of the display panel is saved.

Fig. 4 is a driving timing diagram according to an embodiment of the present invention, where the driving timing diagram shown in fig. 4 can be used to drive the display panel shown in fig. 3, and referring to fig. 3 and fig. 4, for example, when the folding position of the display panel is located at the position of the p (p is greater than or equal to 1 and less than or equal to N-1) th stage shift register, the on-state control signal can be transmitted to each switch unit 112 through the control signal line CL in the previous p/N frame, where N is the total number of stages of the shift register 111 in the gate driving circuit, so that the previous p stages of shift registers output the scan signal, and thus completing the data writing of the previous p rows of pixel circuits; in the subsequent (1-p/N) frame, the off control signal is transmitted to each of the switch units 112 through the control signal line CL, so that the p +1 th to nth shift registers do not output the scan signal, and further, the p +1 th to nth pixel circuits do not write data.

Alternatively, in the display panel shown in fig. 3, the shift register 111 is a bidirectional shift register.

Specifically, the bidirectional shift register can realize bidirectional scanning. For example, when the bidirectional shift register is scanned in the forward direction, the cascaded shift registers can realize the step-by-step scanning from the first stage to the last stage, the scanning signals are output step-by-step from the first stage, and the pixel circuits of the display panel start to drive the light-emitting devices to emit light from the first row. When the bidirectional shift register is in reverse scanning, the cascaded shift registers can realize the step-by-step scanning from the last stage to the first stage, scanning signals are output step by step from the last stage, and the pixel circuits of the display panel start to drive the light-emitting devices to emit light from the last line. It can be seen that by setting the first shift register as a bidirectional shift register, when the display panel displays partially, if the display panel displays partially the first to the p-th rows on the display panel, the bidirectional shift register can be driven by forward scanning, and the switch control signal on the control signal line CL controls the switch unit 112 to be turned on in the first p/N frame and the switch unit 112 to be turned off in the last (1-p/N) frame. If the display panel displays the last row to the p-last row of the display panel, the bidirectional shift register may be driven by the reverse scan, the switch control signal controls the switch unit 112 to be turned on in the previous p/N frames, and controls the switch unit 112 to be turned off in the following (1-p/N) frames, where N is the total number of stages of the shift register included in the gate driving circuit. Therefore, when the display panel part displays different positions of the display panel, the display panel part can normally display under the condition of not changing the time sequence of the switch control signal by changing the scanning direction of the bidirectional shift register, thereby reducing the difficulty of driving the display panel to display different parts and being beneficial to the design of a driving circuit of the display panel.

Fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 5, optionally, the non-display area includes a first sub non-display area NAA1 and a second sub non-display area NAA2 located at two opposite sides of the display area AA along the extending direction of the scan line, and the gate driving circuit 110, the start signal line SL, and n clock signal lines are disposed in both the first sub non-display area NAA1 and the second sub non-display area NAA2 (fig. 5 schematically illustrates that the display panel includes 3 clock signal lines); the output terminals Scan of the sibling shift registers 111 in the first and second sub non-display areas NAA1 and NAA1 are connected to the same Scan line 120.

Specifically, the gate driving circuits 110 are disposed in the first and second sub non-display areas NAA1 and NAA2 located at two opposite sides of the display area AA along the extending direction of the scanning lines, and the output ends Scan of the same-level shift registers 111 in the first and second sub non-display areas NAA1 and NAA2 are connected to the same scanning lines 120, so that when scanning the pixel circuits in the display panel, the scanning times of the pixel circuits close to the first side and the second side of the display panel can be more consistent, that is, the data writing times of the pixel circuits close to the first side and the second side of the display panel can be more consistent, compared with the scanning of the pixel circuits from one side of the display panel, and the display uniformity of the display panel can be further improved.

Fig. 6 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and referring to fig. 6, on the basis of the foregoing technical solution, optionally, the shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor Cst1, and a second capacitor Cst 2;

a gate of the first transistor T1 is electrically connected to the first node N1, a first pole of the first transistor T1 is electrically connected to the first clock signal input terminal C1, and a second pole of the first transistor T1 is electrically connected to the second node N2; a gate of the second transistor T2 is electrically connected to the first clock signal input terminal C1, a first pole of the second transistor T2 is electrically connected to the first potential signal input terminal VGL, and a second pole of the second transistor T2 is electrically connected to the second node N2;

a gate of the third transistor T3 is electrically connected to the first clock signal input terminal C1, a first pole of the third transistor T3 is electrically connected to the shift signal input terminal SIN, and a second pole of the third transistor T3 is electrically connected to the first node N1; a gate of the fourth transistor T4 is electrically connected to the second clock signal input terminal C2, a first pole of the fourth transistor T4 is electrically connected to a second pole of the fifth transistor T5, and a second pole of the fourth transistor T4 is electrically connected to a second pole of the third transistor T3; a gate of the fifth transistor T5 is electrically connected to the second node N2, and a first pole of the fifth transistor T5 is electrically connected to the second potential signal input terminal VGH;

a gate of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the second potential signal input terminal VGH, a second electrode of the sixth transistor T6 is electrically connected to the output terminal of the shift register, and both ends of the first capacitor Cst1 are electrically connected to the gate and the first electrode of the sixth transistor T6, respectively;

a gate of the seventh transistor T7 is electrically connected to the first node N1, a first pole of the seventh transistor T7 is electrically connected to the second clock signal input terminal C2, and a second pole of the seventh transistor T7 is electrically connected to the output terminal Scan of the shift register;

both ends of the second capacitor Cst2 are electrically connected to the gate and the second pole of the seventh transistor T7, respectively;

preferably, the shift register further includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the first potential signal input terminal VGL, a first pole of the eighth transistor T8 is electrically connected to the first node N1, and a second pole of the eighth transistor T8 is electrically connected to the gate of the seventh transistor T7.

Fig. 7 is a driving timing diagram of a scan circuit according to an embodiment of the present invention, and the driving timing diagram shown in fig. 7 is applicable to the scan circuit shown in fig. 6, and specifically, referring to fig. 6 and fig. 7, the driving timing diagram of the scan circuit includes three stages, and each transistor is a P-type transistor for example. Referring to fig. 6 and 7, the operation timings of the scanning circuit shown in fig. 6 are as follows:

in the first stage t1, the shift signal input terminal SIN inputs a low signal, the first clock signal input terminal C1 inputs a low signal, and the second clock signal input terminal C2 inputs a high signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal C1, so that the gate of the second transistor T2 inputs a low-potential signal, the second transistor T2 is turned on, and the low-potential signal input by the first pole of the second transistor T2 is transmitted to the second node N2, so that the second node N2 is at a low potential, the sixth transistor T6 is turned on according to the low-potential signal of the gate thereof, and transmits the high-potential signal input by the second potential signal input terminal VGH to the output terminal Scan of the shift register through the sixth transistor T6, so that the output terminal Scan outputs a high-potential signal.

The gate of the third transistor T3 is electrically connected to the first clock signal input terminal C1, so that the third transistor T3 is turned on according to the low-potential signal inputted from the gate thereof, and the first pole of the third transistor T3 is electrically connected to the shift signal input terminal SIN, so that the low-potential signal inputted from the shift signal input terminal SIN is transmitted to the first node N1; since the gate of the seventh transistor T7 is electrically connected to the first node N1, the seventh transistor T7 is turned on according to the low potential signal at the gate thereof, and the high potential signal inputted from the second clock signal input terminal C2 is outputted to the output terminal Scan through the seventh transistor T7, and the potential outputted from the output terminal Scan is the high potential signal. The gate of the fourth transistor T4 is electrically connected to the second clock signal input terminal C2, and therefore, a high potential signal is input to the gate of the fourth transistor T4, and the fourth transistor T4 is turned off according to the high potential of the gate thereof. As described above, the potential of the second node N2 is low, so the potential of the gate of the fifth transistor T5 is low, and the fifth transistor T5 is turned on according to the low potential of the gate thereof, but the high potential signal inputted from the second potential signal input terminal VGH cannot be transmitted to the first node N1 because the fourth transistor T4 is turned off at this stage.

As described above, since the first node N1 is at a low voltage level, the first transistor T1 is turned on according to the low voltage signal at the first node N1, such that the low voltage signal inputted from the first clock signal input terminal C1 is transmitted to the second node N2.

In the second stage t2, the signal inputted from the shift signal input terminal SIN is reset to a high signal, the first clock signal input terminal C1 inputs a high signal, and the second clock signal input terminal C2 inputs a low pulse signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal C1, so that the gate of the second transistor T2 inputs a high-voltage signal, and the second transistor T2 is turned off according to the high-voltage signal input by the gate thereof, so that the low-voltage signal input by the first electrode of the second transistor T2 cannot be transmitted to the second node N2. Due to the charge retention of the second capacitor Cst2, the potential of the gate of the seventh transistor T7, that is, the first node N1, is retained, so that the first node N1 retains the low potential at the previous stage, and accordingly, the potential of the gate of the first transistor T1 is at the low potential, so that the first transistor T1 is turned on, the high potential signal inputted from the second potential signal input terminal VGH is transmitted to the second node N2, and the sixth transistor T6 is turned off according to the high potential inputted from the control terminal thereof.

The gate of the third transistor T3 is electrically connected to the first clock signal input terminal C1, so that the third transistor T3 is turned off according to the high signal inputted from the gate thereof, and the signal inputted from the shift signal input terminal SIN cannot be transmitted to the first node N1; the gate of the fourth transistor T4 is electrically connected to the second clock signal input terminal C2, and thus a low potential signal is input to the gate of the fourth transistor T4, and the fourth transistor T4 is turned on; the gate of the fifth transistor T5 is at the same potential as the second node N2, i.e., at a high potential, so that the fifth transistor T5 is turned off and the high potential signal inputted from the second potential signal input terminal VGH cannot be transmitted to the first node N1.

The gate of the seventh transistor T7 maintains the low voltage level of the first node N1 due to the storage and retention of the charges by the second capacitor Cst2, so that the seventh transistor T7 is turned on, and the low voltage signal inputted from the second clock signal input terminal C2 is outputted to the output terminal Scan through the seventh transistor T7, and the voltage outputted from the Scan output terminal Scan is the low voltage signal. That is, in the second stage t2, the Scan signal output terminal Scan outputs the same signal as the signal input at the second clock signal input terminal C2.

After entering the third stage t3, the first clock signal input terminal C1 inputs a low-level signal, and the second clock signal input terminal C2 and the scan signal input terminal both input high-level signals. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal C1, so that the gate of the second transistor T2 inputs a low-potential signal, the second transistor T2 is turned on, and the low-potential signal input by the first pole of the second transistor T2 is transmitted to the second node N2; the sixth transistor T6 is turned on according to the low potential of the second node N2 electrically connected to the gate thereof, and transmits the high potential inputted from the first potential signal input terminal VGH to the SCAN signal output terminal SCAN.

The third transistor T3 is turned on according to the low potential signal inputted from the first clock signal input terminal C1 electrically connected to the gate thereof, so that the high potential signal inputted from the shift signal input terminal SIN is transmitted from the first pole of the third transistor T3 to the first node N1; the fourth transistor T4 is turned off according to the high voltage input from the second clock signal input terminal C2 electrically connected to the gate thereof, the gate of the fifth transistor T5 is at the same voltage level as the second node N2, i.e., at a low voltage level, and the fifth transistor T5 is turned on. Since the first node N1 is at a high level, the seventh transistor T7 is turned off according to a high signal at its gate. That is, in the third stage t3, when the low-level signal is input to the first clock signal input terminal C1, and the high-level signals are input to both the second clock signal input terminal C2 and the Scan signal input terminal, the high-level signal is output from the output terminal Scan, which is the same as the level input from the second level signal input terminal VGH.

In the third stage t3, when the second clock signal input terminal C2 inputs a low-level pulse signal, the first clock signal input terminal C1 and the shift signal input terminal SIN both input a high-level signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal C1, so that the gate of the second transistor T2 inputs a high-potential signal, and the second transistor T2 is turned off, so that the low-potential signal input by the first pole of the second transistor T2 cannot be transmitted to the second node N2. However, the second node N2 is kept at the low potential due to the storage and retention of the charges by the first capacitor Cst1, accordingly, the sixth transistor T6 is turned on, and the high potential inputted from the second potential signal input terminal VGH is transmitted to the Scan signal output terminal Scan.

The third transistor T3 is turned off according to the second high potential signal inputted from the first clock signal input terminal C1 electrically connected to the gate thereof; the fourth transistor T4 is turned on according to the low potential of the signal inputted from the second clock signal input terminal C2 electrically connected to the gate thereof, the gate of the fifth transistor T5 is the same as the second node N2 in potential, i.e., the low potential, and thus the fifth transistor T5 is also turned on, so that the high potential signal inputted from the second potential signal input terminal VGH is transmitted to the first node N1 through the fifth transistor T5 and the fourth transistor T4, the first node N1 is the high potential, and thus the seventh transistor T7 is turned off according to the high potential signal of the first node N1 electrically connected to the gate thereof.

In addition, since the gate of the eighth transistor T8 is connected to the first potential signal input terminal VGL, that is, the gate of the ninth transistor T8 is always inputted with the low potential signal, the eighth transistor T8 is always turned on in the above stages. The eighth transistor T8 is disposed between the first node N1 and the gate of the seventh transistor T7, and at this time, the first node N1 and the gate of the seventh transistor T7 are indirectly connected to each other, so that the eighth transistor T8 can bear a certain voltage drop, thereby reducing the risk of breakdown of the seventh transistor T7 and improving the reliability of the scanning circuit.

In the timing sequence of the above embodiment, the clock signals input by the first clock signal input terminal and the second clock signal input terminal may be the clock signals on the jth clock signal line and the jth +1 clock signal line in the display panel of the embodiment of the present invention, where j is greater than or equal to 1 and is less than or equal to n-1; the clock signals input by the first clock signal input terminal and the second clock signal input terminal may be clock signals on the nth clock signal line and the 1 st clock signal line in the display panel according to the embodiment of the present invention.

The shift register in the above embodiment is only an exemplary structure of the shift register included in the display panel provided in the embodiment of the present invention, and in the display panel in the embodiment of the present invention, the shift register may also be another circuit structure including a first clock signal input terminal and a second clock signal input terminal, which is not limited specifically herein.

An embodiment of the present invention further provides a driving method of a display panel, where the driving method is used to drive the display panel provided in any of the above embodiments of the present invention, fig. 8 is a flowchart of the driving method of the display panel provided in the embodiment of the present invention, and referring to fig. 8, the driving method of the display panel includes:

step 210, in a frame, periodically providing clock pulse signals to a first clock signal line to an nth clock signal line in sequence; wherein, in a first period of supplying clock pulse signals to the first clock signal line to the nth clock signal line in sequence, a start pulse signal is supplied to the start signal line, wherein the start pulse signal is at least overlapped with the clock signal supplied to the first clock signal line.

Fig. 9 is a driving timing chart of another display panel according to the present invention, where the driving timing chart may correspond to the driving method of the display panel, and in conjunction with fig. 1, the driving timing chart shown in fig. 9 may be used for driving the display panel shown in fig. 1. Referring to fig. 9, in a first period t21 where pulses are sequentially supplied to the first to nth clock signal lines, a start pulse signal is supplied to the start signal line, so that in the first period t21, the first stage shift register starts to operate, and the second stage shift register is driven to operate by a signal output from its output terminal, so that each shift register sequentially outputs a scan pulse signal.

The embodiment of the invention provides a driving method of a display panel, wherein the display panel comprises n clock signal lines, and n is more than or equal to 3; a first clock signal input end of the kn + i-th stage shift register is electrically connected with the ith clock signal line, a second clock signal input end of the kn + i-th stage shift register is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and less than or equal to n-1; and a first clock signal input end of the mth x n-stage shift register is electrically connected with the nth clock signal line, and a second clock signal input end of the mth x n-stage shift register is electrically connected with the (m-1) n +1 clock signal line. In a first period in which clock pulse signals are sequentially supplied to the first clock signal line to the nth clock signal line, a start pulse signal is supplied to the start signal line, so that each shift register sequentially outputs a scan pulse signal. Compared with the existing display panel and the driving method which only comprise two clock signal lines, the number of the shift registers connected with each clock signal line is reduced, correspondingly, the paths through which the clock signals are transmitted to the shift registers on the upper portion of the display panel and output as scanning signals are reduced, the overall RC Loading during clock signal transmission is reduced, the time of the rising edge and the falling edge of the clock signals is shortened, the overall pulse length of the clock signals is prolonged, the data writing time of pixel circuits on the upper portion of the display panel is prolonged, the data writing time of the pixel circuits on the upper portion and the lower portion of the display panel is consistent, and the brightness difference of the upper area and the lower area of the display panel is improved.

With continued reference to fig. 9, based on the above technical solution, optionally, a rising edge of the start pulse signal coincides with a rising edge of the clock pulse signal provided to the first clock signal line, and the start pulse signal coincides with a falling edge of the clock pulse signal provided to the nth clock signal line.

Specifically, the rising edge of the start signal coincides with the rising edge of the clock pulse signal provided by the first clock signal line, and the falling edge of the start pulse signal coincides with the falling edge of the clock pulse signal provided to the nth clock signal line, so that the clock signals on the clock signals can be fully written into the shift registers, and the shift registers can work normally.

Optionally, the display area further includes a plurality of data lines and a plurality of pixel circuits; the data lines extend along a second direction y, each data line is connected with one column of pixel circuits, and the driving method further comprises the following steps:

the data signal is supplied to the data line from the second period t22 in which the clock pulse signal is sequentially supplied to the first clock signal line to the nth clock signal line.

In conjunction with the driving timing chart shown in fig. 9, a Data signal is supplied to the Data line (where the Data signal in the timing chart shown in fig. 9 may correspond to a signal on one Data line) from the second period t22 in which the clock pulse signal is supplied to the first clock signal line to the nth clock signal line in sequence, that is, the Data voltage is written to the pixel circuit in the display panel from the second period t 22. A second period t22 in which clock pulse signals are sequentially provided to the first to nth clock signal lines begins, each clock signal in each period is transmitted to the scan line corresponding to a write signal of the first-stage shift register, so as to complete scanning of each row of pixel circuits, and then the pixel circuits are turned on, and data signals are correspondingly provided to the data lines to complete writing of data signals of the pixel circuits, for example, in fig. 9, the first data write stage t221, the second data write stage t222, the third data write stage t223, and the fourth data write stage t224 may correspond to writing of 4 rows of pixel circuit data, respectively. Specifically, because the clock signal provided by the driving chip at the initial time of display may be unstable, the data signal is provided to the data line from the second period in which the clock pulse signal is provided to the first clock signal line to the nth clock signal line in sequence, so that the clock signal is gradually stable after the clock pulse signal is provided to the first clock signal line to the nth clock signal line in sequence for one period, thereby ensuring the stability of the scanning signal output by each shift register and ensuring the normal operation of the display panel.

Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 10, the display device includes the display panel 100 according to any embodiment of the present invention, and further includes a driver chip 200, where the driver chip 200 includes n clock signal output ends, and the n clock signal output ends are respectively electrically connected to the n clock signal lines in a one-to-one correspondence manner, where fig. 10 schematically illustrates a case where n is 4. The display device may be a mobile phone as shown in fig. 10, or may be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel is characterized by comprising a display area and a non-display area at the periphery of the display area;

at least one side of the non-display area is provided with a grid driving circuit, and a starting signal line and n clock signal lines which correspond to the grid driving circuit, wherein n is more than or equal to 3; the grid driving circuit comprises a plurality of cascaded shift registers, each shift register comprises a shift signal input end, and the shift signal input end of the first stage of shift register is electrically connected with the starting signal line;

the shift register also comprises a first clock signal input end, a second clock signal input end and an output end, wherein the output end of each stage of the shift register is correspondingly and electrically connected with at least one scanning line, the first clock signal input end of the kn + i stage of the shift register is electrically connected with the ith clock signal line, the second clock input end of the kn + i stage of the shift register is electrically connected with the (i +1) th clock signal line, wherein k is more than or equal to 0, and i is more than or equal to 1 and is less than or equal to n-1;

the first clock signal input end of the mth x n stage of the shift register is electrically connected with the nth clock signal line, the second clock signal input end of the mth x n stage of the shift register is electrically connected with (m-1) n +1 clock signal lines, wherein m is more than or equal to 1;

wherein m, n, k and i are integers.

2. The display panel according to claim 1, wherein n is 4.

3. The display panel according to claim 1, wherein in the gate driving circuit, two adjacent stages of the shift registers are cascaded by a switch unit, wherein in the two adjacent stages of the shift registers to which a first switch unit is connected, an output terminal of a previous stage of the shift register is electrically connected to a first terminal of the first switch unit, a shift signal input terminal of a next stage of the shift register is electrically connected to a second terminal of the first switch unit, and the first switch unit is any one of the switch units in the gate driving circuit;

the display panel further comprises a control signal line for controlling the conduction state of the switch units, and the control signal line is electrically connected with the control end of each switch unit.

4. The display panel according to claim 3, wherein the shift register is a bidirectional shift register.

5. The display panel according to claim 1, wherein the non-display area includes a first sub non-display area and a second sub non-display area located on opposite sides of the display area in a scan line extending direction,

a grid driving circuit, a starting signal line and n clock signal lines are arranged in the first sub non-display area and the second sub non-display area respectively; and the output ends of the same-level shift registers in the first sub non-display area and the second sub non-display area are connected with the same scanning line.

6. The display panel according to claim 1, wherein the shift register comprises: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor;

a gate of the first transistor is electrically connected to a first node, a first pole of the first transistor is electrically connected to the first clock signal input terminal, and a second pole of the first transistor is electrically connected to a second node; a grid electrode of the second transistor is electrically connected with the first clock signal input end, a first pole of the second transistor is electrically connected with the first potential signal input end, and a second pole of the second transistor is electrically connected with the second node;

a gate of the third transistor is electrically connected to the first clock signal input terminal, a first pole of the third transistor is electrically connected to the shift signal input terminal, and a second pole of the third transistor is electrically connected to a first node; a gate of the fourth transistor is electrically connected to the second clock signal input terminal, a first pole of the fourth transistor is electrically connected to a second pole of the fifth transistor, and a second pole of the fourth transistor is electrically connected to a second pole of the third transistor; the grid electrode of the fifth transistor is electrically connected with the second node, and the first electrode of the fifth transistor is electrically connected with the second potential signal input end;

a gate of the sixth transistor is electrically connected to the second node, a first pole of the sixth transistor is electrically connected to the second potential signal input terminal, a second pole of the sixth transistor is electrically connected to the output terminal of the shift register, and two ends of the first capacitor are respectively electrically connected to the gate and the first pole of the sixth transistor;

a gate of the seventh transistor is electrically connected to a first node, a first pole of the seventh transistor is electrically connected to the second clock signal input terminal, and a second pole of the seventh transistor is electrically connected to the output terminal of the shift register;

two ends of the second capacitor are respectively and electrically connected with the grid electrode and the second pole of the seventh transistor;

the shift register further comprises an eighth transistor, a gate of the eighth transistor is electrically connected to the second potential signal input terminal, a first pole of the eighth transistor is electrically connected to the first node, and a second pole of the eighth transistor is electrically connected to a gate of the seventh transistor.

7. A driving method of a display panel for driving the display panel according to any one of claims 1 to 6, the driving method comprising:

wherein, in a first period of supplying clock pulse signals to a first clock signal line to an nth clock signal line in sequence, a start pulse signal is supplied to a start signal line, wherein the start pulse signal is at least overlapped with the clock signal supplied to the first clock signal line.

8. The method for driving a display panel according to claim 7, wherein a rising edge of the start pulse signal coincides with a rising edge of a clock pulse signal supplied to a first clock signal line, and wherein the start pulse signal coincides with a falling edge of the clock pulse signal supplied to an nth clock signal line.

9. The method for driving a display panel according to claim 7, wherein the display region further includes a plurality of data lines and a plurality of pixel circuits; the data lines extend along a second direction, and each data line is connected with one column of the pixel circuits

The driving method further includes:

supplying a data signal to the data line from a second period in which clock pulse signals are sequentially supplied to the first clock signal line to the nth clock signal line;

before the periodically supplying the clock pulse signals to the first to nth clock signal lines, the method includes:

the start signal line is supplied with a level signal opposite to the start pulse signal, and the n clock signal lines are supplied with level signals opposite to the clock pulse signal.

10. A display device comprising the display panel according to any one of claims 1 to 6 and a driver chip, wherein the driver chip comprises n clock signal output terminals, and the n clock signal output terminals are electrically connected to the n clock signal lines in a one-to-one correspondence.