CN111710285B - Scanning circuit of display panel, driving method of display panel and display device - Google Patents
Scanning circuit of display panel, driving method of display panel and display device Download PDFInfo
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- CN111710285B CN111710285B CN202010561914.0A CN202010561914A CN111710285B CN 111710285 B CN111710285 B CN 111710285B CN 202010561914 A CN202010561914 A CN 202010561914A CN 111710285 B CN111710285 B CN 111710285B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a scanning circuit of a display panel, the display panel, a driving method of the display panel and a display device. The scanning circuit comprises a first shift register and a second shift register; the scanning circuit further includes: a control end of the first switch module is electrically connected with a first node of the second shift register, and a first end of the first switch module is electrically connected with a shift signal output end of the first shift register; and the control end of the second switch module is electrically connected with the first node of the first shift register, the first end of the second switch module is electrically connected with the shift signal output end of the second shift register, and the second end of the first switch module is electrically connected with the second end of the second switch module and then is used as the scanning signal output end of the scanning circuit. The scanning circuit has the advantages of simple structure, low design difficulty and the like.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a scanning circuit of a display panel, the display panel, a driving method of the display panel and a display device.
Background
With the development of display technology, the application of display panels is more and more extensive, and accordingly, the requirements on display panels are higher and higher.
The display panel needs to use a scan circuit to write data or control the light emitting duration of the sub-pixels, however, the scan circuit of the prior art is complex and difficult to design.
Disclosure of Invention
The invention provides a scanning circuit of a display panel, the display panel, a driving method of the display panel and a display device.
In a first aspect, an embodiment of the present invention provides a scanning circuit of a display panel, where the scanning circuit includes two shift registers, a first shift register and a second shift register; each shift register comprises a first node, a second node, a first output module, a second output module, a shift signal input end and a shift signal output end; the first node is used for controlling the conducting state of the first output module, the second node is used for controlling the conducting state of the second output module, and the potential of the first node is opposite to the potential of the shift signal output end; the shift register is used for shifting the signal input by the shift signal input end and then outputting the signal through the shift signal output end; the scanning circuit further includes: a control end of the first switch module is electrically connected with a first node of the second shift register, and a first end of the first switch module is electrically connected with a shift signal output end of the first shift register; and the control end of the second switch module is electrically connected with the first node of the first shift register, the first end of the second switch module is electrically connected with the shift signal output end of the second shift register, and the second end of the first switch module is electrically connected with the second end of the second switch module and then is used as the scanning signal output end of the scanning circuit.
Optionally, each of the shift registers includes: an input module, the first output module, the second output module, a first output control module, a second output control module, the first node, the second node, a first clock signal input terminal, a second clock signal input terminal, a first potential signal input terminal, a second potential signal input terminal, a shift signal input terminal, and the shift signal output terminal; the input module is electrically connected with the second node, the first clock signal input end and the shift signal input end, and is used for controlling the potential of the second node; the first output control module is electrically connected with the first node, the second node, the first potential signal input end and the second clock signal input end; the first output control module is used for controlling the potential of the second node; the second output control module is electrically connected with the first node, the second potential signal input end and the first clock signal input end; the second output control module is used for controlling the potential of the first node; the first output module is electrically connected with the second node, the second clock signal input end and the shift signal output end; during the conduction period of the first output module, a signal input by the second clock signal input end is transmitted to the shift signal output end; the second output module is electrically connected with the first node, the first potential signal input end and the displacement signal output end; during the conduction period of the second output module, the signal input by the first potential signal input end is transmitted to the shift signal output end.
Optionally, the first switch module includes a first transistor, a control terminal of the first transistor is used as a control terminal of the first switch module, a first terminal of the first transistor is used as a first terminal of the first switch module, and a second terminal of the first transistor is used as a second terminal of the first switch module; and/or the second switch module comprises a second transistor, a control end of the second transistor is used as a control end of the second switch module, a first end of the second transistor is used as a first end of the second switch module, and a second end of the second transistor is used as a second end of the second switch module.
In a second aspect, an embodiment of the present invention further provides a display panel, which includes a gate driver and a plurality of rows of sub-pixels, wherein the gate driver includes a plurality of scan circuits as described in the first aspect, a scan signal output terminal of each scan circuit is connected to a first scan line, and the first scan line is used for controlling the light emitting duration of the sub-pixels.
Optionally, a first shift register in the plurality of scan circuits is cascaded, and a second shift register in the plurality of scan circuits is cascaded; the display panel further comprises a time sequence controller, wherein a shifting signal input end of a first shifting register in the first scanning circuit is electrically connected with the time sequence controller, and a shifting signal input end of a second shifting register in the first scanning circuit is electrically connected with the time sequence controller.
Optionally, a shift signal output terminal of the first shift register in each of the scan circuits is connected to a second scan line, and the second scan line controls writing of data voltages to the sub-pixels.
Optionally, the sub-pixel includes a pixel circuit and a light emitting unit, and the pixel circuit includes a data writing module, a driving module, a first storage module, a light emitting control module, a second storage module, and a light emitting duration writing module; the control end of the data writing module is electrically connected with the second scanning signal input end, the first end of the data writing module is electrically connected with the data voltage input end, and the second end of the data writing module is electrically connected with the control end of the driving module; the first end of the driving module is electrically connected with the first voltage input end, and the second end of the driving module is electrically connected with the first end of the light-emitting control module; the first end of the first storage module is electrically connected with the first voltage input end, and the second end of the first storage module is electrically connected with the control end of the driving module; the control end of the light-emitting control module is electrically connected with the first end of the light-emitting duration writing module, and the second end of the light-emitting control module is electrically connected with the first end of the light-emitting unit; the first end of the second storage module is electrically connected with the first voltage input end, and the second end of the second storage module is electrically connected with the control end of the light-emitting control module; the control end of the luminous duration writing module is electrically connected with the first scanning signal input end, and the second end of the luminous duration writing module is electrically connected with the third scanning signal input end; the second pole of the light-emitting unit is electrically connected with the second voltage input end; the first scanning signal input end is electrically connected with the first scanning line, and the second scanning signal input end is electrically connected with the second scanning signal line.
Optionally, the sub-pixel includes a pixel circuit and a light emitting unit, and the pixel circuit includes a data writing module, a storage module, a first light emitting control module, a driving module, a threshold compensation module, a second light emitting control module, a bypass module, and a reset module; the control end of the reset module is electrically connected with the first scanning signal input end, the first end of the reset module is electrically connected with the reference signal input end, and the second end of the reset module is electrically connected with the control end of the driving module; the control end of the data writing module is electrically connected with the second scanning signal input end, the first end of the data writing module is electrically connected with the data voltage input end, and the second end of the data writing module is electrically connected with the first end of the driving module; the first end of the storage module is electrically connected with the first voltage input end, and the second end of the storage module is electrically connected with the control end of the driving module; the first end of the first light-emitting control module is electrically connected with the first voltage input end, the control end of the first light-emitting control module is electrically connected with the enable signal input end, and the second end of the first light-emitting control module is electrically connected with the first end of the driving module; the second end of the driving module is electrically connected with the first end of the threshold compensation module; the second end of the threshold compensation module is electrically connected with the control end of the driving module, and the control end of the threshold compensation module is electrically connected with the second scanning signal input end; the control end of the second light-emitting control module is electrically connected with the enable signal input end, the second end of the second light-emitting control module is electrically connected with the first end of the light-emitting unit, and the second end of the light-emitting unit is electrically connected with the second voltage input end; the control end of the bypass module is electrically connected with the third scanning signal input end, the first end of the bypass module is electrically connected with the reference signal input end, and the second end of the bypass module is electrically connected with the first end of the light-emitting unit; the third scanning signal input end is electrically connected with the first scanning line, and the second scanning signal input end is electrically connected with the second scanning line.
In a third aspect, an embodiment of the present invention further provides a method for driving a display panel, where the display panel is the display panel according to the second aspect, and the method includes: and in the same line period, controlling the time interval between the pulse signal input by the shift signal input end of the first shift register and the pulse signal input by the shift signal input end of the second shift register so as to control the light-emitting time of the sub-pixels.
In a fourth aspect, an embodiment of the present invention further provides a display device, including the display panel according to the second aspect.
According to the technical scheme, the adopted scanning circuit comprises a first switch module, a control end of the first switch module is electrically connected with a first node of a second shift register, and a first end of the first switch module is electrically connected with a shift signal output end of the first shift register; and the control end of the second switch module is electrically connected with the first node of the first shift register, the first end of the second switch module is electrically connected with the shift signal output end of the second shift register, and the second end of the first switch module is electrically connected with the second end of the second switch module and then is used as the scanning signal output end of the scanning circuit. The shift register and the switch module are commonly used modules in the display panel, and the two shift registers and the two switch modules are combined to output signals with two pulse signals in a line period and adjustable time intervals of the two pulse signals, so that the design difficulty of the scanning circuit is greatly simplified, and the cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram of a scan circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a timing diagram of FIG. 3;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 7 is a timing diagram of FIG. 6;
fig. 8 is a schematic circuit diagram of a pixel circuit according to yet another embodiment of the present invention;
FIG. 9 is a timing diagram of FIG. 8;
fig. 10 is a flowchart illustrating a driving method of a display panel according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the scanning circuit of the prior art is complicated, and the inventor has found through careful study that the reason for this technical problem is: for a pixel circuit which needs to be digitally driven, when the pixel circuit is digitally driven, some transistors in the pixel circuit need to be turned on twice in a row period, namely, light emitting is turned on and light emitting is finished, and meanwhile, the time interval between the light emitting is turned on and the light emitting is finished needs to be adjustable, namely, a scanning circuit needs to output two pulse signals in a row period, and the time interval between the two pulse signals needs to be adjustable, so that the existing scanning circuit is complex and the design difficulty is high.
Based on the technical problem, the invention provides the following solution:
fig. 1 is a schematic structural diagram of a scan circuit, which can be applied to a display panel according to an embodiment of the present invention, and referring to fig. 1, a scan circuit 10 includes two shift registers, a first shift register GIPA and a second shift register GIPB; each shift register comprises a first node Q, a second node P, a first output module, a second output module, a shift signal input end and a shift signal output end OUT; the first node Q is used for controlling the conducting state of the first output module, the second node is used for controlling the conducting state of the second output module, and the potential of the first node Q is opposite to the potential of the shift signal output end OUT; the shift register is used for shifting the signal input by the shift signal input end and then outputting the signal through the shift signal output end; the scanning circuit 10 further includes: a control end of the first switch module 11 is electrically connected to the first node QB of the second shift register GIPB, and a first end of the first switch module 11 is electrically connected to the shift signal output end OUTA of the first shift register GIPA; and a control terminal of the second switch module 12 is electrically connected to the first node QA of the first shift register GIPA, a first terminal of the second switch module 12 is electrically connected to the shift signal output terminal OUTB of the second shift register GIPB, and a second terminal of the first switch module 11 and a second terminal of the second switch module 12 are electrically connected to each other and then serve as a scan signal line OUTC of the scan circuit 10.
Specifically, the display panel may be, for example, an OLED (Organic Light-Emitting Diode) display panel, which includes a plurality of sub-pixels arranged in an array, each of the sub-pixels may include a pixel circuit and a Light-Emitting unit, and the pixel circuit provides a driving current for the Light-Emitting unit to drive the Light-Emitting unit to emit Light for display. The pixel circuit may be, for example, a digital driving or a digital-analog hybrid driving, and controls the gray scale displayed by the light emitting unit by controlling the light emitting duration of the light emitting unit, the pixel circuit needs to provide an on signal and an off signal to the light emitting unit, and the time interval between the on signal and the off signal needs to be adjustable, so as to control the light emitting unit to emit different lights.
The display panel generally includes a plurality of shift registers, the shift registers provide scan signals to the sub-pixels, and the shift registers include at least a first output module, a second output module, a first node, a second node, a shift signal input terminal, and a shift signal output terminal, and a potential of the first node is opposite to a potential of the shift signal output terminal at any time during normal operation of the shift registers. Fig. 2 is a timing diagram of a scan circuit according to an embodiment of the present invention, which is combined with fig. 1 and fig. 2, and is illustrated by taking the effective low level of the shift signal output terminal of the shift register as an example, at a stage t1, the shift signal output terminal OUTA of the first shift register GIPA outputs a high level, the first node QA of the first shift register GIPA outputs a low level, so as to control the second switch module 12 to be turned on, and at this time, the shift signal output terminal OUTB of the second shift register GIPB outputs a high level, and the first node QB of the second shift register GIPB outputs a low level, so as to control the first switch module 11 to be turned on, that is, at this time, the first switch module 11 and the second switch module 12 are both turned on, so as to ensure that the scan signal output terminal OUTC outputs a high level; at the stage t2, the shift signal output terminal OUTA of the first shift register GIPA outputs a low level, the first node QA of the first shift register GIPA outputs a high level, so as to control the second switch module 11 to turn off, and at this time, the shift signal output terminal OUTB of the second shift register GIPB outputs a high level, the first node QB of the second shift register GIPB outputs a low level, so as to control the first switch module 11 to turn on, and the scan signal output terminal OUTC outputs a signal of the shift signal output terminal OUTA of the first shift register GIPA, that is, a low level; the stage t3 is the same as the stage t1, and the scanning signal output terminal OUTC outputs high level; at the stage t4, the shift signal output terminal OUTA of the first shift register GIPA outputs a high level, the first node QA of the first shift register GIPA outputs a low level, so as to control the second switch module 11 to be turned on, and at this time, the shift signal output terminal OUTB of the second shift register GIPB outputs a low level, the first node QB of the second shift register GIPB outputs a high level, so as to control the first switch module 11 to be turned off, and the scan signal output terminal OUTC outputs a signal of the shift signal output terminal OUTB of the second shift register GIPB, that is, a low level; that is, the first switch module 11 and the second switch module 12 realize the superposition of the pulse signal output by the shift signal output terminal OUTA of the first shift register GIPA and the pulse signal output by the shift signal output terminal OUTB of the second shift register GIPB on the time sequence, that is, the output signal of the scan signal output terminal OUTC has two pulses (one of which is used as the on signal and the other is used as the off signal) in one row period, so that the light emitting time of the sub-pixels can be controlled, and further the gray scale of the display can be controlled. When the time interval between two pulses in the output signal of the scanning signal output end OUTC needs to be adjusted, the signal of the shifting signal input end of the first shifting register GIPA is adjusted, and/or the signal of the shifting signal input end of the second shifting register GIPB is adjusted, so that the debugging is simple, and the time interval between two pulses can be accurately adjusted. The shift register and the switch module are commonly used modules in the display panel, and the two shift registers and the two switch modules are combined to output signals which have two pulse signals in a line period and the time interval of the two pulse signals is adjustable, so that the design difficulty of the scanning circuit is greatly simplified, and the cost is reduced.
In the technical scheme of this embodiment, the adopted scanning circuit includes a first switch module, a control end of the first switch module is electrically connected with a first node of the second shift register, and a first end of the first switch module is electrically connected with a shift signal output end of the first shift register; and the control end of the second switch module is electrically connected with the first node of the first shift register, the first end of the second switch module is electrically connected with the shift signal output end of the second shift register, and the second end of the first switch module is electrically connected with the second end of the second switch module and then is used as the scanning signal output end of the scanning circuit. The shift register and the switch module are commonly used modules in the display panel, and the two shift registers and the two switch modules are combined to output signals with two pulse signals in a line period and adjustable time intervals of the two pulse signals, so that the design difficulty of the scanning circuit is greatly simplified, and the cost is reduced.
Illustratively, with continued reference to fig. 1, the first switch module 11 includes a first transistor M1, a control terminal of the first transistor M1 being a control terminal of the first switch module 11, a first terminal of the first transistor M1 being a first terminal of the first switch module 11, a second terminal of the first transistor M1 being a second terminal of the first switch module 11; and/or the second switch module 12 includes a second transistor M2, a control terminal of the second transistor M2 is used as a control terminal of the second switch module 12, a first terminal of the second transistor M2 is used as a first terminal of the second switch module 12, and a second terminal of the second transistor M2 is used as a second terminal of the second switch module 12.
The first transistor M1 and the second transistor M2 may both be P-type transistors, a pixel circuit in the display panel also includes a plurality of transistors, the first transistor M1 and the second transistor M2 may be formed simultaneously with the transistors in the pixel circuit, that is, the active layer, the gate insulating layer, the interlayer insulating layer, the source drain layer, and the like are respectively disposed in the same layer, the manufacturing process of the transistors in the display panel is mature, and the first transistor M1 and the second transistor M2 are formed simultaneously with the transistors in the pixel circuit, which not only reduces the process difficulty, but also improves the stability of the transistors in operation.
It should be noted that, when the output signal of the shift signal output terminal of the shift register is active high, the first transistor M1 and the second transistor M2 can be N-type transistors.
Alternatively, fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, and fig. 4 is a timing diagram of fig. 3, with reference to fig. 3 and fig. 4; the shift register comprises an input module 103, a first output module 101, a second output module 102, a first output control module 104, a second output control module 105, a first node Q, a second node P, a first clock signal input end CK, a second clock signal input end CKB, a first potential signal input end VGH, a second potential signal input end VGL, a shift signal input end STV and a shift signal output end OUT; the input module 103 is electrically connected with the second node P, the first clock signal input terminal CK and the shift signal input terminal STV, and the input module 103 is used for controlling the potential of the second node P; the first output control module 104 is electrically connected to the first node Q, the second node P, the first potential signal input terminal VGH, and the second clock signal input terminal CKB; the first output control module 104 is used for controlling the potential of the second node P; the second output control module 105 is electrically connected with the first node Q, the second node P, the second potential signal input terminal VGL and the first clock signal input terminal CK; the second output control module 105 is used for controlling the potential of the first node Q; the first output module 101 is electrically connected to the second node P, the second clock signal input terminal CKB, and the shift signal output terminal OUT; during the on period of the first output module 101, the signal inputted from the second clock signal input terminal CKB is transmitted to the shift signal output terminal OUT; the second output module 102 is electrically connected to the first node Q, the first potential signal input terminal VGH and the shift signal output terminal OUT; during the on period of the second output module 102, the signal inputted from the first voltage level signal input terminal VGH is transmitted to the shift signal output terminal OUT.
The first output module 101 may include a third transistor M3 and a first capacitor C1, the second output module 102 may include a fourth transistor M4 and a second capacitor C2, the input module 103 may include a fifth transistor M5, the first output control module 104 may include a sixth transistor M6 and a seventh transistor M7, the second output control module 105 may include an eighth transistor M8 and a ninth transistor M9, and the shift register may further include a tenth transistor M10 electrically connected to the structure shown in fig. 3, that is:
a control terminal of the third transistor M3 is electrically connected to the first terminal of the first capacitor C1, the first terminal thereof is electrically connected to the second clock signal input terminal CKB, the second terminal thereof is electrically connected to the second terminal of the first capacitor C1, and the shift signal output terminal OUT;
a control end of the fourth transistor M4 is electrically connected to the first end of the second capacitor C2, the first end is electrically connected to the first potential signal input terminal VGH, and the second end is electrically connected to the shift signal output terminal OUT;
a control terminal of the fifth transistor M5 is electrically connected to the first clock signal input terminal CK, a first terminal thereof is electrically connected to the shift signal input terminal STV, and a second terminal thereof is electrically connected to the first terminal of the tenth transistor M10;
a first terminal of the sixth transistor M6 is electrically connected to the first potential signal input terminal VGH, a control terminal is electrically connected to the first node Q, and a second terminal is electrically connected to the first terminal of the seventh transistor M7;
a control terminal of the seventh transistor M7 is electrically connected to the second clock signal input terminal CKB, and a second terminal is electrically connected to the first terminal of the tenth transistor M10;
a first terminal of the eighth transistor M8 is electrically connected to the second potential signal input terminal VGL, a control terminal thereof is electrically connected to the first clock signal input terminal CK, and a second terminal thereof is electrically connected to the first node Q;
a control terminal of the ninth transistor M9 is electrically connected to the first terminal of the tenth transistor M10, the first terminal is electrically connected to the first node Q, and the second terminal is electrically connected to the first clock signal CK;
a control terminal of the tenth transistor M10 is electrically connected to the second potential signal input terminal VGL, and a second terminal is electrically connected to the second node P.
The first voltage signal input terminal VGH and the second voltage signal input terminal VGL input different voltages, for example, the first voltage signal input terminal VGH inputs a high level, and the second voltage signal input terminal VGL inputs a low level. The working process of the shift register is as follows:
in the first stage t1, the STV input signal at the shift signal input terminal is at a high level, the CK input signal is at a low level, and the CKB input signal at the second clock signal input terminal is at a low level, at this time, the eighth transistor M8, the fifth transistor M5, the seventh transistor M7, the sixth transistor M6 and the tenth transistor M10 are turned on, so that the fourth transistor M4 is turned on, the third transistor M3 and the ninth transistor M9 are turned off, the shift signal output terminal OUT outputs a high level, and the first node Q is at a low level; in the second stage t2, the STV input signal at the shift signal input terminal is at a high level, the CK input signal is at a high level, the CKB input signal at the second clock signal input terminal is at a low level, the eighth transistor M8, the ninth transistor M9, the fifth transistor M5, and the third transistor M3 are turned off, the sixth transistor M6, the fourth transistor M4, and the seventh transistor M7 are turned on, the shift signal output terminal OUT is held by the first capacitor C1, and the signal input by the VGH input terminal is transmitted to the shift signal output terminal OUT through the fourth transistor M4, the shift signal output terminal OUT still outputs a high level, and the first node Q is at a low level; in the third stage t3, the STV input signal at the shift signal input terminal is at a low level, the CK input signal is at a low level, the CKB input signal at the second clock signal input terminal is at a high level, at this time, the eighth transistor M8, the ninth transistor M9, the fifth transistor M5, and the sixth transistor M6 are turned on, the seventh transistor M7 is turned off, so that the fourth transistor M4 is turned on, the shift signal output terminal OUT outputs a high level, the first node Q outputs a low level, at this time, the third transistor M3 is also turned on, the CKB input signal at the second clock signal input terminal is at a high level, and the shift signal output terminal OUT is further ensured; at a fourth stage t4, when the input signal of the shift signal input terminal STV is at a high level, the input signal of the first clock signal CK is at a high level, and the input signal of the second clock signal input terminal CKB is at a low level, the eighth transistor M8, the fifth transistor M5, the sixth transistor M6, and the fourth transistor M4 are turned off, the seventh transistor M7, the third transistor M3, and the ninth transistor M9 are turned on, so that the first node Q is at a high level, and the shift signal output terminal OUT outputs a low level; thereby achieving a shift of the STV input signal at the shift signal input.
The shift register of the present embodiment is also referred to as an "8T 2C" structure, which has advantages of high stability and universal usage, and the potential of the first node Q is opposite to the potential of the shift signal output terminal OUT, and can be combined with the first switch module and the second switch module to form the scan circuit provided by the present embodiment.
Fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 5, the display panel 20 includes a gate driver 201 and a plurality of rows of subpixels PX, the gate driver 201 includes a plurality of scanning circuits 10 according to any embodiment of the present invention, a scanning signal output terminal OUTC of each scanning circuit 10 is connected to a first scanning line SR, and the first scanning line SR is used for controlling a light emitting duration of the subpixels PX.
Specifically, the display panel 20 may include a plurality of sub-pixels PX arranged in an array, where the sub-pixels PX may be, for example, red sub-pixels, green sub-pixels, or blue sub-pixels, the display panel 20 may include a plurality of scanning lines and data lines interlaced in a horizontal direction and a vertical direction, for example, the display panel may include j data lines (DL1 to DLj), where j is an integer, and k first scanning lines (SR1 to SRk), where k is an integer, the data lines and the scanning lines define a region of the sub-pixels PX, the sub-pixels PX may be a digitally driven light emitting manner or a digital-analog hybrid driven light emitting manner, the first scanning lines SR may be used to control a light emitting period of the sub-pixels, scanning signals on the first scanning lines SR may be provided by the scanning circuit 10 according to any of the embodiments of the present invention, the scanning circuit 10 may have advantages of low design difficulty, and the display panel according to the embodiments of the present invention may also have advantages of low design difficulty.
Alternatively, with continued reference to fig. 5, a first shift register GIPA in the plurality of scan circuits 10 is cascaded, and a second shift register GIPB in the plurality of scan circuits 10 is cascaded; the display panel 20 further includes a timing controller 202, and the shift signal input terminal STVA of the first shift register GIPA in the first scan circuit 10 is electrically connected to the timing controller 202, and the shift signal input terminal STVB of the second shift register GIPB in the first scan circuit 10 is electrically connected to the timing controller 202.
Specifically, the first shift register GIPA cascade and the second shift register GIPB cascade are used to enable the first scan line SR corresponding to each row of sub-pixels PX to receive a scan signal containing two pulses in one row period, and the circuit structure is simple, and when the pulse time interval in the output signal of the scan signal line OUTC of the corresponding scan circuit 10 needs to be adjusted, the timing controller 202 may adjust the input signal of the first shift register GIPA in the first scan circuit 10 and/or adjust the input signal of the second shift register GIPB in the first scan circuit 10.
Alternatively, with continued reference to fig. 5, the shift signal output terminal OUTA of the first shift register GIPA in each scan circuit 10 is connected to one second scan line SL that controls data voltage writing of the sub-pixels PX.
Specifically, the sub-pixels PX may be driven by a digital-analog hybrid driving method, and when the display panel (for example, when the display panel is lower than 32 gray scales or lower than 64 gray scales) displays a low gray scale, the driving current of the driving transistor in the pure analog driving circuit is relatively small, which makes the adjustment difficult, and the display inequality gate driver 201 is easy to occur, and besides the scanning signal for controlling the length of the light emitting time needs to be provided to the sub-pixels PX, the scanning signal for controlling the data writing needs to be provided to the sub-pixels PX, so that the gray scale displayed by the sub-pixels PX is relatively accurate through the common control of the data voltage and the light emitting time. In this embodiment, the shift signal output terminal OUTA of the first shift register GIPA may be electrically connected to the second scan line SL to provide a scan signal to the second scan line SL, so that multiplexing of the first shift register GIPA is achieved, the number of shift registers in the display panel may be reduced, and the frame may be reduced. When the time interval of the pulse signal output by the scanning signal line OUTC of the scanning circuit 10 needs to be adjusted, the adjustment can be realized by adjusting the input signal of the second shift register GIPB in the first scanning circuit 10, so that inconvenience caused by the need of adjusting the data voltage when the input signal of the first shift register GIPB is adjusted is avoided.
It should be noted that the second scan lines SL correspond to the first scan lines SR one to one, that is, the number of the second scan lines SL is the same as that of the first scan lines SR. The display panel may further include a source driver 203, and the source driver 203 is configured to provide a data voltage to each data line DL.
Optionally, fig. 6 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention, referring to fig. 6, a sub-pixel includes a pixel circuit and a light emitting unit D, the pixel circuit includes a data writing module 301, a driving module 302, a first storage module 303, a light emitting control module 304, a second storage module 305, and a light emitting duration writing module 306; the control end of the data writing module is electrically connected with the second scanning signal input end Scan _ L, the first end of the data writing module is electrically connected with the data voltage input end, and the second end of the data writing module is electrically connected with the control end of the driving module; a first end of the driving module 302 is electrically connected to the first voltage input terminal VDD, and a second end of the driving module 302 is electrically connected to a first end of the light emitting control module 304; a first end of the first storage module 303 is electrically connected to the first voltage input terminal VDD, and a second end of the first storage module 303 is electrically connected to the control terminal of the driving module 302; a control end of the light-emitting control module 304 is electrically connected with a first end of the light-emitting duration writing module 306, and a second end of the light-emitting control module 304 is electrically connected with a first end of the light-emitting unit D; a first end of the second storage module 305 is electrically connected to the first voltage input terminal VDD, and a second end of the second storage module 305 is electrically connected to the control terminal of the light emitting control module 304; a control terminal of the light emitting duration writing module 306 is electrically connected to the first scanning signal input terminal Scan _ R, and a second terminal of the light emitting duration writing module is electrically connected to the third scanning signal input terminal ofs; the second pole of the light-emitting unit D is electrically connected with the second voltage input end VSS; the first scanning signal input end is electrically connected with the first scanning line, and the second scanning signal input end is electrically connected with the second scanning signal line.
Specifically, the first voltage input terminal VDD may input a high level signal, the second voltage input terminal VSS may input a low level signal, the Data write module 301, the driving module 302, the light emitting control module 304, and the light emitting duration write module 306 are all transistors, the first memory module 303 and the second memory module 305 are all capacitors, fig. 7 is a timing diagram of fig. 6, in combination with fig. 6 and 7, the first Scan signal input terminal Scan _ R may be electrically connected to the first Scan line SR, the second Scan signal input terminal Scan _ L and the third Scan signal input terminal ofs may be electrically connected to the second Scan line SL, in a stage t1, the first Scan signal input terminal Scan _ R, the second Scan signal input terminal Scan _ L, and the third Scan signal input terminal ofs are all low levels, the Data write module is turned on, the Data signal input terminal Data writes a Data voltage into the first memory module 303, and controls the driving module 302 to output a driving current, at this time, the light-emitting duration writing module 306 is turned on, and the scanning signal at the third scanning signal input terminal ofs controls the light-emitting control module 304 to be turned on, so that the driving current flows into the light-emitting unit D, and the light-emitting unit emits light; at stage t2, due to the holding of the first storage module 303 and the second storage module 305, the driving module 302 and the light-emitting control module 304 are still turned on, i.e. the light-emitting unit D still emits light; at the stage t3, since the first Scan signal input terminal Scan _ R inputs a low level, the light-emitting duration writing module 306 is turned on, and the control terminals of the second storage module 305 and the light-emitting control module 304 write a high level, so as to control the light-emitting control module 304 to turn off, thereby stopping the light-emitting unit D from emitting light; when the signals on the first scan line SR are different, the duration of the t2 stage is also different, so that the light emitting duration of the light emitting unit D is different, and accurate gray scale display is achieved.
Optionally, fig. 8 is a schematic circuit structure diagram of another pixel circuit provided in an embodiment of the present invention, fig. 9 is a timing diagram of fig. 8, and with reference to fig. 8 and 9, a sub-pixel includes a pixel circuit and a light emitting unit, the pixel circuit includes a data writing module 401, a storage module 402, a first light emitting control module 403, a driving module 404, a threshold compensation module 405, a second light emitting control module 406, and a bypass module 407; the control end of the reset module 408 is electrically connected to the first scan signal input end S1, the first end of the reset module 408 is electrically connected to the reference signal input end Vref, and the second end of the reset module 408 is electrically connected to the control end of the driving module 404; the control end of the Data writing module 401 is electrically connected to the second scanning signal input end S2, the first end of the Data writing module 401 is electrically connected to the Data voltage input end Data, and the second end of the Data writing module 401 is electrically connected to the first end of the driving module 404; a first end of the memory module 402 is electrically connected to the first voltage input end VDD, and a second end of the memory module 402 is electrically connected to the control end of the driving module 404; a first end of the first light-emitting control module 403 is electrically connected to the first voltage input terminal VDD, a control end of the first light-emitting control module 403 is electrically connected to the enable signal input terminal EM, and a second end of the first light-emitting control module 403 is electrically connected to a first end of the driving module 404; a second end of the driving module 404 is electrically connected with a first end of the threshold compensation module 405; a second end of the threshold compensation module 405 is electrically connected to a control end of the driving module 404, and the control end of the threshold compensation module 405 is electrically connected to the second scanning signal input end S2; a control end of the second light-emitting control module 406 is electrically connected with the enable signal input end EM, a second end of the second light-emitting control module 406 is electrically connected with a first end of the light-emitting unit D, and a second end of the light-emitting unit D is electrically connected with the second voltage input end VSS; a control terminal of the bypass module 407 is electrically connected to the third scan signal input terminal S3, a first terminal of the bypass module 407 is electrically connected to the reference signal input terminal Vref, and a second terminal of the bypass module 407 is electrically connected to the first terminal of the light emitting unit D; the third scan signal input terminal S3 is electrically connected to the first scan line SR, and the second scan signal input terminal S2 is electrically connected to the second scan line SL.
Specifically, the first voltage input terminal VDD may input a high level, the second voltage input terminal VSS may input a low level, the data writing module 401, the first light emitting control module 403, the driving module 404, the threshold compensation module 405, the second light emitting control module 406, and the bypass module 407 may employ transistors, the storage module 402 may employ a capacitor, the pixel circuit of this embodiment has a threshold compensation function, and the threshold compensation process is well known in the art and is not described herein again. In this embodiment, the control end of the bypass module 407 is connected to the first scan line SR, the bypass module 407 is turned on twice in a row period, the light emitting unit D is initialized when turned on for the first time to eliminate data residue during displaying of a previous frame, and the light emitting unit D is initialized again when turned on for the second time to eliminate data of a current frame, that is, to control turn-off of the light emitting unit D, so as to control the light emitting time of the light emitting unit D, thereby implementing accurate gray scale display.
Fig. 10 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, and referring to fig. 10, the driving method of the display panel includes:
in step S501, in the same line period, a time interval between the pulse signal input from the shift signal input terminal of the first shift register and the pulse signal input from the shift signal input terminal of the second shift register is controlled to control the light emitting time of the sub-pixels.
Specifically, the pulse signal input by the shift signal input end of the first shift register can be adjusted through the time sequence controller, and/or the pulse signal input by the one-dimensional signal input end of the second shift register can be adjusted through the time sequence controller, so that the time interval between the pulse signal input by the shift signal input end of the first shift register and the pulse signal input by the shift signal input end of the second shift register is controlled, the light emitting time of the sub-pixels is controlled, the display panel can achieve accurate gray scale display, the problem of display unevenness is solved, and the display effect is improved.
Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 11, the display device includes a display panel according to any embodiment of the present invention, and the display device may be, for example, a mobile phone, a tablet, a notebook, a display, a smart watch, an MP3, an MP4, or other wearable devices.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. The scanning circuit of a kind of display panel, characterized by, the said scanning circuit includes two shift registers of the first shift register and second shift register;
each shift register comprises a first node, a second node, a first output module, a second output module, a shift signal input end and a shift signal output end; the first node is used for controlling the conducting state of the first output module, the second node is used for controlling the conducting state of the second output module, and the potential of the first node is opposite to the potential of the shifting signal output end; the shift register is used for shifting the signal input by the shift signal input end and then outputting the signal through the shift signal output end;
the scanning circuit further includes:
a control end of the first switch module is electrically connected with a first node of the second shift register, and a first end of the first switch module is electrically connected with a shift signal output end of the first shift register;
a control end of the second switch module is electrically connected with the first node of the first shift register, a first end of the second switch module is electrically connected with a shift signal output end of the second shift register, and a second end of the first switch module is electrically connected with a second end of the second switch module and then serves as a scanning signal output end of the scanning circuit;
and when the time interval between two pulses in the output signal of the scanning signal output end needs to be adjusted, adjusting the signal of the shifting signal input end of the first shifting register and/or adjusting the signal of the shifting signal input end of the second shifting register.
2. The scan circuit of claim 1, wherein each of the shift registers comprises: an input module, the first output module, the second output module, a first output control module, a second output control module, the first node, the second node, a first clock signal input terminal, a second clock signal input terminal, a first potential signal input terminal, a second potential signal input terminal, a shift signal input terminal, and the shift signal output terminal;
the input module is electrically connected with the second node, the first clock signal input end and the shift signal input end, and is used for controlling the potential of the second node;
the first output control module is electrically connected with the first node, the second node, the first potential signal input end and the second clock signal input end; the first output control module is used for controlling the potential of the second node;
the second output control module is electrically connected with the first node, the second potential signal input end and the first clock signal input end; the second output control module is used for controlling the potential of the first node;
the first output module is electrically connected with the second node, the second clock signal input end and the shift signal output end; during the conduction period of the first output module, a signal input by the second clock signal input end is transmitted to the shift signal output end; the second output module is electrically connected with the first node, the first potential signal input end and the shift signal output end; during the conduction period of the second output module, the signal input by the first potential signal input end is transmitted to the shift signal output end.
3. The scan circuit of claim 1, wherein the first switch module comprises a first transistor, a control terminal of the first transistor is used as the control terminal of the first switch module, a first terminal of the first transistor is used as the first terminal of the first switch module, and a second terminal of the first transistor is used as the second terminal of the first switch module; and/or the presence of a gas in the gas,
the second switch module comprises a second transistor, a control end of the second transistor is used as a control end of the second switch module, a first end of the second transistor is used as a first end of the second switch module, and a second end of the second transistor is used as a second end of the second switch module.
4. A display panel comprising a gate driver and a plurality of rows of sub-pixels, wherein the gate driver comprises a plurality of scanning circuits according to any one of claims 1 to 3, and a scanning signal output terminal of each scanning circuit is connected to a first scanning line for controlling the light emitting duration of the sub-pixels.
5. The display panel according to claim 4, wherein a first shift register of a plurality of the scanning circuits is cascade-connected, and a second shift register of the plurality of the scanning circuits is cascade-connected; the display panel further comprises a time sequence controller, wherein the shift signal input end of a first shift register in the first scanning circuit is electrically connected with the time sequence controller, and the shift signal input end of a second shift register in the first scanning circuit is electrically connected with the time sequence controller.
6. The display panel according to claim 5, wherein the shift signal output terminal of the first shift register in each of the scanning circuits is connected to a second scanning line, and the second scanning line controls writing of the data voltage to the sub-pixel.
7. The display panel according to claim 6, wherein the sub-pixel includes a pixel circuit and a light emitting unit, and the pixel circuit includes a data writing module, a driving module, a first storage module, a light emission control module, a second storage module, and a light emission period writing module;
the control end of the data writing module is electrically connected with the second scanning signal input end, the first end of the data writing module is electrically connected with the data voltage input end, and the second end of the data writing module is electrically connected with the control end of the driving module;
the first end of the driving module is electrically connected with the first voltage input end, and the second end of the driving module is electrically connected with the first end of the light-emitting control module;
the first end of the first storage module is electrically connected with the first voltage input end, and the second end of the first storage module is electrically connected with the control end of the driving module;
the control end of the light-emitting control module is electrically connected with the first end of the light-emitting duration writing module, and the second end of the light-emitting control module is electrically connected with the first end of the light-emitting unit;
the first end of the second storage module is electrically connected with the first voltage input end, and the second end of the second storage module is electrically connected with the control end of the light-emitting control module;
the control end of the luminous duration writing module is electrically connected with the first scanning signal input end, and the second end of the luminous duration writing module is electrically connected with the third scanning signal input end;
the second pole of the light-emitting unit is electrically connected with the second voltage input end;
the first scanning signal input end is electrically connected with the first scanning line, and the second scanning signal input end is electrically connected with the second scanning signal line.
8. The display panel according to claim 6, wherein the sub-pixel includes a pixel circuit and a light emitting unit, the pixel circuit including a data writing module, a storage module, a first light emitting control module, a driving module, a threshold value compensation module, a second light emitting control module, a bypass module, and a reset module;
the control end of the reset module is electrically connected with the first scanning signal input end, the first end of the reset module is electrically connected with the reference signal input end, and the second end of the reset module is electrically connected with the control end of the driving module;
the control end of the data writing module is electrically connected with the second scanning signal input end, the first end of the data writing module is electrically connected with the data voltage input end, and the second end of the data writing module is electrically connected with the first end of the driving module;
the first end of the storage module is electrically connected with the first voltage input end, and the second end of the storage module is electrically connected with the control end of the driving module;
the first end of the first light-emitting control module is electrically connected with the first voltage input end, the control end of the first light-emitting control module is electrically connected with the enabling signal input end, and the second end of the first light-emitting control module is electrically connected with the first end of the driving module;
the second end of the driving module is electrically connected with the first end of the threshold compensation module;
the second end of the threshold compensation module is electrically connected with the control end of the driving module, and the control end of the threshold compensation module is electrically connected with the second scanning signal input end;
the control end of the second light-emitting control module is electrically connected with the enable signal input end, the second end of the second light-emitting control module is electrically connected with the first end of the light-emitting unit, and the second end of the light-emitting unit is electrically connected with the second voltage input end;
the control end of the bypass module is electrically connected with the third scanning signal input end, the first end of the bypass module is electrically connected with the reference signal input end, and the second end of the bypass module is electrically connected with the first end of the light-emitting unit;
the third scanning signal input end is electrically connected with the first scanning line, and the second scanning signal input end is electrically connected with the second scanning line.
9. A method of driving a display panel according to any one of claims 4 to 8, the method comprising:
and in the same line period, controlling the time interval between the pulse signal input by the shift signal input end of the first shift register and the pulse signal input by the shift signal input end of the second shift register so as to control the light-emitting time of the sub-pixels.
10. A display device characterized by comprising the display panel according to any one of claims 4 to 8.
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| WO2023044816A1 (en) * | 2021-09-24 | 2023-03-30 | 京东方科技集团股份有限公司 | Pixel circuit, driving method therefor, and display device |
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| WO2020228017A1 (en) * | 2019-05-16 | 2020-11-19 | 京东方科技集团股份有限公司 | Signal generation method, signal generation circuit, and display apparatus |
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