CN109523969B - Driving circuit and method of display panel, and display device - Google Patents
Driving circuit and method of display panel, and display device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000003990 capacitor Substances 0.000 claims abstract description 35
- 239000010409 thin film Substances 0.000 claims description 56
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 230000009194 climbing Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000009467 reduction Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 238000006243 chemical reaction Methods 0.000 description 1
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- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a driving circuit of a display panel, a method thereof and a display device, wherein the circuit comprises: a timing controller configured to output a timing control signal; the grid electrode starting voltage is set to receive the driving power supply to drive the sub-pixels in the corresponding row; a chamfering circuit configured to generate a ground chamfering control signal and a second chamfering control signal upon receiving the timing control signal; the driving power supply is further configured to perform chamfering on the gate start voltage output to the gate driving circuit when receiving the first chamfering control signal, wherein the chamfering time is a first preset time, so as to control the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows to be a first preset voltage; and when receiving a second chamfering control signal, chamfering the grid starting voltage output to the grid driving circuit, wherein the chamfering time is a second preset time, and the first preset time is less than the second preset time. The invention improves the picture quality of the display device.
Description
Technical Field
The present invention relates to the field of liquid crystal driving technologies, and in particular, to a driving circuit and a driving method for a display panel, and a display device.
Background
At present, in a design of a liquid crystal display panel adopting a dual-gate pixel driving structure, in order to ensure high pixel charging rate and good image quality of the panel, the dual-gate pixel driving structure is usually configured with a 1+2line or 2line inversion method to drive polarity inversion of a capacitor in a pixel array.
However, in the inversion method, the voltage across the data voltage is too high, so that the charging saturation levels of two adjacent pixels are inconsistent, and the problem of bright and dark lines occurs, which may result in the degradation of the picture quality of the liquid crystal display panel.
Disclosure of Invention
The present invention provides a driving circuit of a display panel, a method thereof and a display device, aiming to improve the picture quality of the display device.
In order to achieve the above object, the present invention provides a driving circuit of a display panel, the display panel having a plurality of sub-pixels; the drive circuit of the display panel includes:
a timing controller configured to output a timing control signal;
a driving power supply configured to output a gate-on voltage and/or a gate-off voltage;
the grid driving circuit is used for receiving the grid starting voltage of the driving power supply and driving the sub-pixels in the corresponding row;
the chamfering circuit is arranged for generating a first chamfering control signal and a second chamfering control signal when receiving the time sequence control signal;
the driving power supply is further configured to perform chamfering on the gate start voltage output to the gate driving circuit when the first chamfering control signal is received, wherein the chamfering time is a first preset time, so that the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows is controlled to be a first preset voltage; and
when the driving power supply receives the second chamfering control signal, chamfering is carried out on the grid starting voltage output to the grid driving circuit, the chamfering time is second preset time, so that the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows is controlled to be equal to the first preset voltage, and the first preset time is shorter than the second preset time.
Optionally, the chamfering circuit includes a signal trigger circuit and a switch control circuit, a controlled end of the signal trigger circuit is connected to the timing controller, an output end of the signal trigger circuit is connected to the switch control circuit, a first input end of the second switch control circuit is connected to the first chamfering control signal, and a second input end of the second switch control circuit is connected to the second chamfering control signal; the output end of the switch control circuit is connected with the driving power supply;
the signal trigger circuit is configured to generate and output a trigger signal of a high/low level according to the timing control signal;
the switch control circuit is configured to control the time of the gate on voltage output by the driving power supply to the gate driving circuit to be a first preset time according to the high-level trigger signal;
and controlling the time of the grid opening voltage output from the driving power supply to the grid driving circuit to be second preset time according to the low-level trigger signal.
Optionally, the signal trigger circuit includes a flip-flop and an inverter, a clock signal input end of the flip-flop is connected to the timing controller, and a trigger signal input end of the flip-flop is interconnected with the output ends of the switch control circuit and the inverter; and the output end of the trigger is connected with the output end of the phase inverter.
Optionally, the switch control circuit includes a first switch tube and a second switch tube, controlled ends of the first switch tube and the second switch tube are interconnected with an output end of the signal trigger circuit, an input end of the first switch tube is a first input end of the switch control circuit, and an input end of the second switch tube is a second input end of the switch control circuit; the output end of the first switch tube and the output end of the second switch tube are respectively connected with the driving power supply.
Optionally, the switch control circuit further includes a first resistor, one end of the first resistor is interconnected with the controlled ends of the first switch tube and the second switch tube, and the other end of the first resistor is grounded.
Optionally, the display panel comprises a switch array; the drive circuit of the display panel further comprises a plurality of data lines and a plurality of scanning lines electrically connected with the gate drive circuit, the switch array comprises a plurality of thin film transistors, the thin film transistors in odd columns in each row are respectively and electrically connected with the scanning lines in odd rows, the thin film transistors in even columns in each row are respectively and electrically connected with the electric connection ends of the scanning lines in even rows, and the adjacent thin film transistors in odd columns and the thin film transistors in even columns are electrically connected with the same data line.
Optionally, the display panel comprises a switch array; the drive circuit of the display panel further comprises a plurality of data lines and a plurality of scanning lines electrically connected with the gate drive circuit, the switch array comprises a plurality of thin film transistors, the thin film transistors in odd columns in all rows are respectively and electrically connected with the scanning lines in even rows, the thin film transistors in even columns in all rows are respectively and electrically connected with the electric connection ends of the scanning lines in odd rows, and the adjacent thin film transistors in odd columns and the thin film transistors in even columns are electrically connected with the same data line.
Optionally, the polarity inversion manner of the switch array is 1+2 rows of pixel row line signal inversion;
or, the polarity inversion mode of the switch array is 2 rows of pixel row line signal inversion.
The invention also provides a display device, which comprises a display panel with a plurality of sub-pixels, and a driving circuit of the display panel; the driving circuit of the display panel includes:
a timing controller configured to output a timing control signal;
a driving power supply configured to output a gate-on voltage and/or a gate-off voltage;
the grid driving circuit is used for receiving the grid starting voltage of the driving power supply and driving the sub-pixels in the corresponding row;
the corner cutting circuit is set to control the time of the grid starting voltage output by the driving power supply to the grid driving circuit to be a first preset time when the time sequence control signal is received so as to control the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows to be a first preset voltage; and
controlling the time of the grid starting voltage output by the driving power supply to the grid driving circuit to be second preset time so as to control the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time.
The invention also provides a driving method of a display panel, which comprises the following steps:
when the display panel works, the time sequence controller outputs a time sequence control signal;
when receiving a first chamfering control signal, the driving power supply performs chamfering on the grid opening voltage for a first preset time so as to control the capacitor charging voltage of the sub-pixels in the previous row in two adjacent rows to be a first preset voltage; and
and when a second chamfering control signal is received, chamfering the grid opening voltage for a second preset time, wherein the first preset time is less than the second preset time.
The driving circuit of the display panel outputs the time sequence control signal through the time sequence controller so that the chamfering circuit receives the time sequence control signal, and the driving power supply outputs the grid opening voltage so as to drive the grid driving circuit to drive the sub-pixels of the corresponding row to work according to the grid opening voltage of the driving power supply. Therefore, in the process that the gate driving circuit outputs corresponding row scanning signals to the thin film transistor through the row scanning lines to sequentially start the gate driving circuit from a first row scanning line to a last row scanning line of the scanning lines line by line, the time of the driving power supply outputting a gate starting voltage to the gate driving circuit is controlled by the chamfering circuit to be first preset time, and the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows is controlled to be first preset voltage; controlling the time of the grid starting voltage output from the driving power supply to the grid driving circuit to be second preset time so as to control the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time. Therefore, the chamfering time of the scanning line in the previous row in the two adjacent rows is controlled and adjusted to be smaller than the chamfering time of the scanning line in the next row in the two adjacent rows. And further, the chamfering slope of the waveform of the row driving voltage output by the scanning line of the previous row in each two adjacent rows is smaller than that of the waveform of the row driving voltage output by the scanning line of the adjacent row, so that the opening area of the thin film transistor of the previous row in the two adjacent rows is larger than that of the thin film transistor adjacent to the previous row, that is, the charging efficiency of the sub-pixel corresponding to the scanning line of the previous row in the two adjacent rows is improved, and the time lost due to voltage switching and climbing is compensated. Therefore, the charging saturation degree of the sub-pixels corresponding to the scanning line of the previous row in the two adjacent rows is consistent with the charging saturation degree of the sub-pixels corresponding to the scanning line of the even row. By the arrangement, when the voltage of the data signal is switched from the positive polarity to the negative polarity or from the negative polarity to the positive polarity, the same charging effect and consistent brightness of each sub-pixel are ensured. The invention solves the problem that when the polarity of the data signal voltage is reversed, because the voltage across the data signal voltage is larger, the charging saturation degree of two adjacent sub-pixels sharing one data line is different, and a low gray scale bright and dark line appears, and improves the picture quality of the display device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of a driving circuit of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an embodiment of the corner cutting circuit in FIG. 1;
FIG. 3 is a schematic structural diagram of a dual-gate pixel driving structure in a display device according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another embodiment of a dual-gate pixel driving structure in a display device according to the present invention;
fig. 5 is a waveform diagram of signal input/output at each signal terminal of the chamfering circuit in fig. 1.
Fig. 6 is a flow chart illustrating an embodiment of a gate driving method of the dual gate pixel driving structure according to the present invention, which is configured as a display device.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a driving circuit of a display panel, which is applied to a display device.
In this embodiment, the display device may be a display device having a liquid crystal display screen, such as a computer display screen, a mobile phone, a monitor, or a television. The display device includes a display panel 100; a timing controller 200 configured to output a first timing control signal and a second timing control signal; a driving power supply 300 configured to output a gate-on voltage and/or a gate-off voltage, and a gate driving circuit 400.
The display device further includes a source driving circuit 600, the timing controller 200 is respectively connected to the gate driving circuit 400, the source driving circuit 600 and the driving power source 300, and the timing controller 200 is configured to receive the data signal, the control signal and the clock signal output by the external circuit module, and convert the data signal, the control signal and the clock signal into the data signal, the control signal and the clock signal suitable for the gate driving circuit 400 and the source driving circuit 600, thereby implementing image display of the liquid crystal panel. The signal format input by the timing controller 200 generally includes transistor-transistor logic signal TTL, Low Voltage Differential Signaling (LVDS), embedded display signal (eDP) and V-by-One signals. The control signals output from the timing controller 200 include a gate control signal and a source control signal, and the source driving signal includes a Start Horizontal (STH) signal, a Clock Pulse (CPH) signal, a data output signal (TP), and a data polarity inversion signal (MPOL or POL). The gate driving signals include a frame Start Signal (STV), a scan Clock signal (CPV), and an Enable signal (OE).
The driving power supply 300 integrates a plurality of dc-dc conversion circuits having different circuit functions, each of which outputs a different voltage value. The input terminal of the driving power supply 300 generally inputs a voltage of 5V or 12V, and the output voltage includes an operating voltage DVDD supplied to the timing controller 200, and a gate-on voltage VGH and a gate-off voltage supplied to the gate driving circuit 400.
The display area is composed of a plurality of pixels, and each pixel is composed of three sub-pixels of red, green and blue. Each sub-pixel is composed of a thin film transistor and a capacitor. The thin film transistors and the capacitors of the plurality of odd-numbered rows and the plurality of even-numbered rows may constitute the display panel 100. Wherein the plurality of thin film transistors constitute a switch array.
Referring to fig. 3 and 4, fig. 3 and 4 show two embodiments of the display panel 100, in the display panel 100, as shown in fig. 3, the thin film transistors in odd columns in each row are respectively electrically connected to the scan lines in even rows, the thin film transistors in even columns in each row are respectively connected to the electrical connection terminals of the scan lines in odd rows, and adjacent thin film transistors in odd columns and thin film transistors in even columns are electrically connected to the same data line. Or, as shown in fig. 4, the thin film transistors in the odd columns in each row are respectively electrically connected to the scan lines in the odd rows, the thin film transistors in the even columns in each row are respectively connected to the electrical connection ends of the scan lines in the even rows, and the adjacent thin film transistors in the odd columns and the thin film transistors in the even columns are electrically connected to the same data line.
It should be noted that, depending on the number of rows turned on at a certain time and the input of corresponding pixel signals, the pixel driving structure can be divided into a 1G1D structure in which only one row is turned on at a certain time, a 2G2D structure in which two rows are simultaneously turned on at a certain time, and a Dual-gate pixel driving structure (Dual-gate), the present embodiment is preferably implemented using the Dual-gate pixel structure, since the number of the scan lines in the display panel 100 is doubled and the number of the data lines in the display panel 100 is doubled, the number of the integrated chips in the gate driving circuit 400 is doubled, and the number of the integrated chips in the source driving circuit 600 is reduced by half, since the fabrication cost of the integrated chip in the source driver circuit 600 is much higher than that of the integrated chip in the gate driver circuit, therefore, the Dual-gate driving structure can effectively reduce the production cost of the display device.
Compared to the 1G1D structure, the Dual-gate pixel driving structure (Dual-gate) has a row writing time reduced to half of the original row writing time, and in the design of the liquid crystal display panel, the important factor of the pixel driving structure is to ensure that the pixel has a sufficient pixel charging rate, and the reduction of the row writing time affects the reduction of the pixel charging rate, so as to ensure that the pixel charging rate is high and the image quality of the panel is good, the display panel is usually configured with a 1+2line or 2line inversion method to drive the polarity inversion of the capacitor in the pixel array.
When the display panel 100 adopts a 2-line or 1+ 2-line polarity inversion method to drive the polarity inversion of the capacitor in the pixel array, the ac driving of the liquid crystal molecules is realized in a manner that the potential of the common electrode is kept unchanged, which is equivalent to the change of the potential of the other electrode of the capacitor from high to low relative to the potential of the common electrode. That is, the data signal output from the source driving circuit 600 increases or decreases with respect to the common electrode voltage. In the process that the voltage of the data signal is increased relative to the voltage of the common electrode and is switched from the voltage of the negative polarity to the voltage of the positive polarity, or is reduced to realize the switching from the voltage of the positive polarity to the negative polarity, the voltage across the voltage of the data signal is large, and due to RC load, the voltage switching needs climbing time. Therefore, in the case of a certain charging time, the charging saturation degree of the sub-pixel which needs to undergo voltage switching, i.e. the ramp-up time, is lower than that of the sub-pixel whose voltage tends to be stable, and the brightness of the pixel which is charged to saturation is larger than that of the pixel which is not fully charged to saturation. For example, in the display panel 100 of the present embodiment, the adjacent odd-numbered columns of tfts and the adjacent even-numbered columns of tfts are electrically connected to the same data line, and the gates of the adjacent odd-numbered columns of tfts and the adjacent even-numbered columns of tfts are controlled by the two adjacent scan lines respectively. For example, a sub-pixel located in a first row and a first column and a sub-pixel located in a first row and a second column. The gate of the sub-pixel in the first row and the first column is connected to the scan line G1, the source is connected to the data line D1, the gate of the sub-pixel in the first row and the second column is connected to the scan line G2, and the source is connected to the data line D1. When the two adjacent sub-pixels adopt a 2Line Inversion (2 rows of pixel row Line signal Inversion) method to perform polarity Inversion, the polarities of the two adjacent sub-pixels are consistent, or when the polarity Inversion adopts a l +2Line Inversion (1+2 rows of pixel row Line signal Inversion), the first row of the scanning Line is single polarity, and the polarities of the two adjacent sub-pixels in the rest scanning lines are the same. The present embodiment will be described by taking a 2-Line Inversion (2-column pixel and row Line signal Inversion) method as an example. When the gate driving circuit 400 performs progressive scanning, scanning lines of G1 lines are firstly opened, and scanning lines of G2 lines are then opened; in the l +2Line Inversion (1+2 row pixel row Line signal Inversion), the scanning Line of the G2 row is turned on first, and the scanning Line of the G3 row is turned on later), the polarity of the color sub-pixels in the first row and the first column is inverted from positive to negative, during the charging process of the color sub-pixels in the first row and the first column, the data voltage on the data Line D1 is gradually reduced from high level to low level, i.e., the positive is switched to negative and kept at low level, at this time, the voltage of the data signal is larger, and when the charging of the color sub-pixels in the first row and the first column is completed, the charging is not saturated. After the charging of the color sub-pixels in the first row and the first column is completed, the scanning line in the G1 row is turned off, the scanning line in the G2 row is turned on, so as to charge the sub-pixels in the first row and the second column, and during the charging of the sub-pixels in the first row and the second column, the data voltage on the data line D1 is kept at a low level, which is equivalent to that the negative pole is switched to the negative pole, at this time, the voltage step of the data signal is small or no step, so that the saturation degree is high when the charging of the blue sub-pixel is completed. This results in the luminance of the color sub-pixels in the first row and the second column being higher than the luminance of the color sub-pixels in the first row and the first column, and so on, and the problem of bright/dark lines appears on the whole liquid crystal panel.
To solve the above problem, referring to fig. 1 and 2, in an embodiment of the present invention, a driving circuit of a display panel includes:
a timing controller 200 configured to output a timing control signal;
a driving power supply 300 configured to output a gate-on voltage and/or a gate-off voltage;
a gate driving circuit 400 configured to receive a gate turn-on voltage of the driving power source 300 to drive the sub-pixels in the corresponding row;
a chamfering circuit 500 configured to generate a first chamfering control signal and a second chamfering control signal upon receiving the timing control signal;
the driving power supply 300 is further configured to perform chamfering on the gate-on voltage output to the gate driving circuit 400 when receiving the first chamfering control signal, where the chamfering time is a first preset time, so as to control a capacitor charging voltage of a previous row of sub-pixels in two adjacent rows to be a first preset voltage; and
when receiving the second chamfering control signal, the driving power supply 300 performs chamfering on the gate-on voltage output to the gate driving circuit 400, where the chamfering time is a second preset time, and controls the capacitor charging voltage of the sub-pixels in the next row of the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time.
In this embodiment, the driving circuit of the display panel further includes a source driving circuit 600.
In this embodiment, the timing signal input terminal of the chamfering circuit 500 is connected to the timing controller 200, and the control terminal of the chamfering circuit 500 is connected to the input terminal of the driving power supply 300; the output terminal of the driving power source 300 is connected to the gate driving circuit 400, and the control terminal of the timing controller 200 is connected to the controlled terminal of the gate driving circuit 400. The odd-numbered rows are G1, G3 and G5 … G2n + 1, and the even-numbered rows are G2, G4 and G6 … G2n + 2. The gate driving circuit 400 drives the corresponding thin film transistors in the G1 row to the G2n +2 row by row through the scan lines when the driving power supply 300 outputs the gate-on voltage VGH based on the control of the frame Start Signal (STV), the scan Clock signal (CPV), and the Enable signal (OE) Output by the timing controller 200, and realizes that the data signal of the on row is input to the corresponding pixel under the action of the control signal Output by the timing controller 200, and the corresponding thin film transistors in the driving pixel array 110 are turned off when the driving power supply 300 outputs the off voltage. When the gate driving circuit 400 drives the pixel array 110 to be turned on row by row once, all the column data signal lines transmit data signals to the sub-pixels in the row to charge the sub-pixel capacitors, so that the signal voltage of the pixel is written and maintained, and the liquid crystal molecules in the sub-pixel region rotate under the voltage, so that the transmittance of incident light passing through the liquid crystal molecules is changed, that is, the light valve effect on the incident light is realized.
In this embodiment, the timing control signal output from the timing controller 200 to the chamfering circuit 500 is a continuous pulse signal, that is, each time a timing control signal is output, the timing control signal controls one row of sub-pixels to be turned on and charged, and at the same time, the chamfering circuit 500 is controlled to generate a chamfering control signal, in the Dual-gate driving structure (Dual-gate), the polarities of two adjacent rows are the same, for example, in 2line polarity inversion, the polarities of the sub-pixels corresponding to the scanning rows G1 and G2 are the same, the polarities of the sub-pixels corresponding to the scanning rows G3 and G4 are the same, the polarities of the sub-pixels corresponding to the scanning rows G5 and G6 are the same, and the polarities of the sub-pixels corresponding to the scanning rows G3 and G4 are opposite to the polarities of the sub-pixels corresponding to the scanning rows G1 and G2 and the sub-pixels corresponding to the scanning rows G5 and G6. Therefore, the sub-pixels corresponding to each row of the display panel 100 can be analogized according to the above rule, and are not listed here. In the 2-line polarity inversion, the odd-numbered lines such as G1, G3, and G5 … G2n +1 (in the 1+ 2-line polarity inversion, the second line G2 is started, that is, G2 and G4 … G2n +2) need to undergo the climbing time, and the adjacent even-numbered lines such as G2 and G4 … G2n +2 need not to undergo the climbing. Therefore, in this embodiment, the chamfering circuit 500 can output two chamfering control signals, i.e. a first chamfering control signal and a second chamfering control signal, according to the timing control signal output by the timing controller 200, wherein the first chamfering control signal performs chamfering on the odd rows corresponding to the turning-on of the odd rows G1, G3, G5 … G2n + 1, and the second chamfering control signal performs chamfering on the even rows corresponding to the turning-on of the even rows G2, G4 … G2n + 2.
The chamfering circuit 500 generates a first chamfering control signal and a second chamfering control signal when receiving the timing control signal output by the timing controller 200; so as to output the first or second chamfering control signal when the driving power supply 300 outputs the gate-on voltage to the gate driving circuit 400. Specifically, when the driving power supply 300 drives the gate driving circuit 400 to control the previous row of sub-pixels in two adjacent rows to be turned on (in 2-line polarity inversion, odd rows such as G1, G3, G5 … G2n + 1, and even rows such as G2, G4, G6 … G2n in 1+ 2-line polarity inversion), a first chamfering control signal is output so that the time of the gate-on voltage output by the driving power supply 300 is a first preset time, the gate driving circuit 400 performs chamfering voltage reduction according to the first preset time and the gate-on voltage, and controls the capacitor charging voltage of the sub-pixels to be a first preset voltage; when the driving power supply 300 drives the gate driving circuit 400 to control the sub-pixels in the next row in the two adjacent rows (in 2line polarity inversion, even rows such as G2, G4, G6 … G2n + 2, and odd rows such as G3, G5, G7 … G2n +1 in 1+2line polarity inversion) to be turned on, a second chamfering control signal is output to make the time of the gate-on voltage output by the driving power supply 300 be a second preset time, the gate driving circuit 400 performs chamfering and voltage reduction according to the second preset time and the gate-on voltage VGH, and controls the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage. In the process, the chamfering time of the sub-pixels in the previous row in the two adjacent rows is shorter than that of the sub-pixels in the next row, so that the voltage area of the row opening of the sub-pixels in the previous row is ensured to be larger than that of the sub-pixels in the next row, that is, the charging efficiency of the odd rows is improved, and the charging time lost due to voltage switching and climbing is compensated.
The driving circuit of the display panel of the present invention outputs the timing control signal through the timing controller 200, so that the chamfering circuit 500 receives the timing control signal, and the driving power supply 300 outputs the gate-on voltage, so as to drive the gate driving circuit 400 to drive the corresponding row sub-pixels to operate according to the gate-on voltage of the driving power supply 300. Therefore, in the process that the gate driving circuit 400 outputs corresponding row scanning signals to the thin film transistors through the row scanning lines to sequentially start the sub-pixels on the previous row of the adjacent two rows line by line from the first row scanning line to the last row scanning line of the scanning lines, when the sub-pixels on the previous row of the adjacent two rows are charged, the chamfering time of the gate start voltage by the chamfering circuit 500 is a first preset time, so as to control the capacitor charging voltage of the sub-pixels on the previous row of the adjacent two rows to be a first preset voltage; when the sub-pixels in the next row in the two adjacent rows are charged, the chamfering time of the gate turn-on voltage by the chamfering circuit 500 is a second preset time so as to control the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time. Therefore, the chamfering time of the scanning line in the previous row in the two adjacent rows is controlled and adjusted to be smaller than the chamfering time of the scanning line in the next row in the two adjacent rows. And further, the chamfering slope of the waveform of the row driving voltage output by the scanning line of the previous row in each two adjacent rows is smaller than that of the waveform of the row driving voltage output by the scanning line of the adjacent row, so that the opening area of the thin film transistor of the previous row in the two adjacent rows is larger than that of the thin film transistor adjacent to the previous row, that is, the charging efficiency of the sub-pixel corresponding to the scanning line of the previous row in the two adjacent rows is improved, and the time lost due to voltage switching and climbing is compensated. Therefore, the charging saturation degree of the sub-pixels corresponding to the scanning line of the previous row in the two adjacent rows is consistent with the charging saturation degree of the sub-pixels corresponding to the scanning line of the even row. By the arrangement, when the voltage of the data signal is switched from the positive polarity to the negative polarity or from the negative polarity to the positive polarity, the same charging effect and consistent brightness of each sub-pixel are ensured. The invention solves the problem that when the polarity of the data signal voltage is reversed, because the voltage across the data signal voltage is larger, the charging saturation degree of two adjacent sub-pixels sharing one data line is different, and a low gray scale bright and dark line appears, and improves the picture quality of the display device.
It can be understood that, when the polarity Inversion is performed in the l +2Line Inversion (1+2 rows of pixel row Line signal Inversion), and the gate driving circuit 400 outputs corresponding row scanning signals to the pixel array 110 through the row scanning lines for scanning, the second row of the scanning lines is referred to as a previous row scanning Line in two adjacent rows (or referred to as an odd row), the third row is referred to as a next row in two adjacent rows (or referred to as an even row), and so on until the last row of the display panel 100 is scanned, the chamfering process is the same as the polarity Inversion performed in the 2Line Inversion (2 rows of pixel row Line signal Inversion), and details thereof are not repeated here.
Referring to fig. 1 and fig. 2, in an embodiment, the chamfering circuit 500 includes a signal triggering circuit 510 and a switch control circuit 520, a controlled end of the signal triggering circuit 510 is connected to the timing controller 200, an output end of the signal triggering circuit 510 is connected to the switch control circuit 520, a first input end of the first switch control circuit 520 is connected to a first chamfering control signal, and a second input end of the first switch control circuit 520 is connected to a second chamfering control signal; the output end of the switch control circuit 520 is connected with the driving power supply 300;
the signal trigger circuit 510 is configured to generate and output a trigger signal of a high/low level according to the timing control signal;
the switch control circuit 520 is configured to control a time when the driving power supply 300 outputs the gate-on voltage to the gate driving circuit 400 to be a first preset time according to the high-level trigger signal;
according to the low-level trigger signal, controlling the time of the gate-on voltage output from the driving power supply 300 to the gate driving circuit 400 to be a second preset time.
In this embodiment, the driving power supply 300 may be implemented by a power management integrated circuit, the output terminal of the switch control circuit 520 and the chamfered time setting pin of the power management integrated circuit are connected to the timing control signal output by the timing controller 200 and are continuous pulse signals, and the signal triggering circuit 510 receives the timing control signal output by the timing controller 200 and triggers at the rising edge of the timing control signal, thereby generating a triggering signal with alternating high/low levels. The switch control circuit 520 receives the low-level trigger signal, switches in the first chamfering control signal and outputs the first chamfering control signal, and receives the high-level trigger signal, switches in the second chamfering control signal and outputs the second chamfering control signal. When receiving the timing signal output from the timing controller 200, the driving power supply 300 outputs a gate-on voltage to the gate driving circuit 400 to drive the gate driving circuit 400 to turn on row by row and charge the turned-on sub-pixels. When the first chamfering control signal is received, chamfering is carried out on the output grid opening voltage, and the chamfering time is first preset time. And when the second chamfering control signal is received, chamfering is started to be carried out on the output gate driving voltage, and the chamfering time is a second preset time. The first preset time is less than the second preset time, so that the area of the grid opening voltage of the front row of sub-pixels in the two adjacent rows of sub-pixels is larger than the area of the grid opening voltage of the back row of sub-pixels. In this embodiment, the first chamfering control signal and the second timing control signal may be output by the timing controller 200, or provided by the chamfering control circuit module, which is not limited herein.
Referring to fig. 1 and 2, in an embodiment, the signal triggering circuit 510 includes a flip-flop D1 and an inverter D2, a clock signal input terminal of the flip-flop D1 is connected to the timing controller 200, and a triggering signal input terminal of the flip-flop D1 is interconnected with the switch control circuit 520 and an output terminal of the inverter D2; the output terminal of the flip-flop D1 is connected to the output terminal of the inverter D2.
In this embodiment, the flip-flop D1 may be implemented by a rising edge D-flip-flop D1, the flip-flop D1 assigns the value of the trigger signal input terminal D to the output terminal Q when the clock signal input terminal C receives a rising edge of the timing control signal, and the inverter D2 inverts the trigger signal output from the output terminal Q and outputs the inverted trigger signal to the switch control circuit 520. In the present embodiment, when the display device is in an initial state, the level of the trigger signal input end D is a high level, when the trigger D1 is on a rising edge of the timing control signal, the trigger signal input end D assigns a high level trigger signal to the output end, the low level trigger signal is output to the switch control circuit 520 after inversion by the inverter D2, and the input end of the trigger signal input end D is connected to the inverter D2, that is, the inverter D2 outputs a low level trigger signal to the trigger signal input end, when the rising edge of the next clock signal comes, the trigger signal input end assigns a low level trigger signal to the output end, and the low level trigger signal is output to the switch control circuit 520 after inversion by the inverter D2, so that the output of the trigger signal with alternating high and low levels is realized.
Referring to fig. 1 and 2, in an embodiment, the switch control circuit 520 includes a first switch transistor M1 and a second switch transistor M2, controlled terminals of the first switch transistor M1 and the second switch transistor M2 are interconnected with an output terminal of the signal trigger circuit 510, an input terminal of the first switch transistor M1 is a first input terminal of the switch control circuit 520, and an input terminal of the second switch transistor M2 is a second input terminal of the switch control circuit 520; the output end of the first switch tube M1 and the output end of the second switch tube M2 are respectively connected to the driving power supply 300.
In this embodiment, the trigger signals of the first switch transistor M1 and the second switch transistor M2 are opposite control signals, that is, at a low level, the first switch transistor M1 is turned on, the second switch transistor M2 is turned off, and at a high level, the first switch transistor M1 is turned off, and the second switch transistor M2 is turned on, so as to gate different switch paths. The first switch tube M1 and the second switch tube M2 may be implemented by switching tubes such as a triode, a MOS tube, and the like. The first switch tube M1 can be implemented by an N-MOS transistor, and the second switch tube M2 can be implemented by a P-MOS transistor. Of course, the first switch tube M1 and the second switch tube M2 may be implemented by using analog switches, and one input interface and two output interfaces of the analog switches are used to gate different switch paths.
In the above embodiment, the output waveforms of the first input terminal a, the second input terminal B, the output terminal C, the clock signal input terminal CLK and the scan signal Gate of the chamfering circuit 500 can be referred to fig. 5. In this embodiment, the signal input by the first input terminal a of the chamfering circuit 500 is a, the signal input by the second input terminal B is B, and the signal output by the output terminal C is either a signal a or a signal B. When the display device works, the trigger signals of the controlled terminal of the first switching tube M1 and the controlled terminal of the second switching tube M2 are L, that is, in an initial state, the first switching tube M1 is turned on, the second switching tube M2 is turned off, and at this time, the output end signal C of the chamfering circuit 500 is equal to a; when the first rising edge of the timing control signal CLK arrives, the flip-flop D1 assigns the value of L of the trigger signal input D to the output terminal Q, and after the inversion of the inverter D2, the trigger signals of the first switch tube M1 and the second switch tube M2 become H, the second switch tube M2 is turned on, the first switch tube M1 is turned off, and at this time, the chamfering control signal C output by the output terminal of the chamfering circuit 500 is equal to B; in the same way, when the second rising edge of CLK arrives, the output end of the chamfering circuit 500 outputs the chamfering control signal C ═ a. In this embodiment, the first and second chamfering control signals output by the output terminal C of the chamfering circuit 500 control the start and end times of chamfering, and when C is H, the VGH voltage starts chamfering; and when C is L, the angle cutting of the VGH voltage is stopped. By such arrangement, the chamfering slope of the previous row is smaller than that of the next row, so that the opening area of the previous row is larger than that of the G2n +2 row, namely, the charging efficiency of the previous row is improved, the time lost due to climbing due to voltage switching is compensated, and the charging saturation degree of the previous row is consistent with that of the next row. Finally, the charging saturation degree of the sub-pixels corresponding to the scanning lines in the previous line such as G1, G3, G5 …, G2n +1 and the like in the 2line inversion mode is the same as that of the sub-pixels corresponding to the scanning lines in the next line such as G2, G4, G6 …, G2n +2 and the like in the 2line inversion mode (in the 1+2line inversion mode, the charging saturation degree of the sub-pixels corresponding to the scanning lines in the previous line such as G2, G4, G6 …, G2n and the sub-pixels corresponding to the scanning lines in the next line such as G3, G5 …, G2n +1 and the like are the same). Therefore, the brightness of each sub-pixel on the whole display panel 100 of the display device is consistent, so as to solve the problem that bright/dark lines occur among the sub-pixels due to different charging saturation degrees.
Referring to fig. 1 and 2, in an embodiment, the switch control circuit 520 further includes a first resistor R1, one end of the first resistor R1 is interconnected with the controlled ends of the first switching tube M1 and the second switching tube M2, and the other end of the first resistor R1 is grounded.
In this embodiment, the first resistor R1 is a pull-down resistor, and is configured to ensure that, in an initial state of the display device, the trigger signals received by the controlled terminals of the first switch tube M1 and the second switch tube M2 are at a low level L, so as to ensure that the first chamfering control signal connected to the first switch tube M1 is output by the output terminal C of the chamfering circuit 500, and the first resistor R1 is also a current-limiting resistor, so as to prevent the trigger D1 from being damaged due to an excessively high voltage output to the trigger signal input terminal of the trigger D1.
Referring to fig. 3, in an embodiment, the display panel 100 includes a pixel array 110; the driving circuit of the display panel further includes a plurality of data lines and a plurality of scan lines electrically connected to the gate driving circuit 400, the pixel array 110 includes a plurality of thin film transistors, the thin film transistors in odd columns in each row are respectively electrically connected to the scan lines in odd rows, the thin film transistors in even columns in each row are respectively connected to the electrical connection terminals of the scan lines in even rows, and adjacent thin film transistors in odd columns and thin film transistors in even columns are electrically connected to the same data line.
Referring to fig. 4, in an embodiment, the display panel 100 includes a pixel array 110B; the driving circuit of the display panel further includes a plurality of data lines and a plurality of scan lines electrically connected to the gate driving circuit 400, the pixel array 110 includes a plurality of thin film transistors, the thin film transistors in odd columns in each row are respectively electrically connected to the scan lines in even rows, the thin film transistors in even columns in each row are respectively connected to the electrical connection terminals of the scan lines in odd rows, and adjacent thin film transistors in odd columns and thin film transistors in even columns are electrically connected to the same data line.
In this embodiment, the pixel array 110 of the display panel 100 is composed of a plurality of sub-pixels, and three sub-pixels (red, green, and blue) constitute one pixel, for example, when the sub-pixels in the same horizontal row are distributed on the display panel 100, the on-time of each sub-pixel is the same, each sub-pixel includes a thin film transistor and a capacitor, the gate of the thin film transistor is connected to the gate driver through the scan line, the source of the thin film transistor is connected to the source driving circuit 600 through the data line, and the drain of the thin film transistor is connected to one end of the capacitor.
Referring to fig. 1, in some embodiments, the display device is further provided with a source driving circuit 600, the source driving circuit 600 is provided as the source driving circuit 600 that inputs a data signal, the source driving circuit 600 is connected to the timing controller 200, a plurality of output terminals of the source driving circuit 600 are respectively connected to corresponding data lines of the pixel array 110, the timing controller 200 receives signals of an external circuit, such as a data signal, a control signal, and a clock signal output by a control system SOC of the television, and converts the signals into the data signal, the control signal, and the clock signal suitable for each array substrate row driving circuit 100 and the source driving circuit 600, and the source driving circuit 600 outputs the data signal to the corresponding pixels through the data lines, thereby implementing image display of the display panel 100.
The invention also provides a display device.
Referring to fig. 1, the display device includes the driving circuit of the display panel as described above; the driving circuit of the display panel includes:
a timing controller 200 configured to output a timing control signal;
a driving power supply 300 configured to output a gate-on voltage and/or a gate-off voltage;
a gate driving circuit 400 configured to receive a gate turn-on voltage of the driving power source 300 to drive the sub-pixels in the corresponding row;
the chamfering circuit 500 is configured to control the time of the gate turn-on voltage output from the driving power supply 300 to the gate driving circuit 400 to be a first preset time when the timing control signal is received, so as to control the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows to be a first preset voltage; and
controlling the time of the gate-on voltage output from the driving power supply 300 to the gate driving circuit 400 to be a second preset time, so as to control the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time.
It can be understood that, because the display device of the present invention uses the driving circuit of the display panel, the embodiment of the display device of the present invention includes all the technical solutions of all the embodiments of the driving circuit of the display panel, and the achieved technical effects are also completely the same, and are not described herein again.
The invention also provides a driving method of the display panel.
Referring to fig. 6, the display panel includes a plurality of sub-pixels, and the driving method of the display panel includes:
step S10, when the display panel works, the time sequence controller outputs a time sequence control signal;
step S20, when the driving power supply receives the first chamfering control signal, chamfering the grid opening voltage for a first preset time to control the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows to be a first preset voltage; and
step S30, when a second chamfering control signal is received, chamfering the gate-on voltage for a second preset time, where the first preset time is less than the second preset time.
It is understood that step S30 may be performed before step S20 is performed, and those skilled in the art may set the charging saturation level of the pixel capacitors in two adjacent rows according to the chamfering circuit and the polarity inversion type used, so as to achieve the consistent charging saturation level when the pixel capacitors are charged, and this is not limited herein.
The chamfering and voltage reducing of the gate turn-on voltage output to the gate driving circuit specifically comprises:
the invention outputs the time sequence control signal through the time sequence controller, so that the chamfering circuit receives the time sequence control signal, and the driving power supply outputs the grid opening voltage, so that the grid driving circuit drives the sub-pixels of the corresponding row to work according to the grid opening voltage of the driving power supply. Therefore, in the process that the gate drive circuit outputs corresponding row scanning signals to the thin film transistor through the row scanning lines to sequentially start the sub-pixels of the front row of the adjacent two rows line by line from the first row scanning line to the last row scanning line of the scanning lines, when the sub-pixels of the front row of the adjacent two rows are charged, the chamfering time of the gate start voltage by the chamfering circuit is first preset time so as to control the capacitor charging voltage of the sub-pixels of the front row of the adjacent two rows to be first preset voltage; when the sub-pixels in the next row in the two adjacent rows are charged, the chamfering time of the gate turn-on voltage by the chamfering circuit is second preset time so as to control the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time. Therefore, the chamfering time of the scanning line in the previous row in the two adjacent rows is controlled and adjusted to be smaller than the chamfering time of the scanning line in the next row in the two adjacent rows. And further, the chamfering slope of the waveform of the row driving voltage output by the scanning line of the previous row in each two adjacent rows is smaller than that of the waveform of the row driving voltage output by the scanning line of the adjacent row, so that the opening area of the thin film transistor of the previous row in the two adjacent rows is larger than that of the thin film transistor adjacent to the previous row, that is, the charging efficiency of the sub-pixel corresponding to the scanning line of the previous row in the two adjacent rows is improved, and the time lost due to voltage switching and climbing is compensated. Therefore, the charging saturation degree of the sub-pixels corresponding to the scanning line of the previous row in the two adjacent rows is consistent with the charging saturation degree of the sub-pixels corresponding to the scanning line of the even row. By the arrangement, when the voltage of the data signal is switched from the positive polarity to the negative polarity or from the negative polarity to the positive polarity, the charging effect of each sub-pixel is ensured to be the same, and the brightness is consistent. The invention solves the problem that when the polarity of the data signal voltage is reversed, because the voltage across the data signal voltage is larger, the charging saturation degree of two adjacent sub-pixels sharing one data line is different, and a low gray scale bright and dark line appears, and the invention improves the picture quality of the display device.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A driving circuit of a display panel, the display panel having a plurality of sub-pixels; the drive circuit of the display panel is characterized by comprising:
a timing controller configured to output a timing control signal and a data signal;
a driving power supply configured to output a gate-on voltage and/or a gate-off voltage;
the grid driving circuit is used for receiving the grid starting voltage of the driving power supply and driving the sub-pixels in the corresponding row;
the chamfering circuit is arranged for generating a first chamfering control signal and a second chamfering control signal when receiving the time sequence control signal;
the chamfering circuit comprises a signal trigger circuit and a switch control circuit, wherein a controlled end of the signal trigger circuit is connected with the time schedule controller, an output end of the signal trigger circuit is connected with the switch control circuit, a first input end of the switch control circuit is accessed to a first chamfering control signal, and a second input end of the switch control circuit is accessed to a second chamfering control signal;
the signal trigger circuit is configured to generate and output a trigger signal of a high/low level according to the timing control signal;
when receiving a low-level trigger signal, the switch control circuit accesses a first chamfering control signal and outputs the first chamfering control signal so as to enable the time of the grid starting voltage output by the driving power supply to be first preset time;
when receiving a high-level trigger signal, the switch control circuit accesses a second chamfering control signal and outputs the second chamfering control signal so as to enable the time of the grid starting voltage of the driving power supply to be second preset time;
the output end of the switch control circuit is connected with the driving power supply;
the driving power supply is further configured to perform chamfering on the gate start voltage output to the gate driving circuit when the first chamfering control signal is received, wherein the chamfering time is a first preset time, so that the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows is controlled to be a first preset voltage; and
when the driving power supply receives the second chamfering control signal, chamfering is carried out on the grid starting voltage output to the grid driving circuit, the chamfering time is second preset time, so that the capacitor charging voltage of the sub-pixels in the next row in two adjacent rows is controlled to be equal to the first preset voltage, and the first preset time is shorter than the second preset time;
and the source electrode driving circuit is arranged to receive the data signals output by the time sequence controller and output the data signals to the corresponding column sub-pixels.
2. The driving circuit of the display panel according to claim 1, wherein the signal trigger circuit comprises a flip-flop and an inverter, a clock signal input terminal of the flip-flop is connected to the timing controller, and a trigger signal input terminal of the flip-flop is interconnected with the switch control circuit and an output terminal of the inverter; and the output end of the trigger is connected with the output end of the phase inverter.
3. The driving circuit of the display panel according to claim 1, wherein the switch control circuit comprises a first switch tube and a second switch tube, controlled terminals of the first switch tube and the second switch tube are interconnected with an output terminal of the signal trigger circuit, an input terminal of the first switch tube is a first input terminal of the switch control circuit, and an input terminal of the second switch tube is a second input terminal of the switch control circuit; the output end of the first switch tube and the output end of the second switch tube are respectively connected with the driving power supply.
4. The driving circuit of a display panel according to claim 3, wherein the switch control circuit further comprises a first resistor, one end of the first resistor is interconnected with the controlled ends of the first and second switching tubes, and the other end of the first resistor is grounded.
5. The drive circuit of the display panel according to claim 1, wherein the display panel includes a switch array; the drive circuit of the display panel further comprises a plurality of data lines and a plurality of scanning lines electrically connected with the gate drive circuit, the switch array comprises a plurality of thin film transistors, the thin film transistors in odd columns in each row are respectively and electrically connected with the scanning lines in odd rows, the thin film transistors in even columns in each row are respectively and electrically connected with the electric connection ends of the scanning lines in even rows, and the adjacent thin film transistors in odd columns and the thin film transistors in even columns are electrically connected with the same data line.
6. The drive circuit of the display panel according to claim 1, wherein the display panel includes a switch array; the drive circuit of the display panel further comprises a plurality of data lines and a plurality of scanning lines electrically connected with the gate drive circuit, the switch array comprises a plurality of thin film transistors, the thin film transistors in odd columns in all rows are respectively and electrically connected with the scanning lines in even rows, the thin film transistors in even columns in all rows are respectively and electrically connected with the electric connection ends of the scanning lines in odd rows, and the adjacent thin film transistors in odd columns and the thin film transistors in even columns are electrically connected with the same data line.
7. The driving circuit of the display panel according to claim 5 or 6, wherein the polarity inversion of the switch array is 1+2 rows of pixel row line signal inversion;
or, the polarity inversion mode of the switch array is 2 rows of pixel row line signal inversion.
8. A display device comprises a display panel with a plurality of sub-pixels, a time schedule controller and a driving power supply, wherein the time schedule controller is set to output a sequence control signal; characterized in that the display device further comprises a drive circuit of the display panel according to any one of claims 1 to 7; the driving circuit of the display panel includes:
a timing controller configured to output a timing control signal;
a driving power supply configured to output a gate-on voltage and/or a gate-off voltage;
the grid driving circuit is used for receiving the grid starting voltage of the driving power supply and driving the sub-pixels in the corresponding row;
the corner cutting circuit is arranged to control the time of the grid starting voltage output by the driving power supply to the grid driving circuit to be a first preset time when the timing sequence control signal is received so as to control the capacitor charging voltage of the sub-pixels in the previous row in the two adjacent rows to be a first preset voltage; and
controlling the time of the grid starting voltage output by the driving power supply to the grid driving circuit to be second preset time so as to control the capacitor charging voltage of the sub-pixels in the next row in the two adjacent rows to be equal to the first preset voltage; the first preset time is less than the second preset time.
9. A driving method of a display panel, the display panel including a plurality of sub-pixels, the driving method comprising:
when the display panel works, the time sequence controller outputs a time sequence control signal;
when receiving a first chamfering control signal, the driving power supply performs chamfering on the grid opening voltage for a first preset time so as to control the capacitor charging voltage of the sub-pixels in the previous row in two adjacent rows to be a first preset voltage; and
when a second chamfering control signal is received, chamfering the grid starting voltage for a second preset time, wherein the first preset time is less than the second preset time;
the first chamfering control signal and the second chamfering control signal are both configured to be generated by a chamfering circuit when the timing control signal is received;
the chamfering circuit comprises a signal trigger circuit and a switch control circuit, wherein a controlled end of the signal trigger circuit is connected with the time schedule controller, an output end of the signal trigger circuit is connected with the switch control circuit, a first input end of the switch control circuit is accessed to a first chamfering control signal, and a second input end of the switch control circuit is accessed to a second chamfering control signal;
the signal trigger circuit is configured to generate and output a high/low level trigger signal according to the timing control signal, so that the time of the gate-on voltage output by the driving power supply is a first preset time;
the switch control circuit is connected to the first chamfering control signal and outputs the first chamfering control signal when receiving a low-level trigger signal; when receiving a high-level trigger signal, the switch control circuit accesses a second chamfering control signal and outputs the second chamfering control signal so as to enable the time of the grid starting voltage of the driving power supply to be second preset time;
the output end of the switch control circuit is configured to be connected with the driving power supply.
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| CN110660444B (en) * | 2019-09-30 | 2022-01-07 | 合肥京东方卓印科技有限公司 | Display device, grid drive circuit, shift register circuit and drive method thereof |
| CN110767194A (en) * | 2019-11-11 | 2020-02-07 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display panel |
| KR20210082904A (en) * | 2019-12-26 | 2021-07-06 | 엘지디스플레이 주식회사 | Gate driving circuit and display device using the same |
| CN113851067B (en) * | 2020-06-28 | 2023-07-04 | 京东方科技集团股份有限公司 | Charging circuit, display device, wearable equipment and display driving method and device |
| CN112994436B (en) * | 2021-02-04 | 2022-06-03 | 重庆先进光电显示技术研究院 | Grid opening voltage generation circuit, display panel driving device and display device |
| CN113570995B (en) * | 2021-07-30 | 2023-11-24 | 北京京东方显示技术有限公司 | Signal timing control method, gate driving circuit and display panel |
| CN113744698B (en) | 2021-07-30 | 2023-03-17 | 北海惠科光电技术有限公司 | Driving method of array substrate, array substrate and display panel |
| CN114220374B (en) * | 2021-12-23 | 2024-03-26 | 绵阳惠科光电科技有限公司 | Display panel's chamfer circuit and display panel |
| CN116543723A (en) * | 2023-05-31 | 2023-08-04 | 绵阳惠科光电科技有限公司 | Driving method and driving device of display panel, display device and storage medium |
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