CN112669753B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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Abstract
The embodiment of the invention discloses a display panel, a driving method thereof and a display device, wherein each group of clock signal lines of the display panel comprises a first clock signal line and a second clock signal line; the first clock signal line is used for transmitting a first clock signal; the second clock signal line is used for transmitting a second clock signal; each switch unit of the same gating circuit is conducted in a time-sharing way; in the same gating circuit, the grid electrode of the N-type transistor of each switching unit is electrically connected with the first clock signal line of each group of clock signal lines in a one-to-one correspondence manner, and the grid electrode of the P-type transistor of each switching unit is electrically connected with the second clock signal line of each group of clock signal lines in a one-to-one correspondence manner; wherein the effective time of the effective pulse of the first clock signal and the effective pulse of the second clock signal transmitted by the same group of clock signal lines are overlapped; the transition time of at least part of pulses of the first clock signal transmitted by the same group of clock signal lines is staggered with the transition time of at least part of pulses of the second clock signal.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.
Background
At present, electromagnetic interference of a display panel is mainly generated by external radiation energy caused by high-frequency components in clock signal jump, and when the radiation energy of a plurality of clock signal jump at the same time is overlapped, larger electromagnetic interference is generated, so that normal operation of surrounding electronic elements is influenced, display effect of the display panel is influenced, and particularly when the display panel is applied to a vehicle-mounted display screen, the larger electromagnetic interference can influence normal operation of other electronic equipment in a vehicle.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention provide a display panel, a driving method thereof, and a display device, so as to weaken electromagnetic interference generated by clock signal transitions in the display panel, thereby ensuring that other electronic components and electronic devices around the display panel can normally operate.
In a first aspect, an embodiment of the present invention provides a display panel, including: a plurality of data lines, a plurality of gating circuits, a plurality of groups of clock signal lines and a plurality of data pins;
each group of the clock signal lines comprises a first clock signal line and a second clock signal line; the first clock signal line is used for transmitting a first clock signal; the second clock signal line is used for transmitting a second clock signal;
Each gating circuit comprises at least one switching unit; each switch unit of the same gating circuit is conducted in a time-sharing way; the input ends of the switch units of the same gating circuit are electrically connected with the same data pin; the output end of each switch unit is electrically connected with each data line in a one-to-one correspondence manner;
the switch unit comprises an N-type transistor and a P-type transistor; in the same gating circuit, the grid electrode of the N-type transistor of each switching unit is electrically connected with the first clock signal line of each group of clock signal lines in a one-to-one correspondence manner; in the same gating circuit, the grid electrode of the P-type transistor of each switching unit is electrically connected with the second clock signal line of each group of clock signal lines in a one-to-one correspondence manner; the first electrode of the N-type transistor and the first electrode of the P-type transistor of the same switching unit are electrically connected, and are both input ends of the switching unit; the second pole of the N-type transistor and the second pole of the P-type transistor of the same switching unit are electrically connected and are both output ends of the switching unit;
wherein the effective time of the effective pulse of the first clock signal and the effective pulse of the second clock signal transmitted by the same group of clock signal lines are overlapped; the transition time of at least part of pulses of the first clock signal transmitted by the same group of clock signal lines is staggered with the transition time of at least part of pulses of the second clock signal.
In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, for driving the display panel, where the driving method includes:
providing data signals to the data pins in a one-to-one correspondence manner, sequentially providing a first clock signal to the first clock signal lines of each group of clock signal lines, sequentially providing a second clock signal to the second clock signal lines of each group of clock signal lines, and controlling N-type transistors and P-type transistors of each switch unit of the same gating circuit to be sequentially conducted so that the data signals are transmitted to each data line through the conducted N-type transistors and/or P-type transistors;
wherein the active times of the active pulses of the first clock signal and the second clock signal provided to the same set of clock signal lines have an overlap; the transition moments of at least part of the pulses of the first clock signal and the transition moments of at least part of the pulses of the second clock signal provided to the same group of clock signal lines are staggered.
In a third aspect, an embodiment of the present invention further provides a display apparatus, including: a driving chip and the display panel;
the driving chip is used for executing the driving method of the display panel.
According to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the effective time of the effective pulse of the first clock signal for controlling the N-type transistor and the effective pulse of the second clock signal for controlling the P-type transistor in the same switch unit are overlapped, so that the N-type transistor and the P-type transistor of the same switch unit can be simultaneously conducted in the overlapped time of the effective pulse of the first clock signal and the effective pulse of the second clock signal, the current signal output by the switch unit can be increased, the loss of the data signal transmitted to each data line by the data pin is reduced, the accuracy of the data signal transmitted to each data line is improved, and the display effect of the display panel is improved; meanwhile, the jump time of at least part of pulses of the first clock signal for controlling the N-type transistor and the second clock signal for controlling the P-type transistor in the same switch unit are staggered, so that electromagnetic interference generated by simultaneous jump of the first clock signal and the second clock signal can be weakened, the phenomenon that normal operation of electronic elements in a display panel is influenced due to larger electromagnetic interference is avoided, the display effect of the display panel can be improved, and when the display panel is applied to a vehicle-mounted display screen, the influence on normal operation of other electronic equipment on a vehicle due to larger electromagnetic interference can be avoided, and the safe and stable operation of other electronic equipment on the vehicle can be ensured.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a timing diagram of a prior art gating circuit;
FIG. 3 is a timing chart of a gate circuit according to an embodiment of the present invention
FIG. 4 is a timing chart of driving a gate circuit according to another embodiment of the present invention
FIG. 5 is a timing diagram of driving a gate circuit according to another embodiment of the present invention;
FIG. 6 is a timing diagram of driving a gate circuit according to another embodiment of the present invention;
FIG. 7 is a timing diagram of driving a gate circuit according to another embodiment of the present invention;
FIG. 8 is a timing diagram of driving a gate circuit according to another embodiment of the present invention;
FIG. 9 is a timing diagram of driving a gate circuit according to another embodiment of the present invention;
FIG. 10 is a timing diagram of driving a gate circuit according to another embodiment of the present invention;
FIG. 11 is a timing diagram of driving a further gating circuit according to an embodiment of the present invention;
FIG. 12 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 13 is a schematic view of a portion of a film structure of a display panel taken along section A-A in FIG. 12;
fig. 14 is a schematic structural view of a display panel according to another embodiment of the present invention;
Fig. 15 is a driving timing diagram of a display panel according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 1, the display panel 100 may include a display region 110 and a non-display region 120 surrounding the display region 110. The display area 110 of the display panel 100 may be provided with a plurality of sub-pixels (not shown), a plurality of data lines 10, and a plurality of scan signal lines (not shown). The sub-pixels in the same column may share the data line 10, and the sub-pixels in the same row may share the scan signal line. The scanning signals transmitted through the scanning signal lines can gate the sub-pixels of the corresponding row so that the data signals transmitted by the data lines 10 can be written into the sub-pixels of the row, thereby enabling each sub-pixel to display according to the data signals transmitted by the data lines.
A plurality of gate circuits 20, a plurality of sets of clock signal lines (301 and 302), and a plurality of data pins 40 are disposed in the non-display area 120 of the display panel 100. Each group of clock signal lines 301 (302) includes a first clock signal line 311 (321) and a second clock signal line 312 (322), and the first clock signal line 311 (321) is used to transmit a first clock signal CK11 (CK 21) and the second clock signal line 312 (322) is used to transmit a second clock signal CK12 (CK 22). Each gate circuit 20 includes at least one switch unit, for example, each gate circuit 20 includes two switch units 21 and 22, input ends of the switch units (21 and 22) of the same gate circuit 20 are electrically connected with the same data pin 41, output ends of the switch units (21 and 22) are electrically connected with the data lines 10 in a one-to-one correspondence, and the switch units (21 and 22) of the same gate circuit 20 are in time-sharing conduction so as to transmit data signals received by the data pin 41 to the corresponding data line 10 in time-sharing manner and write the data signals into corresponding sub-pixels through the data lines 10, so that the sub-pixels can display according to the corresponding data signals. For example, when the data signal received by the data pin 41 is written into the sub-pixel electrically connected to the data line 10 corresponding to the switch unit 21, the switch unit 21 in the gate circuit 20 may be controlled to be turned on, so that the data signal received by the data pin 41 can be transmitted to the data line 10 electrically connected to the switch unit 21 through the turned-on switch unit 21, and written into the corresponding sub-pixel by the data line 10; when the data signal received by the data pin 41 is written into the sub-pixel electrically connected to the data line 10 corresponding to the switch unit 22, the switch unit 22 in the gating circuit 20 can be controlled to be turned on, so that the data signal received by the data pin 41 can be transmitted to the data line 10 electrically connected to the switch unit 22 through the turned-on switch unit 22, and written into the corresponding sub-pixel by the data line 10; that is, by controlling the switching units 21 and 22 in the gate circuit 20 to be turned on in a time-sharing manner, the data signals received by the data pins 41 can be written into the sub-pixels in a one-to-one correspondence. Accordingly, since each data pin 41 is respectively connected with two data lines 10 through the gating circuit 20, compared with the case that one data pin 41 corresponds to one data line 10, the number of data pins 41 is reduced; meanwhile, since the data pins in the display panel 100 are in one-to-one correspondence with the data signal output terminals in the driving chip, and the cost of the driving chip is higher as the number of the data signal output terminals in the driving chip is increased, when the data of the data pins in the display panel is reduced, the number of the data signal output terminals in the driving chip can be reduced, and the cost of the driving chip can be further reduced, namely, the cost of the display panel 100 driven by the driving chip is reduced.
It should be noted that, fig. 1 is only an exemplary drawing of an embodiment of the present invention, and fig. 1 only illustrates that each gate circuit includes two switch units; in the embodiment of the present invention, each gate circuit includes at least one switch unit, that is, each gate circuit includes one switch unit, two switch units, or a plurality of switch units, which is not particularly limited in the embodiment of the present invention. For convenience of description, the embodiment of the present invention takes that each gate circuit includes two switch units as an example, and the technical solution of the embodiment of the present invention is described in an exemplary manner.
With continued reference to fig. 1, each switching unit 21 (22) in the gate circuit 20 includes an N-type transistor M11 (M21) and a P-type transistor M12 (M22); in the same gating circuit, the gates of the N-type transistors M11 (M21) of the switch units 21 (22) are electrically connected to the first clock signal lines 311 (321) of the clock signal lines 301 (302) in a one-to-one correspondence; in the same gate circuit 20, the gates of the P-type transistors M12 (M22) of the respective switch units 21 (22) are electrically connected in one-to-one correspondence with the second clock signal lines 312 (322) of the respective sets of clock signal lines 301 (302); the first pole of the M11 (M21) of the N-type transistor of the same switch unit 21 (22) is electrically connected with the first pole of the P-type transistor M12 (M22), and the first poles are all input ends of the switch unit 21 (22); the second pole of the N-type transistor M11 (M21) and the second pole of the P-type transistor M12 (M22) of the same switching unit 21 (22) are electrically connected, and are both output terminals of the switching unit 21 (22). In this way, when the data signal is supplied to the sub-pixel corresponding to the data line 10 electrically connected to the output terminal of the switching unit 21 of the gate circuit 20, the N-type transistor M11 and the P-type transistor M21 in the switching unit 21 can be controlled to be simultaneously turned on, so that the switching unit 21 can output a larger current signal to enable the sub-pixel to require a smaller amount of power, thereby minimizing the loss of the data signal transmitted from the data pin 41 to the corresponding sub-pixel and ensuring the accuracy of the data signal transmitted from each data pin 41 to the corresponding sub-pixel while reducing the charging time.
Fig. 2 is a driving timing diagram of a gating circuit according to the prior art. As shown in fig. 2, in the prior art, the clock signals for controlling the on or off of the N-type transistor and the P-type transistor of the same switching unit in the gate circuit are a pair of opposite clock signals CK 'and XCK'; that is, when the switch unit is turned on, the clock signal CK 'for controlling the N-type transistor of the switch unit transitions from a low level to a high level, and the clock signal XCK' for controlling the P-type transistor of the switch unit is transitions from a high level to a low level; correspondingly, when the switch unit is turned off, the clock signal CK 'for controlling the N-type transistor of the switch unit jumps from a high level to a low level, and the clock signal XCK' for controlling the P-type transistor of the switch on jumps from a low level to a high level; in addition, to ensure the accuracy of the data signal transmitted by the switch unit, the N-type transistor and the P-type transistor in the same switch unit are usually controlled to be turned on or off simultaneously. In this way, the pulse transition time of the clock signal CK 'received by the N-type transistor and the pulse transition time of the clock signal XCK' received by the P-type transistor in the same switch unit are the same, for example, when the N-type transistor and the P-type transistor are turned on, the transition time of the clock signal CK 'and the clock signal XCK' are both t1', and when the N-type transistor and the P-type transistor are turned off, the transition time of the clock signal CK' and the clock signal XCK 'are both t2', so that the radiation energy generated by the high-frequency component when the clock signal CK 'transitions and the radiation energy generated by the high-frequency component when the clock signal XCK' transitions are overlapped to generate a larger electromagnetic interference, thereby affecting the normal operation of other electronic components in the display panel.
Fig. 3 is a driving timing diagram of a gate circuit according to an embodiment of the present invention. As shown in conjunction with fig. 1 and 3, since the gate of the N-type transistor M11 (M21) and the gate of the P-type transistor M12 (M22) of the same switching unit 21 (22) in the gate circuit 20 are electrically connected to the first clock signal line 311 (321) and the second clock signal line 312 (322) of the same group of clock signal lines 301 (302), respectively, the first clock signal CK1 (CK 2) transmitted by the first clock signal line 311 (321) and the second clock signal XCK1 (XCK 2) transmitted by the second clock signal line 312 (322) of the same group of clock signal lines 301 (302) can control on or off of the N-type transistor M11 (M21) and the P-type transistor M12 (M22), respectively, of the same switching unit 21 (22). At this time, by overlapping the effective time of the effective pulse of the first clock signal CK1 (CK 2) and the effective time of the effective pulse of the second clock signal XCK1 (XCK 2), that is, the time period t2 to t3 (time period t6 to t 7) and the time period t1 to t4 (time period t5 to t 8) transmitted by the same group of clock signal lines 301 (302), the N-type transistor M11 (M21) and the P-type transistor M12 (M22) of the same switching unit 21 (22) can be controlled to be simultaneously turned on during the overlapping time of the effective pulse, so that the switching unit 21 (22) can have a larger output current during the time, and the data signal transmitted by the switching unit 21 (22) can have a smaller loss. In the embodiment of the present invention, the active time of the active pulse of the first clock signal CK1 (CK 2) is a period when the first clock signal CK1 (CK 2) can control the N-type transistor M11 (M21) to be turned on, and the active time of the active pulse of the second clock signal XCK1 (XCK 2) is a period when the second clock signal XCK1 (XCK 2) can control the P-type transistor M12 (M22) to be turned on.
Meanwhile, transition times t2 and t3 (t 6 and t 7) of at least part of pulses of the first clock signal CK1 (CK 2) and transition times t1 and t4 (t 5 and t 8) of at least part of pulses of the second clock signal XCK1 (XCK 2) transmitted by the same group of clock signal lines 301 (302) are distributed in a staggered manner, for example, a time t2 (t 6) when the first clock signal CK1 (CK 2) transitions from a low level to a high level and a time t1 (t 5) when the second clock signal XCK1 (XCK 2) transitions from a high level to a low level are different times, and a time t2 (t 6) when the first clock signal CK1 (CK 2) transitions from a high level to a low level and a time t1 (t 5) when the second clock signal XCK1 (XCK 2) transitions from a low level to a high level are different times. In this way, electromagnetic interference generated by simultaneous transitions of the pulses of the first clock signal CK1 (CK 2) and the second clock signal XCK1 (XCK 2) can be weakened, and the phenomenon that normal operation of electronic components in the display panel 100 is affected due to the larger electromagnetic interference is avoided, so that the display effect of the display panel 100 can be improved. Accordingly, when the display panel 100 is applied to a vehicle-mounted display screen, the influence on the normal operation of other electronic devices on a vehicle caused by larger electromagnetic interference can be avoided, and the safe and stable operation of the other electronic devices on the vehicle can be ensured.
In the embodiment of the invention, the phase of the first clock signal and the phase of the second clock signal transmitted by the same group of clock signal lines are not mutually influenced, and the phase of the first clock signal and the phase of the second clock signal can be independently adjusted, so that the overlapping time of the effective pulse of the first clock signal and the effective pulse of the second clock signal, the on time of the N-type transistor controlled by the first clock signal and the on time of the P-type transistor controlled by the second clock signal can be adjusted according to the requirement, and the embodiment of the invention is not particularly limited.
Because each gating circuit may include a plurality of switching units, the plurality of switching units need a plurality of groups of clock signal lines to respectively transmit different clock signals, so that each switching unit in the same gating circuit is turned on in a time-sharing manner, and the relative relationships between the first clock signal and the second clock signal transmitted by each group of clock signal lines are similar, so that the same technical effect can be achieved, and therefore, for convenience of description, the embodiment of the present invention will be described by taking the pulse transition condition of the first clock signal CK1 transmitted by the first clock signal line 311 and the second clock signal XCK1 transmitted by the second clock signal line 312 in the same group of clock signal lines 301 as an example.
Note that, in fig. 3, pulses of the first clock signal CK1 (CK 2) and the second clock signal XCK1 (XCK 2) are each rectangular, which is only exemplarily shown; in the embodiment of the present invention, the pulses of the first clock signal and the second clock signal may be in other forms such as trapezoids, which is not limited in particular.
Fig. 4 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in fig. 4, the pulses of the first clock signal CK1 and the second clock signal XCK1 are trapezoidal. At this time, on the premise that the effective time T4 to T5 of the effective pulse of the first clock signal CK1 and the effective time T2 to T7 of the effective pulse of the second clock signal XCK1 overlap, the pulse rising periods T3 to T4 of the first clock signal CK1 and the pulse falling periods T1 to T2 of the second clock signal XCK1 may be distributed in a staggered manner, and the pulse falling periods T5 to T6 of the first clock signal CK1 and the pulse rising periods T7 to T8 of the second clock signal XCK1 may be distributed in a staggered manner. In this way, electromagnetic interference generated when different clock signals are changed simultaneously can be weakened, the display effect of the display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic equipment on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
It should be noted that fig. 3 and fig. 4 are only exemplary drawings of the embodiment of the present invention, in fig. 3, the time T2 (T6) at which the first clock signal CK1 (CK 2) transmitted by the same group of clock signal lines 301 (302) transitions from low to high is located after the time T1 (T5) at which the second clock signal XCK1 (XCK 2) transitions from high to low, the time T2 (T6) at which the first clock signal CK1 (CK 2) transitions from high to low is located before the time T1 (T5) at which the second clock signal XCK1 (XCK 2) transitions from low to high, and the time T3 to T4 in fig. 4, which the first clock signal CK1 transitions from low to high, are located after the pulse falling period T1 to T2 at which the second clock signal XCK1 transitions from high to low, are located before the pulse falling period T6 at which the first clock signal CK1 transitions from high to low to the pulse falling period T6 is located before the second clock signal XCK1 transitions from low to high to the pulse falling period T8; in the embodiment of the invention, at least one of the jump time, the rising stage and the falling stage of at least part of pulses of the first clock signal and the second clock signal transmitted by the same group of clock signal lines are distributed in a staggered manner, so that the purpose of weakening electromagnetic interference can be achieved.
In fig. 4, it is exemplarily shown that T2 and T3 are different times, and T6 and T7 are different times, that is, the start time of the pulse rising phase of the first clock signal and the end time of the pulse falling phase of the second clock signal are different times, and the end time of the pulse falling phase of the first clock signal and the start time of the pulse rising phase of the second clock signal are different times; in the embodiment of the present invention, the end time or the start time of the pulse rising phase of the first clock signal and the start time or the end time of the pulse falling phase of the second clock signal may be the same time, and the end time or the end time of the pulse falling phase of the first clock signal and the end time or the start time of the pulse rising phase of the second clock signal may also be the same time. The pulse duty ratio of the first clock signal and the pulse duty ratio of the second clock signal provided to the same clock signal line may be the same or different, and the embodiment of the present invention is not limited thereto in particular.
Accordingly, the first clock signal or the second clock signal transmitted by each clock signal line may be provided by the driving chip of the display panel provided by the embodiment of the present invention, and when the transition time of at least part of the pulses of the first clock signal and the second clock signal provided by the driving chip to the same group of clock signal lines is different, the generation of larger electromagnetic interference due to the transition of the first clock signal and the second clock signal transmitted by the same group of clock signal lines can be avoided. For convenience of description, the following description will be given by taking, as an example, that the pulses of the first clock signal and the second clock signal are trapezoidal, and the end time or the start time of the pulse rising phase of the first clock signal and the start time or the end time of the pulse falling phase of the second clock signal may be the same time, and/or the start time or the end time of the pulse falling phase of the first clock signal and the end time or the start time of the pulse rising phase of the second clock signal may also be the same time.
Optionally, fig. 5 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in fig. 1 and 5, the pulse rising phases T1 'to T2' of the first clock signal CK1 supplied to the same group of clock signal lines 301 are located before the pulse falling phases T2 'to T3' of the second clock signal XCK 1; at this time, the pulse falling phases T4 'to T5' of the first clock signal CK1 and the pulse rising phases T4 'to T5' of the second clock signal XCK1 may be the same phase. In this way, the pulse rising stage of the first clock signal CK1 and the pulse falling stage of the second clock signal XCK1 are staggered, and compared with the situation that all pulse changing stages of the first clock signal and the second clock signal are the same in the prior art, electromagnetic interference generated when different clock signals change simultaneously can be weakened, the display effect of the display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic equipment on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
Optionally, fig. 6 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in fig. 1 and 6, on the premise that the pulse falling phases T4 'to T5' of the first clock signal CK1 and the pulse rising phases T4 'to T5' of the second clock signal XCK1 are the same phase, the effective pulse falling phases T1 'to T2' of the second clock signal XCK1 provided to the same group of clock signal lines 301 are located before the pulse rising phases T2 'to T3' of the first clock signal; at this time, electromagnetic interference generated when different clock signals are changed at the same time can be weakened as well, so that the display effect of the display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic equipment on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
Optionally, fig. 7 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in fig. 1 and 7, the pulse falling phases T3 "to T4" of the first clock signal CK1 supplied to the same group of clock signal lines 301 are located before the pulse rising phases T4 "to T5" of the second clock signal XCK 1; at this time, the pulse rising phases T1 "to T2" of the first clock signal CK1 and the pulse falling phases T1 "to T2" of the second clock signal XCK1 may be the same phase. Compared with the condition that all pulse change phases of the first clock signal and the second clock signal are the same in the prior art, the pulse falling phase of the first clock signal CK1 and the pulse rising phase of the second clock signal XCK1 are staggered, electromagnetic interference generated when different clock signals are changed simultaneously can be weakened, so that the display effect of a display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic equipment on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
Optionally, fig. 8 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in fig. 1 and 8, when the pulse rising phases T1 "to T2" of the first clock signal CK1 and the pulse falling phases T1 "to T2" of the second clock signal XCK1 may be the same phase, the pulse rising phases T3 "to T4" of the second clock signal XCK1 provided to the same group of clock signal lines 301 may be located before the pulse falling phases T4 "to T5" of the first clock signal CK 1; at this time, electromagnetic interference generated when different clock signals are changed at the same time can be weakened as well, so that the display effect of the display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic equipment on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
Optionally, fig. 9 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in conjunction with fig. 1 and 9, the pulse rising phases T1 '"to T2'" of the first clock signal CK1 supplied to the same group of clock signal lines 301 are located before the pulse falling phases T2 '"to T3'" of the second clock signal XCK1, and the pulse falling phases T4 '"to T5'" of the first clock signal CK1 supplied to the same group of clock signal lines 301 are located before the pulse rising phases T5 '"to T6'" of the second clock signal XCK 1. In this way, the pulse rising phase of the first clock signal CK1 and the pulse falling phase of the second clock signal XCK1 are staggered, and the pulse falling phase of the first clock signal CK1 and the pulse rising phase of the second clock signal XCK1 are staggered, so that electromagnetic interference generated when different clock signals change simultaneously can be weakened, the display effect of the display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic equipment on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
Optionally, fig. 10 is a driving timing diagram of a gate circuit according to another embodiment of the present invention. As shown in conjunction with fig. 1 and 10, the pulse falling phases T1 '"to T2'" of the second clock signal XCK1 supplied to the same group of clock signal lines 301 are located before the pulse rising phases T2 '"to T3'" of the first clock signal CK1, and the pulse rising phases T4 '"to T5'" of the second clock signal XCK1 supplied to the same group of clock signal lines 301 are located before the pulse falling phases T5 '"to T6'" of the first clock signal CK 1. At this time, the pulse rising phase of the first clock signal CK1 and the pulse falling phase of the second clock signal XCK1 are also staggered, and the pulse falling phase of the first clock signal CK1 and the pulse rising phase of the second clock signal XCK1 are staggered, so as to weaken electromagnetic interference generated when different clock signals are changed simultaneously, thereby improving the display effect of the display panel, and ensuring that other electronic devices on a vehicle including the vehicle-mounted display screen can safely and stably operate when the display panel is applied to the vehicle-mounted display screen.
In addition, fig. 11 is a driving timing chart of a gate circuit according to another embodiment of the present invention. As shown in fig. 11, the pulse rising phases T1"" -T2 "", of the first clock signal CK1 supplied to the same group of clock signal lines are located before the pulse falling phases T2"" -T3 "", of the second clock signal XCK1, and the pulse rising phases T4"" -T5 "", of the second clock signal XCK1 are located before the pulse falling phases T5"" -T6 "", of the first clock signal CK 1. In this way, the pulse rising stage of the first clock signal CK1 and the pulse falling stage of the second clock signal XCK1 are staggered, and the pulse falling stage of the first clock signal CK1 and the pulse rising stage of the second clock signal XCK1 are staggered, so that electromagnetic interference generated when different clock signals change simultaneously is weakened, the display effect of the display panel is improved, and when the display panel is applied to a vehicle-mounted display screen, other electronic devices on a vehicle comprising the vehicle-mounted display screen can be ensured to safely and stably operate.
The technical solution of the embodiment of the present invention has been described by taking the phase difference between the first clock signal and the second clock signal provided by the driving chip for driving the display panel according to the embodiment of the present invention to the same group of clock signal lines as an example, but in the embodiment of the present invention, the transition time of at least part of the pulses of the first clock signal and the second clock signal transmitted by the same group of clock signal lines may be staggered by combining the structural design of the first clock signal line and the second clock signal in the same group of clock signal lines, the structural design of the N-type transistor and the P-type transistor of the same switching unit, and the like; or when the driving chip cannot provide a pair of first clock signals and second clock signals with staggered phases, the transition time of at least part of pulses of the first clock signals and the second clock signals transmitted by the same group of clock signal lines can be staggered through the structural design of the first clock signal lines and the second clock signals in the same group of clock signal lines, the structural design of N-type transistors and P-type transistors of the same switch unit and the like.
Optionally, the aspect ratio of the N-type transistor in the switching unit of the gating circuit is different from the aspect ratio of the P-type transistor M.
Fig. 12 is a schematic view illustrating a partial top view structure of a display panel according to an embodiment of the present invention, and fig. 13 is a schematic view illustrating a partial film structure of a display panel along a section A-A in fig. 12. As shown in fig. 1, 12 and 13, the N-type transistor M11 of the switching unit 21 in the gate circuit 20 includes an active layer M1, a gate electrode g1, a first electrode s1 and a second electrode d1; the position of the active layer M1 of the N-type transistor M11 overlapping the gate g1 thereof may be a channel region of the N-type transistor M11, the length of the channel region of the N-type transistor M11 is L1, and the width of the channel region is W1, such that the aspect ratio of the N-type transistor M11 is W1/L1. Accordingly, the P-type transistor M12 of the switching unit 21 in the gate circuit 20 includes an active layer M2, a gate electrode g2, a first electrode s2 and a second electrode d2; the position of the active layer M2 of the P-type transistor M12 overlapping the gate g2 thereof may be a channel region of the P-type transistor M12, the length of the channel region of the P-type transistor M12 is L2, and the width of the channel region is W2, such that the aspect ratio of the P-type transistor M12 is W2/L2. Wherein the width-to-length ratio W1/L1 of the N-type transistor M11 may be greater than the width-to-length ratio W2/L2 of the P-type transistor M12, or the width-to-length ratio W1/L1 of the N-type transistor M11 may be less than the width-to-length ratio W2/L2 of the P-type transistor M12; at this time, although the transition times of at least part of the pulses of the first clock signal CK1 received by the gate of the N-type transistor M11 and the second clock signal XCK1 received by the gate of the P-type transistor M12 are staggered, the N-type transistor and the P-type transistor may be turned on simultaneously, so that the switching unit 21 may have a larger output current, so that the sub-pixel may be charged to a desired potential in a shorter time, thereby being beneficial to improving the driving capability.
Optionally, the width of the first clock signal line is different from the width of the second clock signal line in each group of clock signal lines.
As an example, referring to fig. 1 and 12 in combination, the first clock signal line 311 has a width L1 'and the second clock signal line 312 has a width L2'; the width L1 'of the first clock signal line 311 may be greater than the width L2' of the second clock signal line 312, or the width L1 'of the first clock signal line 311 may be less than the width L2' of the second clock signal line 312 such that the impedance per unit length in the first clock signal line 311 is different from the impedance per unit length in the second clock signal line 312; at this time, the pulse transition time of the first clock signal CK1 transmitted from the first clock signal line 311 to the gate of the N-type transistor M11 and the pulse transition time of the second clock signal XCK1 transmitted from the second clock signal line 312 to the gate of the P-type transistor M12 can be made different, so that electromagnetic interference generated when different clock signals are simultaneously changed is weakened, the display effect of the display panel can be improved, and when the display panel is applied to the vehicle-mounted display panel, other electronic devices on the vehicle including the vehicle-mounted display panel can be ensured to safely and stably operate
It should be noted that, fig. 12 and fig. 13 are only exemplary drawings of an embodiment of the present invention, and fig. 12 and fig. 13 are only schematic structural diagrams illustrating one switch unit and one group of clock signal lines in the gating circuit; while the schematic of the structure of other switching units and other groups of clock signal lines in the gating circuit may be similar to that shown in fig. 12 and 13; alternatively, the structure of the switch unit of the gate circuit and the structure of each group of clock signal lines in the display panel according to the embodiment of the present invention may be any other structure, and fig. 12 and 13 are only exemplary illustrations of the relative relationship between the width-to-length ratios of the N-type transistors and the P-type transistors in the switch unit, and the relative relationship between the widths of the first clock signal line and the second clock signal line in the same group of clock signal lines, which are not particularly limited in the embodiment of the present invention.
Further alternatively, as shown with continued reference to fig. 1, when each gate circuit 20 includes two switching units 21 and 22, the two switching units are a first switching unit 21 and a second switching unit 22, respectively; at this time, the plurality of sets of clock signal lines may include a first set of clock signal lines 301 and a second set of clock signal lines 302; wherein, the gate of the N-type transistor M11 of each first switch unit 21 is electrically connected to the first clock signal line 311 of the first group of clock signal lines 301; the gates of the P-type transistors M12 of the respective first switching units 21 are electrically connected to the second clock signal lines 312 of the first group of clock signal lines 301; the gates of the N-type transistors M21 of the respective second switching units 22 are electrically connected to the first clock signal lines 321 of the second group of clock signal lines 302; the gates of the P-type transistors M22 of each second switching unit 22 are electrically connected to the second clock signal lines 322 of the second group of clock signal lines 302.
On the premise that the switch units of the same gating circuit can be conducted in a time-sharing mode, the N-type transistors of the first switch units of different gating circuits share the first clock signal line, the P-type transistors of the first switch units of different gating circuits share the second clock signal line, the N-type transistors of the second switch units of different gating circuits share the second clock signal line, and the P-type transistors of the second switch units of different gating circuits share the second clock signal line, so that the number of the clock signal lines can be reduced, the frame size of the display panel can be reduced, namely the narrow frame of the display panel is facilitated, and the screen duty ratio of the display panel can be improved.
Optionally, fig. 14 is a schematic structural diagram of another display panel according to an embodiment of the present invention. As shown in fig. 14, the non-display area 120 of the display panel 100 is further provided with a scan driving circuit 50, and the display area 110 of the display panel 100 is further provided with a plurality of scan lines 60. Wherein, each output end of the scanning driving circuit 50 is electrically connected with each scanning line 60 in a one-to-one correspondence; wherein the scan line 60 crosses the data line 10 to define the position of the sub-pixel 101. At this time, each gate circuit may include N switch units (N is an integer greater than or equal to 1), and when the N-type transistors (M11, M21) and the P-type transistors (M21, M22) of the switch units (21, 22) of the same gate circuit 20 are sequentially turned on, the scan driving circuit 50 is further controlled to sequentially supply the scan signals to the scan lines 60 such that the data signals are transmitted to the data lines 10 through the turned-on N-type transistors and/or P-type transistors, and written into the sub-pixels 101 receiving the scan signals by the data lines 10, so that the data signals can be written into the sub-pixels one by one and the data signals are displayed according to the data signals received by the sub-pixels.
Wherein the overlapping width of the effective time of the effective pulse of the first clock signal and the effective pulse of the second clock signal provided to the same group of clock signal lines is delta T, and the sum of the widths of the effective time of the effective pulse of the first clock signal and the effective pulse of the second clock signal provided to the same group of clock signal lines is T; the pulse width of the scanning signal is greater than or equal to N x (T- Δt).
Fig. 15 is a driving timing chart of a display panel according to an embodiment of the present invention. As shown in fig. 14 and 15, the effective time of the effective pulse of the first clock signal CK1 supplied to the first clock signal line 311 is a period of T2 to T3, the effective time of the effective pulse of the second clock signal XCK1 supplied to the second clock signal line 312 is a period of T1 to T4, so that the overlapping width Δt1 of the effective pulse of the first clock signal CK1 and the effective pulse of the second clock signal XCK1 is T3 to T2, and the sum T1 of the width T3 to T2 of the effective pulse of the first clock signal CK1 and the width T4 to T1 of the effective pulse of the second clock signal XCK1 is (T3 to T2) + (T4 to T1); the effective time of the effective pulse of the first clock signal CK2 supplied to the first clock signal line 321 is in the period of T5 to T6, the effective time of the effective pulse of the second clock signal XCK2 supplied to the second clock signal line 322 is in the period of T4 to T7, so that the overlapping width Δt2 of the effective pulse of the first clock signal CK2 and the effective pulse of the second clock signal XCK2 is in the period of T6 to T5, and the sum T2 of the widths T6 to T5 of the effective pulse of the first clock signal CK2 and the widths T7 to T4 of the effective pulse of the second clock signal XCK1 is (T6 to T5) + (T7 to T4). When t1- Δt1=t2- Δt2=t- Δt, by making the pulse width T9-T8 of the scanning signal Gout greater than or equal to n×t (T- Δt), it is possible to ensure that each data signal is written into each sub-pixel in one-to-one correspondence when the data signals of the same data pin 41 are time-division transmitted by each switch unit (21, 22) of the same gate unit 20.
Based on the same inventive concept, the embodiment of the present invention further provides a driving method of a display panel, where the driving method of the display panel is used for driving the display panel provided by the embodiment of the present invention, and the driving method of the display panel provided by the embodiment of the present invention has the technical features and beneficial effects of the display panel provided by the embodiment of the present invention, and the same points can be referred to the description of the display panel provided by the embodiment of the present invention, and are not repeated herein.
The driving method provided by the embodiment of the invention at least comprises the following steps: providing data signals to the data pins in a one-to-one correspondence manner, sequentially providing first clock signals to the first clock signal lines of each group of clock signal lines, sequentially providing second clock signals to the second clock signal lines of each group of clock signal lines, and controlling the N-type transistors and the P-type transistors of each switch unit of the same gating circuit to be sequentially conducted so that the data signals are transmitted to each data line through the conducted N-type transistors and/or P-type transistors; wherein the active pulses of the first clock signal and the second clock signal provided to the same set of clock signal lines have an overlap; the transition times of at least part of the pulses of the first clock signal and the transition times of at least part of the pulses of the second clock signal supplied to the same group of clock signal lines are staggered.
Therefore, when the jump time of at least part of the pulses of the first clock signal and the jump time of at least part of the pulses of the second clock signal provided for the same group of clock signal lines are staggered, electromagnetic interference generated by simultaneous jump of the pulses of the first clock signal and the second clock signal can be weakened, the phenomenon that normal operation of electronic elements in the display panel is influenced due to larger electromagnetic interference is avoided, and the display effect of the display panel can be improved. Accordingly, when the display panel is applied to the vehicle-mounted display screen, the influence on the normal operation of other electronic equipment on the vehicle caused by larger electromagnetic interference can be avoided, and the safe and stable operation of the other electronic equipment on the vehicle can be ensured.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the driving chip and the display panel provided by the embodiment of the invention, and the driving chip can execute the driving method of the display panel provided in real time. Therefore, the display device provided by the embodiment of the invention has the technical characteristics and beneficial effects of the display panel provided by the embodiment of the invention, and the technical characteristics and beneficial effects of the driving method of the display panel provided by the embodiment of the invention. The same points can be referred to the display panel provided by the embodiment of the present invention and the driving method of the display panel provided by the embodiment of the present invention, and will not be described herein.
Fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 16, the display device 200 includes a driving chip 210 and the display panel 100 provided in the embodiment of the present invention. The driving chip 210 is used for executing the driving method of the display panel provided by the embodiment of the invention, so as to drive the display panel 100 provided by the embodiment of the invention. The display device may include, for example, but not limited to, an in-vehicle display screen, a computer display, a portable device having a display function, and the like.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. A display panel, comprising: a plurality of data lines, a plurality of gating circuits, a plurality of groups of clock signal lines and a plurality of data pins;
each group of the clock signal lines comprises a first clock signal line and a second clock signal line; the first clock signal line is used for transmitting a first clock signal; the second clock signal line is used for transmitting a second clock signal;
each gating circuit comprises at least one switching unit; each switch unit of the same gating circuit is conducted in a time-sharing way; the input ends of the switch units of the same gating circuit are electrically connected with the same data pin; the output end of each switch unit is electrically connected with each data line in a one-to-one correspondence manner;
the switch unit comprises an N-type transistor and a P-type transistor; in the same gating circuit, the grid electrode of the N-type transistor of each switching unit is electrically connected with the first clock signal line of each group of clock signal lines in a one-to-one correspondence manner; in the same gating circuit, the grid electrode of the P-type transistor of each switching unit is electrically connected with the second clock signal line of each group of clock signal lines in a one-to-one correspondence manner; the first electrode of the N-type transistor and the first electrode of the P-type transistor of the same switching unit are electrically connected, and are both input ends of the switching unit; the second pole of the N-type transistor and the second pole of the P-type transistor of the same switching unit are electrically connected and are both output ends of the switching unit;
Wherein the effective time of the effective pulse of the first clock signal and the effective pulse of the second clock signal transmitted by the same group of clock signal lines are overlapped; the transition time of at least part of pulses of the first clock signal transmitted by the same group of clock signal lines is staggered with the transition time of at least part of pulses of the second clock signal;
the display panel also comprises a scanning driving circuit and a plurality of scanning lines; each output end of the scanning driving circuit is electrically connected with each scanning line in a one-to-one correspondence manner; the scanning line crosses the data line; each gating circuit comprises N switch units; wherein N is an integer greater than or equal to 1;
the display panel further comprises, when the control on of the display panel is performed: controlling the scanning driving circuit to sequentially provide scanning signals for each scanning line;
wherein an overlapping width of effective times of the first clock signal and the second clock signal supplied to the same group of clock signal lines is Δt, and a sum of overlapping widths of effective times of the first clock signal and the second clock signal supplied to the same group of clock signal lines is T; the pulse width of the scanning signal is greater than or equal to N (T-delta T).
2. The display panel of claim 1, wherein the N-type transistor has a different aspect ratio than the P-type transistor.
3. The display panel according to claim 1, wherein a width of the first clock signal line is different from a width of the second clock signal line.
4. The display panel according to claim 1, wherein each of the gate circuits includes two switch units, the two switch units being a first switch unit and a second switch unit, respectively;
the plurality of groups of clock signal lines comprise a first group of clock signal lines and a second group of clock signal lines;
the grid electrode of the N-type transistor of each first switch unit is electrically connected with a first clock signal line of the first group of clock signal lines; the grid electrode of the P-type transistor of each first switch unit is electrically connected with the second clock signal line of the first group of clock signal lines;
the grid electrode of the N-type transistor of each second switch unit is electrically connected with the first clock signal line of the second group of clock signal lines; the grid electrode of the P-type transistor of each second switch unit is electrically connected with the second clock signal line of the second group of clock signal lines.
5. A driving method of a display panel for driving the display panel according to any one of claims 1 to 4, comprising:
providing data signals to the data pins in a one-to-one correspondence manner, sequentially providing a first clock signal to the first clock signal lines of each group of clock signal lines, sequentially providing a second clock signal to the second clock signal lines of each group of clock signal lines, and controlling N-type transistors and P-type transistors of each switch unit of the same gating circuit to be sequentially conducted so that the data signals are transmitted to each data line through the conducted N-type transistors and/or P-type transistors;
wherein the active times of the active pulses of the first clock signal and the second clock signal provided to the same set of clock signal lines have an overlap; the transition time of at least part of pulses of the first clock signal and the transition time of at least part of pulses of the second clock signal provided to the same group of clock signal lines are distributed in a staggered manner;
the display panel also comprises a scanning driving circuit and a plurality of scanning lines; each output end of the scanning driving circuit is electrically connected with each scanning line in a one-to-one correspondence manner; the scanning line crosses the data line; each gating circuit comprises N switch units; wherein N is an integer greater than or equal to 1;
The driving method further includes:
controlling the scanning driving circuit to sequentially provide scanning signals for each scanning line;
wherein an overlapping width of effective times of the first clock signal and the second clock signal supplied to the same group of clock signal lines is Δt, and a sum of overlapping widths of effective times of the first clock signal and the second clock signal supplied to the same group of clock signal lines is T; the pulse width of the scanning signal is greater than or equal to N (T-delta T).
6. The driving method of a display panel according to claim 5, wherein a pulse rising period of the first clock signal supplied to the same group of the clock signal lines is located before a pulse falling period of the second clock signal;
alternatively, the second clock signal active pulse falling phase provided to the same set of the clock signal lines is located before the pulse rising phase of the first clock signal.
7. The driving method of a display panel according to claim 5 or 6, wherein a pulse falling phase of the first clock signal supplied to the same group of the clock signal lines is located before a pulse rising phase of the second clock signal;
Alternatively, the pulse rising phase of the second clock signal supplied to the same set of the clock signal lines is located before the pulse falling phase of the first clock signal.
8. The driving method of a display panel according to claim 7, wherein a pulse duty ratio of the first clock signal is the same as a pulse duty ratio of the second clock signal.
9. A display device, comprising: a driving chip and the display panel of any one of claims 1 to 4;
the driving chip is used for executing the driving method of the display panel according to any one of claims 5 to 8.
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| CN115223505A (en) * | 2022-07-20 | 2022-10-21 | 厦门天马微电子有限公司 | Display device and driving method of display panel |
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| JP2008287134A (en) * | 2007-05-21 | 2008-11-27 | Seiko Epson Corp | Pulse output circuit, shift register, scanning line driving circuit, data line driving circuit, electro-optical device and electronic equipment |
| CN106444192A (en) * | 2016-11-09 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and drive method, display panel thereof |
| CN110796124A (en) * | 2019-11-27 | 2020-02-14 | 厦门天马微电子有限公司 | Display panel driving method and display device |
| CN111179812A (en) * | 2020-03-16 | 2020-05-19 | 昆山国显光电有限公司 | Display panel, driving method thereof and display device |
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| JP2008287134A (en) * | 2007-05-21 | 2008-11-27 | Seiko Epson Corp | Pulse output circuit, shift register, scanning line driving circuit, data line driving circuit, electro-optical device and electronic equipment |
| CN106444192A (en) * | 2016-11-09 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and drive method, display panel thereof |
| CN110796124A (en) * | 2019-11-27 | 2020-02-14 | 厦门天马微电子有限公司 | Display panel driving method and display device |
| CN111179812A (en) * | 2020-03-16 | 2020-05-19 | 昆山国显光电有限公司 | Display panel, driving method thereof and display device |
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