CN114550668A

CN114550668A - Display panel and display device

Info

Publication number: CN114550668A
Application number: CN202210187779.7A
Authority: CN
Inventors: 刘荣铖; 付伟
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2022-05-27

Abstract

In the display panel and the display device provided by the embodiment of the present disclosure, the non-display area further includes a plurality of sharing circuits. Wherein, divide many clock signal lines into at least one signal line group; the signal line group comprises two clock signal lines; the two clock signal lines in the same signal line group transmit clock signals with opposite levels. And the two clock signal lines in each signal line group are electrically connected through at least one sharing circuit. And the sharing circuit is configured to turn on the electrically connected timing signal line in response to the control signal loaded by the control signal terminal. Therefore, the sharing circuit is arranged in the display panel, a mode of sharing charges of the clock signal line can be adopted, and the technical effect of avoiding serious heating of local positions in the display panel is achieved. Particularly, the technical problem that the local position in the display panel with high resolution and high refresh rate generates heat seriously can be solved, and the quality of the product is improved.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

In displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting diodes (OLEDs), a plurality of pixel cells are generally included. Each pixel unit may include: red, green, and blue sub-pixels. And controlling the corresponding brightness of each sub-pixel so as to mix the colors required to be displayed to display a color image.

Disclosure of Invention

The display panel provided by the embodiment of the disclosure includes:

a substrate including a display region and a non-display region;

the grid driving circuit is positioned in the non-display area;

the clock signal lines are positioned in the non-display area and are electrically connected with the grid driving circuit; wherein the plurality of clock signal lines are divided into at least one signal line group; the signal line group comprises two clock signal lines; the levels of clock signals transmitted by two clock signal lines in the same signal line group are opposite;

a plurality of shared circuits located in the non-display area; wherein two of the clock signal lines in each of the signal line groups are electrically connected through at least one of the sharing circuits; and the sharing circuit is configured to turn on the electrically connected timing signal line in response to a control signal applied from the control signal terminal.

In some examples, the display area includes a bonding area;

and one shared circuit electrically connected with at least one signal line group is positioned at one end of the clock signal line, which is far away from the bonding area.

In some examples, when there are a plurality of shared circuits electrically connected to each signal line group, for the shared circuits electrically connected to the same signal line group, except for the shared circuit located at the end of the clock signal line away from the bonding region, the remaining shared circuits are sequentially arranged at intervals on one side of the plurality of clocks newly departing from the gate driving circuit.

In some examples, the remaining shared circuits corresponding to different ones of the signal line groups are alternately arranged.

In some examples, the shared circuits electrically connected to the same signal line group are electrically connected to the same control signal terminal.

In some examples, one clock signal and control signal correspond to the same signal line group;

each rising edge and each falling edge of the clock signal respectively correspond to the effective level of the control signal;

for an active level corresponding to a rising edge of the clock signal, a start time of the active level is located before the corresponding rising edge, and an end time of the active level is located after the corresponding rising edge;

and aiming at the effective level corresponding to the falling edge of the clock signal, the starting time of the effective level is positioned before the corresponding falling edge, and the ending time of the effective level is positioned after the corresponding falling edge.

In some examples, for an active level corresponding to a rising edge of the clock signal, a start time of the active level and the corresponding rising edge have a first set interval duration therebetween, and an end time of the active level and the corresponding rising edge have a second set interval duration therebetween;

and aiming at the effective level corresponding to the falling edge of the clock signal, a third set interval duration is arranged between the starting time of the effective level and the corresponding falling edge, and a fourth set interval duration is arranged between the ending time of the effective level and the corresponding falling edge.

In some examples, the first set interval duration is the same as the third set interval duration; and/or the presence of a gas in the gas,

the second set interval duration is the same as the fourth set interval duration.

In some examples, a sum of the first set interval duration and the second set interval duration corresponding to the same active level of the control signal is a first set sustain duration; the first set maintaining time length is the half-width time length of a current peak appearing when a rising edge appears on the clock signal line;

the sum of the third set interval duration and the fourth set interval duration corresponding to the same effective level of the control signal is a second set maintaining duration; the second set sustain duration is a full width at half maximum duration of a current spike occurring when a falling edge occurs on the clock signal line.

In some examples, the shared circuit includes a control transistor;

the gate of the control transistor is electrically connected with the control signal end, the first electrode of the control transistor is electrically connected with one of the two clock signal lines, and the first electrode of the control transistor is electrically connected with the other of the two clock signal lines.

The embodiment of the disclosure also provides a display device comprising the display panel.

The embodiment of the present disclosure further provides a driving method of the display panel, including:

inputting clock signals to the plurality of clock signal lines, and conducting the electrically connected timing signal lines in response to the effective level of the control signal loaded by the control signal end when the level of the clock signals on the clock signal lines electrically connected with the shared circuit is switched; wherein the plurality of clock signal lines are divided into at least one signal line group; the signal line group comprises two clock signal lines; the levels of the clock signals transmitted by the two clock signal wires in the same signal wire group are opposite.

Drawings

FIG. 1 is a schematic diagram of some structures of a display device according to an embodiment of the present disclosure;

FIG. 2 is another schematic structural diagram of a display device according to an embodiment of the disclosure;

FIG. 3 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 4 is a timing diagram of further signals in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of some structures of a display panel according to an embodiment of the present disclosure;

FIG. 6 is another schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 7 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 8a is a timing diagram of some further signals in the disclosed embodiment;

FIG. 8b is a timing diagram of some further signals in the disclosed embodiment;

FIG. 8c is a timing diagram of some further signals in the disclosed embodiment;

FIG. 9 is a timing diagram of further signals in the disclosed embodiment;

fig. 10 is a schematic structural diagram of display panels in an embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And like reference numerals refer to like or similar elements or elements having like or similar functions throughout.

Referring to fig. 1 and 2, the display device may include a display panel 100, a Level Shift (Level Shift) circuit 200, and a timing controller 300. Among other things, the display panel 100 may include a substrate base including a display area AA and a non-display area BB (i.e., an area other than the display area AA). The display area AA may include a plurality of pixel units arranged in an array, a plurality of gate lines (e.g., GA1, GA2, GA3, GA4), and a plurality of data lines (e.g., DA1, DA2, DA 3). The non-display area BB may include a plurality of clock signal lines (e.g., CK1 to CK6), the gate driving circuit 110, and the source driving circuit 120. The gate driving circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, respectively, and the source driving circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. Illustratively, each pixel unit includes a plurality of sub-pixels SPX. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing may be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display may be realized by performing color mixing of red, green, blue, and white. Of course, in practical applications, the light emitting color of the sub-pixels in the pixel unit may be determined according to practical application environments, and is not limited herein.

Referring to fig. 1, each sub-pixel includes a transistor 01 and a pixel electrode 02. The sub-pixels in a row correspond to a grid line, and the sub-pixels in a column correspond to a data line. The gate of the transistor 01 is electrically connected to the corresponding gate line, the source of the transistor 01 is electrically connected to the corresponding data line, and the drain of the transistor 01 is electrically connected to the pixel electrode 02. it should be noted that the pixel array structure of the present disclosure may also be a dual-gate structure, that is, two gate lines are disposed between two adjacent rows of pixels, and this arrangement mode may reduce half of the data lines, that is, include data lines between two adjacent rows of pixels, and some adjacent rows of pixels do not include data lines, and the specific pixel arrangement structure and data lines, and the arrangement mode of the scan lines is not limited.

In some embodiments of the present disclosure, as shown in fig. 2, the clock signal lines (e.g., CK 1-CK 6) are electrically connected to the gate driving circuit 110. A plurality of clock signal lines (e.g., CK1 to CK6) are electrically connected to a clock PAD (PAD) in the bonding area BD through a clock fanout line in the fanout area FO in the display panel, and the level shifter circuit 200 is electrically connected to the clock PAD (PAD) in the bonding area BD. Illustratively, the timing controller 300 inputs a control signal to the Level Shift circuit 200 to cause the Level Shift circuit 200 to input a clock signal to the gate driving circuit 110, and the timing controller 300 inputs a frame start signal to the gate driving circuit 110 to cause the gate driving circuit 110 to output a gate driving signal according to the clock signal and the frame start signal to drive the gate lines GA1, GA2, GA3, GA 4. The timing controller 300 inputs the received display data to the source driving circuit 120, so that the source driving circuit 120 can input a data voltage to the data line according to the received display data, thereby charging the sub-pixel SPX, and inputting a corresponding data voltage to the sub-pixel SPX to implement a picture display function.

It should be noted that the display panel in the embodiment of the present disclosure may be a liquid crystal display panel. Illustratively, a liquid crystal display panel generally includes upper and lower substrates facing each other, and liquid crystal molecules encapsulated between the upper and lower substrates. When a picture is displayed, a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage applied to the common electrode, and the voltage difference can form an electric field, so that liquid crystal molecules are deflected by the electric field. The electric fields with different intensities enable the deflection degrees of the liquid crystal molecules to be different, so that the transmittance of the sub-pixel SPX is different, the sub-pixel SPX can realize the brightness with different gray scales, and the picture display can be further realized. Of course, the display panel in the embodiments of the present disclosure may be an OLED display panel, and is not limited herein.

Fig. 2 shows a signal timing diagram corresponding to the gate driving circuit, as shown in fig. 3. Wherein CK1 represents the clock signal transmitted on clock line CK1, CK2 represents the clock signal transmitted on clock line CK2, CK3 represents the clock signal transmitted on clock line CK3, CK4 represents the clock signal transmitted on clock line CK4, CK5 represents the clock signal transmitted on clock line CK5, and CK6 represents the clock signal transmitted on clock line CK 6. And, the signal GA1 represents the signal transmitted on the gate line GA1, and the gate driving circuit 110 outputs the first high level of the clock signal ck1 to the gate line GA1 to generate the high level of the signal GA 1. The signal GA2 represents the signal transmitted on the gate line GA2, and the gate driving circuit 110 outputs the first high level of the clock signal ck2 to the gate line GA2 to generate the high level of the signal GA 2. The signal GA3 represents the signal transmitted on the gate line GA3, and the gate driving circuit 110 outputs the first high level of the clock signal ck3 to the gate line GA3 to generate the high level of the signal GA 3. The signal GA4 represents the signal transmitted on the gate line GA4, and the gate driving circuit 110 outputs the first high level of the clock signal ck4 to the gate line GA4 to generate the high level of the signal GA 4. The signal GA5 represents the signal transmitted on the gate line GA5, and the gate driving circuit 110 outputs the first high level of the clock signal ck5 to the gate line GA5 to generate the high level of the signal GA 5. The signal GA6 represents the signal transmitted on the gate line GA6, and the gate driving circuit 110 outputs the first high level of the clock signal ck6 to the gate line GA6 to generate the high level of the signal GA 6. In the embodiment of the present disclosure, the level shifter circuit inputs CK1 to CK6 to the clock signal lines CK1 to CK6, respectively, so that the gate driver circuit 110 can output signals ga1 to ga 6. In practical applications, at the instant when the clock signals CK1 CK6 change from high to low levels, sharp current spikes appear on the clock lines CK1 CK6, as shown in fig. 4, taking the clock signals CK1 and CK4 as examples, I (CK1) represents the current on the clock line CK1, and I (CK4) represents the current on the clock line CK 4. Then, at the instant when the clock signal CK1 changes from low to high, a current spike FS11 occurs in the current I (CK1) on the clock signal line CK 1. And, at the instant when the clock signal CK1 changes from high to low, a current spike FS12 also appears in the current I (CK1) on the clock signal line CK 1. Similarly, at the instant when the clock signal CK4 changes from high to low, a current spike FS21 occurs in the current I (CK4) on the clock signal line CK 4. And, at the instant when the clock signal CK4 changes from low to high, a current spike FS22 occurs in the current I (CK3) on the clock signal line CK 4. Taking current I (CK1) as an example, heat generation occurs at these locations because current I (CK1) passes through the corner of clock signal line CK1, the corner of the clock fan-out line in fan-out region FO, bonding region BD, etc. Due to the fact that the number of clock signal lines arranged in the display panel is large (for example, the number of the clock signal lines is 4, 6, 8, 10, 12, and the like), the number of the clock fan-out lines and the number of the clock bonding pads are also large, so that heat is generated at corners (such as an FR region) of the clock signal lines, corners of the clock fan-out lines and a bonding region, and even the temperature is over 100 ℃ (such as a 75-inch 4K 240Hz display panel), the quality of a product is seriously affected.

In order to solve the above problem, embodiments of the present disclosure provide some display panels, and the non-display area further includes a plurality of shared circuits. Wherein, divide many clock signal lines into at least one signal line group; the signal line group comprises two clock signal lines; the two clock signal lines in the same signal line group transmit clock signals with opposite levels. And the two clock signal lines in each signal line group are electrically connected through at least one sharing circuit. And the sharing circuit is configured to turn on the electrically connected timing signal line in response to the control signal loaded by the control signal terminal. Therefore, by arranging the sharing circuit in the display panel, a Charge sharing (Charge sharing) mode can be adopted for the clock signal line, and the technical effect of avoiding serious heating of a local position in the display panel is achieved. Particularly, the technical problem that the local position in the display panel with high resolution and high refresh rate generates heat seriously can be solved, and the quality of the product is improved.

Illustratively, the two clock signal lines in each signal line group may be electrically connected by one shared circuit. The control signal terminals connected with the sharing circuits corresponding to different signal line groups are different. For example, as shown in fig. 5 and 6, the display panel may have clock signal lines CK1 to CK6, and the clock signal lines CK1 to CK6 may be divided into 3 signal line groups. Among them, since the levels of the clock signals CK1 and CK4 are opposite, it is possible to divide the clock signal lines CK1 and CK4 into a signal line group Z-1, and to electrically connect the clock signal lines CK1 and CK4 through a shared circuit GS-1. This makes it possible to turn on the clock signal lines CK1 and CK4 in the shared circuit GS-1 in response to the control signal applied from the control signal terminal CS-1. Also, since the levels of the clock signals CK2 and CK5 are opposite, it is possible to divide the clock signal lines CK2 and CK5 into one signal line group Z-2 and electrically connect the clock signal lines CK2 and CK3 through one shared circuit GS-2. This makes it possible to turn on the clock signal lines CK2 and CK5 of the shared circuit GS-2 in response to a control signal applied from the control signal terminal CS-2. And, the levels of the clock signals CK3 and CK6 are opposite, it is possible to divide the clock signal lines CK3 and CK6 into a signal line group Z-3, and to electrically connect the clock signal lines CK3 and CK6 through a shared circuit GS-3. This makes it possible to turn on the clock signal lines CK3 and CK6 in the shared circuit GS-3 in response to the control signal applied from the control signal terminal CS-3.

In the disclosed embodiment, one shared circuit, which may electrically connect at least one signal line group, is located at an end of the clock signal line that faces away from the bonding area. Illustratively, one shared circuit that may electrically connect each signal line group is located at an end of the clock signal line that faces away from the bonding area. For example, as shown in FIG. 5, the shared circuits GS-1 to GS-3 may be provided at the ends of the clock signal lines CK1 to CK6 facing away from the bonding area BD. Therefore, the shared circuits GS-1 to GS-3 can be far away from the corner of the clock signal line (such as an FR region), the corner of the clock fan-out line and the bonding region, and the heating problems of the corner of the clock signal line (such as the FR region), the corner of the clock fan-out line and the bonding region are further improved.

In the disclosed embodiments, the shared circuitry may include a control transistor; the grid electrode of the control transistor is electrically connected with the control signal end, the first electrode of the control transistor is electrically connected with one of the two clock signal lines, and the first electrode of the control transistor is electrically connected with the other of the two clock signal lines. In specific implementation, the control transistor is turned on when the loaded control signal is at an active level and turned off when the loaded control signal is at an inactive level. For example, when the control transistor is an N-type transistor, the active level of the loaded control signal may be set to a high level, and the inactive level may be set to a low level. When the control transistor is a P-type transistor, the active level of the applied control signal may be set to a low level and the inactive level may be set to a high level. And the first pole of the control transistor may serve as its source and the second pole may serve as its drain. Alternatively, the first pole of the control transistor may be used as its drain, and the second pole may be used as its source, which is not limited herein.

Illustratively, as shown in fig. 6 and 7, the sharing circuit GS-1 includes a control transistor M-1, a gate of the control transistor M-1 is electrically connected to the control signal terminal CS-1, a first pole of the control transistor M-1 is electrically connected to the clock signal line CK1, and a second pole of the control transistor M-1 is electrically connected to the clock signal line CK 4. The shared circuit GS-2 includes a control transistor M-2, a gate of the control transistor M-2 is electrically connected to the control signal terminal CS-2, a first pole of the control transistor M-2 is electrically connected to the clock signal line CK2, and a second pole of the control transistor M-2 is electrically connected to the clock signal line CK 5. The sharing circuit GS-3 includes a control transistor M-3, a gate of the control transistor M-3 is electrically connected to the control signal terminal CS-3, a first pole of the control transistor M-3 is electrically connected to the clock signal line CK3, and a second pole of the control transistor M-3 is electrically connected to the clock signal line CK 6. Referring to fig. 7 to 8c, CS-1 represents a control signal of the control signal terminal CS-1, CS-2 represents a control signal of the control signal terminal CS-2, CS-3 represents a control signal of the control signal terminal CS-3, the control transistors M-1 to M-3 are N-type transistors, the control transistor M-1 can be turned on under the control of the high level of the control signal CS-1 loaded by the control signal terminal CS-1, the control transistor M-2 can be turned on under the control of the high level of the control signal CS-2 loaded by the control signal terminal CS-2, and the control transistor M-3 can be turned on under the control of the high level of the control signal CS-3 loaded by the control signal terminal CS-2.

In the embodiment of the present disclosure, a clock signal and a control signal may correspond to the same signal line group; wherein, each rising edge and each falling edge of the clock signal respectively correspond to the effective level of the control signal. Illustratively, for an active level corresponding to a rising edge of the clock signal, a start time of the active level is located before the corresponding rising edge, and an end time of the active level is located after the corresponding rising edge. And aiming at the effective level corresponding to the falling edge of the clock signal, the starting time of the effective level is positioned before the corresponding falling edge, and the ending time of the effective level is positioned after the corresponding falling edge. For example, referring to FIG. 7 and FIG. 8a, CS-1 represents the control signal of the control signal terminal CS-1, CS-2 represents the control signal of the control signal terminal CS-2, CS-3 represents the control signal of the control signal terminal CS-3, and the high level of the control signals CS-1 to CS-3 can be used as the active level. For the clock signal ck1 and the control signal cs-1 corresponding to the signal line group Z-1, each rising edge and each falling edge of the clock signal ck1 respectively correspond to the high level of the control signal cs-1. In the high level DP11 of the control signal cs-1 corresponding to the rising edge of the clock signal ck1, the start time of the active level DP11 is before the rising edge of the corresponding clock signal ck1, and the end time of the active level DP11 is after the rising edge of the corresponding clock signal ck 1. And a high level DP12 of the control signal cs-1 corresponding to the falling edge of the clock signal ck1, wherein the start time of the high level DP12 is before the falling edge of the corresponding clock signal ck1, and the end time of the high level DP12 is after the falling edge of the corresponding clock signal ck 1.

For example, as shown in FIG. 7 and FIG. 8b, for the clock signal ck2 and the control signal cs-2 corresponding to the signal line group Z-2, each rising edge and each falling edge of the clock signal ck2 correspond to a high level of the control signal cs-2, respectively. In the high level DP21 of the control signal cs-2 corresponding to the rising edge of the clock signal ck2, the start time of the active level DP21 is before the rising edge of the corresponding clock signal ck2, and the end time of the active level DP21 is after the rising edge of the corresponding clock signal ck 2. And a high level DP22 of the control signal cs-2 corresponding to the falling edge of the clock signal ck2, wherein the start time of the high level DP22 is before the falling edge of the corresponding clock signal ck2, and the end time of the high level DP22 is after the falling edge of the corresponding clock signal ck 2.

For example, referring to FIG. 7 and FIG. 8c, for the clock signal ck3 and the control signal cs-3 corresponding to the signal line group Z-3, each rising edge and each falling edge of the clock signal ck3 correspond to a high level of the control signal cs-3, respectively. In the high level DP31 of the control signal cs-3 corresponding to the rising edge of the clock signal ck3, the start time of the active level DP31 is before the rising edge of the corresponding clock signal ck3, and the end time of the active level DP31 is after the rising edge of the corresponding clock signal ck 3. And a high level DP32 of the control signal cs-3 corresponding to the falling edge of the clock signal ck3, wherein the start time of the high level DP32 is before the falling edge of the corresponding clock signal ck3, and the end time of the high level DP32 is after the falling edge of the corresponding clock signal ck 3.

In the embodiment of the disclosure, for an active level corresponding to a rising edge of a clock signal, a first set interval duration is provided between a start time of the active level and the corresponding rising edge, and a second set interval duration is provided between an end time of the active level and the corresponding rising edge. And aiming at the effective level corresponding to the falling edge of the clock signal, a third set interval duration is arranged between the starting time of the effective level and the corresponding falling edge, and a fourth set interval duration is arranged between the ending time of the effective level and the corresponding falling edge. For example, the first set interval duration may be made the same as the third set interval duration; and/or, the second set interval duration may be the same as the fourth set interval duration.

For example, as shown in fig. 7 and 8a, for the high level DP11 of the control signal cs-1 corresponding to the rising edge of the clock signal ck1, the start time of the active level DP11 and the rising edge of the corresponding clock signal ck1 have a first set interval duration ts11, and the end time of the active level DP11 and the rising edge of the corresponding clock signal ck1 have a second set interval duration ts 12. And a high level DP12 of the control signal cs-1 corresponding to the falling edge of the clock signal ck1, wherein a third set interval duration ts13 is provided between the start time of the high level DP12 and the falling edge of the corresponding clock signal ck1, and a fourth set interval duration ts14 is provided between the end time of the high level DP12 and the falling edge of the corresponding clock signal ck 1. The first set interval time period ts11 may be made the same as the third set interval time period ts13, and the second set interval time period ts12 may be made the same as the fourth set interval time period ts 14.

For example, as shown in fig. 7 and 8b, for the high level DP21 of the control signal cs-2 corresponding to the rising edge of the clock signal ck2, the start time of the active level DP21 and the rising edge of the corresponding clock signal ck2 have a first set interval duration ts21, and the end time of the active level DP21 and the rising edge of the corresponding clock signal ck2 have a second set interval duration ts 22. And a high level DP22 of the control signal cs-2 corresponding to the falling edge of the clock signal ck2, wherein a third set interval duration ts23 is provided between the start time of the high level DP22 and the falling edge of the corresponding clock signal ck2, and a fourth set interval duration ts24 is provided between the end time of the high level DP22 and the falling edge of the corresponding clock signal ck 2. The first set interval time period ts21 may be made the same as the third set interval time period ts23, and the second set interval time period ts22 may be made the same as the fourth set interval time period ts 24.

For example, as shown in fig. 7 and 8c, for the high level DP31 of the control signal cs-3 corresponding to the rising edge of the clock signal ck3, the start time of the active level DP31 and the rising edge of the corresponding clock signal ck3 have a first set interval duration ts31, and the end time of the active level DP31 and the rising edge of the corresponding clock signal ck3 have a second set interval duration ts 32. And a high level DP32 of the control signal cs-3 corresponding to the falling edge of the clock signal ck3, wherein a third set interval duration ts33 is provided between the start time of the high level DP32 and the falling edge of the corresponding clock signal ck3, and a fourth set interval duration ts34 is provided between the end time of the high level DP32 and the falling edge of the corresponding clock signal ck 3. The first set interval time period ts31 may be made the same as the third set interval time period ts33, and the second set interval time period ts32 may be made the same as the fourth set interval time period ts 34.

In the embodiment of the disclosure, the first set duration is set after the second set interval corresponding to the same active level of the control signal. And the first set maintaining time length is the half-width time length of the current peak appearing when the rising edge appears on the clock signal line. For example, as shown in conjunction with fig. 7 to 8c, the sum of the first set interval time period ts11 and the second set interval time period ts12 is the set maintenance time period: ts11+ ts12 allows ts11+ ts12 to be half-width long for the current spike on the clock line CK1 when a rising edge occurs. The sum of the first set interval duration ts21 and the second set interval duration ts22 is the first set maintenance duration: ts21+ ts22 allows ts21+ ts22 to be half-width long for the current spike on the clock line CK2 when a rising edge occurs. The sum of the first set interval duration ts31 and the second set interval duration ts32 is the first set maintenance duration: ts31+ ts32 allows ts31+ ts32 to be half-width long for the current spike on the clock line CK3 when a rising edge occurs. It should be noted that, in practical applications, the first set duration may be adjusted according to requirements of practical applications, and is not limited herein.

In the embodiment of the present disclosure, the sum of the third set interval duration and the fourth set interval duration corresponding to the same effective level of the control signal is the second set maintaining duration; the second set hold duration is the full width at half maximum duration of the current spike that occurs when a falling edge occurs on the clock signal line. For example, as shown in conjunction with fig. 7 to 8c, the sum of the third set interval time period ts13 and the fourth set interval time period ts14 is the set maintenance time period: ts13+ ts14 allows ts13+ ts14 to be half-width long in time of the current spike on the clock line CK1 when the falling edge occurs. The sum of the third set interval time period ts23 and the fourth set interval time period ts24 is the set maintenance time period: ts23+ ts24 allows ts23+ ts24 to be half-width long in time of the current spike on the clock line CK2 when the falling edge occurs. The sum of the third set interval time period ts33 and the fourth set interval time period ts34 is the set maintenance time period: ts33+ ts34 allows ts33+ ts34 to be half-width long in time of the current spike on the clock line CK3 when the falling edge occurs. It should be noted that, in practical applications, the second set duration may be adjusted according to requirements of practical applications, and is not limited herein.

The embodiment of the present disclosure also provides a driving method of a display panel, which may include: and inputting clock signals to the plurality of clock signal lines, and conducting the electrically connected time sequence signal lines in response to the effective level of the control signal loaded by the control signal end when the level of the clock signals on the clock signal lines electrically connected with the shared circuit is switched.

Taking the structure shown in fig. 7 as an example, the signal timing diagram is shown in fig. 9. gs-1 represents the signal that controls transistor M-1 to turn on, gs-2 represents the signal that controls transistor M-2 to turn on, and gs-3 represents the signal that controls transistor M-3 to turn on. Under the control of each high level of the control signal cs-1, the transistor M-1 is controlled to be turned on to short-circuit the clock signal lines CK1 and CK4, thereby achieving charge sharing of the clock signal lines CK1 and CK 4. And, under the control of each high level of the control signal cs-2, controlling the transistor M-2 to be turned on to short-circuit the clock signal lines CK2 and CK5, thereby achieving charge sharing of the clock signal lines CK2 and CK 5. And, under the control of each high level of the control signal cs-3, controlling the transistor M-3 to be turned on to short-circuit the clock signal lines CK3 and CK6, thereby achieving charge sharing of the clock signal lines CK3 and CK 6.

In the disclosed embodiment, the first set maintenance period and the second set maintenance period may be the same.

The embodiments of the present disclosure provide other schematic structural diagrams of a display panel, as shown in fig. 10, which are modified from the embodiments in the foregoing embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In the embodiment of the present disclosure, the shared circuit electrically connected to each signal line group may be provided in plurality. And aiming at the shared circuits electrically connected with the same signal line group, except the shared circuit at one end of the clock signal line, which is far away from the bonding area, the other shared circuits are sequentially arranged at intervals at one side of the plurality of clocks, which is far away from the gate drive circuit. Illustratively, the remaining shared circuits corresponding to different signal line groups may be alternately arranged. For example, the shared circuits electrically connected to the same signal line group may be electrically connected to the same control signal terminal. In a specific implementation, the shared circuit electrically connected to each signal line group may be set up; two, three, four or more, without limitation.

Illustratively, as shown in fig. 10, the shared circuits electrically connected to each signal line group are provided in two. The signal line group Z-1 corresponds to the sharing circuits GS-1 and GS-1 ', the sharing circuit GS-1 has a control transistor M-1, the sharing circuit GS-1' has a control transistor M-1 ', and the gates of the control transistor M-1 and the control transistor M-1' are electrically connected to a control signal terminal CS 1. The signal line group Z-2 corresponds to the shared circuits GS-2 and GS-2 ', the shared circuit GS-2 has a control transistor M-2, the shared circuit GS-2' has a control transistor M-2 ', and the gates of the control transistor M-2 and the control transistor M-2' are electrically connected to the control signal terminal CS 2. The signal line group Z-3 corresponds to the shared circuits GS-3 and GS-3 ', the shared circuit GS-3 has a control transistor M-3, the shared circuit GS-3' has a control transistor M-3 ', and the gates of the control transistor M-3 and the control transistor M-3' are electrically connected to the control signal terminal CS 3. The control transistors M-1 ', M-2 ', and M-3 ' are alternately arranged along the extending direction of the clock signal line. This makes it possible to distribute the shared circuits dispersedly in the display panel to avoid concentration of heat generation.

The signal timing diagram shown in fig. 10 can be as shown in fig. 9, and the specific working process thereof can be substantially the same as that described above, and is not described herein again.

It should be noted that, in the prior art, a charge sharing mechanism is applied in the level shift circuit, which mainly solves the power consumption problem of the small-sized display panel, and the charge sharing occurs inside the level shift circuit, which cannot reduce the amount of charge flowing through each clock signal line inside the display panel. In the embodiment of the present disclosure, a charge sharing mechanism is provided to mainly address the problem of heat generation inside the display panel, so as to ensure no or little heat generation. In particular to the heating problem of the display panel with large size, high resolution and high refresh rate.

In specific implementation, in the embodiment of the present disclosure, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

In the display panel and the display device provided by the disclosed embodiments, the non-display region further includes a plurality of sharing circuits. Wherein, divide many clock signal lines into at least one signal line group; the signal line group comprises two clock signal lines; the two clock signal lines in the same signal line group transmit clock signals with opposite levels. And the two clock signal lines in each signal line group are electrically connected through at least one sharing circuit. And the sharing circuit is configured to turn on the electrically connected timing signal line in response to a control signal loaded by the control signal terminal. Therefore, the sharing circuit is arranged in the display panel, a mode of sharing charges of the clock signal line can be adopted, and the technical effect of avoiding serious heating of local positions in the display panel is achieved. Particularly, the technical problem that the local position in the display panel with high resolution and high refresh rate generates heat seriously can be solved, and the quality of the product is improved.

It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.

Claims

1. A display panel, comprising:

a substrate including a display region and a non-display region;

the grid driving circuit is positioned in the non-display area;

2. The display panel of claim 1, wherein the display area comprises a bonding area;

3. The display panel according to claim 2, wherein when there are a plurality of shared circuits electrically connected to each signal line group, for the shared circuits electrically connected to the same signal line group, except for the shared circuit located at the end of the clock signal line away from the bonding area, the other shared circuits are sequentially arranged at intervals on the side of the plurality of clocks newly away from the gate driving circuit.

4. The display panel according to claim 3, wherein the remaining shared circuits corresponding to different signal line groups are alternately arranged.

5. The display panel according to claim 3, wherein the common circuits electrically connected to the same signal line group are electrically connected to the same control signal terminal.

6. The display panel according to any one of claims 1 to 5, wherein one clock signal and control signal correspond to the same signal line group;

7. The display panel of claim 6, wherein for an active level corresponding to a rising edge of the clock signal, a start time of the active level and the corresponding rising edge have a first set interval duration therebetween, and an end time of the active level and the corresponding rising edge have a second set interval duration therebetween;

8. The display panel according to claim 7, wherein the first set interval duration is the same as the third set interval duration; and/or the presence of a gas in the gas,

9. The display panel according to claim 8, wherein a sum of the first set interval duration and the second set interval duration corresponding to a same active level of the control signal is a first set sustain duration; the first set maintaining time length is the half-width time length of a current peak appearing when a rising edge appears on the clock signal line;

10. The display panel according to any one of claims 1 to 5, wherein the shared circuit includes a control transistor;

the control transistor is electrically connected with the control signal end at the grid electrode, the first electrode of the control transistor is electrically connected with one of the two clock signal lines at the clock signal end, and the first electrode of the control transistor is electrically connected with the other of the two clock signal lines at the clock signal end.

11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.

12. A driving method of the display panel according to any one of claims 1 to 10, comprising:

inputting clock signals to the plurality of clock signal lines, and conducting electrically connected timing signal lines in response to the effective level of the control signal loaded by the control signal end when the level of the clock signals on the clock signal lines electrically connected with the shared circuit is switched; wherein the plurality of clock signal lines are divided into at least one signal line group; the signal line group comprises two clock signal lines; the levels of the clock signals transmitted by the two clock signal lines in the same signal line group are opposite.

13. The driving method according to claim 12, wherein one clock signal and control signal corresponding to the same signal line group;

14. The driving method according to claim 13, wherein for an active level corresponding to a rising edge of the clock signal, a start time of the active level and the corresponding rising edge have a first set interval duration therebetween, and an end time of the active level and the corresponding rising edge have a second set interval duration therebetween;

15. The driving method according to claim 14, wherein a sum of the first set interval period and the second set interval period corresponding to a same active level of the control signal is a first set sustain period; the first set maintaining time length is the half-width time length of a current peak appearing when a rising edge appears on the clock signal line;