CN110687731A

CN110687731A - Display panel, driving method and display device

Info

Publication number: CN110687731A
Application number: CN201910967554.1A
Authority: CN
Inventors: 贺俊博; 周良; 张明玮; 章玲玲
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2019-10-12
Filing date: 2019-10-12
Publication date: 2020-01-14

Abstract

The application provides a display panel, a driving aspect and a display device. The display panel comprises a plurality of scanning lines, a plurality of data lines and a plurality of control lines; a plurality of scanning lines and a plurality of data lines are crossed to define a plurality of pixel regions; the pixel region comprises a pixel electrode, a first thin film transistor and a second thin film transistor, wherein the first pole of the first thin film transistor is electrically connected with the data line, the second pole of the first thin film transistor is electrically connected with the first pole of the second thin film transistor, and the second pole of the second thin film transistor is electrically connected with the pixel electrode; the grid electrode of the first thin film transistor is electrically connected with the control line, and the grid electrode of the second thin film transistor is electrically connected with the scanning line; the control lines are electrically connected to each other. The display method and the display device can achieve low-power-consumption display and reduce power consumption of a display maintaining stage.

Description

Display panel, driving method and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel, a driving aspect and a display device.

Background

With the development of display technology, display products are more and more widely applied, and in addition to traditional applications, such as mobile phones and computer monitors, in recent years, display screens are also widely applied to industrial manufacturing, medical treatment, wearing, public area display and the like. Particularly, for industrial manufacturing, medical treatment, wearing, and public area display, the power consumption of the display panel is required to be relatively high, that is, extremely low power consumption is required. Display products such as watches, electronic tags, and bulletin boards are required to consume more power because of their long display time.

Therefore, it is an urgent problem to be solved in the art to provide a display panel with low power consumption.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a low power consumption display panel, a driving method and a display device, so as to solve the technical problem that low power consumption display products are urgently needed in the existing industrial manufacturing, medical treatment, wearing, public area display, and the like.

In one aspect, an embodiment of the present invention provides a display panel, including:

a plurality of scanning lines extending in a first direction and arranged in a second direction;

a plurality of data lines extending in the second direction and arranged in the first direction;

a plurality of control lines;

the plurality of scanning lines and the plurality of data lines intersect to define a plurality of pixel regions;

the pixel region comprises a pixel electrode, a first thin film transistor and a second thin film transistor, wherein a first pole of the first thin film transistor is electrically connected with the data line, a second pole of the first thin film transistor is electrically connected with a first pole of the second thin film transistor, and a second pole of the second thin film transistor is electrically connected with the pixel electrode;

the grid electrode of the first thin film transistor is electrically connected with the control line, and the grid electrode of the second thin film transistor is electrically connected with the scanning line;

each of the control lines is electrically connected to each other.

On the other hand, an embodiment of the present invention further provides a driving method for the display panel, which includes a charging phase and a holding phase, in the charging phase, the scanning line is provided with a scanning signal to turn on the second thin film transistor, and at the same time, the control line is provided with a control signal to turn on the first thin film transistor, and a signal of the data line is written into the pixel electrode; in the holding phase, a control signal is not supplied to the control line while a scan signal is supplied to the scan line, or a scan signal is not supplied to the scan line while a control signal is supplied to the control line.

In another aspect, an embodiment of the present invention further provides a display device.

Compared with the prior art, the display panel, the driving method and the display device provided by the embodiment of the invention have the following technical effects:

1. the leakage current of the thin film transistor can be reduced, and the display effect is improved; 2. the display device can perform low-frequency scanning on a display holding stage, realize low-frequency driving and reduce the power consumption of a display panel; 3. for a display product which is directly connected with the drive control chip, namely, a display product in which all signal lines are electrically connected with an Integrated Circuit (IC) (pin all out), the number of pins corresponding to the scanning lines can be reduced, so that the number of pins corresponding to the drive control chip is reduced, and the power consumption of the drive control chip is reduced; 4. for a display product adopting the shift register, the working frequency of the shift register in a display holding stage can be further reduced, and the power consumption of the display product is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of the array substrate shown in FIG. 1;

FIG. 3 is an enlarged schematic view of region A of FIG. 2;

FIG. 4 is a schematic cross-sectional view along AB of FIG. 3;

FIG. 5 is a schematic view of another structure of the array substrate shown in FIG. 1;

FIG. 6 is a schematic view of another structure of the array substrate shown in FIG. 1;

FIG. 7 is an enlarged schematic view of region B of FIG. 6;

FIG. 8 is a schematic view of another structure of the array substrate shown in FIG. 1;

FIG. 9 is a schematic view of another structure of the array substrate shown in FIG. 1;

fig. 10 is a timing diagram of a charging phase of a driving method of a display panel according to an embodiment of the present disclosure;

fig. 11 is a timing diagram of a hold phase of a driving method of a display panel according to an embodiment of the present application;

fig. 12 is another timing diagram of a hold phase of a driving method of a display panel according to an embodiment of the present application;

fig. 13 is a timing chart of a hold phase of a driving method of a display panel according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a display device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 to 4, fig. 1 is a schematic structural view of a display panel according to an embodiment of the present disclosure, fig. 2 is a schematic structural view of an array substrate shown in fig. 1, fig. 3 is an enlarged structural view of a region a in fig. 2, and fig. 4 is a schematic structural view of a cross section along line AB in fig. 3. The display panel provided in the embodiment of the present invention includes an array substrate 10, a counter substrate 20 disposed opposite to the array substrate 10, and a liquid crystal layer 30 disposed between the array substrate 10 and the counter substrate 20. In the structure shown in fig. 1, the display panel includes a display area AA and a non-display area NAA surrounding the display area AA, wherein the array substrate 10 includes a substrate 100 and a pixel electrode 102 on a side of the substrate 100 facing the opposite substrate 20; the opposite substrate 20 includes a base substrate 200, and a color resist layer, a black matrix layer 202 and a common electrode COM, which are located on a side of the base substrate 200 facing the array substrate 10, and the color resist layer may include a red color resist R, a green color resist G and a blue color resist B. It should be noted that fig. 1 is only one display panel provided in the embodiment of the present invention, but the embodiment of the present invention is not limited thereto. For example, in some other embodiments provided by the embodiments of the present invention, the display function layer of the display panel may be an electrophoretic layer, a plasma layer, or the like; the common electrode COM may be positioned on the array substrate, etc.

Referring further to fig. 1 to 4, the array substrate 10 includes a plurality of scan lines 104, the plurality of scan lines 104 extend along a first direction X and are arranged along a second direction Y; a plurality of data lines 106, the plurality of data lines 106 extending along the second direction Y and arranged along the first direction X; a plurality of control lines 108, a plurality of scan lines 104 and a plurality of data lines 106 crossing to define a plurality of pixel regions P; the pixel region P includes a pixel electrode 102, a first thin film transistor T1 and a second thin film transistor T2, a first pole of the first thin film transistor T1 is electrically connected to the data line 106, a second pole of the first thin film transistor T1 is electrically connected to a first pole of the second thin film transistor T2, and a second pole of the second thin film transistor T2 is electrically connected to the pixel electrode 102; the gate of the first thin film transistor T1 is electrically connected to the control line 108, and the gate of the second thin film transistor T2 is electrically connected to the scan line 104; the individual control lines 108 are electrically connected to each other.

Specifically, in some embodiments provided herein, the data lines 106, the scan lines 104, and the control lines 108 are all electrically connected to an Integrated Circuit (IC). Note that the array substrate 10 is provided with first pads 112 to be bonded to the IC, and the IC is also provided with second pads (not shown) corresponding to the first pads 112 one by one.

In the embodiment provided by the present application, since the pixel electrode 102 in the pixel region P passes through two thin film transistors (the first thin film transistor T1 and the second thin film transistor T2), and gates of the two thin film transistors are connected to different control signal lines, specifically, the gate of the first thin film transistor T1 is connected to the control line 108, the gate of the second thin film transistor T2 is connected to the scan line 104, and the control lines 108 are electrically connected to each other, the display panel provided by the present application has the following advantages: 1. the leakage current of the thin film transistor can be reduced, and the display effect is improved; 2. the display device can perform low-frequency scanning on a display holding stage, realize low-frequency driving and reduce the power consumption of a display panel; 3. for a display product directly connected with the drive control chip, namely a full pin display product, the number of pins corresponding to the scanning lines can be reduced, so that the number of pins corresponding to the drive control chip is reduced, and the power consumption of the drive control chip is reduced; 4. for a display product adopting the shift register, the working frequency of the shift register in a display holding stage can be further reduced, and the power consumption of the display product is further reduced.

Specifically, in some embodiments provided herein, the first direction X and the second direction Y intersect. Further, in other embodiments, the first direction X and the second direction Y are perpendicular to each other.

Specifically, in some embodiments provided herein, the first poles of the first thin film transistors T1 in the same column are electrically connected to one data line 106, and the first thin film transistors T1 in different columns are electrically connected to the data lines 106 in a one-to-one correspondence. Wherein the second direction Y may be a column direction.

Specifically, in some embodiments provided herein, the gates of the second thin film transistors T2 in the same row are electrically connected to one scan line 104, and the second thin film transistors T2 in different rows are electrically connected to the scan lines 104 in a one-to-one correspondence. Wherein the first direction X may be a row direction.

Optionally, in some embodiments provided herein, with continued reference to fig. 2, the display panel includes a display area AA and a non-display area NAA surrounding the display area AA, and each control line 108 is connected to one control bus 110 in the non-display area NAA. Since each control line 108 is connected to one control bus in the non-display area NAA, and is finally connected to the IC through the control bus 108, and the IC is located in the non-display area NAA of the display panel, the control lines 110C can be electrically connected, and meanwhile, the complicated routing is avoided, and the occupation of the control bus 110 on the display area AA is further reduced.

With continued reference to fig. 2, optionally, if the non-display area NAA where the IC is located is defined as a first side area, the non-display area NAA opposite to the first side area is defined as a second side area, and each control line 108 is electrically connected to the control bus 110 in the second side area. It should be noted that, if the control bus 110 and the control bus 108 are located on different metal film layers, it is necessary to implement electrical connection through a via hole, and a certain space is required for setting the via hole, however, the first side region needs to be provided with an IC and also has a lot of signal connection wires connected to the IC, further, since the display panel needs to be sealed and packaged, the second side region inevitably exists, and the second side region does not have complicated and numerous wires, and therefore, the electrical connection position of the control bus 108 and the control bus 110 is set in the second side region, the non-display region NAA can be effectively utilized, and meanwhile, the area of the first side region is not increased, that is, the lower frame is not increased.

Alternatively, in some embodiments provided herein, with continued reference to fig. 2, the plurality of control lines 108 extend along the second direction Y and are arranged along the first direction X. However, the present application is not limited thereto, and in other embodiments provided in the present application, specifically, referring to fig. 5, fig. 5 and fig. 2 are another structural schematic diagram of the array substrate shown in fig. 1, and the plurality of control lines 108 may extend along the first direction X and be arranged along the second direction Y. Since the scan lines 104 extend along the first direction X and the data lines 106 extend along the second direction Y, the control lines 108 are disposed to extend along the first direction X, or extend along the second direction Y, and at this time, the control lines 108 are parallel to the scan lines 104 or the data lines 106, so that the control lines 108 and the scan lines 104 can be disposed at the same layer, or disposed at the same layer as the data lines 106, thereby avoiding an increase in manufacturing process and an increase in manufacturing cost.

Further alternatively, referring to fig. 2 and 5, the non-display area NAA includes a bonding area BA, the bonding area BA includes a plurality of first pads 112, the plurality of data lines 106 are electrically connected to the corresponding plurality of first pads 112, the plurality of scan lines 104 are electrically connected to the corresponding plurality of first pads 112, and the plurality of data lines 106 are electrically connected to the corresponding plurality of first pads 112. In this embodiment, each data line 106 and each scan line 104 of the display panel are electrically connected to the first pad 112, which is a display panel with all pins. In the present embodiment, the IC is also provided with second pads (not shown in the figure) connected in one-to-one correspondence with the first pads 112.

Referring to fig. 6 and 7, fig. 6 is a schematic view of another structure of the array substrate shown in fig. 1, and fig. 7 is an enlarged view of a region B of fig. 6, in which pixel regions P are arranged in a plurality of rows and a plurality of columns according to some embodiments provided herein; the display panel includes a plurality of pixel row groups PP including a first row pixel region PP1 and a second row pixel region PP2 which are adjacently disposed, and between the first row pixel region PP1 and the second row pixel region PP2, a first scan line 104a, a second scan line 104b, and a control line 108 are included, the first scan line 104a is used for controlling the first row pixel region PP1, the second scan line 104b is used for controlling the second row pixel region PP2, and the control line 108 is used for controlling signal writing of the data line 106. In this embodiment, two rows of pixel regions P share one control line 108, which can reduce the number of signal lines in the display region AA and increase the opening area of the pixel regions P.

With continued reference to fig. 6 and 7, the first scan line 104a is located on a side of the control line 108 near the first row of pixel regions PP1, the second scan line 104b is located on a side of the control line 108 near the second row of pixel regions PP2, and the control line 108 is located between the first scan line 104a and the second scan line 104 b. By such an arrangement, the scanning line 104 for controlling the corresponding pixel region P is closest to the corresponding pixel region P, and the control line 108 is located between the two scanning lines 104 and arranged in parallel thereto, so that the cross-over between the signal lines can be avoided, and the control line 108 and the scanning line 104 can be arranged in the same layer. On the other hand, the control line 108 is disposed between the two scan lines 104, and the distance between the control line 108 and the two scan lines 104 is equal, so that the coupling capacitance between the control line 108 and the two scan lines 104 is the same, thereby ensuring that the loads of the two scan lines 104 during signal transmission are the same, and further ensuring that the display effects of the two adjacent rows of pixel regions P are the same.

Specifically, with continued reference to fig. 3, fig. 6 and fig. 7, in the embodiment provided in the present application, the data line 106 serves as one electrode of the first thin film transistor T1, which can further reduce the area of the thin film transistor occupying the display area AA. The scan line 104 serves as a gate of the second thin film transistor T2, and further reduces the area of the thin film transistor occupying the display area AA.

Further referring to fig. 2, 3 and 4, when the control line 108 and the data line 106 are parallel, the control line 108 and the data line 106 may be disposed at the same layer, and the gate g1 of the first thin film transistor T1 is disposed at the same layer as the scan line 104, and the control line 108 and the gate g1 of the first thin film transistor T1 are electrically connected through a via hole penetrating an insulating film between the control line 108 and the gate g 1. One electrode of the first thin film transistor T1 is a source electrode s1, the other electrode thereof is a drain electrode d1, one electrode of the second thin film transistor T2 is a source electrode s2, and the other electrode thereof is a drain electrode d2, wherein the drain electrode d1 of the first thin film transistor T1 simultaneously serves as a source electrode of the second thin film transistor T2, and is electrically connected to the semiconductor a1 of the first thin film transistor T1 and the second thin film transistor a 2.

Optionally, referring to fig. 8, fig. 8 is a schematic structural diagram of another structure of the array substrate shown in fig. 1, the non-display area NAA is provided with a shift register and a clock signal line, the shift register includes a plurality of shift register units 112 connected in cascade, the plurality of scan lines 104 are electrically connected to the plurality of shift register units 104 correspondingly, and the plurality of shift register units 112 are electrically connected to the clock signal line. Specifically, in the structure shown in fig. 8, the control line 108 is located in the non-display area NAA, and specifically, the non-display area NAA includes opposite sides in the first direction X, and the control line 108 may be located only on one side thereof, and on the opposite side of the IC. The clock signal line comprises a first clock signal line CK and a second clock signal line CKB, the first clock signal line CK and the second clock signal line CKB are both square wave signals, and the square wave signals of the first clock signal line CK and the second clock signal line CKB are complementary in time sequence; the shift register further includes a start signal STV; the output end of each stage of shift register unit 112 is connected to the corresponding scan line 104, and the output end of each stage of shift register unit 112 is electrically connected to the input end of the next stage of shift register unit 112 except the last stage. It should be noted that the shift register further includes a low level signal and a high level signal (not shown in the figure)

For a display panel using a shift register, the number of the first pads 112 can be reduced, and specifically, in a general display panel, the number of scan lines is large, for example, even for a small-sized display device such as a wristwatch, the number of scan lines is on the order of several tens to hundreds, but when a shift register is employed, the scan lines are directly connected to the shift register unit, and there is no need to provide the first pads for connection with an IC, and the shift register only needs to provide five first pads for connecting the start signal STV, the low level signal, the high level signal, the first clock signal line CK, and the second clock signal line CKB to the IC.

Optionally, in this embodiment of the present application, the control line 108 may also be a zigzag type. Specifically, referring to fig. 9, fig. 9 is a schematic view of another structure of the array substrate shown in fig. 1, in which the control line 108 includes a plurality of segments, and each segment is parallel to the data line 106 or the scan line 104. The control line 108 of the broken line type may be connected to the control bus 110 in the non-display area NAA.

On the other hand, the embodiment of the application also provides a driving method of the display panel, and the driving method is used for any one of the display panels. Specifically, please refer to fig. 2, 10 and 11, in which fig. 10 is a timing diagram of a charging phase of a driving method of a display panel provided in an embodiment of the present application, and fig. 11 is a timing diagram of a holding phase of the driving method of the display panel provided in the embodiment of the present application, the driving method provided in the embodiment of the present application includes a charging phase and a holding phase, in the charging phase, a scan signal is provided to a scan line 104 to turn on a second thin film transistor T2, and at the same time, a control signal is provided to a control line 108 to turn on the first thin film transistor T1, and a signal of a data line 106 is written to a pixel electrode 102; in the holding phase, a control signal is not supplied to the control line 108 while a scan signal is supplied to the scan line 104, or a scan signal is not supplied to the scan line 104 while a control signal is supplied to the control line 108.

In fig. 10 and 11, the signal timing corresponding to GC represents the signal timing provided by the control line 108, the signal timing corresponding to G1 represents the signal timing provided by the first scan line 104, the signal timing corresponding to G2 represents the signal timing provided by the second scan line 104, and so on, and for a display panel with n scan lines 104, the signal timing corresponding to Gn represents the signal timing provided by the nth scan line 104.

Optionally, the first thin film transistor T1 and the second thin film transistor T2 are both N-type. That is, when the gate signals of the first and second thin film transistors T1 and T2 are at a high level, the first and second thin film transistors T1 and T2 are turned on. In the drawings of the present application, the driving timing signals are given by taking only the first thin film transistor T1 and the second thin film transistor T2 as N-type as an example, but the first thin film transistor T1 and the second thin film transistor T2 may also be P-type in the present application, and at this time, the on signal of the thin film transistor is low level.

Specifically, with further reference to fig. 10 and 11, in the charging phase, scanning signals are sequentially supplied to the plurality of scanning lines 104 in the direction of the pixel region columns, while all the control lines are supplied with control signals; in the holding phase, the scanning signals are supplied to the respective scanning lines 104 at the same time, while the control signals are not supplied to the respective control lines 108, or the control signals are supplied to the respective control lines 108 while the scanning signals are not supplied to the respective scanning lines 104. In this case, in the holding stage, the scan lines 104 do not need to be scanned line by line, but the same timing is provided to all the scan lines 104, so that the IC calculation difficulty can be reduced, and the power consumption in the holding stage can be further reduced.

Note that, in the charging phase, when a signal is supplied to the scan line 104, the control lines 108 are each supplied with a signal so that the first thin film transistor T1 and the second thin film transistor T2 are each turned on, thereby enabling a signal of the data line 106 to be written to the pixel electrode 102. Optionally, the square wave signal of the control signal line 108 has a square wave signal when each scan line 104 has a square wave signal, and the pulse width of the square wave signal of the control line 108 is the same as the pulse width of the square wave signal of the scan line 104.

Further, the pulse width of the square wave signal of the control line 108 in the holding phase is larger than that of the square wave signal in the charging phase, and the control line 108 and all the scan lines 104 are alternately supplied with signals in the holding phase. Further, as shown in fig. 11, in the holding period, the control line 108 is supplied with a signal or the scan line 104 is supplied with a signal so that the first thin film transistor T1 is not turned on and the second thin film transistor T2 is not turned on in the holding period. Since no charging is required in the holding period, the first thin film transistor T1 and the second thin film transistor T2 cannot be turned on at the same time, and if both the first thin film transistor T1 and the second thin film transistor T2 are turned on, the pixel electrode P may leak. However, if the first and second thin film transistors T1 and T2 are turned off or on for a long time, characteristic drift of the thin film transistors may occur, thereby causing leakage of current of the thin film transistors, and therefore, the first and second transistors T1 and T2 are alternately turned on in the sustain period to prevent the characteristic drift of the thin film transistors.

Alternatively, referring to fig. 12, fig. 12 is another timing diagram of a hold phase of a driving method of a display panel provided in the embodiment of the present application, in the hold phase of the display panel, a plurality of blank periods h may be included, in the blank periods h, neither the control line 108 nor the scan line 104 is provided with a signal, that is, neither the first thin film transistor T1 nor the second thin film transistor T2 is turned on. Note that the blank period h and the period in which the thin film transistor is supplied with a signal are distributed at intervals. By the arrangement mode, the thin film transistor can not be turned on or off for a long time, and characteristic drift of the transistor is prevented. On the other hand, in the timing provided in fig. 12, the IC does not need to supply a signal to the signal line in the blank period h, and therefore, the power consumption of the display panel in the holding stage can be further reduced.

Alternatively, when the display panel is provided with a shift register and clock signal lines, with reference to fig. 8 and 13, fig. 13 is still another timing diagram of a holding phase of a driving method of the display panel provided in the embodiment of the present application, in the charging phase, the shift register sequentially provides scan signals to the plurality of scan lines 104, and simultaneously provides control signals to the control lines 108; in the holding phase, the scanning signals are sequentially supplied to the respective scanning lines 104 while the control signals are not supplied to the respective control lines 108, or the control signals are supplied to the respective control lines 108 while the scanning signals are not supplied to the respective scanning lines 104. In fig. 13, the signal timing corresponding to GC represents the signal timing provided by the control line 108, the signal timing corresponding to G1 represents the signal timing provided by the first scan line 104, the signal timing corresponding to G2 represents the signal timing provided by the second scan line 104, and so on, for a display panel with n scan lines 104, the signal timing corresponding to Gn represents the signal timing provided by the nth scan line 104.

For a display panel using a shift register, signals of the scan lines 104 are provided by the shift register, and therefore, without special design, all the scan lines 104 will be scanned sequentially as long as the first stage of the shift register unit is activated. In the charging stage, when the scan line 104 is supplied with a signal, the control lines 108 are each supplied with a signal so that the first thin film transistor T1 and the second thin film transistor T2 are each turned on, thereby enabling a signal of the data line 106 to be written to the pixel electrode 102. Optionally, the square wave signal of the control signal line 108 has a square wave signal when each scan line 104 has a square wave signal, and the pulse width of the square wave signal of the control line 108 is the same as the pulse width of the square wave signal of the scan line 104.

With further reference to fig. 10 and 13, during the charging phase, the plurality of scan lines 104 are sequentially supplied with the scan signal at a frequency f1, and during the holding phase, the plurality of scan lines 104 are sequentially supplied with the scan signal at a frequency f2, f1 being greater than f 2. In the charging stage, the display picture needs to be updated, the scanning frequency can meet the picture updating requirement, and the updating action needs to avoid the perception of human eyes as much as possible, so the scanning frequency is higher; in the holding stage, the display screen does not need to be updated, and the characteristic drift of the thin film transistor is only prevented, so that the power consumption in the holding stage can be reduced by adopting a relatively low scanning frequency, and the power consumption of the display panel can be reduced. For a display panel provided with a shift register, in the timing of the start signal STV, the pitch between pulses in the charge phase is smaller than the pitch in the hold phase, and specifically, the ratio of the pitch in the charge phase to the pitch in the hold phase may be smaller than one third.

In the present embodiment, the "charging phase" refers to a phase in which a screen update is performed, and the "holding phase" refers to a phase in which a screen update is not performed.

Finally, an embodiment of the present application further provides a display device, please refer to fig. 14, fig. 14 is a schematic structural diagram of the display device provided in the present application, and the display device includes the display panel 1000 described above. Further, the driving method described in any one of the above may be adopted.

Specifically, reference may be made to fig. 14, where the display device shown in fig. 14 is a watch, but the embodiment of the present application is not limited to this, and may also be other display devices, for example, a billboard, a label, a display, and the like. In the wristwatch shown in fig. 14, the display panel 1000 may display not only the scale but also other pattern display such as weather, date, motion information, and the like.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, comprising:

a plurality of control lines for controlling the operation of the motor,

each of the control lines is electrically connected to each other.

2. The display panel according to claim 1, comprising a display region, and a non-display region surrounding the display region, wherein each of the control lines is connected to one control bus in the non-display region.

3. The display panel according to claim 2, wherein the plurality of control lines extend in the second direction and are arranged in the first direction, or wherein the plurality of control lines extend in the first direction and are arranged in the second direction.

4. The display panel according to claim 3, wherein the non-display region includes a bonding region, the bonding region includes a plurality of first pads, the plurality of data lines are electrically connected to the corresponding first pads, the plurality of scan lines are electrically connected to the corresponding first pads, and the plurality of data lines are electrically connected to the corresponding first pads.

5. The display panel according to claim 1, wherein the pixel regions are arranged in a plurality of rows and a plurality of columns; the display panel comprises a plurality of pixel row groups, each pixel row group comprises a first row of pixel regions and a second row of pixel regions which are arranged adjacently, a first scanning line, a second scanning line and the control line are arranged between the first row of pixel regions and the second row of pixel regions, the first scanning line is used for controlling the first row of pixel regions, the second scanning line is used for controlling the second row of pixel regions, and the control line is used for controlling signal writing of the data lines.

6. The display panel according to claim 5, wherein the first scan line is located on a side of the control line adjacent to the first row of pixel regions, wherein the second scan line is located on a side of the control line adjacent to the second row of pixel regions, and wherein the control line is located between the first scan line and the second scan line.

7. The display panel according to claim 3, wherein the non-display region is provided with a shift register and a clock signal line, wherein the shift register includes a plurality of shift register units connected in cascade, the plurality of scan lines are electrically connected to the plurality of shift register units, and the plurality of shift register units are electrically connected to the clock signal line.

8. A driving method for the display panel of any one of claims 1 to 7, comprising a charging phase in which the scanning line is supplied with a scanning signal to turn on the second thin film transistor while the control line is supplied with a control signal to turn on the first thin film transistor, and a holding phase in which a signal of the data line is written to the pixel electrode; in the holding phase, a control signal is not supplied to the control line while a scan signal is supplied to the scan line, or a scan signal is not supplied to the scan line while a control signal is supplied to the control line.

9. The driving method according to claim 8, wherein the first thin film transistor and the second thin film transistor are both N-type.

10. The driving method according to claim 8, wherein in the charging phase, scanning signals are sequentially supplied to the plurality of scanning lines in a direction along the pixel region column, and at the same time, all the control lines are supplied with control signals; in the holding phase, a scan signal is simultaneously supplied to each of the plurality of scan lines while no control signal is supplied to each of the control lines, or a control signal is supplied to each of the control lines while no scan signal is supplied to each of the plurality of scan lines.

11. The driving method according to claim 8, wherein when the display panel is provided with a shift register and a clock signal line, in the charging stage, the plurality of scanning lines are sequentially supplied with scanning signals, and at the same time, control signals are supplied to the control lines; in the holding stage, a scanning signal is sequentially supplied to each of the plurality of scanning lines while a control signal is not supplied to each of the control lines, or a control signal is supplied to each of the control lines while a scanning signal is not supplied to the plurality of scanning lines.

12. The driving method as claimed in claim 11, wherein the plurality of scan lines are sequentially supplied with the scan signal at a frequency f1 in the charging phase, and the plurality of scan lines are sequentially supplied with the scan signal at a frequency f2 in the holding phase, wherein f1 is greater than f 2.

13. A display device characterized by comprising the display panel according to any one of claims 1 to 7.

14. A display device according to claim 13, wherein the driving method according to any one of claims 8 to 12 is used.