CN113934062B

CN113934062B - Liquid crystal handwriting board and driving method thereof

Info

Publication number: CN113934062B
Application number: CN202111241141.9A
Authority: CN
Inventors: 葛杨; 王修亮; 赵宇; 王建; 张勇; 王先; 马建威; 石磊; 冯大伟; 关星星; 唐亮珍; 王家星; 武晓娟
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2023-12-08
Anticipated expiration: 2041-10-25
Also published as: CN113934062A

Abstract

The application discloses a liquid crystal handwriting board and a driving method thereof, and belongs to the technical field of display. The liquid crystal handwriting board has a first substrate, which may include: the pixel electrode, the first transistor, the second transistor, the first grid line, the second grid line and the data line are arranged on one side of the first substrate, which is close to the second substrate. In the non-charging phase of the pixel electrode, one of the first transistor and the second transistor is in an off state even if the first level is switched on. Therefore, at least one of the first transistor and the second transistor is not always connected with the second level, so that the problem that the threshold voltage of the first transistor and/or the second transistor is shifted after being in a bias state for a long time is effectively avoided, the stability of the first transistor and/or the second transistor is further improved, and the service life of the liquid crystal handwriting board is prolonged.

Description

Liquid crystal handwriting board and driving method thereof

Technical Field

The application relates to the technical field of display, in particular to a liquid crystal handwriting board and a driving method thereof.

Background

A handwriting board is an electronic device for realizing writing and drawing of characters. Among them, the liquid crystal handwriting board has the advantages of low power consumption and clear handwriting, and has taken up a lot of market share in recent years.

The liquid crystal handwriting pad may generally include: the liquid crystal display device comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate. Wherein the first substrate may include: the liquid crystal display device includes a first substrate, and a plurality of Thin Film Transistors (TFTs) and a plurality of pixel electrodes on the first substrate, wherein the TFTs may be electrically connected to the pixel electrodes. The second substrate may include: a second substrate, and a common electrode on the second substrate. By controlling the TFTs in the area to be erased, a voltage difference can be formed between the pixel electrode and the common electrode in the area to be erased, so that the writing trace in the area to be erased can be locally erased.

However, the stability of the TFT in the current liquid crystal handwriting board is poor, resulting in a lower service life of the liquid crystal handwriting board.

Disclosure of Invention

The embodiment of the application provides a liquid crystal handwriting board and a driving method thereof. The problem of the poor stability of TFT in the liquid crystal handwriting board among the prior art can be solved, the technical scheme is as follows:

In one aspect, a liquid crystal handwriting board is provided, including: a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer between the first substrate and the second substrate;

the first substrate includes: a first substrate, a data line, a first gate line, a second gate line, a first transistor, a second transistor and a pixel electrode, wherein the data line, the first gate line, the second gate line, the first transistor, the second transistor and the pixel electrode are positioned on one side of the first substrate close to the second substrate;

the first electrode of the first transistor is electrically connected with the data line, the second electrode of the first transistor is electrically connected with the first electrode of the second transistor, the second electrode of the second transistor is electrically connected with the pixel electrode, the grid electrode of the first transistor is electrically connected with the first grid line, and the grid electrode of the second transistor is electrically connected with the second grid line.

Optionally, the first substrate has a plurality of pixel areas arranged in an array, and one of the pixel areas is distributed with one of the first transistors, one of the second transistors and one of the pixel electrodes;

and the first grid lines and the second grid lines are distributed between two adjacent rows of pixel areas and are respectively and electrically connected with the grid electrodes of the first transistors and the grid electrodes of the second transistors in the same row of pixel areas.

Optionally, the number of the first gate lines and the number of the second gate lines are multiple, the multiple first gate lines and the multiple second gate lines are electrically connected in a one-to-one correspondence manner, and a row of pixel areas are distributed between the first gate lines and the corresponding second gate lines.

Optionally, the first substrate further includes: and the signal access lines are respectively and electrically connected with the first grid lines and the corresponding second grid lines.

Optionally, the extending direction of the first gate line is parallel to the extending direction of the second gate line, and for the first gate line and the second gate line between two adjacent rows of the pixel regions, the first gate line is far away from the target pixel electrode row relative to the second gate line, and the target pixel row: and a row of pixel regions in which a first transistor electrically connected with the first gate line and a second transistor electrically connected with the second gate line are located in two rows of adjacent pixel regions.

Optionally, the aspect ratio of the channel region of the first transistor is smaller than the aspect ratio of the channel region of the second transistor.

Optionally, the length of the channel region of the first transistor and the length of the channel region of the second transistor are in the range of 4 micrometers to 6 micrometers; the width of the channel region of the first transistor is in the range of 6 microns to 8 microns; the channel region of the second transistor has a width in the range of 100 micrometers to 120 micrometers.

Optionally, the second substrate includes: a second substrate and a common electrode positioned on one side of the second substrate close to the first substrate or on one side of the second substrate far from the first substrate, wherein the second substrate is a flexible substrate;

the first transistor and the second transistor are each configured to: and the data line connected with the first transistor can apply pixel voltage to the pixel electrode connected with the second transistor under the irradiation of target light, so that a voltage difference is formed between the pixel electrode applied with the pixel voltage and the common electrode.

Optionally, the liquid crystal layer comprises bistable liquid crystal molecules configured to: after the liquid crystal handwriting board is subjected to external pressure, the focal conic texture is converted into a planar texture; and after a voltage difference is formed between the pixel electrode and the common electrode in the irradiation area of the target light, converting the planar texture into a focal conic texture.

In another aspect, a driving method of a liquid crystal handwriting board is provided, including: when the liquid crystal handwriting board is in an erasing mode, a first scanning signal and a second scanning signal are respectively input to the first grid line and the second grid line;

Wherein, when the pixel electrode is in a charging stage, the first scanning signal and the second scanning signal are both at a first level; at least part of the pixel electrode is in a non-charging stage, one of the first scanning signal and the second scanning signal is at a first level, and the other is at a second level.

Optionally, the first scan signal and the second scan signal each have a plurality of first levels and a plurality of second levels, and the plurality of first levels and the plurality of second levels are alternately distributed when the pixel electrode is in a non-charging stage.

Optionally, the first levels in the first scan signal and the first levels in the second scan signal are alternately distributed when the pixel electrode is in a non-charging stage, so that the first transistor and the second transistor do not access the first levels at the same time.

Optionally, when the pixel electrode is in the non-charging stage and the first scan signal is at the second level, the first scan signal is at the first level or the second level.

Optionally, when the pixel electrode is in the non-charging stage, the duration of the first scanning signal with the first level is the same as the duration of the second scanning signal with the first level.

Optionally, when the liquid crystal handwriting board is in the writing mode, stopping inputting the first scanning signal and the second scanning signal to the first grid line and the second grid line respectively.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

a liquid crystal handwriting pad comprising: the liquid crystal display device comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate. Wherein the first substrate may include: the pixel electrode, the first transistor, the second transistor, the first grid line, the second grid line and the data line are arranged on one side of the first substrate, which is close to the second substrate. In the application, when the pixel electrode is in a non-charging stage, a plurality of first levels and second levels loaded on the first grid line and the second grid line are alternately distributed, so that one of the first transistor and the second transistor is still in an off state even if the first level is accessed, and the data signal loaded on the data line does not charge the pixel electrode. Therefore, at least one of the first transistor and the second transistor is not always connected with the second level, the problem that the threshold voltage of the first transistor and/or the second transistor is shifted after being in a bias state for a long time is effectively avoided, and even the problem that the first transistor and the second transistor cannot be turned on or turned off can be caused, so that the stability of the first transistor and/or the second transistor is improved, and the service life of the liquid crystal handwriting board is prolonged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a film structure of a liquid crystal handwriting board provided in the related art;

fig. 2 is a top view of a first substrate in the liquid crystal handwriting board shown in fig. 1;

FIG. 3 is a timing diagram of a gate scan signal applied to a gate line as is commonly known in the prior art;

fig. 4 is a schematic diagram of a film structure of a liquid crystal handwriting board according to an embodiment of the present application;

fig. 5 is a top view of a first substrate in the liquid crystal handwriting board shown in fig. 4;

FIG. 6 is a schematic view of the film structure of the first substrate at A-A' shown in FIG. 5;

FIG. 7 is a timing diagram of a first scan signal and a second scan signal according to an embodiment of the present application;

FIG. 8 is a top view of another first substrate according to an embodiment of the present application;

FIG. 9 is an enlarged partial schematic view of the region Q shown in FIG. 8;

Fig. 10 is a top view of a first transistor according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a film structure of another liquid crystal handwriting board according to the embodiment of the application;

fig. 12 is a schematic diagram of a product structure of a liquid crystal handwriting board according to an embodiment of the application;

fig. 13 is a top view of a first substrate in the liquid crystal handwriting board shown in fig. 11.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

In the related art, please refer to fig. 1, fig. 1 is a schematic diagram of a film structure of a liquid crystal handwriting board provided in the related art. The liquid crystal handwriting board 00 may include: a first substrate 01 and a second substrate 02 disposed opposite to each other, and a liquid crystal layer 03 therebetween. The first substrate 01 may generally include: a first substrate 013, a plurality of pixel electrodes 011 and a plurality of TFTs 012 arrayed on the first substrate 013. The second substrate 02 may include: a second substrate 022, and a planar common electrode 021 located on the second substrate 022. The liquid crystal molecules in the liquid crystal layer 03 may be bistable liquid crystal molecules.

Wherein, TFT 012 may include: a gate 012a, a first pole 012b, a second pole 012c, and an active layer 012d. In the TFT 012, the first pole 012b and the second pole 012c overlap with the active layer 012d, and the active layer 012d and the gate electrode 012a are insulated from each other by the gate insulating layer 016. Here, the first pole 012b may be one of a source and a drain, and the second pole 012c may be the other of the source and the drain.

As shown in fig. 2, fig. 2 is a top view of a first substrate in the liquid crystal handwriting board shown in fig. 1. The first substrate may further include: a gate line 014 and a data line 015. The gate line 014 may be electrically connected to the gate electrode 012a of the TFT 012, the data line 015 may be electrically connected to the first electrode 012b of the TFT 012, and the second electrode 012c of the TFT 012 may be electrically connected to the pixel electrode 011. In this way, after an electric signal is applied to the gate 012a of the TFT 012 via the gate line 014 to control the first pole 012b and the second pole 012c of the TFT 012 to be turned on, the electric signal applied to the data line 015 can apply a pixel voltage to the pixel electrode 011 to charge the pixel electrode 011.

When the liquid crystal handwriting board 00 is in a writing mode, the liquid crystal handwriting board 00 is subjected to externally applied pressure, and part of bistable liquid crystal molecules in the liquid crystal layer 03 in the liquid crystal handwriting board 00 are subjected to the pressure to be converted into a planar texture from a focal conic texture. In this way, the liquid crystal molecules transformed into the planar texture can reflect light of a certain wavelength (for example, green light) among the incident ambient light, so that the liquid crystal handwriting pad can display the handwriting.

When the liquid crystal handwriting board 00 is in the erasing mode, the data line 015 of the liquid crystal handwriting board 00 needs to apply pixel voltage to the pixel electrode 011 in the area to be erased, so that a voltage difference can be formed between the pixel electrode 011 and the common electrode 021 in the area to be erased, and bistable liquid crystal molecules in the area to be erased can be rearranged under the action of the voltage difference, that is, the bistable liquid crystal molecules can be converted from a planar texture into a focal conic texture, and further, writing handwriting in the area to be erased can be erased.

For this reason, when the liquid crystal handwriting board 00 is in the erasing mode, the data line 015 and the gate line 014 in the liquid crystal handwriting board 00 need to be loaded with electrical signals to ensure that the pixel electrode 011 in the area to be erased can be loaded with pixel voltage.

The electrical signal applied to the gate line 014 is typically a gate scan signal, which has a high level and a low level. In general, when the gate line 014 is charged with a high level, the active layer 012d between the first pole 012b and the second pole 012c may generate a leakage current, and an electric signal charged on the data line 015 may charge the pixel electrode 011 through the TFT 012, so that a pixel voltage may be charged on the pixel electrode 011; when the gate line 014 is charged with a low level, the TFT 012 is in an off state, and an electric signal charged on the data line 015 cannot charge the pixel electrode 011 through the TFT 012. For this reason, in general, the stage in which the gate line 014 is charged with a high level may be regarded as the pixel electrode 101 being in a charging stage, and the stage in which the gate line 014 is charged with a low level may be regarded as the pixel electrode 101 being in a non-charging stage.

However, referring to fig. 3, fig. 3 is a timing chart of a gate scan signal loaded on a gate line in the prior art. In one scanning period T, the period of time during which the pixel electrode 011 is charged by the TFT 012 is generally much smaller than the off period of the TFT 012, that is, the period of time during which the pixel electrode 101 is in the charging stage T1 is much smaller than the period of time during which the pixel electrode 101 is in the non-charging stage T2. In order to reduce the power consumption of the liquid crystal writing pad 00, the refresh rate of the liquid crystal writing pad 00 is generally low, that is, the duration of one scan period T is long, typically about several hundred milliseconds.

For this reason, the gate 012a in the TFT 012 will be turned on low for a long time, resulting in the TFT 012 being in a biased state for a large part of the time. After the TFT 012 is in the bias state for a long time, the threshold voltage of the TFT 012 turned on may shift, resulting in poor stability of the TFT 012, and even may cause a problem that the TFT 012 cannot be turned on or off, which seriously affects the service life of the liquid crystal handwriting board.

Referring to fig. 4, fig. 4 is a schematic diagram of a film structure of a liquid crystal handwriting board according to an embodiment of the application. The liquid crystal handwriting board 000 may include: the liquid crystal display device includes a first substrate 100 and a second substrate 200 disposed opposite to each other, and a liquid crystal layer 300 between the first substrate 100 and the second substrate 200.

Referring to fig. 5 and 6, fig. 5 is a top view of a first substrate in the liquid crystal handwriting board shown in fig. 4, and fig. 6 is a schematic diagram of a film structure of the first substrate at A-A' shown in fig. 5. The first substrate 100 may include: a first substrate 101, a pixel electrode 102, a first transistor 103, a second transistor 104, a first gate line G1, a second gate line G2, and a data line D on a side of the first substrate 101 near the second substrate 200.

Wherein, the first transistor 103 and the second transistor 104 may be TFTs. To this end, the first transistor 103 and the second transistor 104 each include: the active layer may overlap the first electrode and the second electrode, respectively, and may be insulated from the gate electrode. Here, the first pole in the transistor may be one of the source and the drain, and the second pole may be the other of the source and the drain.

In the embodiment of the present application, the first transistor 103 and the second transistor 104 are bottom gate thin film transistors, which are illustrated schematically. In other alternative implementations, the thin film transistor may also be a top gate thin film transistor, which is not limited by the embodiments of the present application.

In the embodiment of the present application, the first electrode 103b of the first transistor 103 is electrically connected to the data line D, the second electrode 103c of the first transistor 103 may be electrically connected to the first electrode 104b of the second transistor 104, and the second electrode 104c of the second transistor 104 is electrically connected to the pixel electrode 102. The gate 103a of the first transistor 103 is electrically connected to the first gate line G1, and the gate 104a of the second transistor 104 is electrically connected to the first gate line G2.

As such, the first transistor 103 and the second transistor 104 may be two transistors connected in series, and the data line D may be electrically connected to the pixel electrode 102 through the first transistor 103 and the second transistor 104 connected in series.

In the embodiment of the present application, when the liquid crystal handwriting pad is in the erasing mode, the data signal line D, the first gate line G1 and the second gate line G2 may be connected to the data signal, the first scanning signal and the second scanning signal, respectively. In this way, the data signal loaded on the data line D can charge the pixel electrode 102 when both the first scan signal and the second scan signal are at the first level. That is, the pixel electrode 102 is in a charging stage.

The timing of the first scan signal loaded on the first gate line G1 and the timing of the second scan signal loaded on the first gate line G2 may be different. For example, while the pixel electrode 102 is in the charging phase, the first scan signal and the second scan signal are both at the first level; in at least a part of the non-charging phase of the pixel electrode 102, one of the first scan signal and the second scan signal is at a first level, and the other is at a second level.

It should be noted that the first level and the second level only represent that the level of the signal has 2 state amounts, and do not represent that the first level or the second level has a specific value throughout. For example, when the first transistor 103 and the second transistor 104 are both N-type switching transistors, the first level may represent a high level and the second level may represent a low level. The N-type switching transistor is turned on when the grid electrode is at a high level, and turned off when the grid electrode is at a low level.

Referring to fig. 7, fig. 7 is a timing chart of a first scan signal and a second scan signal according to an embodiment of the application. In a scanning period T, when the first scanning signal and the second scanning signal are both at the first level, the data signal loaded on the data line D can charge the pixel electrode 102, so that the pixel electrode 102 can load the pixel voltage, and the pixel electrode 102 is in the charging stage T1; when one of the gate 103a of the first transistor 103 and the gate 104a of the second transistor 104 is at the first level and the other is at the second level, the first transistor 103 and one of the second transistor 104 are in the off state, the data signal loaded on the data line D cannot charge the pixel electrode 102, and the pixel electrode 102 is in the non-charging stage T2.

In this case, in the non-charging period T2 of the pixel electrode 102, one of the first transistor 103 and the second transistor 104 is in an off state even if the first level is turned on, so that the data signal loaded on the data line D does not charge the pixel electrode 102. For this reason, at least one of the first transistor 103 and the second transistor 104 is not always connected to the second level when the pixel electrode 102 is in the non-charging stage T2, so that the problem that the threshold voltage of the first transistor 103 and/or the second transistor 104 is shifted after being in the bias state for a long time is effectively avoided, and further the stability of the first transistor 103 and/or the second transistor 104 is improved, and the service life of the liquid crystal handwriting board 000 is ensured to be longer.

In the present application, when the pixel electrode 102 is in the non-charging period T2, the first scan signal and the second scan signal each have a plurality of first levels and a plurality of second levels, and the plurality of first levels and the plurality of second levels are alternately distributed. In this way, both the first transistor 103 and the second transistor 104 are turned on at the first level when the pixel electrode 102 is in the non-charging stage T2, and one of the first scan signal and the second scan signal is at the first level and the other is at the second level, so as to ensure that one of the first transistor 103 and the second transistor 104 is in the off state when the pixel electrode 102 is in the non-charging stage. In this case, neither the first transistor 103 nor the second transistor 104 is connected to the first level or the second level for a long period of time, further improving the stability of the first transistor 103 and the second transistor 104.

Optionally, in the non-charging phase T2 of the pixel electrode 102, the first levels in the first scan signal and the first levels in the second scan signal are alternately distributed, so as to ensure that the first transistor 103 and the second transistor 104 do not access the first levels at the same time.

In the embodiment of the present application, when the pixel electrode 102 is in the non-charging phase T2, the first scan signal may be at the first level or the second level when the first scan signal is at the second level. That is, when the first transistor 103 is connected to the second level, the second transistor 104 may be connected to the second level or the first level.

Optionally, in the non-charging phase T2 of the pixel electrode 102, the duration of the first scan signal at the first level is the same as the duration of the second scan signal at the first level. That is, the duration of the first transistor 103 switching on the first level is the same as the duration of the second transistor 104 switching on the first level. In this manner, the stability of the first transistor 103 and the second transistor 104 can be ensured to be substantially uniform.

In summary, an embodiment of the present application provides a liquid crystal handwriting board, including: the liquid crystal display device comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate. Wherein the first substrate may include: the pixel electrode, the first transistor, the second transistor, the first grid line, the second grid line and the data line are arranged on one side of the first substrate, which is close to the second substrate. In at least part of the non-charging phase of the pixel electrode, one of the first scanning signal loaded on the first grid line and the second scanning signal loaded on the second grid line is at a first level, the other scanning signal is at a second level, so that one of the first transistor and the second transistor is still in an off state even if the first level is accessed, and the data signal loaded on the data line does not charge the pixel electrode. Therefore, at least one of the first transistor and the second transistor is not always connected with the second level, so that the problem that the threshold voltage of the first transistor and/or the second transistor is shifted after being in a bias state for a long time is effectively avoided, the stability of the first transistor and/or the second transistor is further improved, and the service life of the liquid crystal handwriting board is prolonged.

In the embodiment of the present application, referring to fig. 5, a first substrate 101 of a first substrate 100 has a plurality of pixel regions 100a arranged in an array, and a first transistor 103, a second transistor 104 and a pixel electrode 102 are distributed in one pixel region 100a. Here, one first transistor 103, one second transistor 104, and one pixel electrode 102 distributed within each pixel region 100a may also be generally referred to as one pixel.

The number of the data lines D, the first gate lines G1, and the second gate lines G2 in the first substrate 100 is plural, and a region surrounded by any two adjacent data lines D and any two adjacent gate lines (may be the first gate line G1 or the second gate line G2) is a pixel region 100a.

In the present application, a data line D may be distributed between two adjacent rows of pixel regions 100a, and the data line D may be electrically connected to one row of pixels. For example, the data line D may be electrically connected to the first electrode 103b of each first transistor 103 within a column of the pixel region 100a.

A first gate line G1 and a second gate line G2 may be distributed between two adjacent rows of pixel regions 100a, and the first gate line G1 and the second gate line G2 between two adjacent rows of pixel regions 100a may be electrically connected to the pixels of the same row. For example, the first gate line G1 and the second gate line G2 may be electrically connected to the gate 103a of each first transistor 103 and the gate 104a of each second transistor 104 in the same row of pixel regions 100a, respectively. In this case, after the first scan signal and the second scan signal are respectively applied to the first gate line G1 and the second gate line G2 between the two adjacent pixel regions 100a, when the first scan signal and the second scan signal are at the first level, leakage current is generated in the active layer 103d of the first transistor 103 and the active layer 104d of the second transistor 104 in the same row of pixel regions 100a. If a data signal is applied to the data line D electrically connected to a certain pixel electrode 102 in the row of pixel regions 100a, the data signal applied to the data line D can charge the pixel electrode 102.

Optionally, referring to fig. 8, fig. 8 is a top view of another first substrate according to an embodiment of the present application. The first gate lines G1 and the second gate lines G2 in the first substrate 100 may be electrically connected in a one-to-one correspondence, and a row of pixel regions 100a are distributed between the first gate lines G1 and the corresponding second gate lines G2.

In this case, even though the first and second gate lines G1 and G2 in the first substrate 100 of the embodiment of the present application need to be electrically connected to one row of pixels at the same time, the number of gate lines is twice that of the first substrate in the related art, in the first substrate 100 of the embodiment of the present application, each first gate line G1 and the corresponding second gate line G2 are electrically connected, and the first gate line G1 and the second gate line G2 electrically connected to each other can be connected to the same signal output terminal. In this way, it is ensured that the number of signal output terminals of the first substrate 100 for outputting the scan signal in the embodiment of the present application is half the number of gate lines, and the number of signal output terminals is not increased.

By way of example, the first substrate 100 may further include: the signal access lines 105 may be electrically connected to the first gate lines G1 and the corresponding second gate lines G2, respectively. Thus, the first gate line G1 and the second gate line G2 electrically connected to each other may be electrically connected to the same signal access terminal through the signal access line 105.

Alternatively, please refer to fig. 9, fig. 9 is a partially enlarged schematic view of the Q region shown in fig. 8. The extending direction of the first gate line G1 is parallel to the extending direction of the second gate line G2, and for the first gate line G1 and the second gate line G2 between two adjacent rows of pixel regions 100a, the first gate line G1 is distant from the target pixel electrode row with respect to the second gate line G2. The target pixel electrode is arranged in a row of pixel regions where the first transistor 103 electrically connected to the first gate line G1 and the second transistor 104 electrically connected to the second gate line G2 are located in two rows of adjacent pixel regions 100 a.

In the present application, the arrangement direction of the first transistor 103 and the second transistor 104 may be perpendicular to the extending direction of the data line D. In this way, the first gate line G1 may be directly electrically connected to the gate electrode 103a of the first transistor 103, and the second gate line G2 may be directly electrically connected to the gate electrode 104a of the second transistor 104. Thus, the first gate line G1 and the gate electrode 103a of the first transistor 103 can be electrically connected without passing through the transfer electrode, and the second gate line G2 and the gate electrode 104a of the second transistor 104 can be electrically connected, so that the manufacturing difficulty of the liquid crystal handwriting board 000 is simplified.

In the related art, as shown in fig. 1 and 2, when the liquid crystal handwriting board 00 adopts the optical erasing technique, an erasing tool capable of emitting a target light may be used to erase writing lines presented on the liquid crystal handwriting board 00. In this case, when the liquid crystal writing pad 00 is in the erase mode, the gate line 014 needs to load the gate scan signal, and the voltage of the gate scan signal at the high level is small, so that the active layer 012d of the TFT 012 generates a leakage current when the gate scan signal is at the high level, but the leakage current is generally small. After the active layer 012d of the TFT 012 is irradiated by the target light, the active layer 012d generates carriers, so that the leakage current on the active layer 012d increases, the TFT 012 may be in an on state, and the electric signal loaded on the data line 015 may charge the pixel electrode 011 through the TFT 012, so that the pixel electrode 011 may load the pixel voltage. In this way, a voltage difference is generated between the pixel electrode 011 and the common electrode 021 in the area irradiated by the target light, so that bistable liquid crystal molecules in the area irradiated by the target light can be converted from planar texture into focal conic texture, and writing in the area irradiated by the target light can be erased.

However, the liquid crystal writing pad 00 using the optical erasing technique is loaded with an electrical signal on both the gate line 014 and the data line 015 when in the erasing mode. Although the electrical signal loaded on the gate line 014 is insufficient to make the TFT 012 fully turned on, a leakage current still occurs on the active layer 012d of the TFT 012, so that the data signal loaded on the data line 015 may charge the pixel electrode 011 in the non-erasing area, and further the phenomenon of shallowing writing in the non-erasing area may occur, which seriously affects the display effect of the liquid crystal handwriting board.

In order to solve the problem that the writing trace in the non-erasing area of the liquid crystal writing pad in the related art becomes shallow, the channel regions of the first transistor 103 and the second transistor 104 in the first substrate 100 in the present application need to be designed. Meanwhile, in order to facilitate understanding of the contents of the following examples, the following examples will first explain the names of professionals to which the present application relates.

Referring to fig. 10, fig. 10 is a top view of a first transistor according to an embodiment of the present application. The active layer 103d in the first transistor 103 has a channel region, which refers to a region of the active layer 103d between a first region where the active layer 103d contacts the first electrode 103b and a second region where the active layer 103d contacts the second electrode 103 c. The length L of the channel region refers to the distance between the first region and the second region, and the width W of the channel region refers to the smaller length of the first region and the second region. The width-to-length ratio W/L of the channel region of the first transistor 103 refers to the ratio between the width W of the channel region of the first transistor 103 and the length L of the channel region of the first transistor 103, and the larger the value of the width-to-length ratio W/L of the channel region, the smaller the resistance between the first pole 103b and the second stage 103c in the first transistor 103, the larger the magnitude of the leakage current that can be transmitted between the two; conversely, the smaller the value of the width-to-length ratio W/L of the channel region, the smaller the magnitude of the leakage current transferred between the first pole 103b and the second pole 103c in the first transistor 103. It should be noted that the active layer 104d in the second transistor 104 also has a channel region, and the related meaning of the channel region of the active layer 104d is the same as that of the channel region of the active layer 103d of the first transistor 103, which is not described herein.

In an embodiment of the present application, the aspect ratio of the channel region of the first transistor 103 may be smaller than the aspect ratio of the channel region of the second transistor 104. It should be noted that, in order to ensure current transmission of the transistor in the on state, the length of the channel region of the transistor is generally fixed, for example, the length of the channel region of the transistor is in the range of 4 micrometers to 6 micrometers. For this, the length of the channel region of the first transistor 103 may be equal to the length of the channel region of the second transistor 104, so that after ensuring that the width of the channel region of the first transistor 103 is smaller than the width of the channel region of the second transistor 104, the aspect ratio of the channel region of the first transistor 103 is smaller than the aspect ratio of the channel region of the second transistor 104.

In this case, the channel region of the first transistor 103 electrically connected to the data signal line D has a small width to length ratio. In this way, when the gate 103a of the first transistor 103 is loaded with the first scanning signal, the magnitude of the leakage current generated by the active layer 103d of the first transistor 103 can be further reduced, so that the magnitude of the pixel voltage applied to the pixel electrode 102 in the non-erasing area is further reduced, the probability of the phenomenon that writing in the non-erasing area becomes shallow is reduced, and the display effect of the liquid crystal handwriting board 000 is effectively improved.

And the channel region of the second transistor 104 electrically connected to the pixel electrode 102 has a relatively large width. In this way, when the target light irradiates the region to be erased, carriers are generated in both the channel region of the first transistor 103 and the second transistor 104, and the number of carriers generated in the channel region of the second transistor 104 is large. Since the data line D is loaded with the data signal, carriers generated in the channel region of the second transistor 104 can flow in the direction of the pixel electrode 102 under the action of the data signal, so that the magnitude of the leakage current generated by the active layer 104D of the second transistor 104 can be increased, and the data signal loaded on the data line D can be ensured to normally charge the pixel electrode 102. In this way, pixel voltages can be applied to the pixel electrode 102 in the area to be erased, so that writing traces in the area to be erased can be erased.

By way of example, the length of the channel region of the first transistor 103 and the length of the channel region of the second transistor 104 are in the range of 4 micrometers to 6 micrometers; the width of the channel region of the first transistor 103 is in the range of 6 micrometers to 8 micrometers; the width of the channel region of the second transistor 104 is in the range of 100 micrometers to 120 micrometers. Also, the size of the pixel region 101a of the first substrate 100 may be 1×1 mm. In this way, it is ensured that the pixel electrode 102 in a certain pixel region can be normally charged by loading the data signal on the data line D when the target light irradiates the pixel region on the premise of ensuring that the leakage current generated by the active layer 103D of the first transistor 103 is small when the gate electrode 103a of the first transistor 103 is loaded with the first scanning signal.

In the embodiment of the present application, as shown in fig. 11, fig. 11 is a schematic diagram of a film structure of another liquid crystal handwriting board provided by the embodiment of the present application. The second substrate 200 in the liquid crystal handwriting board 000 may include: the second substrate 201, the common electrode 202 located on a side of the second substrate 201 close to the first substrate 100 or on a side of the second substrate 201 remote from the first substrate 100. The liquid crystal layer 300 in the liquid crystal writing pad 000 may include bistable liquid crystal molecules. In the present application, the common electrode 202 is illustrated as being close to the first substrate 100 with respect to the second substrate 201.

When the liquid crystal handwriting board 000 is in the writing mode, no electric signals are loaded on the data line D, the first grid line G1 and the second grid line G2 in the first substrate 100, that is, no voltage is applied on the data line D, the first grid line G1 and the second grid line G2, so that lower power consumption of the liquid crystal handwriting board 000 can be ensured. By way of example, bistable liquid crystal molecules in liquid crystal handwriting pad 000 may be configured to: when the liquid crystal writing pad 000 is subjected to external pressure, the focal conic texture is changed into a planar texture. For example, when a user writes on the liquid crystal writing pad 000 through a writing tool (e.g., a writing pen), the user may apply pressure to the liquid crystal writing pad 000 through the writing tool, so that bistable liquid crystal molecules in a region of the liquid crystal writing pad 000 subjected to the pressure are converted from a focal conic texture to a planar texture. In this case, the bistable liquid crystal molecules in a planar texture can reflect light of a certain wavelength (e.g., green light) among the ambient light irradiated on the liquid crystal writing pad 000, so that the liquid crystal writing pad 000 can display the corresponding writing.

The data line D, the first gate line G1, and the second gate line G2 in the first substrate 100 may be loaded with a data signal, a first scan signal, and a second scan signal, respectively, when the liquid crystal handwriting panel 000 is in the erase mode. By way of example, the first transistor 103 and the second transistor 104 in the liquid crystal handwriting pad 000 are each configured to: the data line D connected to the first transistor 103 is turned on under the irradiation of the target light, so that the pixel electrode 102 connected to the second transistor 104 can be charged, so as to ensure that the pixel voltage is applied to the pixel electrode 102, and further, a voltage difference is formed between the pixel electrode 102 to which the pixel voltage is applied and the common electrode 202.

The bistable liquid crystal molecules may also be configured to: after a voltage difference is formed between the pixel electrode 102 and the common electrode 202 in the irradiation region of the target light, the planar texture is changed into the focal conic texture. For example, when a user erases on the liquid crystal handwriting board 000 by using an erasing tool capable of emitting the target light, the user can emit the target light to the liquid crystal handwriting board 000 by using the erasing tool, and a voltage difference is formed between the pixel electrodes 102 in the irradiation area of the target light in the liquid crystal handwriting board 000 and the common 202, so that bistable liquid crystal molecules in the irradiation area of the target light in the liquid crystal handwriting board 000 are restored from a planar texture to a focal conic texture. In this way, bistable liquid crystal molecules with focal conic texture can transmit ambient light irradiated on the liquid crystal writing pad 000 to erase writing in the irradiation area of the target light. Thus, the irradiation area of the target light is the area to be erased.

It should be noted that, the light intensity of the target light needs to be greater than the light intensity of the ambient light, so as to ensure that the first transistor 103 and the second transistor 104 are turned on only under the irradiation of the target light, and are not turned on under the irradiation of the ambient light.

Alternatively, as shown in fig. 12, fig. 12 is a schematic diagram of a product structure of a liquid crystal handwriting board according to an embodiment of the application. The liquid crystal handwriting board 000 may further include: switch 400 is switched. Wherein the switch 400 is used to control the liquid crystal writing pad 000 to switch between the erasing mode and the writing mode. When the liquid crystal handwriting board 000 is in a writing mode, the liquid crystal handwriting board 000 is in a non-powered state, and no electric signals are loaded on the data line D, the first grid line G1 and the second grid line G2; when the liquid crystal handwriting board 000 is in the erasing mode, the liquid crystal handwriting board 000 is in a power-on state, and the data line D, the first grid line G1 and the second grid line G2 are all required to be loaded with electrical signals. Thus, only when the liquid crystal handwriting board 000 is in the erasing mode, the liquid crystal handwriting board 000 needs to consume electric energy, and the power consumption of the liquid crystal handwriting board 000 is effectively reduced.

In the embodiment of the present application, as shown in fig. 11 and 13, fig. 13 is a top view of a first substrate in the liquid crystal handwriting board shown in fig. 11. The first substrate 100 in the liquid crystal handwriting board 000 may further include: the auxiliary electrode line 106 is disposed on a side of the first substrate 101 adjacent to the second substrate 200, the auxiliary electrode line 106 may be disposed on the same layer as the first gate line G1 and the second gate line G2, and an extending direction of the auxiliary electrode line 106 is parallel to an extending direction of the first gate line G1.

For example, the pixel electrodes 102 in the first substrate 100 are arranged in a plurality of rows, and the number of the auxiliary electrode lines 106 in the first substrate 100 is the same as the number of rows of the pixel electrodes 102. The front projection of each auxiliary electrode line 106 on the first substrate 101 overlaps with the front projection of a corresponding row of pixel electrodes 102 on the first substrate 101, and the auxiliary electrode line 106 may constitute a storage capacitor Cst with each pixel electrode 102 of the row of pixel electrodes 102. The storage capacitor Cst may be used to maintain the pixel voltage of the pixel electrode 102, so that when the liquid crystal writing pad 000 is erased, the storage capacitor Cst may prevent the voltage of the pixel electrode 102 in the pixel area to be erased from changing, and may affect the voltage of the pixel electrode 102 around the pixel area to be erased, thereby preventing the display effect of the pixel area around the pixel area to be erased from being affected.

Optionally, as shown in fig. 11, the first substrate 100 may further include: a gate insulating layer 107, a first insulating layer 108, and a second insulating layer 109.

Wherein the gate insulating layer 107 may be located between the gate electrode and the active layer of the transistor. For example, the gate electrode 103a and the active layer 103d of the first transistor 103 may be insulated by a gate insulating layer, and the gate electrode 104a and the active layer 104d of the second transistor 104 may be insulated by a gate insulating layer.

The first insulating layer 108 may be located between the transistor and the pixel electrode 102. Here, the pixel electrode 102 may be located on the first insulating layer 108, and the first insulating layer 108 can not only protect the transistor but also improve the flatness of the pixel electrode 102. In this case, the first insulating layer 108 has a connection via hole through which the pixel electrode 102 can be electrically connected to the second electrode 1014c in the second transistor 104.

The second insulating layer 109 is located at a side of the pixel electrode 102 remote from the first substrate 101. When the first substrate 100 and the second substrate 200 are disposed opposite to each other, since the device environment is not a dust-free environment, a foreign material may be generated between the first substrate 100 and the second substrate 200, and the second insulating layer 109 may be used to prevent the foreign material between the first substrate 100 and the second substrate 200 from conducting the pixel electrode 102 in the first substrate 100 and the common electrode 202 in the second substrate 200.

In an embodiment of the present application, as shown in fig. 11, the materials of the common electrode 202 in the second substrate 200 and the pixel electrode 102 in the first substrate 100 may include: transparent conductive materials such as Indium Tin Oxide (ITO) or Indium zinc Oxide (Indium Zinc Oxide) and IZO. The first substrate 101 in the first base plate 100 may be a rigid substrate, for example, the first substrate 101 may be a glass base; the second substrate 201 in the second base plate 200 may be a flexible substrate, and for example, the second substrate 201 may be a polyethylene terephthalate (english: polyethylene Terephthalate; abbreviated as PET) base.

The embodiment of the application also provides a driving method of the liquid crystal handwriting board, which is applied to the liquid crystal handwriting board in the embodiment. The liquid crystal handwriting board is exemplified by the liquid crystal handwriting boards shown in fig. 4 and 11.

The driving method of the liquid crystal handwriting board may include: when the liquid crystal handwriting board is in an erasing mode, a first scanning signal and a second scanning signal are respectively input to the first grid line and the second grid line.

It should be noted that, the timing diagrams of the first scan signal and the second scan signal may refer to the timing diagram shown in fig. 7.

Optionally, the driving method of the liquid crystal handwriting board may include: and when the liquid crystal handwriting board is in a writing mode, stopping inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line respectively.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working principle of the driving method of the liquid crystal handwriting board described above may refer to the corresponding parts in the structural embodiment of the liquid crystal handwriting board described above, and will not be described herein again.

It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.

In the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but is intended to cover all modifications, equivalents, alternatives, and improvements falling within the spirit and principles of the application.

Claims

1. A liquid crystal handwriting board, comprising: a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer between the first substrate and the second substrate;

the first electrode of the first transistor is electrically connected with the data line, the second electrode of the first transistor is electrically connected with the first electrode of the second transistor, the second electrode of the second transistor is electrically connected with the pixel electrode, the grid electrode of the first transistor is electrically connected with the first grid line, and the grid electrode of the second transistor is electrically connected with the second grid line;

The channel region of the first transistor has a smaller aspect ratio than the second transistor.

2. The liquid crystal display panel according to claim 1, wherein the first substrate has a plurality of pixel areas arranged in an array, and one of the pixel areas is distributed with one of the first transistor, one of the second transistor and one of the pixel electrodes;

3. The liquid crystal display panel according to claim 2, wherein the number of the first grid lines and the number of the second grid lines are multiple, the multiple first grid lines and the multiple second grid lines are electrically connected in a one-to-one correspondence manner, and a row of pixel areas are distributed between the first grid lines and the corresponding second grid lines.

4. The liquid crystal display tablet of claim 3 wherein the first substrate further comprises: and the signal access lines are respectively and electrically connected with the first grid lines and the corresponding second grid lines.

5. The liquid crystal display panel according to claim 2, wherein an extending direction of the first gate line is parallel to an extending direction of the second gate line, and for the first gate line and the second gate line between the pixel regions adjacent to two rows, the first gate line is distant from a target pixel electrode row with respect to the second gate line, the target pixel row: and a row of pixel regions in which a first transistor electrically connected with the first gate line and a second transistor electrically connected with the second gate line are located in two rows of adjacent pixel regions.

6. The liquid crystal display panel according to any one of claims 1 to 5, wherein a length of a channel region of the first transistor and a length of a channel region of the second transistor are in a range of 4 micrometers to 6 micrometers; the width of the channel region of the first transistor is in the range of 6 microns to 8 microns; the channel region of the second transistor has a width in the range of 100 micrometers to 120 micrometers.

7. The liquid crystal display panel of any one of claims 1 to 5, wherein the second substrate comprises: a second substrate and a common electrode positioned on one side of the second substrate close to the first substrate or on one side of the second substrate far from the first substrate, wherein the second substrate is a flexible substrate;

8. The liquid crystal handwriting pad of claim 7 wherein the liquid crystal layer comprises bistable liquid crystal molecules configured to: after the liquid crystal handwriting board is subjected to external pressure, the focal conic texture is converted into a planar texture; and after a voltage difference is formed between the pixel electrode and the common electrode in the irradiation area of the target light, converting the planar texture into a focal conic texture.

9. A driving method of a liquid crystal handwriting board, which is applied to the liquid crystal handwriting board of any one of claims 1 to 8, the method comprising:

when the liquid crystal handwriting board is in an erasing mode, a first scanning signal and a second scanning signal are respectively input to the first grid line and the second grid line;

10. The method of claim 9, wherein the first scan signal and the second scan signal each have a plurality of first levels and a plurality of second levels, the plurality of first levels and the plurality of second levels being alternately distributed while the pixel electrode is in a non-charging phase.

11. The method of claim 10, wherein the plurality of first levels in the first scan signal alternate with the plurality of first levels in the second scan signal such that the first transistor and the second transistor do not simultaneously access the first levels while the pixel electrode is in a non-charging phase.

12. The method of claim 11, wherein the first scan signal is at a first level or a second level when the first scan signal is at a second level while the pixel electrode is in a non-charging phase.

13. The method of claim 11, wherein a duration of the first scan signal being at the first level is the same as a duration of the second scan signal being at the first level while the pixel electrode is in the non-charging phase.

14. The method according to any one of claims 9 to 13, characterized in that the method comprises:

And when the liquid crystal handwriting board is in a writing mode, stopping inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line respectively.