CN113934062A

CN113934062A - Liquid crystal handwriting board and driving method thereof

Info

Publication number: CN113934062A
Application number: CN202111241141.9A
Authority: CN
Inventors: 葛杨; 王修亮; 赵宇; 王建; 张勇; 王先; 马建威; 石磊; 冯大伟; 关星星; 唐亮珍; 王家星; 武晓娟
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2022-01-14
Anticipated expiration: 2041-10-25
Also published as: CN113934062B

Abstract

The application discloses a liquid crystal handwriting board and a driving method thereof, and belongs to the technical field of display. The liquid crystal writing pad has a first substrate, which may include: the pixel structure comprises a first substrate, a pixel electrode, a first transistor, a second transistor, a first grid line, a second grid line and a data line, wherein the pixel electrode, the first transistor, the second transistor, the first grid line, the second grid line and the data line are positioned on one side of the first substrate, which is close to a second substrate. When the pixel electrode is in a non-charging stage, one of the first transistor and the second transistor is in an off state even if the other of the first transistor and the second transistor is switched to the first level. Therefore, at least one of the first transistor and the second transistor is not always connected to the second level, the problem that the threshold voltage of the first transistor and/or the second transistor is shifted after the first transistor and/or the second transistor are in a bias state for a long time is effectively avoided, the stability of the first transistor and/or the second transistor is improved, and the service life of the liquid crystal handwriting board is prolonged.

Description

Liquid crystal handwriting board and driving method thereof

Technical Field

The application relates to the technical field of display, in particular to a liquid crystal handwriting board and a driving method thereof.

Background

A handwriting pad is an electronic device for implementing writing and drawing of characters. Among them, the liquid crystal writing pad has the advantages of low power consumption and clear handwriting, and occupies more market share in recent years.

Liquid crystal writing tablets may generally include: the liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate. Wherein the first substrate may include: the liquid crystal display device comprises a first substrate, and a plurality of Thin-film transistors (TFTs) and a plurality of pixel electrodes, wherein the TFTs and the pixel electrodes are located on the first substrate, and the TFTs can be correspondingly and electrically connected with the pixel electrodes. The second substrate may include: a second substrate, and a common electrode on the second substrate. By controlling the TFT in the area to be erased, a voltage difference can be formed between the pixel electrode and the common electrode in the area to be erased, so that the writing in the area to be erased can be partially erased.

However, the stability of the TFT in the current liquid crystal writing pad is poor, which results in a short service life of the liquid crystal writing pad.

Disclosure of Invention

The embodiment of the application provides a liquid crystal handwriting board and a driving method thereof. The problem that the stability of a TFT in a liquid crystal handwriting board in the prior art is poor can be solved, and the technical scheme is as follows:

in one aspect, a liquid crystal writing pad is provided, including: the liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate;

the first substrate includes: the liquid crystal display panel comprises a first substrate, and a data line, a first grid line, a second grid line, a first transistor, a second transistor and a pixel electrode which are positioned on one side of the first substrate close to a second substrate;

wherein a first electrode of the first transistor is electrically connected to the data line, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor, a second electrode of the second transistor is electrically connected to the pixel electrode, a gate electrode of the first transistor is electrically connected to the first gate line, and a gate electrode of the second transistor is electrically connected to the second gate line.

Optionally, the first substrate has a plurality of pixel regions arranged in an array, and one of the first transistors, one of the second transistors, and one of the pixel electrodes are arranged in one of the pixel regions;

one first grid line and one second grid line are distributed between two adjacent rows of pixel regions, and the first grid line and the second grid line which are positioned between the two adjacent rows of pixel regions are respectively and electrically connected with the grid electrode of each first transistor and the grid electrode of each second transistor in the same row of pixel regions.

Optionally, the number of the first gate lines and the number of the second gate lines are both multiple, the multiple first gate lines and the multiple second gate lines are electrically connected in a one-to-one correspondence manner, and a row of the pixel regions is distributed between the first gate lines and the corresponding second gate lines.

Optionally, the first substrate further includes: and the signal access lines are electrically connected with the first grid lines and the corresponding second grid lines respectively.

Optionally, an extending direction of the first gate line is parallel to an extending direction of the second gate line, for the first gate line and the second gate line between two adjacent rows of the pixel regions, the first gate line is far away from a target pixel electrode row relative to the second gate line, and the target pixel row: and the pixel regions in two adjacent rows are provided with first transistors electrically connected with the first grid lines and a row of pixel regions provided with second transistors electrically connected with the second grid lines.

Optionally, a width-to-length ratio of a channel region of the first transistor is smaller than a width-to-length ratio of a channel region of the second transistor.

Optionally, the length of the channel region of the first transistor and the length of the channel region of the second transistor are in a range of 4 micrometers to 6 micrometers; a width of a channel region of the first transistor is in a range of 6 to 8 micrometers; the width of the channel region of the second transistor is in the range of 100 to 120 microns.

Optionally, the second substrate includes: the second substrate is a flexible substrate, and the common electrode is positioned on one side of the second substrate close to the first substrate or on one side of the second substrate far away from the first substrate;

the first transistor and the second transistor are each configured to: and the pixel circuit is conducted under the irradiation of target light, so that a data line connected with the first transistor can apply pixel voltage to a pixel electrode connected with the second transistor, and a voltage difference is formed between the pixel electrode applied with the pixel voltage and the common electrode.

Optionally, the liquid crystal layer comprises bistable liquid crystal molecules configured to: after the liquid crystal handwriting board is subjected to external pressure, the focal conic texture is converted into a plane texture; and after a voltage difference is formed between the pixel electrode and the common electrode in the irradiation area of the target light, the planar texture is converted into a focal conic texture.

In another aspect, a method for driving a liquid crystal writing pad is provided, including: when the liquid crystal handwriting board is in an erasing mode, inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line respectively;

when the pixel electrode is in a charging stage, the first scanning signal and the second scanning signal are both at a first level; one of the first scanning signal and the second scanning signal is at a first level and the other is at a second level during at least part of a non-charging period of the pixel electrode.

Optionally, when the pixel electrode is in a non-charging phase, the first scan signal and the second scan signal each have a plurality of first levels and a plurality of second levels, and the plurality of first levels and the plurality of second levels are alternately distributed.

Optionally, when the pixel electrode is in a non-charging phase, the plurality of first levels in the first scan signal and the plurality of first levels in the second scan signal are alternately distributed, so that the first transistor and the second transistor are not switched in the first level at the same time.

Optionally, in a non-charging stage of the pixel electrode, when the first scan signal is at the second level, the first scan signal is at the first level or the second level.

Optionally, when the pixel electrode is in a non-charging stage, a duration of the first scan signal being at a first level is the same as a duration of the second scan signal being at the first level.

Optionally, when the liquid crystal handwriting board is in a writing mode, stopping inputting the first scanning signal and the second scanning signal to the first gate line and the second gate line, respectively.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

a liquid crystal writing pad comprising: the liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate. Wherein the first substrate may include: the pixel structure comprises a first substrate, a pixel electrode, a first transistor, a second transistor, a first grid line, a second grid line and a data line, wherein the pixel electrode, the first transistor, the second transistor, the first grid line, the second grid line and the data line are positioned on one side of the first substrate, which is close to a second substrate. In the present application, a plurality of first and second levels applied to the first and second gate lines are alternately distributed when the pixel electrode is in a non-charging stage, so that one of the first and second transistors is in an off state even if the other of the first and second transistors is switched on to the first level, and thus the pixel electrode is not charged by a data signal applied to the data line. Therefore, at least one of the first transistor and the second transistor is not always connected to the second level, the problem that the threshold voltage of the first transistor and/or the second transistor is shifted after the first transistor and/or the second transistor are in a bias state for a long time is effectively avoided, and even the problem that the first transistor and the second transistor cannot be started or shut down can be possibly caused, so that the stability of the first transistor and/or the second transistor is improved, and the service life of the liquid crystal handwriting board is prolonged.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a film structure of a liquid crystal handwriting board provided in the related art;

FIG. 2 is a top view of a first substrate in the liquid crystal writing pad shown in FIG. 1;

FIG. 3 is a timing diagram of gate scan signals applied to a gate line;

FIG. 4 is a schematic diagram of a film structure of a liquid crystal handwriting board provided in an embodiment of the present application;

FIG. 5 is a top view of the first substrate in the liquid crystal writing pad shown in FIG. 4;

FIG. 6 is a schematic view of a film structure of the first substrate shown in FIG. 5 at A-A';

FIG. 7 is a timing diagram of a first scan signal and a second scan signal according to an embodiment of the present application;

FIG. 8 is a top view of another first substrate provided in accordance with an embodiment of the present disclosure;

FIG. 9 is a partially enlarged schematic view of the Q region shown in FIG. 8;

fig. 10 is a top view of a first transistor provided in an embodiment of the present application;

FIG. 11 is a schematic diagram of a film structure of another liquid crystal handwriting pad provided in the present application;

FIG. 12 is a schematic product structure diagram of a liquid crystal handwriting board provided in an embodiment of the present application;

fig. 13 is a plan view of the first substrate in the liquid crystal handwriting board shown in fig. 11.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

In the related art, please refer to fig. 1, in which fig. 1 is a schematic diagram of a film structure of a liquid crystal handwriting board provided in the related art. Liquid crystal tablet 00 may include: a first substrate 01 and a second substrate 02 disposed opposite to each other, and a liquid crystal layer 03 interposed therebetween. The first substrate 01 may generally include: a first substrate 013, and a plurality of pixel electrodes 011 and TFTs 012 arranged in an array on the first substrate 013. The second substrate 02 may include: a second substrate 022, and a planar common electrode 021 located on the second substrate 022. The liquid crystal molecules in the liquid crystal layer 03 may be bistable liquid crystal molecules.

Among them, the TFT 012 may include: a gate 012a, a first electrode 012b, a second electrode 012c, and an active layer 012 d. In the TFT 012, both the first electrode 012b and the second electrode 012c overlap with the active layer 012d, and the active layer 012d and the gate 012a are insulated from each other by the gate insulating layer 016. Here, the first pole 012b may be one of a source and a drain, and the second pole 012c may be the other of the source and the drain.

As shown in fig. 2, fig. 2 is a plan view of the first substrate in the liquid crystal writing pad shown in fig. 1. The first substrate may further include: a gate line 014, and a data line 015. The gate line 014 may be electrically connected to the gate electrode 012a of the TFT 012, the data line 015 may be electrically connected to the first electrode 012b of the TFT 012, and the second electrode 012c of the TFT 012 may be electrically connected to the pixel electrode 011. In this way, after the gate line 014 applies an electric signal to the gate electrode 012a of the TFT 012 to control the first and

second electrodes

012b and 012c of the TFT 012 to be turned on, the electric signal applied to the data line 015 can apply a pixel voltage to the pixel electrode 011 to charge the pixel electrode 011.

When the liquid crystal handwriting board 00 is in a writing mode, the liquid crystal handwriting board 00 is subjected to an externally applied pressure, and a part of bistable liquid crystal molecules in a liquid crystal layer 03 in the liquid crystal handwriting board 00 is converted into a plane texture from a focal conic texture under the action of the pressure. In this way, the liquid crystal molecules converted into the planar texture can reflect light (for example, green light) with a certain wavelength in the incident ambient light, so that the liquid crystal handwriting board can display handwriting.

When the liquid crystal handwriting board 00 is in the erasing mode, the data line 015 in the liquid crystal handwriting board 00 needs to apply a pixel voltage to the pixel electrode 011 in the region to be erased, so that a voltage difference can be formed between the pixel electrode 011 and the common electrode 021 in the region to be erased, and then bistable liquid crystal molecules in the region to be erased are rearranged under the action of the voltage difference, that is, the bistable liquid crystal molecules can be changed from a planar texture to a focal conic texture, and then erasing of writing in the region to be erased can be realized.

For this reason, when the liquid crystal writing pad 00 is in the erasing mode, the data line 015 and the gate line 014 in the liquid crystal writing pad 00 both need to be applied with electric signals to ensure that the pixel electrode 011 in the region to be erased can be applied with pixel voltage.

The electrical signal applied to the gate line 014 is usually a gate scan signal, and the gate scan signal usually has a high level and a low level. In general, when the gate line 014 is loaded with a high level, the active layer 012d between the first electrode 012b and the second electrode 012c can generate a leakage current, and an electrical signal loaded on the data line 015 can charge the pixel electrode 011 through the TFT 012, so that the pixel electrode 011 can be loaded with a pixel voltage; when the gate line 014 is applied with a low level, the TFT 012 is in an off state, and an electric signal applied to the data line 015 cannot charge the pixel electrode 011 through the TFT 012. Therefore, in general, the pixel electrode 101 may be considered to be in a charging phase when the gate line 014 is applied with a high level, and the pixel electrode 101 may be considered to be in a non-charging phase when the gate line 014 is applied with a low level.

However, referring to fig. 3, fig. 3 is a timing diagram of a gate scan signal applied to a gate line, which is a common method. In one scanning period T, the duration of charging the pixel electrode 011 through the TFT 012 is usually much shorter than the off-duration of the TFT 012, that is, the duration of the pixel electrode 101 in the charging phase T1 is much shorter than the duration of the pixel electrode 101 in the non-charging phase T2. In order to reduce the power consumption of the liquid crystal writing pad 00, the refresh rate of the liquid crystal writing pad 00 is usually low, that is, the duration of one scanning period T is long, usually about several hundred milliseconds.

For this reason, the gate 012a in the TFT 012 is switched on to the low level for a long time, resulting in the TFT 012 being in a bias state most of the time. After the TFT 012 is in a bias state for a long time, the threshold voltage of the turned-on TFT 012 may shift, so that the stability of the TFT 012 is poor, and even the TFT 012 may not be turned on or off, which seriously affects the service life of the liquid crystal handwriting board.

Referring to fig. 4, fig. 4 is a schematic diagram of a film structure of a liquid crystal handwriting board according to an embodiment of the present application. Liquid crystal tablet 000 may include: a first substrate 100 and a second substrate 200 disposed opposite to each other, and a liquid crystal layer 300 between the first substrate 100 and the second substrate 200.

Referring to fig. 5 and fig. 6, fig. 5 is a top view of the first substrate in the liquid crystal handwriting board shown in fig. 4, and fig. 6 is a schematic diagram of a film structure of the first substrate shown in fig. 5 at a-a'. The first substrate 100 may include: a first substrate 101, and a pixel electrode 102, a first transistor 103, a second transistor 104, a first gate line G1, a second gate line G2, and a data line D on a side of the first substrate 101 adjacent to the second substrate 200.

Both the first transistor 103 and the second transistor 104 may be TFTs. To this end, the first transistor 103 and the second transistor 104 each include: the active layer may overlap the first and second electrodes, respectively, and may be insulated from the gate electrode. Here, the first pole in the transistor may be one of a source and a drain, and the second pole may be the other of the source and the drain.

In the embodiment of the present application, the first transistor 103 and the second transistor 104 are both bottom gate thin film transistors, which is taken as an example for schematic explanation. In other alternative implementations, the thin film transistor may also be a top gate thin film transistor, which is not limited in this embodiment of the present application.

In the embodiment of the present application, the first electrode 103b of the first transistor 103 is electrically connected to the data line D, the second electrode 103c of the first transistor 103 may be electrically connected to the first electrode 104b of the second transistor 104, and the second electrode 104c of the second transistor 104 is electrically connected to the pixel electrode 102. The gate 103a of the first transistor 103 is electrically connected to the first gate line G1, and the gate 104a of the second transistor 104 is electrically connected to the first gate line G2.

As such, the first transistor 103 and the second transistor 104 may be two transistors connected in series, and the data line D may be electrically connected to the pixel electrode 102 through the first transistor 103 and the second transistor 104 connected in series.

In the embodiment of the present application, when the liquid crystal writing pad is in the erasing mode, the data signal line D, the first gate line G1, and the second gate line G2 may be respectively connected to a data signal, a first scan signal, and a second scan signal. In this way, when the first scan signal and the second scan signal are both at the first level, the data signal loaded on the data line D can charge the pixel electrode 102. That is, the pixel electrode 102 is in the charging phase.

Here, the timing of the first scan signal applied to the first gate line G1 and the timing of the second scan signal applied to the first gate line G2 may be different. For example, in the charging phase of the pixel electrode 102, both the first scan signal and the second scan signal are at the first level; during at least a portion of the non-charging period of the pixel electrode 102, one of the first scan signal and the second scan signal is at a first level, and the other is at a second level.

It should be noted that the first level and the second level only represent that the level of the signal has 2 state quantities, and do not represent that the first level or the second level has a specific value throughout the text. For example, when the first transistor 103 and the second transistor 104 are both N-type switching transistors, the first level may represent a high level, and the second level may represent a low level. The N-type switch transistor is turned on when the grid electrode is at high level and turned off when the grid electrode is at low level.

Referring to fig. 7, fig. 7 is a timing diagram of a first scan signal and a second scan signal according to an embodiment of the present disclosure. In one scanning period T, when the first scanning signal and the second scanning signal are both at the first level, the data signal loaded on the data line D can charge the pixel electrode 102, so that the pixel electrode 102 can be loaded with the pixel voltage, and the pixel electrode 102 is in the charging phase T1; when the electric signal applied to one of the gate 103a of the first transistor 103 and the gate 104a of the second transistor 104 is at the first level and the electric signal applied to the other is at the second level, one of the first transistor 103 and the second transistor 104 is in an off state, the data signal applied to the data line D cannot charge the pixel electrode 102, and the pixel electrode 102 is in the non-charging period T2.

In this case, when the pixel electrode 102 is in the non-charging period T2, even if one of the first transistor 103 and the second transistor 104 is switched to the first level, the other of the first transistor 103 and the second transistor 104 is still in an off state, so that the data signal loaded on the data line D does not charge the pixel electrode 102. Therefore, when the pixel electrode 102 is in the non-charging stage T2, at least one of the first transistor 103 and the second transistor 104 is not always connected to the second level, which effectively avoids the problem that the threshold voltage of the first transistor 103 and/or the second transistor 104 is shifted after being in the bias state for a long time, further improves the stability of the first transistor 103 and/or the second transistor 104, and ensures that the service life of the liquid crystal handwriting pad 000 is longer.

In the present application, when the pixel electrode 102 is in the non-charging period T2, the first scan signal and the second scan signal each have a plurality of first levels and a plurality of second levels, which are alternately distributed. In this way, the first transistor 103 and the second transistor 104 are both switched to the first level when the pixel electrode 102 is in the non-charging period T2, and one of the first scan signal and the second scan signal is at the first level and the other is at the second level, so as to ensure that one of the first transistor 103 and the second transistor 104 is in the off state when the pixel electrode 102 is in the non-charging period. In this case, neither the first transistor 103 nor the second transistor 104 is switched to the first level or the second level for a long time, which further improves the stability of the first transistor 103 and the second transistor 104.

Optionally, when the pixel electrode 102 is in the non-charging period T2, the plurality of first levels in the first scan signal are alternately distributed with the plurality of first levels in the second scan signal, so as to ensure that the first transistor 103 and the second transistor 104 do not switch on the first levels at the same time.

In the embodiment of the present application, when the pixel electrode 102 is in the non-charging period T2, the first scan signal may be at the first level or the second level when the first scan signal is at the second level. That is, when the first transistor 103 is turned on at the second level, the second transistor 104 may be turned on at the second level, or may be turned on at the first level.

Optionally, when the pixel electrode 102 is in the non-charging period T2, the duration of the first scan signal at the first level is the same as the duration of the second scan signal at the first level. That is, the duration of the first transistor 103 being switched in the first level is the same as the duration of the second transistor 104 being switched in the first level. In this manner, the stability of the first transistor 103 and the second transistor 104 can be ensured to be substantially uniform.

To sum up, the embodiment of the present application provides a liquid crystal handwriting pad, including: the liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate. Wherein the first substrate may include: the pixel structure comprises a first substrate, a pixel electrode, a first transistor, a second transistor, a first grid line, a second grid line and a data line, wherein the pixel electrode, the first transistor, the second transistor, the first grid line, the second grid line and the data line are positioned on one side of the first substrate, which is close to a second substrate. In at least a part of the non-charging period of the pixel electrode, one of the first scan signal applied to the first gate line and the second scan signal applied to the second gate line is at a first level and the other is at a second level, so that even if one of the first transistor and the second transistor is switched on at the first level, the other of the first transistor and the second transistor is still in an off state, and the pixel electrode is not charged by the data signal applied to the data line. Therefore, at least one of the first transistor and the second transistor is not always connected to the second level, the problem that the threshold voltage of the first transistor and/or the second transistor is shifted after the first transistor and/or the second transistor are in a bias state for a long time is effectively avoided, the stability of the first transistor and/or the second transistor is improved, and the service life of the liquid crystal handwriting board is prolonged.

In the embodiment of the present application, referring to fig. 5, a plurality of pixel regions 100a are arranged in an array on a first substrate 101 of a first substrate 100, and a first transistor 103, a second transistor 104 and a pixel electrode 102 are distributed in one pixel region 100 a. Here, one first transistor 103, one second transistor 104, and one pixel electrode 102 distributed in each pixel region 100a may also be generally referred to as one pixel.

The number of the data lines D, the first gate lines G1, and the second gate lines G2 in the first substrate 100 is multiple, and a region surrounded by any two adjacent data lines D and any two adjacent gate lines (which may be the first gate lines G1 or the second gate lines G2) is a pixel region 100 a.

In this application, a data line D may be disposed between two adjacent columns of the pixel regions 100a, and the data line D may be electrically connected to a column of pixels. For example, the data line D may be electrically connected to the first electrode 103b of each first transistor 103 in a column of the pixel region 100 a.

One first gate line G1 and one second gate line G2 may be disposed between two adjacent rows of pixel regions 100a, and the first gate line G1 and the second gate line G2 between the two adjacent rows of pixel regions 100a may be electrically connected to the same row of pixels. For example, the first gate line G1 and the second gate line G2 may be electrically connected to the gate electrode 103a of each first transistor 103 and the gate electrode 104a of each second transistor 104 in the same row of pixel regions 100a, respectively. In this case, when the first and second gate lines G1 and G2 between two adjacent rows of pixel areas 100a are loaded with the first and second scan signals respectively, and the first and second scan signals are at the first level, leakage current is generated in both the active layer 103d of the first transistor 103 and the active layer 104d of the second transistor 104 in the same row of pixel areas 100 a. If a data signal is applied to a data line D electrically connected to a pixel electrode 102 in the row of pixel regions 100a, the data signal applied to the data line D can charge the pixel electrode 102.

Optionally, please refer to fig. 8, where fig. 8 is a top view of another first substrate provided in the embodiment of the present application. The plurality of first gate lines G1 and the plurality of second gate lines G2 in the first substrate 100 may be electrically connected in a one-to-one correspondence, and a row of pixel regions 100a is disposed between the first gate line G1 and the corresponding second gate line G2.

In this case, even though the first gate line G1 and the second gate line G2 need to be electrically connected to a row of pixels at the same time in the first substrate 100 in this embodiment, and the number of the gate lines is twice as many as that in the first substrate in the related art, each first gate line G1 is electrically connected to a corresponding second gate line G2 in the first substrate 100 in this embodiment, and the first gate line G1 and the second gate line G2 which are electrically connected to each other can be connected to the same signal output terminal. In this way, the number of the signal output terminals of the first substrate 100 for outputting the scan signal in the embodiment of the present application is ensured to be half of the number of the gate lines, and the number of the signal output terminals is not increased.

For example, the first substrate 100 may further include: and a signal access line 105, wherein the signal access line 105 can be electrically connected with the first gate line G1 and the corresponding second gate line G2. In this way, the first gate line G1 and the second gate line G2 electrically connected to each other can be electrically connected to the same signal access terminal through the signal access line 105.

Optionally, referring to fig. 9, fig. 9 is a partially enlarged schematic view of a Q region shown in fig. 8. The extending direction of the first gate line G1 is parallel to the extending direction of the second gate line G2, and for the first gate line G1 and the second gate line G2 between two adjacent rows of pixel regions 100a, the first gate line G1 is far from the target pixel electrode row with respect to the second gate line G2. The target pixel electrode row is a row of pixel regions in which the first transistor 103 electrically connected to the first gate line G1 and the second transistor 104 electrically connected to the second gate line G2 are located in two adjacent rows of pixel regions 100 a.

In the present application, the arrangement direction of the first transistor 103 and the second transistor 104 may be perpendicular to the extension direction of the data line D. In this way, the first gate line G1 may be directly electrically connected to the gate electrode 103a of the first transistor 103, and similarly, the second gate line G2 may be directly electrically connected to the gate electrode 104a of the second transistor 104. Thus, the first gate line G1 and the gate electrode 103a of the first transistor 103 can be electrically connected without using a via electrode, and the second gate line G2 and the gate electrode 104a of the second transistor 104 can be electrically connected, thereby simplifying the manufacturing difficulty of the liquid crystal handwriting board 000.

In the related art, as shown in fig. 1 and 2, when the liquid crystal writing pad 00 adopts the optical erasing technique, an erasing tool capable of emitting a target light ray may be used to erase the handwriting presented on the liquid crystal writing pad 00. In this case, when the liquid crystal writing pad 00 is in the erasing mode, the gate line 014 needs to be applied with the gate scan signal, and the voltage at which the gate scan signal is at the high level is small, so that the active layer 012d of the TFT 012 generates a leakage current when the gate scan signal is at the high level, but the leakage current is usually small. After the target light irradiates the active layer 012d of the TFT 012, the active layer 012d generates carriers, so that the leakage current on the active layer 012d increases, the TFT 012 can be in a conducting state, and the electrical signal loaded on the data line 015 can charge the pixel electrode 011 through the TFT 012, so that the pixel electrode 011 can be loaded with pixel voltage. Thus, a voltage difference is generated between the pixel electrode 011 and the common electrode 021 in the region irradiated by the target light, so that bistable liquid crystal molecules in the region irradiated by the target light can be converted from a planar texture to a focal conic texture, and further, handwriting in the region irradiated by the target light can be erased.

However, when the liquid crystal writing pad 00 using the optical erasing technique is in the erasing mode, the gate lines 014 and the data lines 015 are both loaded with electrical signals. Although the electrical signal loaded on the gate line 014 is not enough to completely turn on the TFT 012, the active layer 012d of the TFT 012 still generates leakage current, which may cause the data signal loaded on the data line 015 to possibly charge the pixel electrode 011 in the non-erased area, and further cause the writing in the non-erased area to become shallow, thereby seriously affecting the display effect of the liquid crystal handwriting board.

In order to solve the problem that the writing trace in the non-erasing area of the liquid crystal writing pad in the related art becomes shallow, the channel regions of the first transistor 103 and the second transistor 104 in the first substrate 100 in this application need to be designed. Meanwhile, in order to facilitate understanding of the contents in the subsequent embodiments, the following embodiments first explain the technical names related to the present application.

Referring to fig. 10, fig. 10 is a top view of a first transistor according to an embodiment of the present disclosure. The active layer 103d in the first transistor 103 has a channel region, which refers to a region of the active layer 103d between a first region where the active layer 103d contacts the first electrode 103b and a second region where the active layer 103d contacts the second electrode 103 c. Wherein, the length L of the channel region refers to the distance between the first region and the second region, and the width W of the channel region refers to the smaller length of the first region and the length of the second region. The width-to-length ratio W/L of the channel region of the first transistor 103 is a ratio between the width W of the channel region of the first transistor 103 and the length L of the channel region of the first transistor 103, and the larger the width-to-length ratio W/L of the channel region is, the smaller the resistance between the first electrode 103b and the second electrode 103c in the first transistor 103 is, and the larger the magnitude of the leakage current that can be transmitted therebetween is; conversely, the smaller the value of the width-to-length ratio W/L of the channel region, the smaller the magnitude of the leakage current transmitted between the first electrode 103b and the second electrode 103c in the first transistor 103. It should be noted that the active layer 104d in the second transistor 104 also has a channel region, and the related meaning of the channel region of the active layer 104d is the same as the related meaning of the channel region of the active layer 103d of the first transistor 103, and is not described here again.

In the embodiment of the present application, the width-to-length ratio of the channel region of the first transistor 103 may be smaller than the width-to-length ratio of the channel region of the second transistor 104. It should be noted that, in order to ensure the current transmission of the transistor in the on state, the length of the channel region of the transistor is generally fixed, for example, the length of the channel region of the transistor is in the range of 4 micrometers to 6 micrometers. For this reason, the length of the channel region of the first transistor 103 may be equal to the length of the channel region of the second transistor 104, so that after the width of the channel region of the first transistor 103 is ensured to be smaller than the width of the channel region of the second transistor 104, the width-to-length ratio of the channel region of the first transistor 103 is ensured to be smaller than the width-to-length ratio of the channel region of the second transistor 104.

In this case, the width and length of the channel region of the first transistor 103 electrically connected to the data signal line D are small. Thus, when the gate 103a of the first transistor 103 is loaded with the first scanning signal, the magnitude of the leakage current generated by the active layer 103d of the first transistor 103 can be further reduced, so that the magnitude of the pixel voltage applied to the pixel electrode 102 in the non-erasing area is reduced, the probability of the phenomenon that the written handwriting becomes shallow in the non-erasing area is reduced, and the display effect of the liquid crystal handwriting board 000 is effectively improved.

And the width and length of the channel region of the second transistor 104 electrically connected to the pixel electrode 102 are large. Thus, when the target light irradiates the region to be erased, carriers are generated in both the channel region of the first transistor 103 and the second transistor 104, and the number of carriers generated in the channel region of the second transistor 104 is large. Because the data line D is loaded with the data signal, under the action of the data signal, carriers generated in the channel region of the second transistor 104 can flow toward the pixel electrode 102, so that the magnitude of leakage current generated by the active layer 104D of the second transistor 104 can be increased, and the data signal loaded on the data line D can normally charge the pixel electrode 102. In this way, the pixel electrode 102 in the area to be erased can be loaded with the pixel voltage, so that the writing in the area to be erased can be erased.

Illustratively, the length of the channel region of the first transistor 103 is in a range of 4 to 6 micrometers with the length of the channel region of the second transistor 104; the width of the channel region of the first transistor 103 is in the range of 6 to 8 micrometers; the width of the channel region of the second transistor 104 is in the range of 100 micrometers to 120 micrometers. Also, the size of the pixel region 101a of the first substrate 100 may be 1 × 1 mm. Thus, when the gate 103a of the first transistor 103 is loaded with the first scan signal and the leakage current generated by the active layer 103D of the first transistor 103 is small, it can be ensured that when a certain pixel region is irradiated by the target light, the pixel electrode 102 in the pixel region can be normally charged by loading the data signal on the data line D.

In the embodiment of the present application, as shown in fig. 11, fig. 11 is a schematic diagram of a film layer structure of another liquid crystal handwriting board provided in the present application. The second substrate 200 in the liquid crystal handwriting pad 000 may include: a second substrate 201, and a common electrode 202 located on one side of the second substrate 201 close to the first substrate 100 or on one side of the second substrate 201 far from the first substrate 100. The liquid crystal layer 300 in the liquid crystal handwriting pad 000 may include bistable liquid crystal molecules. Note that, in the drawings in the present application, the common electrode 202 is schematically illustrated as being close to the first substrate 100 with respect to the second substrate 201.

When the liquid crystal handwriting pad 000 is in the writing mode, no electrical signal is loaded on the data line D, the first gate line G1, and the second gate line G2 in the first substrate 100, that is, no voltage is applied on the data line D, the first gate line G1, and the second gate line G2, so that the power consumption of the liquid crystal handwriting pad 000 can be ensured to be low. For example, the bistable liquid crystal molecules in liquid crystal handwriting pad 000 may be configured to: when the liquid crystal handwriting board 000 is subjected to external pressure, the focal conic texture is transformed into the planar texture. For example, when a user writes on liquid crystal handwriting pad 000 with a writing instrument (e.g., a writing pen), the user may apply pressure to liquid crystal handwriting pad 000 with the writing instrument, such that bistable liquid crystal molecules in the area of liquid crystal handwriting pad 000 that is subjected to the pressure are transformed from focal conic texture to planar texture. In this case, the bistable liquid crystal molecules with plane texture can reflect a certain wavelength of light (e.g., green light) in the ambient light irradiated on the liquid crystal writing pad 000, so that the liquid crystal writing pad 000 can display corresponding writing.

When the liquid crystal handwriting pad 000 is in an erase mode, the data line D, the first gate line G1, and the second gate line G2 in the first substrate 100 may be loaded with a data signal, a first scan signal, and a second scan signal, respectively. Illustratively, the first transistor 103 and the second transistor 104 in the liquid crystal handwriting pad 000 are each configured to: the pixel electrode 102 connected to the second transistor 104 can be charged by the data line D connected to the first transistor 103 under the irradiation of the target light, so as to ensure that the pixel voltage is applied to the pixel electrode 102, and thus a voltage difference is formed between the pixel electrode 102 to which the pixel voltage is applied and the common electrode 202.

The bistable liquid crystal molecules may also be configured to: after a voltage difference is formed between the pixel electrode 102 and the common electrode 202 in the irradiation region of the target light, the planar texture is changed into the focal conic texture. For example, when a user erases the liquid crystal handwriting pad 000 by using an erasing tool capable of emitting a target light, the user can emit the target light to the liquid crystal handwriting pad 000 by using the erasing tool, and a voltage difference is formed between the pixel electrode 102 in the irradiation area of the target light in the liquid crystal handwriting pad 000 and the common electrode 202, so that the bistable liquid crystal molecules in the irradiation area of the target light in the liquid crystal handwriting pad 000 are restored from the planar texture to the focal conic texture. Thus, the bistable liquid crystal molecules in the focal conic texture can transmit the ambient light irradiated on the liquid crystal writing pad 000, so as to erase the writing handwriting in the irradiation area of the target light. Thus, the irradiation area of the target light is the area to be erased.

It should be noted that the intensity of the target light needs to be greater than the intensity of the ambient light to ensure that the first transistor 103 and the second transistor 104 are only turned on under the irradiation of the target light and are not turned on under the irradiation of the ambient light.

Optionally, as shown in fig. 12, fig. 12 is a schematic product structure diagram of a liquid crystal handwriting board provided in an embodiment of the present application. The liquid crystal handwriting pad 000 may further include: the switch 400 is switched. The switch 400 is used to control the liquid crystal writing pad 000 to switch between the erasing mode and the writing mode. When the liquid crystal handwriting board 000 is in the writing mode, the liquid crystal handwriting board 000 is in an unpowered state, and no electric signal is loaded on the data line D, the first gate line G1, and the second gate line G2; when the liquid crystal handwriting board 000 is in the erasing mode, the liquid crystal handwriting board 000 is in a power-on state, and the data line D, the first gate line G1 and the second gate line G2 all need to be loaded with electrical signals. Therefore, only when the liquid crystal handwriting board 000 is in the erasing mode, the liquid crystal handwriting board 000 needs to consume electric energy, and the power consumption of the liquid crystal handwriting board 000 is effectively reduced.

In the embodiment of the present application, as shown in fig. 11 and 13, fig. 13 is a plan view of the first substrate in the liquid crystal writing pad shown in fig. 11. The first substrate 100 in the liquid crystal handwriting pad 000 may further include: the auxiliary electrode line 106 is located on one side of the first substrate 101 close to the second substrate 200, the auxiliary electrode line 106 may be disposed at the same layer as the first gate line G1 and the second gate line G2, and an extending direction of the auxiliary electrode line 106 is parallel to an extending direction of the first gate line G1.

Illustratively, the pixel electrodes 102 in the first substrate 100 are arranged in a plurality of rows, and the number of the auxiliary electrode lines 106 in the first substrate 100 is the same as the number of the rows of the pixel electrodes 102. An orthogonal projection of each auxiliary electrode line 106 on the first substrate 101 overlaps an orthogonal projection of a corresponding row of pixel electrodes 102 on the first substrate 101, and the auxiliary electrode line 106 may constitute a storage capacitor Cst with each pixel electrode 102 in the row of pixel electrodes 102. The storage capacitor Cst can be used to maintain the pixel voltage of the pixel electrode 102, so that when the liquid crystal writing pad 000 is erased, the storage capacitor Cst can prevent the voltage variation of the pixel electrode 102 in the pixel area to be erased from affecting the voltage of the pixel electrode 102 around the pixel area to be erased, and further prevent the display effect of the pixel area around the pixel area to be erased from being affected.

Alternatively, as shown in fig. 11, the first substrate 100 may further include: a gate insulating layer 107, a first insulating layer 108, and a second insulating layer 109.

Wherein a gate insulating layer 107 may be located between the gate and the active layer of the transistor. For example, the gate 103a and the active layer 103d of the first transistor 103 may be insulated by a gate insulating layer, and the gate 104a and the active layer 104d of the second transistor 104 may be insulated by a gate insulating layer.

The first insulating layer 108 may be located between the transistor and the pixel electrode 102. Here, the pixel electrode 102 may be located on the first insulating layer 108, and the first insulating layer 108 may not only protect the transistor but also improve the flatness of the pixel electrode 102. In this case, the first insulating layer 108 has a connection via hole through which the pixel electrode 102 can be electrically connected with the second electrode 1014c in the second transistor 104.

The second insulating layer 109 is located on a side of the pixel electrode 102 away from the first substrate 101. When the first substrate 100 and the second substrate 200 are disposed opposite to each other, since the device environment is not a dust-free environment, a foreign substance may be generated between the first substrate 100 and the second substrate 200, and the second insulating layer 109 may be used to prevent the foreign substance located between the first substrate 100 and the second substrate 200 from conducting the pixel electrode 102 in the first substrate 100 and the common electrode 202 in the second substrate 200.

In the embodiment of the present application, as shown in fig. 11, the materials of the common electrode 202 in the second substrate 200 and the pixel electrode 102 in the first substrate 100 may include: indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the like. The first substrate 101 in the first base plate 100 may be a rigid substrate, for example, the first substrate 101 may be a glass base; the second substrate 201 of the second substrate 200 may be a flexible substrate, for example, the second substrate 201 may be a Polyethylene Terephthalate (PET) substrate.

The embodiment of the application also provides a driving method of the liquid crystal handwriting board, which is applied to the liquid crystal handwriting board in the embodiment. The liquid crystal writing pad is exemplified by the liquid crystal writing pads shown in fig. 4 and 11.

The driving method of the liquid crystal handwriting board can comprise the following steps: and when the liquid crystal handwriting board is in an erasing mode, inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line respectively.

Note that, the timing chart of the first scan signal and the second scan signal may refer to the timing chart shown in fig. 7.

Optionally, the driving method of the liquid crystal handwriting board may include: and when the liquid crystal handwriting board is in a writing mode, stopping respectively inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working principle of the driving method of the liquid crystal handwriting board described above may refer to the corresponding parts in the structural embodiment of the liquid crystal handwriting board, and will not be described herein again.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or there can be more than one intermediate layer or element. Like reference numerals refer to like elements throughout.

In this application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.

The above description is intended to be exemplary only, and not to limit the present application, and any modifications, equivalents, improvements, etc. made within the spirit and scope of the present application are intended to be included therein.

Claims

1. A liquid crystal writing pad, comprising: the liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is positioned between the first substrate and the second substrate;

2. The liquid crystal writing pad of claim 1, wherein the first substrate has a plurality of pixel regions arranged in an array, one of the first transistors, one of the second transistors, and one of the pixel electrodes being arranged in one of the pixel regions;

3. The liquid crystal handwriting board according to claim 2, characterized in that the number of the first grid lines and the number of the second grid lines are both multiple, the multiple first grid lines and the multiple second grid lines are electrically connected in a one-to-one correspondence, and a row of the pixel regions is distributed between the first grid lines and the corresponding second grid lines.

4. The liquid crystal writing pad of claim 3, wherein the first substrate further comprises: and the signal access lines are electrically connected with the first grid lines and the corresponding second grid lines respectively.

5. The liquid crystal handwriting board according to claim 2, wherein the extending direction of said first grid line is parallel to the extending direction of said second grid line, for the first grid line and the second grid line between two adjacent rows of said pixel regions, said first grid line is far away from the target pixel electrode row relative to said second grid line, said target pixel row: and the pixel regions in two adjacent rows are provided with first transistors electrically connected with the first grid lines and a row of pixel regions provided with second transistors electrically connected with the second grid lines.

6. The liquid crystal writing pad of any one of claims 1 to 5, wherein the width-to-length ratio of the channel region of the first transistor is smaller than the width-to-length ratio of the second transistor.

7. The liquid crystal handwriting pad of claim 6, wherein the length of the channel region of said first transistor and the length of the channel region of said second transistor are in the range of 4 microns to 6 microns; a width of a channel region of the first transistor is in a range of 6 to 8 micrometers; the width of the channel region of the second transistor is in the range of 100 to 120 microns.

8. The liquid crystal writing pad of claim 6, wherein the second substrate comprises: the second substrate is a flexible substrate, and the common electrode is positioned on one side of the second substrate close to the first substrate or on one side of the second substrate far away from the first substrate;

9. The liquid crystal writing pad of claim 8, wherein the liquid crystal layer includes bistable liquid crystal molecules configured to: after the liquid crystal handwriting board is subjected to external pressure, the focal conic texture is converted into a plane texture; and after a voltage difference is formed between the pixel electrode and the common electrode in the irradiation area of the target light, the planar texture is converted into a focal conic texture.

10. A method for driving a liquid crystal writing pad, which is applied to the liquid crystal writing pad of any one of claims 1 to 9, the method comprising:

when the liquid crystal handwriting board is in an erasing mode, inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line respectively;

11. The method according to claim 10, wherein the first scan signal and the second scan signal each have a plurality of first levels and a plurality of second levels, the plurality of first levels and the plurality of second levels being alternately distributed when the pixel electrode is in a non-charging phase.

12. The method of claim 11, wherein the plurality of first levels of the first scan signal alternate with the plurality of first levels of the second scan signal during the non-charging phase of the pixel electrode such that the first transistor and the second transistor do not switch on the first levels at the same time.

13. The method board of claim 12, wherein the first scan signal is at a first level or a second level when the first scan signal is at the second level during the non-charging phase of the pixel electrode.

14. The method of claim 12, wherein the duration of the first scan signal at the first level is the same as the duration of the second scan signal at the first level during the non-charging period of the pixel electrode.

15. The method according to any one of claims 10 to 14, characterized in that it comprises:

and when the liquid crystal handwriting board is in a writing mode, stopping respectively inputting a first scanning signal and a second scanning signal to the first grid line and the second grid line.