CN113009741A - Array substrate, display panel and manufacturing method thereof - Google Patents
Array substrate, display panel and manufacturing method thereof Download PDFInfo
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- CN113009741A CN113009741A CN202110254156.2A CN202110254156A CN113009741A CN 113009741 A CN113009741 A CN 113009741A CN 202110254156 A CN202110254156 A CN 202110254156A CN 113009741 A CN113009741 A CN 113009741A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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Abstract
The application discloses array substrate, display panel and preparation method thereof, array substrate is divided into display area and non-display area, includes: the data line interface comprises a plurality of data lines, a plurality of first fan-out wires, a plurality of second fan-out wires, a data selection circuit, a first binding area and a second binding area; the plurality of first fan-out wires are arranged in the non-display area, the number of the first fan-out wires is the same as that of the data lines, and the first fan-out wires are connected with one end of each data line in a one-to-one correspondence mode; the plurality of second fan-out wires are arranged in the non-display area, the ratio of the number of the data lines to the number of the second fan-out wires is m, wherein m is an integer larger than 1; the data selection circuit is connected with the second fan-out routing and the data line; the first binding wires are connected with the first fan-out wires in a one-to-one correspondence manner; the second binding region is arranged on one side of the array substrate corresponding to the second fan-out routing to provide a composite array substrate for the display panel with different refresh rates.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a display panel and a manufacturing method of the display panel.
Background
The number of times that the electron beam repeatedly scans the image of the screen when the display panel is displaying is called a refresh rate, and the refresh rate is a vertical refresh rate and a horizontal refresh rate in hertz, and the generally mentioned refresh rate is generally a vertical refresh rate; the vertical refresh rate indicates the number of times the image of the screen is refreshed per second, for example, 60HZ, and the panel can update 60 pictures in one second. The high refresh rate is a performance parameter used by the electronic race display to solve image display problems such as dropped frames, tearing, and streaking of game images. The official standard of the current competitive display is more than 100HZ, and 144HZ is a more highly matched competitive display.
The display panels corresponding to the electronic competition display and the common 60HZ display are produced by different photomasks, and the two display panels are designed by the same photomask, so that the problem to be solved urgently is solved.
Disclosure of Invention
The application aims to provide an array substrate, a display panel and a manufacturing method thereof, so that the display panel with different refresh rates can be suitable for being produced by a composite array substrate.
The application discloses array substrate is divided into display area and non-display area, includes: the data line interface comprises a plurality of data lines, a plurality of first fan-out wires, a plurality of second fan-out wires, a data selection circuit, a first binding area and a second binding area; the data lines provide data signals for the array substrate; a plurality of first fan-out wires are arranged in the non-display area, the number of the first fan-out wires is the same as that of the data lines, and the first fan-out wires are connected with one end of each data line in a one-to-one correspondence mode; a plurality of second fan-out wires are arranged in the non-display area, the ratio of the number of the data lines to the number of the second fan-out wires is m, wherein m is an integer greater than 1; the data selection circuit is connected with the second fan-out routing and the data line; the first binding area is arranged on one side, corresponding to the first fan-out routing, of the array substrate, the first binding area is provided with first binding routing, and the first binding routing and the first fan-out routing are connected in a one-to-one corresponding mode; the second binding area is arranged on one side, corresponding to the second fan-out wiring, of the array substrate, and the second binding area is provided with second binding wirings which are connected with the second fan-out wirings in a one-to-one correspondence mode.
Optionally, the data selection circuit includes a plurality of data selectors, the number of the data selectors is the same as that of the second fan-out traces, an output end of each data selector is connected to m data lines, and an input end of each data selector is connected to one second fan-out trace.
Optionally, each data selector is connected to 3 data lines, and the data selector is a one-out-of-three data selector.
Optionally, the one-out-of-three data selector includes: the output end of the first active switch is connected with the first data line; the output end of the second active switch is connected with a second data line; the output end of the third active switch is connected with a third data line; the input ends of the first active switch, the second active switch and the third active switch are connected to the same second fan-out wiring.
Optionally, the array substrate further includes: the first cutting mark is arranged corresponding to the first fan-out routing; and the second cutting mark is arranged corresponding to the second fan-out routing.
The application also discloses a manufacturing method of the display panel, which comprises the following steps:
forming a substrate;
depositing a metal layer on a substrate;
the patterning metal layer corresponds to the non-display area to form a plurality of first fan-out wires, a plurality of second fan-out wires, a first binding area and a second binding area; forming a plurality of data lines corresponding to the display area;
forming a plurality of data selectors;
forming an array substrate;
binding a data chip on the first binding region or the second binding region of the array substrate;
forming a color film substrate;
the color film substrate and the array substrate are oppositely formed into a display panel;
binding a data chip on the array substrate;
forming a color film substrate;
and the color film substrate and the array substrate are oppositely formed into a display panel.
Optionally, the step of binding the data chip on the array substrate includes:
cutting off the first binding routing and the first fan-out routing along the first cutting mark;
and binding the data chip on the second binding area.
Optionally, the step of binding the data chip on the array substrate includes:
cutting off the second binding routing and the second fan-out routing along the second cutting mark;
and binding the data chip on the first binding area.
Optionally, the step of binding the data chip on the array substrate includes:
and binding the data chip on the first binding area and the second binding area.
The application also discloses a display panel, which comprises an array substrate, a color film substrate arranged in a box-to-box mode with the array substrate, and a display medium layer arranged between the array substrate and the color film substrate.
The array substrate provided by the embodiment of the application has two binding regions, namely a first binding region and a second binding region, so that a data chip which is in matched connection with the binding regions can be bound at any one side of the display panel, the bound side can be flexibly selected according to the requirements of a user, for example, a common 60Hz panel can be bound with the second binding region, and a 144 Hz-240 Hz panel of the electronic competition screen needs to be bound with the first binding region. And data chips can be bound to both sides of the first binding region and the second binding region, so that a composite array substrate is provided to be suitable for display panels with different refresh rates, customers can flexibly select the composite array substrate, and user experience is improved. In addition, because both sides of the array substrate are bound, the array substrate of the embodiment can be externally connected with two devices at the same time, and the utilization rate of the panel can be improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
fig. 2 is a schematic view of an array substrate according to an embodiment of the present application;
fig. 3 is a schematic step diagram illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a data selector according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating a method of fabricating a display panel according to another embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a method of fabricating a display panel according to another embodiment of the present application;
FIG. 7 is a schematic diagram of a display panel manufactured by a method for manufacturing a display panel corresponding to FIG. 6 of the present application;
FIG. 8 is a schematic diagram illustrating a method of fabricating a display panel according to another embodiment of the present application;
fig. 9 is a schematic view of a display panel manufactured by a method for manufacturing a display panel corresponding to fig. 8 of the present application.
Wherein, 1, a display device; 10. a display panel 11, a display area; 12. a non-display area; 13. a first cutting mark; 14. a second cutting mark; 30. a data chip; 100. an array substrate; 110. a data line; 120. a first fan-out trace; 130. a second fan-out trace; 140. a data selection circuit; 141. a first active switch; 142. a second active switch; 143. a third active switch; 150. a first binding region; 160. a second binding region; 200. a color film substrate; 300. a dielectric layer is displayed.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1-2, as an embodiment of the present application, a display panel is disclosed, which is divided into a display area and a non-display area, and includes an array substrate 100, a color filter substrate 200 disposed in a box-to-box manner with the array substrate 100, a display medium layer 300 disposed between the array substrate and the color filter substrate, and a data chip (not labeled in this figure) bound on the array substrate, where the array substrate includes: a plurality of data lines 110, a plurality of first fan-out traces 120, a plurality of second fan-out traces 130, a data selection circuit 140, a first bonding area 150, and a second bonding area 160.
Specifically, the data lines 110 are disposed in the display region and provide data signals to the array substrate. The plurality of first fan-out traces 120 are disposed in the non-display area, the number of the first fan-out traces 120 is the same as that of the data lines 110, and the first fan-out traces 120 are connected to one end of the data lines 110 in a one-to-one correspondence manner. The plurality of second fan-out traces 130 are disposed in the non-display area, and a ratio of the number of the data lines 110 to the number of the second fan-out traces 130 is m, where m is an integer greater than 1, for example, m is 2, 3, or 4, and the numerical values herein are merely used for example, and are not limited to the value of m. The data selection circuit 140 connects the second fan-out trace 130 and the data line 110. The first bonding area 150 is disposed on one side of the array substrate corresponding to the first fan-out trace 120, the first bonding area 150 is disposed with a first bonding trace, and the first bonding trace is connected to the first fan-out trace 120 in a one-to-one correspondence manner. The second bonding area 160 is disposed at a side of the array substrate corresponding to the second fan-out trace 130, the second bonding area 160 is disposed with a second bonding trace, and the second bonding trace is connected to the second fan-out trace 130 in a one-to-one correspondence manner.
The array substrate of the embodiment of the application has two binding regions, namely the first binding region 150 and the second binding region 160, so that a data chip cooperatively connected with the binding regions can be bound at any one side of the display panel, and the bound side can be flexibly selected according to the requirements of a user, for example, a common 60Hz panel can be bound with the second binding region 160, and a 144 Hz-240 Hz panel of an electronic competition screen needs to be bound with the first binding region 150. It should be noted that in some embodiments, data chips may be bound to both sides of the first binding region 150 and the second binding region 160, so that a user can flexibly select the data chips, and user experience is improved. In addition, because both sides of the array substrate are bound, the array substrate of the embodiment can be externally connected with two devices at the same time, and the utilization rate of the panel can be improved.
It should be noted that, in the present application, the first bonding region 150 and the second bonding region 160 are respectively disposed on two sides of the array substrate, and the metal trace corresponding to the first bonding region 150 and the metal trace corresponding to the second bonding region 160, and the first fan-out trace and the second fan-out trace are located on the first metal layer or the second metal layer of the display panel, where the first metal layer and the second metal layer respectively belong to the same metal layer as the gate and the source drain of the thin film transistor in the display region of the display panel. The display panel adopts the mode of film deposition and photomask etching when manufacturing the first metal layer or the second metal layer, the scheme only needs to process the photomask at the corresponding positions of the first fan-out routing, the second fan-out routing, the first binding area 150 and the second binding area 160 after depositing a layer of the first metal layer or the second metal layer, and the corresponding first fan-out routing, the second fan-out routing, the first binding area 150 and the second binding area 160 are etched, and the manufacturing process is not additionally increased, and only the photomask at the corresponding position needs to be changed. Correspondingly, the manufacturing method of the array substrate, as shown in fig. 3, is a schematic step diagram of the manufacturing method of the array substrate; the method comprises the following steps:
s111: forming a substrate;
s112: depositing a metal layer on a substrate;
s113: the patterning metal layer corresponds to the non-display area to form a plurality of first fan-out wires, a plurality of second fan-out wires, a first binding area and a second binding area; forming a plurality of data lines corresponding to the display area;
s114: forming a plurality of data selectors;
s115: and forming an array substrate.
The number of the first fan-out traces 120 is the same as the number of the data lines 110, the first fan-out traces 120 are connected with one end of the data lines 110 in a one-to-one correspondence manner, the ratio of the number of the data lines 110 to the number of the second fan-out traces 130 is m, and the data lines are connected with the second fan-out traces through a plurality of data selectors.
For high refresh, for example, a 120HZ display panel, 120 display frames need to be refreshed every second, and 120 frames of scanning are performed every second, so that, compared with a 60HZ display panel, the output of the data lines of the display panel with high refresh rate is increased by 60 frames of data output, and therefore, the load of the data chips with high refresh rate is increased, if the data lines of the display panel with low refresh rate are adopted as the binding structure, the data chips are overloaded to work, and finally, damage is caused, and the like.
For a 60HZ display panel, the refresh rate per second is not high, and the display source chips need to be driven, and the source chips corresponding to the full number of data lines also need not be used; if a full amount of data chips are used, a great deal of waste is caused, and the cost is high, so the data selection circuit 140 includes a plurality of data selectors 310 through the data selection circuit, the number of the data selectors is the same as that of the second fan-out traces 130, the output end of each data selector 310 is connected to m data lines, and the input end of each data selector 310 is connected to one second fan-out trace 130. In some embodiments where m is 3, the data selector 310 is a one-out-of-three data selector, and the output of each data selector 310 is connected to 3 data lines. For example, for a display panel with RGB horizontal arrangement resolution of 1920 × 1080, the number of data lines is 5760, and for a display panel with RGB horizontal arrangement resolution of 1920 lines, the data driving of 5760 data lines can be realized only by driving two source chips.
In view of the above, the one-out-of-three data selector includes: a first active switch 141, a second active switch 142 and a third active switch 143. Specifically, as shown in fig. 4, the output terminal of the first active switch 141 is connected to the first data line. The output terminal of the second active switch 142 is connected to the second data line. The output terminal of the third active switch 143 is connected to the third data line. The input terminals of the first active switch 141, the second active switch 142, and the third active switch 143 are connected to the same second fan-out trace 130. It is understood that the first active switch 141, the second active switch 142, and the third active switch 143 are also respectively connected to a time division switch control line, and the time division switch control line is connected to separate controllers.
Of course, for the embodiment where m is 4, then the data selector uses a one-out-of-four data selector. For the composition and connection of the one-out-of-four data selector, please refer to the aforementioned embodiment where m is 3, which is not described herein again.
In the embodiment, the data selection circuit 140 is arranged to connect one fan-out wire with a plurality of data lines, so that the number of the fan-out wires can be reduced, the material of the fan-out wires is saved, and the effect of saving cost is achieved.
Because both sides all are provided with the fan-out about the display area of this application embodiment array substrate and walk the line, and the group number that the fan-out was walked the line is different, and the fan-out of different groups number is walked the line and can be satisfied the market demand of different panels. For example, a fan-out trace of 1440 is used if 144HZ is required; the fan-out trace of 960 is used when a 60HZ is required. It should be noted that, in the embodiment, the same set of mask can be used to simultaneously develop two types of panels, and thus, the cost is not increased. In other words, the present application achieves the value of fully developing the panel without increasing the cost.
As shown in fig. 5, an embodiment of the present application further provides a method for manufacturing a display panel, including the following steps:
s110: forming the array substrate in the above embodiment;
s120: binding a data chip on the array substrate;
s130: forming a color film substrate;
s140: and the color film substrate and the array substrate are oppositely formed into a display panel.
By the manufacturing method, the display panel meeting various requirements can be obtained, the functions of the panel are expanded, and the value of the panel is developed. It should be noted that the array substrate of the present application can be used as an intermediate product to provide a composite array substrate including a high refresh display panel and a low refresh display panel, and the composite array substrate can be selected according to the subsequent requirements of the high refresh or low refresh display panel, and specifically, the data chip is bound to the first binding region or the second binding region, so that different types of display panels can be realized.
Taking the low refresh display panel as an example, as shown in fig. 6, in one embodiment, S120: the step of binding the data chip on the array substrate comprises the following substeps:
s121 a: cutting off the first binding routing and the first fan-out routing along the first cutting mark;
s122 a: and binding the data chip on the second binding area.
The data chip is bound on the second binding area, and the first binding routing and the first fan-out routing are cut off, specifically, the cutting mark is located in the middle of the first fan-out routing or the area of the first fan-out routing close to the first binding routing. The first fan-out wiring and the second binding area which are not needed are directly cut off, after the display panel with low refreshing or high refreshing is selected, the first fan-out wiring or the second fan-out wiring on the other side is not needed, the display is not affected after cutting off, the area of the non-display area can be reduced, and the screen occupation ratio is improved. As shown in fig. 7, a display panel is shown in which a portion of the first fan-out traces and the first bonding area are cut away along the first cut marks.
In some other embodiments, the array substrate may further include: a first cutting mark 13 and a second cutting mark 14. Specifically, the first cutting mark 13 is disposed corresponding to the first fan-out trace 120, and the second cutting mark 14 is disposed corresponding to the second fan-out trace 130. Further, a cutting mark passes through the middle area of the fan-out routing and is parallel to one side of the array substrate, and the cutting mark is, for example, a colored dotted line or solid line, or a mark located at the edge of the array substrate, and is used for identifying the cutting position by a machine. Designing the cutting marks facilitates the cutting step of the manufacturing process and can be used as a reference for the cutting step. Specifically, after the array substrate is cut along the first cutting mark, a part of the first fan-out trace is reserved at a position of the array substrate corresponding to the first fan-out trace, and a metal layer and a protective layer which correspondingly form the first fan-out trace are arranged on a film layer corresponding to the position.
As shown in fig. 8, in another embodiment, S120 includes the following sub-steps:
s121 b: cutting off the second binding routing and the second fan-out routing along the second cutting mark;
s122 b: and binding the data chip on the first binding area.
Fig. 9 shows a display panel manufactured by the manufacturing method corresponding to fig. 8, wherein the data chip 30 is bound on the first binding region, and a part of the corresponding second fan-out trace is reserved, but of course, in different types of display panels, the second fan-out trace may be completely cut off.
Different from the two embodiments, the present application also discloses another method for manufacturing a display panel, in S120: the method for binding the data chip on the array substrate comprises the following steps: and binding the data chip on the first binding area and the second binding area. The data chips are bound in the first binding area and the second binding area simultaneously, and can be mutually converted in a low refresh rate and a high refresh rate according to actual needs, for example, the data chips on one side of the first binding area are used for driving under the condition that 60HZ display is needed, and the data chips on one side of the second binding area are used for driving under the condition that 120HZ display is needed.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. An array substrate divided into a display area and a non-display area, comprising:
the data lines are used for providing data signals for the array substrate;
the plurality of first fan-out wires are arranged in the non-display area, the number of the first fan-out wires is the same as that of the data lines, and the first fan-out wires are connected with one end of each data line in a one-to-one correspondence mode;
the second fan-out routing lines are arranged in the non-display area, the ratio of the number of the data lines to the number of the second fan-out routing lines is m, and m is an integer larger than 1;
the data selection circuit is connected with the second fan-out routing and the data line;
the first binding area is arranged on one side, corresponding to the first fan-out routing, of the array substrate, and is provided with first binding routing which is connected with the first fan-out routing in a one-to-one correspondence manner; and
and the second binding area is arranged on one side of the array substrate corresponding to the second fan-out wiring, and is provided with a second binding wiring which is in one-to-one corresponding connection with the second fan-out wiring.
2. The array substrate of claim 1, wherein the data selection circuit comprises a plurality of data selectors, the number of the data selectors is the same as the number of the second fan-out traces, an output terminal of each data selector is connected to m data lines, and an input terminal of each data selector is connected to one second fan-out trace.
3. An array substrate according to claim 2, wherein m is 3, each data selector is connected to 3 data lines, and the data selector is a one-out-of-three data selector.
4. The array substrate of claim 3, wherein the one-out-of-three data selector comprises:
the output end of the first active switch is connected with the first data line;
the output end of the second active switch is connected with a second data line; and
the output end of the third active switch is connected with a third data line;
the input ends of the first active switch, the second active switch and the third active switch are connected to the same second fan-out wiring.
5. The array substrate of claim 1, wherein the array substrate further comprises:
the first cutting mark is arranged corresponding to the first fan-out routing; and
and the second cutting mark is arranged corresponding to the second fan-out routing.
6. A manufacturing method of a display panel is characterized by comprising the following steps:
forming a substrate;
depositing a metal layer on a substrate;
the patterning metal layer corresponds to the non-display area to form a plurality of first fan-out wires, a plurality of second fan-out wires, a first binding area and a second binding area; forming a plurality of data lines corresponding to the display area;
forming a plurality of data selectors;
forming an array substrate;
binding a data chip on the first binding region or the second binding region of the array substrate;
forming a color film substrate;
and the color film substrate and the array substrate are oppositely formed into a display panel.
7. The method of claim 6, wherein the step of bonding the data chips on the array substrate comprises:
cutting off the first binding routing and the first fan-out routing along the first cutting mark; and
and binding the data chip on the second binding area.
8. The method of claim 6, wherein the step of bonding the data chips on the array substrate comprises:
cutting off the second binding routing and the second fan-out routing along the second cutting mark; and
and binding the data chip on the first binding area.
9. The method of claim 6, wherein the step of bonding the data chips on the array substrate comprises:
and binding the data chip on the first binding area and the second binding area.
10. A display panel, comprising the array substrate according to any one of claims 1 to 5, a color filter substrate disposed in a box-to-box relationship with the array substrate, and a display medium layer disposed between the array substrate and the color filter substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110254156.2A CN113009741B (en) | 2021-03-09 | 2021-03-09 | Array substrate, display panel and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110254156.2A CN113009741B (en) | 2021-03-09 | 2021-03-09 | Array substrate, display panel and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113009741A true CN113009741A (en) | 2021-06-22 |
| CN113009741B CN113009741B (en) | 2022-07-08 |
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| CN114283706A (en) * | 2021-12-28 | 2022-04-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN115826297A (en) * | 2022-12-28 | 2023-03-21 | Tcl华星光电技术有限公司 | Backlight module and display device |
| US12009467B1 (en) | 2022-12-28 | 2024-06-11 | Tcl China Star Optoelectronics Technology Co., Ltd. | Backlight modules and display devices |
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| CN115826297A (en) * | 2022-12-28 | 2023-03-21 | Tcl华星光电技术有限公司 | Backlight module and display device |
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