CN111081151A - Display panel - Google Patents
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- CN111081151A CN111081151A CN202010018362.9A CN202010018362A CN111081151A CN 111081151 A CN111081151 A CN 111081151A CN 202010018362 A CN202010018362 A CN 202010018362A CN 111081151 A CN111081151 A CN 111081151A
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- China
- Prior art keywords
- circuit board
- pin
- alignment mark
- display panel
- equal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
Abstract
The application discloses a display panel, which at least comprises a display area and a non-display area, wherein the display panel comprises a first binding part positioned in the non-display area; the circuit board is connected with the first binding part and comprises a first circuit board and a second circuit board which is positioned above the first circuit board and covers part of the first circuit board; the first circuit board is at least provided with a first pin and a first alignment mark arranged on at least one side of the first pin; the second circuit board is at least provided with a second pin and a second alignment mark arranged on at least one side of the second pin; the second alignment mark of the second circuit board is at least partially exposed outside the first circuit board, so that the problems of identification errors of the binding marks and mutual shielding of the binding marks when the circuit board is bound to the first binding part of the display panel are solved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
With the continuous development of display technologies, display panels with high resolution and high refresh rate are widely popular, in order to ensure that each pixel has sufficient charging time under the high refresh rate and avoid the problem of image distortion when the display panel displays due to insufficient charging of the pixels, generally, a pixel driving structure with Half of scanning lines and double of Data lines (Half Gate, twoData, HG2D) is mostly adopted in 8K resolution products, and the number of Data lines and binding terminals of the HG2D pixel driving structure is doubled compared with the pixel driving structure with one Gate and one Data line (l Gate 1Data, 1G 1D). To meet the design of peripheral space, a Chip On Film (COF) design with the number of bonding terminals supporting 960 × 2 is adopted, including a dual L-type COF design. Because the sizes of the 2 COFs designed by the double L-type COFs are basically the same, the problem that the binding marks are mistakenly identified and mutually shielded during binding easily occurs, and the yield is influenced.
Disclosure of Invention
The embodiment of the application provides a display panel, which can solve the problems that when a circuit board is bound with the display panel, the binding marks are identified wrongly and the binding marks are shielded mutually.
The embodiment of the application provides a display panel, display panel has a display area and non-display area at least, display panel includes:
a first binding part located in the non-display area;
the circuit board is connected with the first binding part and comprises a first circuit board and a second circuit board which is positioned above the first circuit board and covers part of the first circuit board;
the first circuit board is at least provided with a first pin and a first alignment mark arranged on at least one side of the first pin;
the second circuit board is at least provided with a second pin and a second alignment mark arranged on at least one side of the second pin;
wherein the second alignment mark of the second circuit board is at least partially exposed outside the first circuit board.
In some embodiments, the first circuit board and the second circuit board are L-like shaped; in a top view, the output pins on the first circuit board and the output pins on the second circuit board are located in different rows.
In some embodiments, the first circuit board comprises two first alignment marks arranged on two sides of the first pin;
the second circuit board comprises two second alignment marks arranged on two sides of the second pin;
the distance between the two first alignment marks is smaller than the distance between the two second alignment marks.
In some embodiments, the difference between the distance between two of the second alignment marks and the distance between two of the first alignment marks is greater than or equal to 1mm and less than or equal to 25 mm.
In some embodiments, the difference between the distance between two of the second alignment marks and the distance between two of the first alignment marks is greater than or equal to 5mm and less than or equal to 20 mm.
In some embodiments, the distance between two of the first alignment marks is greater than or equal to 40mm and less than or equal to 50 mm; the distance between two second alignment marks is greater than or equal to 50mm and less than or equal to 65 mm.
In some embodiments, in a top view, the second circuit board has at least one dummy pin between the second alignment mark and the second pin, and the dummy pin is on the same layer as the second pin.
In some embodiments, the first alignment mark is one of a circle, a T-shape, a rectangle, a groove and a boss, and the second alignment mark is one of a circle, a T-shape, a rectangle, a groove and a boss.
In some embodiments, the first binding part includes first and second binding terminals arranged in a double row;
at least one side of the first binding terminal is provided with a third alignment mark corresponding to the first alignment mark;
and at least one side of the second binding terminal is provided with a fourth alignment mark corresponding to the second alignment mark.
In some embodiments, the first circuit board and the second circuit board are flip-chip on films.
An embodiment of the present application provides a display panel, the display panel has a display area and a non-display area at least, the display panel includes: a first binding part located in the non-display area; the circuit board is connected with the first binding part and comprises a first circuit board and a second circuit board which is positioned above the first circuit board and covers part of the first circuit board; the first circuit board is at least provided with a first pin and a first alignment mark arranged on at least one side of the first pin; the second circuit board is at least provided with a second pin and a second alignment mark arranged on at least one side of the second pin; the second alignment mark of the second circuit board is at least partially exposed outside the first circuit board, so that the problems of identification error of the binding mark and mutual shielding of the binding mark when the circuit board is bound to the first binding part of the display panel are solved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 2A is a schematic structural diagram of a first circuit board according to a first embodiment of the present disclosure;
fig. 2B is a schematic structural diagram of a second circuit board according to the first embodiment of the present application;
fig. 2C is a schematic structural diagram of a first circuit board binding portion according to the first embodiment of the present application;
fig. 3A is a schematic structural diagram of a first circuit board according to a second embodiment of the present application;
fig. 3B is a schematic structural diagram of a second circuit board according to a second embodiment of the present application;
fig. 3C is a schematic structural diagram of a first circuit board binding portion according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of a first binding portion of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Specifically, please refer to fig. 1, which is a schematic structural diagram of a display panel provided in an embodiment of the present application; the display panel 100 at least has a display area 100a and a non-display area 101, and the display panel 100 includes:
a first binding part 101a located in the non-display area 101;
a circuit board 102, the circuit board 102 being connected to the first binding part 101a, the circuit board 102 including a first circuit board 1021 and a second circuit board 1022 located above the first circuit board 1021 and covering a portion of the first circuit board 1021;
fig. 2A is a schematic structural diagram of a first circuit board according to a first embodiment of the present application; the first circuit board 1021 at least has a first pin 1023 and a first alignment mark 1025 arranged on at least one side of the first pin 1023;
fig. 2B is a schematic structural diagram of a second circuit board according to a first embodiment of the present application; the second circuit board 1022 has at least a second pin 1024, and a second alignment mark 1026 disposed on at least one side of the second pin 1024;
the second alignment mark 1026 of the second circuit board 1022 is at least partially exposed outside the first circuit board 1021, so as to avoid the problem that the second alignment mark 1026 of the second circuit board 1022 is shielded by the first circuit board 1021 when the circuit board 102 is bonded to the first bonding portion 101a of the display panel 100, which affects the product yield.
The first alignment mark 1025 is one of a circle, a T-shape, a rectangle, a groove and a boss, and the second alignment mark 1026 is one of a circle, a T-shape, a rectangle, a groove and a boss.
Specifically, referring to fig. 2A, the first alignment mark 1025 is T-shaped; referring to fig. 2B, the second alignment mark 1026 is circular in shape, so as to avoid a problem of a mark recognition error when the first circuit board 1021 and the second circuit board 1022 are bound to the first binding portion 101a of the display panel 100.
If the shape of the first alignment mark 1025 is the same as the shape of the second alignment mark 1026, the size of the first alignment mark 1025 is different from the size of the second alignment mark 1026; specifically, the first alignment mark 1025 and the second alignment mark 1026 are both circular, and the diameter of the first alignment mark 1025 is smaller than the diameter of the second alignment mark 1026, so as to avoid the problem of a mark identification error when the first circuit board 1021 and the second circuit board 1022 are bound to the first binding portion 101a of the display panel 100.
With continued reference to fig. 2A and 2B, first pin 1023 includes a plurality of pins, which can be arranged side by side, and first pin 1023 includes two outermost pins 1023a and 1023B, and first alignment mark 1025 is disposed on a side of pin 1023a away from pin 1023B and/or first alignment mark 1025 is disposed on a side of pin 1023B away from pin 1023 a.
If the first alignment mark 1025 is disposed on the side of the pin 1023a away from the pin 1023b, the distance from the first alignment mark 1025 to the center of the pin 1023a is greater than or equal to 150 μm and less than or equal to 250 μm; further, the first alignment mark 1025 is located a distance equal to 200 μm from the center of pin 1023 a. Similarly, it can be seen that when the first alignment mark 1025 is disposed on the side of the pin 1023b away from the pin 1023a, the first alignment mark 1025 is spaced from the center of the pin 1023 a.
Similarly, the second pin 1024 includes a plurality of pins, a plurality of the pins may be disposed side by side, two outermost pins 1024a and 1024b are disposed in the second pin 1024, the second alignment mark 1026 is disposed on a side of the pin 1024a away from the pin 1024b, and/or the second alignment mark 1026 is disposed on a side of the pin 1024b away from the pin 1024 a.
If the second alignment mark 1026 is disposed on a side of the pin 1024a away from the pin 1024b, a distance between the second alignment mark 1026 and a center of the pin 1024a is greater than or equal to 150 μm and less than or equal to 250 μm; further, the second alignment mark 1026 is located a distance equal to 200 μm from the center of the pin 1024 a. Similarly, when the second alignment mark 1026 is disposed on the side of the pin 1024b away from the pin 1024a, the distance between the second alignment mark 1026 and the center of the pin 1024a can be obtained.
Since the first circuit board 1021 is bonded before the second circuit board 1022 when the first bonding portion 101a of the display panel 100 is bonded, in order to avoid interference between the first circuit board 1021 and the second circuit board, a difference between a distance d2 of the second alignment mark 1026 from the second pin 1024 and a distance d1 of the first alignment mark 1025 from the first pin 1023 is greater than or equal to 0.5mm, that is: d2-d1 is more than or equal to 0.5 mm; further, the difference between the distance d2 of the second alignment mark 1026 from the second pin 1024 and the distance d1 of the first alignment mark 1025 from the first pin 1023 is equal to 5mm, i.e.: d2-d1 is 5 mm.
With reference to fig. 2A and fig. 2B, the first circuit board 1021 and the second circuit board 1022 are L-like; in the top view, the output pins 1027 on the first circuit board 1021 and the output pins 1028 on the second circuit board 1022 are in different columns.
Wherein, the output pin 1027 on the first circuit board 1021 is arranged opposite to the first pin 1023 on the first circuit board 1021; the output pins 1028 on the second circuit board 1022 are disposed opposite to the second pins 1024 on the second circuit board 1022.
Specifically, referring to fig. 2C, which is a schematic structural view illustrating a first circuit board binding portion provided in the first embodiment of the present application, when the first binding portion 101a of the display panel is bound, output pins 1027 on the first circuit board 1021 and output pins 1028 on the second circuit board 1022 are staggered, so as to reduce interference between the first circuit board 1021 and the second circuit board 1022.
The first circuit board 1021 and the second circuit board 1022 are flip-chip films; the output pins 1027 on the first circuit board 1021 and the output pins 1028 on the second circuit board 1022 may be externally connected to the rigid printed circuit board 103, so as to realize electrical interconnection between the display panel and the electronic components on the rigid printed circuit board 103.
On the premise of not affecting the routing and module assembly, the position I in fig. 2A and 2B may be designed to be an arc structure, so as to prevent the first circuit board 1021 and the second circuit board 1022 from being easily torn at the position I, which affects the yield of the product.
Please refer to fig. 3A, which is a schematic structural diagram of a first circuit board according to a second embodiment of the present application; please refer to fig. 3B, which is a schematic structural diagram of a second circuit board according to a second embodiment of the present application;
the first circuit board 1021 includes two first alignment marks 1025 arranged on two sides of the first pin 1023;
the second circuit board 1022 includes two second alignment marks 1026 disposed on two sides of the second pin 1024;
the distance d3 between two of the first alignment marks 1025 is less than the distance d4 between two of the second alignment marks 1025.
Specifically, the difference between the distance d4 between two of the second alignment marks 1026 and the distance d3 between two of the first alignment marks 1025 is greater than or equal to 1mm and less than or equal to 25mm, i.e.: d4-d3 is not less than 1mm and not more than 25 mm.
Further, the difference between the distance d4 between two of the second alignment marks 1026 and the distance d3 between two of the first alignment marks 1025 is greater than or equal to 5mm and less than or equal to 20mm, i.e.: d4-d3 is not less than 5mm and not more than 20 mm.
The distance d3 between the two first alignment marks 1025 and the distance d4 between the two second alignment marks 1026 can be adjusted according to the size of the display panel, and for the convenience of understanding, taking the display panel with a size less than or equal to 85 inches as an example, the distance d3 between the two first alignment marks 1025 is greater than or equal to 40mm and less than or equal to 50mm, that is: d3 is more than or equal to 40mm and less than or equal to 50 mm; the distance d4 between two of the second alignment marks 1026 is greater than or equal to 50mm and less than or equal to 65mm, i.e.: d4 is more than or equal to 50mm and less than or equal to 65 mm.
Further, the distance d3 between two of the first alignment marks 1025 is greater than or equal to 42mm and less than or equal to 50mm, i.e.: d3 is more than or equal to 42mm and less than or equal to 50 mm; the distance d4 between two of the second alignment marks 1026 is greater than or equal to 50mm and less than or equal to 63mm, i.e.: d4 is more than or equal to 50mm and less than or equal to 63 mm.
Since the distance d4 between two of the second alignment marks 1026 is greater than the distance d3 between two of the first alignment marks 1025, the second circuit board 1022 provides dummy pins 1022a between the second pins 1024 and the second alignment marks 1026, as shown in fig. 2B.
Referring to fig. 3C, which is a schematic structural diagram illustrating a circuit board binding a first binding portion according to a second embodiment of the present disclosure, in a top view, the second circuit board 1022 has at least one dummy pin 1022a between the second alignment mark 1026 and the second pin 1024, the dummy pin 1022a is on the same layer as the second pin 1024, and the dummy pin 1022a is not used for signal transmission.
Please refer to fig. 4, which is a schematic structural diagram of a first binding portion of a display panel according to an embodiment of the present application, wherein the first binding portion 101a of the display panel includes a first binding terminal 1013 and a second binding terminal 1014 arranged in a double row;
at least one side of the first binding terminal 1013 is provided with a third alignment mark 1015 corresponding to the first alignment mark 1025;
at least one side of the second binding terminal 1014 is provided with a fourth alignment mark 1016 corresponding to the second alignment mark 1026, so as to avoid a problem of a mark recognition error occurring when the first circuit board 1021 and the second circuit board 1022 bind the first binding portion 101a of the display panel 100.
In some embodiments, the third alignment mark 1015 is the same shape as the first alignment mark 1025; a vertical projection of the first alignment mark 1025 on the first binding portion 101a of the display panel 100 coincides with the third alignment mark 1015, as shown in fig. 2C.
The shape of the fourth alignment mark 1016 is the same as the shape of the second alignment mark 1026; a perpendicular projection of the second alignment mark 1026 onto the first binding portion 101a of the display panel 100 coincides with the fourth alignment mark 1016, as shown in fig. 2C.
Specifically, the first alignment mark 1025 is located a distance from the first pin 1023 that is equal to the third alignment mark 1015 from the first binding terminal 1013; the second alignment mark 1026 is located a distance from the second pin 1024 equal to the fourth alignment mark 1016 is located a distance from the second binding terminal 1014.
In some embodiments, the first binding part 101a includes two of the third alignment marks 1015 disposed on both sides of the first binding terminal 1013, and two of the fourth alignment marks 1016 disposed on both sides of the second binding terminal 1014;
the distance between two of the third alignment marks 1015 is smaller than the distance between two of the fourth alignment marks 1016, and the distance between two of the third alignment marks 1015 is equal to the distance between two of the first alignment marks 1025; the distance between two of the fourth registration marks 1016 is equal to the distance between two of the second registration marks 1026.
In an embodiment of the present application, a display panel 100 is provided, where the display panel 100 at least has a display area 100a and a non-display area 101, and the display panel 100 includes: a first binding part 101a located in the non-display area 101; a circuit board 102, the circuit board 102 being connected to the first binding part 101a, the circuit board 102 including a first circuit board 1021 and a second circuit board 1022 located above the first circuit board 1021 and covering a portion of the first circuit board 1021; the first circuit board 1021 at least has a first pin 1023 and a first alignment mark 1025 arranged on at least one side of the first pin 1023; the second circuit board 1022 has at least a second pin 1024, and a second alignment mark 1026 disposed on at least one side of the second pin 1024; the second alignment mark 1026 of the second circuit board 1022 is at least partially exposed outside the first circuit board 1021, so as to improve the problems of a binding mark recognition error and a binding mark shielding each other when the circuit board 102 is bound to the first binding portion 101a of the display panel 100.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel provided by the embodiment of the present application is described in detail above, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel having at least a display area and a non-display area, the display panel comprising:
a first binding part located in the non-display area;
the circuit board is connected with the first binding part and comprises a first circuit board and a second circuit board which is positioned above the first circuit board and covers part of the first circuit board;
the first circuit board is at least provided with a first pin and a first alignment mark arranged on at least one side of the first pin;
the second circuit board is at least provided with a second pin and a second alignment mark arranged on at least one side of the second pin;
wherein the second alignment mark of the second circuit board is at least partially exposed outside the first circuit board.
2. The display panel according to claim 1, wherein the first circuit board and the second circuit board are L-like shaped; in a top view, the output pins on the first circuit board and the output pins on the second circuit board are located in different rows.
3. The display panel according to claim 1,
the first circuit board comprises two first alignment marks arranged on two sides of the first pin;
the second circuit board comprises two second alignment marks arranged on two sides of the second pin;
the distance between the two first alignment marks is smaller than the distance between the two second alignment marks.
4. The display panel according to claim 3, wherein a difference between a distance between the two second alignment marks and a distance between the two first alignment marks is greater than or equal to 1mm and less than or equal to 25 mm.
5. The display panel according to claim 4, wherein a difference between a distance between the two second alignment marks and a distance between the two first alignment marks is greater than or equal to 5mm and less than or equal to 20 mm.
6. The display panel according to claim 3, wherein a distance between two of the first alignment marks is greater than or equal to 40mm and less than or equal to 50 mm; the distance between two second alignment marks is greater than or equal to 50mm and less than or equal to 65 mm.
7. The display panel of claim 3, wherein the second circuit board has at least one dummy pin between the second alignment mark and the second pin in a top view, and the dummy pin is on the same layer as the second pin.
8. The display panel according to claim 1, wherein the first alignment mark has a shape of one of a circle, a T-shape, a rectangle, a groove and a projection, and the second alignment mark has a shape of one of a circle, a T-shape, a rectangle, a groove and a projection.
9. The display panel according to claim 1, wherein the first binding part includes first and second binding terminals arranged in a double row;
at least one side of the first binding terminal is provided with a third alignment mark corresponding to the first alignment mark;
and at least one side of the second binding terminal is provided with a fourth alignment mark corresponding to the second alignment mark.
10. The display panel of claim 1, wherein the first circuit board and the second circuit board are flip-chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010018362.9A CN111081151A (en) | 2020-01-08 | 2020-01-08 | Display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010018362.9A CN111081151A (en) | 2020-01-08 | 2020-01-08 | Display panel |
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| CN111081151A true CN111081151A (en) | 2020-04-28 |
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| CN202010018362.9A Pending CN111081151A (en) | 2020-01-08 | 2020-01-08 | Display panel |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112800713A (en) * | 2021-02-10 | 2021-05-14 | 深圳市华星光电半导体显示技术有限公司 | Automatic conversion method and system for binding pins |
| CN113009741A (en) * | 2021-03-09 | 2021-06-22 | 北海惠科光电技术有限公司 | Array substrate, display panel and manufacturing method thereof |
| CN113421909A (en) * | 2021-06-24 | 2021-09-21 | 云谷（固安）科技有限公司 | Display panel and display device |
| WO2022236780A1 (en) * | 2021-05-13 | 2022-11-17 | 京东方科技集团股份有限公司 | Circuit board, chip on film, display device, and bonding method |
| WO2023221194A1 (en) * | 2022-05-18 | 2023-11-23 | 武汉华星光电半导体显示技术有限公司 | Display module and mobile terminal |
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