CN109728005B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN109728005B CN109728005B CN201910113120.5A CN201910113120A CN109728005B CN 109728005 B CN109728005 B CN 109728005B CN 201910113120 A CN201910113120 A CN 201910113120A CN 109728005 B CN109728005 B CN 109728005B
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Abstract
The invention discloses an array substrate, a display panel and a display device, belongs to the technical field of display, and is used for improving the phenomenon of split display of a notch screen in the prior art. The first area of the array substrate comprises a first display area, the second area comprises a second display area located on the periphery of the first non-display area, and the number of any row of sub-pixels in the second display area is less than that of any row of sub-pixels in the first display area; further comprising: the first metal layer and the second metal layer are arranged on the substrate base plate, the active layer is positioned between the substrate base plate and the first metal layer, the second metal layer comprises a plurality of data lines, each data line is wired along the first direction of the substrate base plate, and the first metal layer comprises a plurality of grid lines crossed with the data lines; the active layer in the first non-display area is provided with a plurality of first active structures, and each first active structure is overlapped with the grid line in the first non-display area in the direction perpendicular to the substrate base plate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
The full-screen display is a panel framework with the highest proportion of the panel display at present, so that the display panel with the full-screen design is more and more popular with consumers. The utility model provides a design of "qiliu" that comparatively common comprehensive screen adopts and uses iPhone X as the representative, and this kind of screen can be called notch screen again, and the design of dysmorphism groove has been added on the display screen top to notch screen for spare parts such as installing camera, speaker, three-dimensional identification sensor and infrared sensor.
An Active Area (AA) near the existing full screen notch can be driven by an interlaced scanning (interlace) driving method. The gate (gate) lines penetrate through the special-shaped display area through M1 metal layer straight-pull routing, namely only one gate line is adopted in each row, and the data (data) lines are crossed with the gate line routing of the special-shaped display area through the M2 metal layer, so that a coupling capacitance phenomenon similar to that between the M1 metal layer and the M2 metal layer in the normal display area can be formed between the M1 metal layer and the M2 metal layer in the special-shaped display area, and data loading (data loading) of the special-shaped display area is close to that in the normal display area.
However, due to the fact that the notch screen is provided with the special-shaped groove, for the special-shaped display area, the number of sub-pixels through which one Gate line passes is smaller, and therefore compared with the normal display area, the coupling capacitance effect of the M1 metal layer in the special-shaped display area is weaker, the Gate delay (delay) phenomenon of the special-shaped display area is reduced, the brightness of the special-shaped display area is higher, the phenomenon of split display of the whole screen occurs, and the use experience of a user is affected.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for improving the phenomenon of split display of a notch screen in the prior art.
In a first aspect, an array substrate is provided, which includes a first area and a second area, where the first area includes a first display area, the second area includes a first non-display area and a second display area located at a periphery of the first non-display area, and a number of sub-pixels in any row in the second display area is less than a number of sub-pixels in any row in the first display area; the array substrate includes:
the active layer is positioned between the substrate base plate and the first metal layer, the second metal layer comprises a plurality of data lines, each data line is wired along a first direction of the substrate base plate, and the first metal layer comprises a plurality of grid lines intersected with the data lines;
the active layer in the first non-display area is provided with a plurality of first active structures, and each first active structure is overlapped with the grid line in the first non-display area in the direction perpendicular to the substrate base plate.
In one possible implementation, each of the first active structures is electrically connected to a corresponding data line.
In one possible implementation manner, the array substrate further includes an insulating layer located between the first metal layer and the active layer;
the insulating layer in the first non-display area includes a plurality of first via holes;
and each first active structure is electrically connected with the corresponding data line through the corresponding first through hole.
In one possible implementation, the first active structure is a line structure;
the wiring direction of the first active structures is the same as the wiring direction of the data lines, and the projection of each first active structure on the substrate base plate is superposed with the projection of each first active structure corresponding to the data line on the substrate base plate.
In a possible implementation manner, a plurality of display sub-pixels arranged in an array are arranged in the first display area;
the active layer in the first display area is provided with second active structures which correspond to the display sub-pixels one by one;
wherein a width of the first active structure is greater than a width of the second active structure.
In one possible implementation, the width of the first active structure is twice the width of the second active structure.
In one possible implementation, the first active structure is made of a low-temperature polysilicon material.
In one possible implementation, the second display area includes a first sub-display area and a second sub-display area;
and the grid line positioned in the first sub-display area extends to the second sub-display area through the first non-display area.
In a possible implementation manner, the first non-display area includes a first sub non-display area and a second sub non-display area, each of the first active structures is disposed on the active layer located in the first sub non-display area, a plurality of virtual sub-pixels arranged in an array are disposed in the second sub non-display area, and the virtual sub-pixels are always in a dark state; and the number of the first and second groups,
the active layer in the second sub non-display area is provided with a plurality of third active structures which correspond to the virtual sub-pixels one by one;
and each third active structure is overlapped with the grid line in the first non-display area in the direction vertical to the substrate base plate.
In one possible implementation, the third active structure is a U-shaped structure, and includes a horizontal portion and two vertical portions, where the horizontal portion and the vertical portions are perpendicular to each other;
and the projection of the horizontal part of each third active structure on the substrate is overlapped with the projection of the grid line corresponding to each third active structure on the substrate.
In one possible implementation form of the method,
the insulating layer positioned in the second sub non-display area comprises a plurality of second through holes;
and one vertical part of each third active structure is electrically connected with the corresponding data line through the corresponding second through hole.
In a second aspect, an embodiment of the present invention provides a display panel, including: the array substrate is provided.
In a third aspect, an embodiment of the present invention provides a display device, including: the display panel is provided.
The invention has the following beneficial effects:
the embodiment of the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises: the first metal layer comprises a plurality of data lines, each data line is wired along a first direction of the substrate base plate, and the second metal layer comprises a plurality of grid lines intersected with the data lines; the active layer in the first non-display area is provided with a plurality of first active structures, and each first active structure is overlapped with the grid line in the first non-display area in the direction perpendicular to the substrate base plate. According to the array substrate provided by the embodiment of the invention, the first active structure overlapped with the grid lines is arranged in the first non-display area, so that the first active structure and the grid lines in the first non-display area form a capacitance structure, the coupling capacitance effect of the grid lines at the notch area is increased, the coupling capacitance effect of the grid lines in the special-shaped display area is closer to that of the normal display area, the display split phenomenon of the notch screen is improved, and the user experience is improved.
Drawings
FIG. 1 is a schematic top view of a prior art notch screen;
FIG. 2 is a schematic diagram of the wiring of a panel of a notch screen in the prior art;
FIG. 3 is an enlarged schematic view of section I of FIG. 2;
FIG. 4 is a schematic diagram of a prior art connection of a subpixel to poly;
FIG. 5 is a diagram illustrating a split screen phenomenon in the prior art;
fig. 6 is a schematic top view of an array substrate according to an embodiment of the invention;
fig. 7 is a schematic wiring diagram of an array substrate according to an embodiment of the present invention;
fig. 8 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention;
fig. 9 is a schematic view of a local wiring of the array substrate in the first non-display area according to the embodiment of the invention;
fig. 10 is one of schematic views of distribution positions of the deformed grooves P;
fig. 11 is a second schematic diagram of the distribution positions of the profile grooves P;
FIG. 12 is a third schematic view showing the distribution positions of the profile grooves P;
fig. 13 is another schematic top view of an array substrate according to an embodiment of the invention;
fig. 14 is a schematic diagram of a third active structure provided in accordance with an embodiment of the present invention;
fig. 15 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;
fig. 16 is a schematic top view of a mobile phone according to an embodiment of the present invention.
Detailed Description
The full-screen display is a panel framework with the highest proportion of the panel display at present, so that the display panel with the full-screen design is more and more popular with consumers. The utility model provides a design of "qiliu" that comparatively common comprehensive screen adopts and uses iPhone X as the representative, and this kind of screen can be called notch screen again, and the design of dysmorphism groove has been added on the display screen top to notch screen for spare parts such as installing camera, speaker, three-dimensional identification sensor and infrared sensor.
Referring to fig. 1 to 3, fig. 1 is a schematic top view of a notch screen in the prior art, fig. 2 is a schematic panel wiring diagram of the notch screen, and fig. 3 is an enlarged schematic view of a part I of fig. 2.
As shown in fig. 1, the notch screen is generally provided with a special-shaped groove P at the top of the screen, so that the display area of the notch screen is divided into two parts, namely, the special-shaped display area AA1 and the normal display area AA2 by using the bottom of the special-shaped groove P as a boundary.
The gate lines in the irregular display area AA1 penetrate through the irregular display area directly, as shown in fig. 2, after being led out from the gate driver 10, the gate lines in each row in the irregular display area AA1 pass through the irregular display area AA1 on one side of the irregular groove P and extend to the irregular display area on the other side of the irregular groove P along the notch edge, and after being led out from the source driver 30, the data lines intersect with the gate lines in the irregular display area AA1, as shown in fig. 3, so that a coupling capacitance phenomenon similar to that between the M1 metal layer and the M2 metal layer in the normal display area can be formed between the M1 metal layer and the M2 metal layer in the irregular display area AA1, and the data loading of the irregular display area is close to the normal display area.
In the display region, the sub-pixels 501 are arranged in an array, as shown in fig. 4, the pixel electrodes of the sub-pixels 501 are connected to the poly 502 arranged in the active layer through the drain electrodes and via a via N2 arranged on the insulating layer, the poly 502 is further connected to the data line 40 through another via N1, the gate line 20 crosses the poly 502, and thus the overlapping region of the gate line 20 and the poly 502 can form a capacitor structure. However, since the notch screen is provided with the special-shaped groove P, for the special-shaped display area AA1, the number of sub-pixels passed by one Gate line is small, so that compared with the normal display area AA2, the coupling capacitance of the M1 metal layer in the special-shaped display area AA1 is weaker, the Gate delay phenomenon in the special-shaped display area is reduced, the luminance of the special-shaped display area is higher, the phenomenon of split display as shown in fig. 5 occurs on the whole screen, and the user experience is affected.
Aiming at the problem of split display existing in a notch screen, the embodiment of the invention provides an array substrate, a display panel and a display device.
The following describes in detail a specific embodiment of a display panel and a display device according to an embodiment of the present invention with reference to the drawings. The thicknesses and shapes of the components or layers in the drawings are not intended to be actual scale, but are merely illustrative of the present invention.
As shown in fig. 6, an array substrate according to an embodiment of the present invention is a schematic top view of the array substrate, and includes: a first area including a first display area AA2, and a second area including a first non-display area B and a second display area AA1 located at the periphery of the first non-display area, the number of sub-pixels of any row in the second display area AA1 being less than the number of sub-pixels of any row in the first display area AA 2;
as shown in fig. 7 to 9, fig. 7 is a schematic wiring diagram of an array substrate according to an embodiment of the present invention, fig. 8 is a schematic cross-sectional view of C-C in fig. 6 according to an embodiment of the present invention, and fig. 9 is a schematic partial wiring diagram of the array substrate in a first non-display region B according to an embodiment of the present invention, where the array substrate further includes:
a first metal layer M1 and a second metal layer M2 disposed on the substrate base plate 60, and an active layer located between the substrate base plate 60 and the first metal layer M1, wherein the second metal layer M2 includes a plurality of data lines 40, each data line 40 runs along a first direction of the substrate base plate 60, and the second metal layer M2 includes a plurality of gate lines 20 intersecting the data lines 40;
wherein the active layer in the first non-display area B is provided with a plurality of first active structures 801, and each of the first active structures 801 overlaps with the gate line 20 in the first non-display area B in a direction perpendicular to the substrate base plate 60.
According to the array substrate provided by the embodiment of the invention, the first active structure 801 overlapped with the gate line 20 is arranged in the first non-display area B, so that the first active structure 801 and the gate line 20 in the first non-display area B can form a capacitance structure, the coupling capacitance effect of the gate line 20 at the position near the notch area is increased, the coupling capacitance effect of the gate line 20 in the special-shaped display area (namely, the second display area AA1) is closer to the coupling capacitance effect of the normal display area (namely, the first display area AA2), the display split phenomenon of the notch screen is improved, and the user experience is improved.
The array substrate provided in the embodiment of the invention further includes a planarization layer 100 and a buffer layer (buffer)70, and since the structure is the same as that in the prior art, redundant description is not repeated here.
In the array substrate provided by the embodiment of the present invention, the first direction of the substrate 60 is the vertical direction of the screen, the data line 40 is routed along the vertical direction, and the gate line 20 in the first display area AA2 is routed along the horizontal direction, that is, the routing direction of the gate line 20 is perpendicular to the data line 40. The second display area AA1 may include a plurality of sub-display areas, such as a left sub-display area and a right sub-display area as shown in fig. 6, namely, a first sub-display area AA10 and a second sub-display area AA11, wherein the gate line 20 in the first sub-display area AA10 extends into the second sub-display area AA11 through the first non-display area B, and similarly, the gate line 20 in the second sub-display area AA11 extends into the first sub-display area AA10 through the first non-display area B, that is, the gate line 20 in the second sub-display area AA1 also runs along the horizontal direction, but runs around the edge of the shaped groove P at a position close to the shaped groove P and extends to the display area at the other side of the shaped groove P.
In the embodiment of the present invention, the position of the special-shaped groove P illustrated in fig. 6 is only one possible position, and in the specific implementation process, the special-shaped groove P may also be disposed at other positions of the array substrate. As shown in fig. 10 to 12, it is a schematic diagram that several kinds of special-shaped grooves P are disposed at different positions, fig. 10 illustrates that the special-shaped grooves P can be disposed on the left side of the array substrate, fig. 11 illustrates that the special-shaped grooves P can be disposed on the left side of the top end of the array substrate, and fig. 12 illustrates that the special-shaped grooves P can be disposed on the bottom of the array substrate.
In the array substrate provided by the embodiment of the invention, the first active structures 801 may be disposed below the data lines 40, and in order to make the coupling capacitance function of the gate lines 20 stronger, more first active structures 801 may be disposed, for example, the first active structures 801 may correspond to the data lines 40 one by one, that is, one first active structure 801 is disposed below each data line 40. Of course, in practical applications, the number of the first active structures 801 may be reasonably set according to actual requirements, which is not limited in the embodiment of the present invention.
In the array substrate provided by the embodiment of the invention, each first active structure 801 can be electrically connected with a corresponding data line 40, so that the potential of the first active structure 801 is the same as that of the connected data line 40, and the capacitance of the coupling capacitor formed by each first active structure 801 and the gate line 20 can be predicted, thereby facilitating reasonable setting of the number of the first active structures 801 and reasonable setting of the overall structure.
As shown in fig. 8, the array substrate according to the embodiment of the present invention further includes an insulating layer located between the second metal layer M2 and the active layer, and the insulating layer located in the first non-display region B includes a plurality of first vias O1, wherein each first active structure 801 is electrically connected to a corresponding data line 40 through a corresponding first via O1.
Specifically, the number of insulating layers between the second metal layer M2 and the active layer may be multiple, and as shown in fig. 8, the insulating layers include a first insulating layer 901, a second insulating layer 902, and a third insulating layer 903, where the first insulating layer 901 is located between the second metal layer M2 and the first metal layer M1, and the second insulating layer 902 and the third insulating layer 903 are located between the first metal layer M1 and the active layer. For example, a silicon oxide (SiO) material may be used for the third insulating layer 903, and a silicon nitride (SiN) material may be used for the first insulating layer, of course, other possible insulating materials may also be used, which is not limited in this embodiment of the present invention.
In the array substrate provided by the embodiment of the invention, the first active structure 801 may also adopt a U-shaped structure similar to the poly in fig. 4, so that one data line 40 may correspond to a plurality of first active structures 801.
In the array substrate provided in the embodiment of the present invention, the first active structures 801 may also be arranged as linear structures, that is, one data line 40 may correspond to one first active structure 801, which is specifically shown in fig. 9 by taking this as an example. Thus, when the first active structure 801 is fabricated, the fabrication difficulty is lower, and the fabrication time of the first active structure 801 is saved, thereby saving the fabrication time cost.
In an alternative embodiment, the first active structure 801 may be a Low Temperature Polysilicon (LTPS) material, but the first active structure 801 may also be another possible semiconductor material, which is not limited in this embodiment of the invention.
Specifically, when the first active structures 801 are linear structures, the routing direction of the first active structures 801 may be the same as the routing direction of the data lines 40, and the projection of each first active structure 801 on the substrate base 60 coincides with the projection of the data line 40 corresponding to each first active structure 801 on the substrate base 60.
In the array substrate provided in the embodiment of the present invention, in the first display area AA2, a plurality of display sub-pixels arranged in an array are disposed, the active layer located in the first display area AA2 is disposed with second active structures 802 corresponding to the display sub-pixels one by one, and the second active structure 802 may be, for example, poly as shown in fig. 4. Since poly is generally U-shaped, there are two overlapping regions of one gate line 20 and one second active structure 802 in the first display area AA2, and thus the overlapping region of one gate line 20 and one second active structure 802 is substantially twice the width of the second active structure 802.
Therefore, in the array substrate provided in the embodiment of the invention, in order to increase the coupling capacitance effect of the gate line 20 at a position near the notch area and further reduce the difference between the coupling capacitance effect of the gate line 20 in the second display area AA1 and the coupling capacitance effect of the first display area AA2, the width of the first active structure 801 may be set to be greater than the width of the second active structure 802, so that the coupling capacitance effect of the gate line 20 in the second display area AA1 is closer to the coupling capacitance effect of the first display area AA2, thereby further improving the phenomenon of split display occurring in the notch screen and improving the user experience.
Alternatively, since the overlapping area of one gate line 20 and one second active structure 802 is twice the width of the second active structure 802, the width of the first active structure 801 may be set to be twice the width of the second active structure 802, so that the coupling effect of the gate line 20 located in the second display area AA1 is close to or the same as the coupling effect of the gate line 20 in the first display area AA 2.
In the embodiment of the invention, the sub-pixels included in the array substrate are provided with the transistors and used for driving the display sub-pixels to realize image display. The Transistor may be, for example, an N-Metal-Oxide-Semiconductor (NMOS) Transistor, a P-Metal-Oxide-Semiconductor (PMOS) Transistor, or a Thin Film Transistor (TFT).
Referring to fig. 13, fig. 13 is another schematic top view of the array substrate according to the embodiment of the invention, the first non-display area B includes a first sub non-display area B1 and a second sub non-display area B2, and each of the first active structures 801 is disposed in an active layer in the first sub non-display area B1. The second sub non-display area B2, which may be referred to as a dummy area, has a plurality of dummy sub-pixels 502 arranged in an array, the dummy sub-pixels 502 include pixel circuits but are always in a dark state when displaying (usually, although the pixel circuits are disposed in the dummy sub-pixels 502, the pixel electrodes are not disposed), each dummy sub-pixel 502 has a one-to-one corresponding third active structure 803, and each third active structure 803 overlaps with the gate line 20 in the first non-display area B in a direction perpendicular to the substrate 60.
Specifically, as shown in fig. 14, the third active structures 803 may be U-shaped structures similar to the display area, and include a horizontal portion 8030 and two vertical portions 8031, where the horizontal portion 8030 and the vertical portions 8031 are perpendicular to each other, the horizontal portion 8030 is located between the two vertical portions 8031, and a projection of the horizontal portion 8030 of each third active structure 803 on the substrate 60 overlaps a projection of the gate line 20 corresponding to each third active structure 803 on the substrate 60. As shown in fig. 14, different from the existing poly design, in the embodiment of the present invention, the horizontal portion 8030 of the third active structure 803 is lifted to overlap with the gate line 20, so as to increase the overlapping area between the third active structure 803 and the gate line 20, further increase the coupling effect between the third active structure 803 and the gate line 20, further improve the display split phenomenon of the notch screen, and improve the user experience.
In the conventional design, since the dummy sub-pixels in the dummy area are not required to be displayed, a via hole is not formed in the third active structure 803 corresponding to the dummy sub-pixel and is not connected to the data line 40, in the embodiment of the present invention, in order to increase the coupling effect of the gate line 20, a plurality of second via holes O2 are formed in the insulating layer in the dummy area, and the third active structure 803 and the data line 40 can be connected through the corresponding second via holes O2, so that the third active structure 803 can have the same potential as the data line 40, and thus the capacitance of the coupling capacitor formed by each of the three active structures 803 and the gate line 20 can be predicted, thereby facilitating the reasonable setting of the overall structure.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including: the array substrate is provided. The Display panel may be a Liquid Crystal Display (LCD) panel or an Organic Light-Emitting Diode (OLED) Display panel. Referring to fig. 15, taking the LCD panel as an example, the display panel includes an array substrate 1, a color film substrate 2 and a liquid crystal layer 3 disposed between the array substrate 1 and the color film substrate 2, where the array substrate 1 is the above-described array substrate, and the color film substrate 2 and the liquid crystal layer 3 may adopt the existing structure in the prior art, and therefore, the color film substrate 2 and the liquid crystal layer 3 are not described in detail.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including: the display panel is provided. The display device can be a liquid crystal display, a liquid crystal television, an organic light emitting diode OLED display, an OLED television and other display devices, and can also be mobile equipment such as a mobile phone, a tablet computer, a notebook, an intelligent watch, an intelligent bracelet, VR/AR glasses and the like. As shown in fig. 16, a top view of the display device provided in the embodiment of the present invention is a mobile phone, wherein a display screen of the display device may adopt a structure of a display panel including the array substrate, which is not limited herein. Since the display device provided in this embodiment includes the array substrate described in the above embodiments, the display device also has the advantages associated with the array substrate, and the implementation of the display device may refer to the above embodiments of the display panel, and repeated details are omitted.
According to the array substrate, the display panel and the display device provided by the embodiment of the invention, the first active structure 801 overlapped with the gate line 20 is arranged in the first non-display area B, so that the first active structure 801 and the gate line 20 in the first non-display area B can form a capacitance structure, the coupling capacitance effect of the gate line 20 at the position near the notch area is increased, the coupling capacitance effect of the gate line 20 in the special-shaped display area is closer to the coupling capacitance effect of the normal display area, the display split phenomenon of the notch screen is improved, and the use experience of a user is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. An array substrate is characterized by comprising a first area and a second area, wherein the first area comprises a first display area, the second area comprises a first non-display area and a second display area positioned at the periphery of the first non-display area, and the number of sub-pixels in any row in the second display area is less than that of the sub-pixels in any row in the first display area; the array substrate includes:
the active layer is positioned between the substrate base plate and the first metal layer, the second metal layer comprises a plurality of data lines, each data line is wired along a first direction of the substrate base plate, and the first metal layer comprises a plurality of grid lines intersected with the data lines;
the active layer in the first non-display area is provided with a plurality of first active structures which are linear structures, each first active structure is overlapped with a grid line in the first non-display area in a direction perpendicular to the substrate base plate, the routing direction of each first active structure is the same as the routing direction of the data line, and the projection of each first active structure on the substrate base plate is overlapped with the projection of the data line corresponding to each first active structure on the substrate base plate;
a plurality of display sub-pixels arranged in an array are arranged in the first display area; the active layer in the first display area is provided with second active structures which correspond to the display sub-pixels one by one; the width of the first active structure is larger than that of the second active structure, and the second active structure is a U-shaped structure.
2. The array substrate of claim 1, wherein each of the first active structures is electrically connected to a corresponding data line.
3. The array substrate of claim 2, further comprising an insulating layer between the second metal layer and the active layer;
the insulating layer in the first non-display area includes a plurality of first via holes;
and each first active structure is electrically connected with the corresponding data line through the corresponding first through hole.
4. The array substrate of claim 1, wherein the width of the first active structure is twice the width of the second active structure.
5. The array substrate of claim 1, wherein the first active structure is a low temperature polysilicon material.
6. The array substrate of claim 1, wherein the second display region comprises a first sub-display region and a second sub-display region;
and the grid line positioned in the first sub-display area extends to the second sub-display area through the first non-display area.
7. The array substrate of claim 1, wherein the first non-display area comprises a first sub non-display area and a second sub non-display area, each of the first active structures is disposed on the active layer in the first sub non-display area, and a plurality of dummy sub-pixels arranged in an array are disposed in the second sub non-display area, and the dummy sub-pixels are always in a dark state; and the number of the first and second groups,
the active layer in the second sub non-display area is provided with a plurality of third active structures which correspond to the virtual sub-pixels one by one;
and each third active structure is overlapped with the grid line in the first non-display area in the direction vertical to the substrate base plate.
8. The array substrate of claim 7, wherein the third active structure is a U-shaped structure comprising a horizontal portion and two vertical portions, the horizontal portion and the vertical portions being perpendicular to each other;
and the projection of the horizontal part of each third active structure on the substrate is overlapped with the projection of the grid line corresponding to each third active structure on the substrate.
9. The array substrate of claim 8,
the insulating layer positioned in the second sub non-display area comprises a plurality of second through holes;
and one vertical part of each third active structure is electrically connected with the corresponding data line through the corresponding second through hole.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
11. A display device characterized by comprising the display panel according to claim 10.
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| CN110827673A (en) * | 2019-11-26 | 2020-02-21 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN114937410B (en) * | 2019-12-02 | 2023-09-26 | 武汉天马微电子有限公司 | Display panel and display device |
| KR20210083795A (en) * | 2019-12-27 | 2021-07-07 | 엘지디스플레이 주식회사 | Display device |
| CN114067738B (en) * | 2020-07-31 | 2023-11-28 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| US11676532B2 (en) | 2020-11-13 | 2023-06-13 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, display panel, and display device |
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| CN107611142B (en) * | 2017-09-11 | 2020-06-09 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107544189B (en) * | 2017-10-20 | 2020-05-15 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN108364567B (en) * | 2018-01-30 | 2020-06-05 | 厦门天马微电子有限公司 | Display panel and display device |
| CN109283726B (en) * | 2018-11-06 | 2022-08-09 | 厦门天马微电子有限公司 | Array substrate and display panel |
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