CN109283726B - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN109283726B
CN109283726B CN201811313132.4A CN201811313132A CN109283726B CN 109283726 B CN109283726 B CN 109283726B CN 201811313132 A CN201811313132 A CN 201811313132A CN 109283726 B CN109283726 B CN 109283726B
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display area
load
display
gate
array substrate
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CN109283726A (en
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吴晓晓
谢振清
刘冰萍
陈国照
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Xiamen Tianma Microelectronics Co Ltd
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Xiamen Tianma Microelectronics Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses an array substrate and a display panel, wherein the array substrate comprises a display area and a non-display area surrounding the display area; at least one edge of the array substrate is provided with at least one notch; the display area comprises a first display area and second display areas positioned on two sides of the notch; the second display area is provided with a plurality of first gate lines, the loads of the first gate lines in the same second display area are the same or the loads of the first gate lines in the same row in two adjacent second display areas are the same; the non-display area comprises compensation units, the compensation units correspond to the first gate lines one to one, the compensation units provide signal intensity compensation or load compensation for at least two first gate lines with the same load, the purpose of providing compensation in different degrees aiming at the gate lines with the same load is achieved, the display brightness difference between the second display area and the first display area is reduced or eliminated, and the purpose of reducing or eliminating the split screen phenomenon between the second display area and the first display area is achieved.

Description

Array substrate and display panel
Technical Field
The present application relates to the field of display technologies, and more particularly, to an array substrate and a display panel.
Background
With the continuous development of display technologies, the requirements of users on the display effect of display panels are higher and higher, and in order to meet the requirements of users, a 'full-screen' display panel adopting a narrow-frame or frameless design is produced.
As shown in fig. 1, fig. 1 is a schematic top view of a display panel, and a currently mainstream full-screen display panel is usually provided with a notch N1(notch) region having a larger area than two side frames in an upper frame region, so as to provide devices such as a front camera, a photosensitive element, and a fingerprint sensor in the notch N1 region. This makes the display area of the display panel divided into the first display area D1 and the second display area D2 located at both sides of the notch N1 area, and in the actual use, it is found that, because the length of the second display area D2 in the short side direction (parallel to the X-axis direction) is smaller than the length of the first display area D1 in the short side direction, and the number of display pixels connected by the gate lines of the second display area D2 is smaller than the number of display pixels connected by the gate lines in the first display area D1, this results in a smaller load on the gate lines in the second display area D2, and thus the display brightness of the second display area D2 is higher than the brightness of the first display area D1 during the display process, which causes the "split screen phenomenon" as shown in fig. 2, and brings a bad influence to the display effect of the display panel.
Disclosure of Invention
In order to solve the technical problem, the application provides an array substrate and a display panel to reduce or eliminate the display brightness difference between a second display area located on two sides of a notch and a first display area below the second display area, and avoid the screen splitting phenomenon that the brightness difference between the first display area and the second display area is large.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
an array substrate comprises a display area and a non-display area surrounding the display area; at least one edge of the array substrate is provided with at least one notch;
the display area comprises a first display area and second display areas positioned on two sides of the notch;
the second display area is provided with a plurality of first gate lines, the loads of the first gate lines in the same second display area are the same or the loads of the first gate lines in the same row in two adjacent second display areas are the same;
the non-display area comprises compensation units, the compensation units correspond to the first gate lines one to one, and the compensation units provide signal intensity compensation or load compensation for at least two first gate lines with the same load so as to reduce or eliminate display brightness difference between the second display area and the first display area.
A display panel comprises an array substrate and a color film substrate which are arranged oppositely, wherein the array substrate is the array substrate.
It can be seen from the foregoing technical solutions that, in the array substrate, because the compensation units in the non-display area are in one-to-one correspondence with the first gate lines, and the compensation units provide signal strength compensation or load compensation for at least two first gate lines with the same load, different compensation units can provide compensation of different degrees, so that the purpose of providing compensation of different degrees for gate lines with the same load is achieved, the display luminance difference between the second display area and the first display area is reduced or eliminated, and the purpose of reducing or eliminating the split screen phenomenon between the second display area and the first display area is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic top view of a display panel;
FIG. 2 is a schematic diagram illustrating a display effect of a display panel in the prior art;
FIG. 3 is a schematic top view of an array substrate in the prior art;
FIG. 4 is a schematic diagram illustrating a display effect after compensating a second display area in the prior art;
fig. 5 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic view of a partition of an array substrate according to an embodiment of the present application;
fig. 7 is a schematic top view illustrating an array substrate according to another embodiment of the present disclosure;
fig. 8 is a schematic top view illustrating an array substrate according to another embodiment of the present disclosure;
fig. 9 is a schematic top view illustrating an array substrate according to still another embodiment of the present disclosure;
fig. 10 is a schematic top view of an array substrate according to an alternative embodiment of the present application;
fig. 11 is a schematic diagram illustrating simulation results of scan signals applied to the array substrate in the prior art shown in fig. 4;
fig. 12 is a schematic diagram of a simulation structure for performing a scan signal on the array substrate shown in fig. 9 or 10;
fig. 13 is a schematic top view of an array substrate according to another alternative embodiment of the present application;
fig. 14 is a schematic view of a partition of an array substrate according to another embodiment of the present application;
fig. 15 is a schematic top view of an array substrate according to yet another alternative embodiment of the present application;
fig. 16 is a schematic top view illustrating an array substrate according to still another alternative embodiment of the present application;
fig. 17 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
fig. 18 is a schematic sectional view of an array substrate according to still another embodiment of the present application;
FIG. 19 is a schematic diagram of a multilayer capacitor according to an embodiment of the present application;
fig. 20 is a schematic diagram illustrating a multilayer capacitor according to another embodiment of the present application;
fig. 21 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure.
Detailed Description
As described in the background art, the full-screen display panel having the notch shown in fig. 1 in the related art may cause the screen splitting phenomenon shown in fig. 2 due to different loads of the gate lines of the first display area and the second display area in the array substrate. The X direction in fig. 1 and 2 is parallel to the short side direction of the display panel, and the Y direction is parallel to the long side direction of the display panel.
The inventor proposes a preliminary scheme of performing different compensations in the first display area and the second display area in order to solve the screen splitting phenomenon, as shown in fig. 3, fig. 3 is a schematic top view structure diagram of an array substrate in the prior art, in the array substrate shown in fig. 3, a gate driving manner is single-side driving, please refer to fig. 1-3, a first gate circuit G1 is disposed on the left side of the first display area D1 for providing a scan signal to the first gate line G11 in the first display area D1; a second gate circuit G2 for supplying a scan signal to the second gate line G21 in the second display region D2 is disposed at the left side of the second display region D2; in addition, in the array substrate shown in fig. 3, the display brightness difference between the first display area D1 and the second display area D2 is also reduced by providing the second load compensation G22 for the second display area D2. However, as shown in fig. 4, fig. 4 is a schematic diagram of the display effect of the display panel, and in conjunction with fig. 3 and 4, due to the attenuation of the scanning signal provided by the first gate circuit G1, in the first display region D1, the display luminance actually decreases from left to right (X-axis forward direction), that is, in fig. 4, the display luminance at the position 1, the position 2, the position 3 and the position 4 decreases sequentially. Since the second load compensation values provided for the second display area D2 are the same, this results in that in fig. 4, the display luminances at the position (i) and the position (ii) are sequentially attenuated, the display luminances at the position (iii) and the position (iv) are sequentially attenuated, but the display luminances at the position (i) and the position (iii) are substantially the same, and the display luminances at the position (iv) and the position (iv) are substantially the same; thus, still referring to fig. 4, if the display luminance at the position (c) and the position (c) is the same as the display luminance at the position (3) and the position (4), respectively, by setting the value of the second load compensation, the display luminance at the position (c) and the position (c) is significantly lower than the display luminance at the positions (1) and (2); and if the display brightness of the position (r) and the position (g) is the same as the display brightness of the position (1) and the position (2) respectively by setting the value of the second load compensation, the display brightness of the position (r) and the position (g) is obviously higher than the display brightness of the position (3) and the position (4). Therefore, the compensation method still causes the split between the partial second display area D2 and the first display area D1.
In view of this, an embodiment of the present application provides an array substrate, including a display area and a non-display area surrounding the display area; at least one edge of the array substrate is provided with at least one notch;
the display area comprises a first display area and second display areas positioned on two sides of the notch;
the second display area is provided with a plurality of first gate lines, the loads of the first gate lines in the same second display area are the same or the loads of the first gate lines in the same row in two adjacent second display areas are the same;
the non-display area comprises compensation units, the compensation units correspond to the first gate lines one to one, and the compensation units provide signal intensity compensation or load compensation for at least two first gate lines with the same load so as to reduce or eliminate display brightness difference between the second display area and the first display area.
In the array substrate provided by the embodiment of the application, because the compensation units in the non-display area correspond to the first gate lines in a one-to-one manner, and the compensation units provide signal intensity compensation or load compensation for at least two first gate lines with the same load, different compensation units can provide compensation in different degrees, so that the purpose of providing compensation in different degrees for the gate lines with the same load is achieved, the display brightness difference between the second display area and the first display area is reduced or eliminated, and the purpose of reducing or eliminating the split screen phenomenon between the second display area and the first display area is achieved.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 5, fig. 5 is a schematic top view of the array substrate, where the array substrate includes a display area and a non-display area surrounding the display area; at least one edge of the array substrate is provided with at least one notch 20;
the display area comprises a first display area 11 and second display areas 12 positioned at two sides of the gap 20;
the second display area 12 has a plurality of first gate lines 30, and the first gate lines 30 of the same second display area 12 have the same load or the first gate lines 30 in the same row of two adjacent second display areas 12 have the same load;
the non-display area includes a compensation unit 40, the compensation unit 40 corresponds to the first gate lines 30 one by one, and the compensation unit 40 provides signal strength compensation or load compensation for at least two first gate lines 30 with the same load, so as to reduce or eliminate the display brightness difference between the second display area 12 and the first display area 11.
Since the compensation units 40 in the non-display area correspond to the first gate lines 30 one to one, and the compensation units 40 provide signal strength compensation or load compensation for at least two first gate lines 30 with the same load, different compensation units 40 can provide different degrees of compensation, thereby achieving the purpose of providing different degrees of compensation for gate lines with the same load.
In fig. 5, the XY coordinate system is established with the short side direction of the array substrate as the X axis direction and the long side direction as the Y axis direction, and the X axis forward direction is directed from the left side to the right side of the array substrate.
For different gate driving manners, the manner of disposing the compensation unit 40 in the non-display area and the value of the compensation intensity provided by the compensation unit 40 may be different, referring to fig. 6 and 7, fig. 6 is a schematic view of a partition of the array substrate provided in the embodiment of the present application, fig. 7 is a schematic view of a top view structure of the array substrate of the single-side driving gate driving manner provided in an embodiment of the present application, and with reference to fig. 6 and 7, the second display area 12 has a plurality of first gate lines 30 extending along a first direction, and loads of the first gate lines 30 in a same row in adjacent second display areas 12 are the same;
the non-display area includes a first frame area B1 located at one side of the second display area 12 in the first direction, and a second frame area B2 located at one side of the second display area 12 in the second direction, the first direction and the second direction being opposite and parallel to each other;
the non-display region further includes a gate driving circuit connected to the first gate line 30, the gate driving circuit includes a first gate circuit 41 disposed in the first frame region B1, and the first gate circuit 41 is configured to provide a scan signal to the first gate line 30.
In fig. 5 and 7, third gate lines 111 in the first display region 11 and a third gate circuit 112 connecting these third gate lines 111 are also shown.
In fig. 7, the first direction is a negative X-axis pointing direction, and the second direction is a positive X-axis pointing direction. The first gate lines 30 adjacent to the same row in the second display area 12 refer to gate lines adjacent to the same line in the second display area 12 in a direction parallel to the X axis. Since the distribution density of the display pixels in the display area is substantially the same, the load of the first gate line 30 is usually determined by the length of the first gate line 30, and therefore, in this embodiment, the lengths of the first gate lines 30 adjacent to the same row in the second display area 12 are the same, so that the loads of the first gate lines 30 adjacent to the same row in the second display area 12 are the same.
Still referring to fig. 7, the compensation unit 40 includes a first buffer unit 411, the first gate circuit 41 includes the first buffer unit 411, the first buffer unit 411 is configured to provide signal strength compensation for the first gate circuit 41, and values of the signal strength compensation provided by the first buffer units 411 in the first gate circuits 41 arranged along the second direction are sequentially decreased.
In the array substrate of the single-side driving gate driving method shown in fig. 7, the driving direction of the first gate circuit 41 is the X-axis forward direction, and reference numerals 1, 2, 3, and 4 in fig. 7 denote positions of display pixels connected to gate lines 112 connected to third gate circuits 112 located on the same line in the Y-axis direction of 1, 2, 3, and 4 (i.e., positions of black dots on the gate lines 112 in fig. 7); reference numerals (r), (g), (d), and (d) in fig. 7 denote positions of display pixels connected to the first gate lines 30 on the same line in the Y-axis direction (i.e., positions of black dots on the first gate lines 30 in fig. 7).
Still referring to fig. 6 and 7, the driving direction of the third gate circuit 112 in the first display area 11 is also the X-axis forward direction, and at this time, the display luminance of the display pixels in the same row and driven by the same gate line in the first display area 11 is gradually decreased due to the attenuation of the scanning signal, that is, the display luminance of the display pixels at position 1, position 2, position 3, and position 4 in fig. 7 is gradually decreased; however, the loads of the second display area 12 located at one side of the first direction of the notch 20 and the first gate line 30 in the second display area 12 located at one side of the second direction of the notch 20 are smaller than the loads of the gate lines in the first display area 11, so that the attenuation degree of the scanning signal provided by the first gate circuit 41 located at one side of the first direction of the notch 20 at the end of the first gate line 30 is smaller than the attenuation degree of the scanning signal at the end of the gate line in the first display area 11 (i.e., the attenuation degree of the scanning signal in the first gate line 30 at the position @issmaller than the attenuation degree of the scanning signal in the gate line at the position 4); the first gate circuit 41 located on one side of the second direction of the notch 20 provides a scanning signal whose attenuation degree at all positions of the first gate line 30 is less than that at the position corresponding to the gate line in the first display area 11 (i.e., the attenuation degree of the scanning signal in the first gate line 30 at the position c is less than that in the gate line at the position 3, and the attenuation degree of the scanning signal in the first gate line 30 at the position 8 is less than that in the gate line at the position 4). Therefore, in order to make the display brightness at the positions (r), and (4) consistent with the display brightness at the positions (3) and (4), the value of the signal intensity compensation provided by the first buffer unit 411 providing the signal intensity compensation at the positions (r) and (r) needs to be smaller than the value of the signal intensity compensation provided by the first buffer unit 411 providing the signal intensity compensation at the positions (r) and (r), so that the display brightness at the positions (r), and (r) is sequentially attenuated along the positive direction of the X-axis, and the degree of attenuation of the display brightness at the positions (r), and (r) is the same as or similar to the degree of attenuation of the display brightness at the positions (1), (2), (3), and (4) by adjusting the signal intensity compensation value, thereby reducing or eliminating the difference between the display brightness at the positions (r), and (r) and the display brightness at the positions (1), (2), (3), and (4).
It should be noted that the buffer unit may be formed by a plurality of inverters, and the value of the signal strength compensation provided by the buffer unit is in direct proportion to the number and/or size of the inverters, that is, the value of the signal strength compensation provided by the buffer unit may be increased by increasing the number of the inverters in the buffer unit, the value of the signal strength compensation provided by the buffer unit may be increased by enlarging the size of the inverters in the buffer unit, and the value of the signal strength compensation provided by the buffer unit may be increased by increasing the number of the inverters and the size of the inverters at the same time; similarly, when the value of the signal strength compensation provided by the buffer unit needs to be reduced, the signal strength compensation can be realized by reducing the number of inverters in the buffer unit or reducing the size of the inverters. This is not a limitation of the present application.
In addition to adopting a signal strength compensation manner, load compensation may be provided, as shown in fig. 8, fig. 8 is a schematic top view structure diagram of the array substrate, referring to fig. 6 and 8, the compensation unit 40 includes a first load compensation unit 412, the first load compensation unit 412 is connected to the first gate circuit 41, the first load compensation unit 412 is configured to provide load compensation for the scan signal output by the first gate circuit 41, and values of the load compensation provided by the first load compensation units 412 connected to the first gate circuits 41 arranged along the second direction are sequentially increased.
The load compensation is to increase the load of the first gate circuit 41 to increase the attenuation of the scan signal output by the first gate circuit 41.
Similar to the analysis of the array substrate shown in fig. 7, in fig. 8, the value of the load compensation provided by the first load compensation unit 412 for providing the load compensation at the position c and the position c needs to be greater than the value of the load compensation provided by the first load compensation unit 412 for providing the load compensation at the position c and the position c, so that the degree of attenuation of the display luminance of the display pixels at the position c, and the position c is the same as or similar to the degree of attenuation of the display luminance of the display pixels at the position 1, the position 2, the position 3, and the position 4, thereby reducing or eliminating the difference between the display luminance of the display pixels at the position c, and the position c and the display luminance of the display pixels at the position 1, the position 2, the position 3, and the position 4.
In an embodiment of the present application, referring to fig. 6 and 9, fig. 9 is a schematic top view structure diagram of an array substrate, where the array substrate further includes:
a second gate circuit 42 disposed in the second frame region B2;
the second display area 12 further includes a plurality of second gate lines 50 extending along a second direction and connected to the second gate circuits 42, the loads of the second gate lines 50 adjacent to the same row in the second display area 12 are the same, and the second gate circuits 42 are configured to provide scanning signals for the second gate lines 50.
In the array substrate shown in fig. 9, the gate driving modes in the first display region 11 and the second display region 12 are both cross driving, in the cross driving array substrate, two gate circuits provide scanning signals for all display pixels line by line, and under the condition that the number of the display pixels is not changed, the period of the gate circuits providing the scanning signals for a certain line of the display pixels can be shortened by half, which is beneficial to reducing the requirement on the period of the scanning signals of the gate circuits and reducing the cost of the gate circuits.
Still referring to fig. 9, the compensation unit 40 includes a second buffer unit 413, the second gate circuit 42 includes the second buffer unit 413, and the second buffer unit 413 is configured to provide signal strength compensation for the second gate circuit 42; the value of the signal intensity compensation provided by the second buffer unit 413 in the second gate circuits 42 arranged in the first direction is sequentially decreased.
In the array substrate shown in fig. 9, the gate driving manner of the second display area 12 is cross driving, and correspondingly, the gate driving manner of the first display area 11 also needs to be cross driving, that is, a third gate circuit 112 and a fourth gate circuit 113 are respectively disposed at two sides of the first display area 11, and a third gate line 111 connected to the third gate circuit 112 and a fourth gate line 114 connected to the fourth gate circuit 113 are disposed in the first display area; the third gate circuit 112 on one side of the first direction of the first display region 11 provides a scan signal to the third gate line 111 extending along the second direction, the driving direction is the positive X-axis direction, and the fourth gate circuit 113 on one side of the second direction of the first display region 11 provides a scan signal to the fourth gate line 114 extending along the first direction, the driving direction is the negative X-axis direction.
In the present embodiment, the scanning signal provided by the first gate circuit 41 is compared with the third gate circuit 112, which is located at one side of the first direction of the first display region 11 and has the same driving direction; the scanning signal provided by the second gate circuit 42 is the same as the driving direction, and the fourth gate circuit 113 located at one side of the first display region 11 in the second direction is compared, and the compensation mode is similar to the above-described single-side driving mode, that is, for the first gate circuit 41, the first buffer unit 411 therein needs to sequentially attenuate the scanning signal of the first gate circuit 41 at the position (i), the position (ii), the position (iii) and the position (iv); for the second gate circuit 42, the second buffer unit 413 needs to sequentially attenuate the scanning signals of the second gate circuit 42 at the position (r), the position (c), the position (r) and the position (r), so that the value of the signal strength compensation provided by the second buffer unit 413 in the second gate circuit 42 arranged along the first direction sequentially decreases, and the value of the signal strength compensation provided by the first buffer unit 411 in the first gate circuit 41 arranged along the second direction sequentially decreases.
Still referring to fig. 9, when the number of the notches 20 is one, the inventor determines the numerical relationship of the signal strength compensation provided by the buffer units in the first gate circuit 41 and the second gate circuit 42 through simulation analysis, specifically, the value of the signal strength compensation provided by the second buffer unit 413 of the first second gate circuit 42 arranged along the first direction is N times the value of the signal strength compensation provided by the second buffer unit 413 of the other second gate circuit 42;
the value of the signal strength compensation provided by the first buffer unit 411 of the first gate circuit 41 arranged along the second direction is N times the value of the signal strength compensation provided by the first buffer unit 411 of the other first gate circuit 41;
wherein the value range of N is 2-10.
When the value range of N is 2 to 10, the inventor finds, through simulation analysis, that the difference of the display luminance of the display pixels in the first display area 11 and the second display area 12 can be substantially eliminated by adjusting the compensation value of the gate circuit in the first display area 11, so as to achieve the purpose of eliminating the screen splitting phenomenon of the first display area 11 and the second display area 12, and improve the display quality of the display panel with the array substrate.
In addition to adopting the signal strength compensation manner, load compensation may be provided, as shown in fig. 10, fig. 10 is a schematic top view structure diagram of the array substrate, in fig. 10, the compensation unit 40 includes a second load compensation unit 414, the second load compensation unit 414 is connected to the second gate circuit 42, the second load compensation unit 414 is configured to provide load compensation for the scan signal output by the second gate circuit 42, and values of the load compensation provided by the second load compensation units 414 connected to the second gate circuits 42 arranged along the first direction are sequentially increased.
When the load compensation unit is used to compensate the gate circuit in the second display region 12, the first load compensation unit 412 and the second load compensation unit 414 may be formed simultaneously in the patterning process of each layer of the thin film transistor or the pixel electrode and the common electrode in the array substrate, which is beneficial to simplifying the manufacturing process of the array substrate.
Still referring to fig. 10, when the number of the notches 20 is one, the inventors determined the numerical relationship of the load compensation provided by the load compensation unit 40 in the first gate circuit 41 and the second gate circuit 42 through simulation analysis, specifically, the value of the load compensation provided by the second load compensation unit 414 of the first second gate circuit 42 arranged along the first direction is M times the value of the load compensation provided by the second load compensation unit 414 of the other second gate circuit 42;
the value of the load compensation provided by the first load compensation unit 412 of the first one of the first gate circuits 41 arranged in the second direction is M times the value of the load compensation provided by the first load compensation unit 412 of the other one of the first gate circuits 41;
wherein, the value range of M is 0.1-0.5.
When the value range of M is 0.1 to 0.5, the inventor finds, through simulation analysis, that the difference of the display brightness of the display pixels in the first display area 11 and the second display area 12 can be substantially eliminated by adjusting the compensation value of the gate circuit in the first display area 11, so as to achieve the purpose of eliminating the screen splitting phenomenon of the first display area 11 and the second display area 12, and improve the display quality of the display panel with the array substrate.
As a result of the following description, the simulation results of the scan signals of the cross-drive array substrate in the prior art as shown in fig. 4 are shown in fig. 11 and 12, and it can be inferred from fig. 11 that the attenuation degree of the scan signals at the position 4 is significantly greater than that of the scan signals at the position 1 and the position 4, and it is assumed that: the attenuation intensity is gradually increased from position 1 to position 4. As can be seen from fig. 12, the degree of attenuation at position 1 is substantially the same as that at position (r) and position (c), and therefore the attenuation is more severe at position (3) than at position (c). To avoid the screen split phenomenon, the attenuation of the scanning signal at the position I needs to be consistent with that at the position 1, and the attenuation of the scanning signal at the position III needs to be consistent with that at the position 3. Therefore, when load compensation is performed on the position (r) and the position (c), the value to be compensated for at the position (c) is larger than that at the position (r). As described above, in the array substrate having one notch 20, further simulation analysis shows that when signal intensity compensation is adopted and the value range of N is 2 to 10 or load compensation is adopted and the value range of M is 0.1 to 0.5, the difference between the display brightness of the display pixels in the first display area 11 and the display brightness of the display pixels in the second display area 12 can be substantially eliminated under the condition that gate circuit compensation values in different first display areas 11 are satisfied, so that the purpose of eliminating the screen separation phenomenon of the first display area 11 and the second display area 12 is achieved, and the display quality of the display panel having the array substrate is improved.
Next, another case of the cross-drive array substrate will be described, referring to fig. 13 and 14, fig. 13 is a schematic top view of the array substrate, fig. 14 is a schematic partition view of the array substrate shown in fig. 13, in this embodiment, the second display area 12 has a plurality of first gate lines 30 and second gate lines 50 extending along a first direction, and the loads of the first gate lines 30 and the second gate lines 50 in the same second display area 12 are the same;
the non-display area comprises a first frame area B1 positioned at one side of the first direction of the second display area 12, a second frame area B2 positioned at one side of the second direction of the second display area 12, a third frame area B3 positioned at one side of the first direction of the first display area 11 and a fourth frame area B4 positioned at one side of the second direction of the first display area 11, wherein the first direction and the second direction are opposite and are parallel to each other;
the non-display region further includes a gate driving circuit including a first gate circuit 41 disposed in the first frame region B1 and a second gate circuit 42 disposed in a second frame region B2; the first gate circuit 41 is connected to the first gate line 30 for providing a scan signal to the first gate line 30, and the second gate circuit 42 is connected to the second gate line 50 for providing a scan signal to the second gate line 50.
In the array substrate shown in fig. 13 and 14, the purpose of providing compensation of different degrees for the gate lines of the same load is achieved by using the compensation unit, so that the display brightness difference between the second display area and the first display area is reduced or eliminated, and the screen separation phenomenon between the second display area and the first display area is alleviated or eliminated, the notch 20 may be located at a non-central position of the edge of the array substrate, so as to meet the requirements of different layouts of various special-shaped display panels, and improve the applicability of the array substrate.
As mentioned above, the length of the gate line is proportional to the load of the gate line, so the length of the gate line in the same second display area 12 is the same, and the load of the gate line in the same second display area 12 is the same.
Still referring to fig. 13 and 14, the compensation unit 40 includes a first buffer unit 411 and a second buffer unit 413, the first gate circuit 41 includes the first buffer unit 411, and the first buffer unit 411 is used for providing signal strength compensation for the first gate circuit 41; the second gate circuit 42 includes the second buffer unit 413, and the second buffer unit 413 is configured to provide signal strength compensation for the second gate circuit 42; the value of the signal strength compensation provided by the first buffer unit 411 at both sides of the second display area 12 close to the third frame area B3 is greater than the value of the signal strength compensation provided by the second buffer unit 413; the first buffer units 411 at both sides of the second display area 12 near the fourth frame area B4 provide a smaller signal strength compensation value than the second buffer units 413 provide.
In this embodiment, the lengths of the first gate line 30 and the second gate line 50 in the same second display area 12 are the same, and as described above, the number of display pixels connected to the first gate line 30 and the second gate line 50 in the same second display area 12 is the same, so the loads of the first gate line 30 and the second gate line 50 in the same second display area 12 are the same.
In the embodiment shown in fig. 13, taking one notch 20 as an example, the display luminance of the second display region 12 near the third frame region B3 is compared with the display luminance of the display pixels connected to the gate circuits located in the third frame region B3, and the display luminance of the second display region 12 near the fourth frame region B4 is compared with the display luminance of the display pixels connected to the gate circuits located in the fourth frame region B4. This is because the display luminance of the display pixels connected to the gate circuits in the third frame region B3 mainly determines the display luminance of the first display region 11 on the side close to the third frame region B3, and the display luminance of the display pixels connected to the gate circuits in the fourth frame region B4 mainly determines the display luminance of the first display region 11 on the side close to the fourth frame region B4.
That is, in this embodiment, in the process that the scanning signal is transmitted from the position 1 to the position 2 of the gate line, the attenuation degree of the scanning signal is increased progressively, the display brightness at the position 1 is greater than the display brightness at the position 2, in the second display area 12 on the first direction side of the notch 20, for the first gate line 30, the attenuation degree of the scanning signal therein is increased progressively from the position (i) to the position (ii), that is, for the display pixels connected to the first gate line 30, the display brightness at the position (i) is higher than the display brightness at the position (ii); on the contrary, for the display pixels connected to the second gate line 50, the display brightness at the position (i) is lower than that at the position (ii), and therefore, in order to ensure that the variation trend of the display brightness at the positions (i) and (ii) is consistent with the variation trend at the positions (1) and (2), it is required to ensure that the value of the signal intensity compensation provided by the first buffer unit 411 in the first gate circuit 41 at both sides of the second display area 12 is greater than the value of the signal intensity compensation provided by the second buffer unit 413 in the second gate circuit 42.
Correspondingly, in the process that the scanning signal is transmitted from the position 4 to the position 3 of the gate line, the attenuation degree of the scanning signal is increased progressively, the display brightness at the position 4 is greater than that at the position 3, in the second display area 12 on one side of the second direction of the notch 20, for the first gate line 30, the attenuation degree of the scanning signal is increased progressively from the position c to the position iv, namely for the display pixels connected with the first gate line 30, the display brightness at the position c is higher than that at the position iv; on the contrary, for the display pixels connected to the second gate line 50, the display brightness at the position c is lower than that at the position c, and therefore, in order to ensure that the variation trend of the display brightness at the positions c and c is consistent with that at the positions 3 and 4, it is necessary to ensure that the value of the signal intensity compensation provided by the first buffer unit 411 in the first gate circuit 41 at both sides of the second display area 12 is smaller than that provided by the second buffer unit 413 in the second gate circuit 42.
In addition to adopting a signal strength compensation manner, load compensation may be provided, referring to fig. 14 and 15, fig. 15 is a schematic top view structure diagram of the array substrate, in fig. 15, the compensation unit 40 includes a first load unit and a second load unit, the first load unit is connected with the first gate circuit 41, the second load unit is connected with the second gate circuit 42, and the first load unit and the second load unit are used for providing load compensation; the value of the load compensation provided by the first load cells at both sides of the second display area 12 near the third frame area B3 is smaller than the value of the load compensation provided by the second load cells; the first load cells at both sides of the second display area 12 adjacent to the fourth frame area B4 provide a greater value of signal strength compensation than the second load cells provide.
Similar to the analysis of the array substrate in fig. 13, except that the greater the value of the load compensation provided by the load unit, the greater the attenuation degree of the scanning signal, which is opposite to the greater the value of the signal strength compensation, the smaller the attenuation degree of the scanning signal, so when performing the load compensation to achieve the same purpose, it is necessary to ensure that the value of the load compensation provided by the first load unit at both sides of the second display area 12 close to the third frame area B3 is smaller than the value of the load compensation provided by the second load unit; the first load cells at both sides of the second display area 12 adjacent to the fourth frame area B4 provide a greater value of signal strength compensation than the second load cells provide.
By the signal strength compensation and load compensation methods proposed in fig. 13 and fig. 15, the array substrate with the notch 20 located at the non-central position of the edge shown in fig. 14 can be compensated, so as to achieve the purposes of reducing or eliminating the display brightness difference between the second display area 12 and the first display area 11, and alleviating or eliminating the screen separation phenomenon between the second display area 12 and the first display area 11.
Referring to fig. 16, 17 and 18, fig. 16 and 17 are schematic top view structures of the array substrate, fig. 18 is a schematic partition diagram of the array substrate shown in fig. 17 and 18, in the embodiment shown in fig. 16 and 17, the notch 20 is located in a central area of the top frame, so that the loads of the first gate lines 30 in the same row in the adjacent second display regions 12 are the same, and the lengths of the gate lines in the same second display region 12 are the same, so that the loads of the first gate lines 30 and the second gate lines 50 in the same second display region 12 are the same.
In the array substrate shown in fig. 16 and 17, the same load is applied to the first gate lines 30 in the same row in the adjacent second display regions 12, and the same load is applied to the first gate lines 30 and the second gate lines 50 in the same second display region 12. Therefore, when the signal intensity compensation and the load compensation are adopted, two modes can be adopted;
referring to fig. 16, when signal strength compensation is employed, one way of compensation is: the compensation unit 40 includes a first load compensation unit 412, the first load compensation unit 412 is connected to the first gate circuit 41, the first load compensation unit 412 is configured to provide load compensation for the scan signal output by the first gate circuit 41, and values of the load compensation provided by the first load compensation units 412 connected to the first gate circuits 41 arranged along the second direction sequentially increase.
The compensating unit 40 includes a second buffer unit 413, the second gate circuit 42 includes the second buffer unit 413, and the second buffer unit 413 is configured to provide signal strength compensation for the second gate circuit 42; the value of the signal intensity compensation provided by the second buffer unit 413 in the second gate circuit 42 arranged in the first direction is sequentially decreased.
Another compensation method is as follows: the compensation unit 40 includes a first buffer unit 411 and a second buffer unit 413, the first gate circuit 41 includes the first buffer unit 411, and the first buffer unit 411 is used for providing signal strength compensation for the first gate circuit 41; the second gate circuit 42 includes the second buffer unit 413, and the second buffer unit 413 is configured to provide signal strength compensation for the second gate circuit 42; the value of the signal strength compensation provided by the first buffer unit 411 at both sides of the second display area 12 close to the third frame area B3 is greater than the value of the signal strength compensation provided by the second buffer unit 413; the first buffer units 411 at both sides of the second display area 12 near the fourth frame area B4 provide a smaller signal strength compensation value than the second buffer units 413 provide.
When the load compensation mode is adopted, one compensation mode is as follows: the compensation unit 40 includes a first load compensation unit 412, the first load compensation unit 412 is connected to the first gate circuit 41, the first load compensation unit 412 is configured to provide load compensation for the scan signal output by the first gate circuit 41, and values of the load compensation provided by the first load compensation units 412 connected to the first gate circuits 41 arranged along the second direction sequentially increase.
The compensation unit 40 includes a second load compensation unit 414, the second load compensation unit 414 is connected to the second gate circuit 42, the second load compensation unit 414 is configured to provide load compensation for the scan signal output by the second gate circuit 42, and values of the load compensation provided by the second load compensation units 414 connected to the second gate circuits 42 arranged along the first direction sequentially increase.
The other mode is as follows: the compensation unit 40 includes a first load unit connected to the first gate circuit 41 and a second load unit connected to the second gate circuit 42, the first load unit and the second load unit being configured to provide load compensation; the value of the load compensation provided by the first load cells at both sides of the second display area 12 near the third frame area B3 is smaller than the value of the load compensation provided by the second load cells; the first load cells at both sides of the second display area 12 adjacent to the fourth frame area B4 provide a larger value of signal strength compensation than the second load cells provide.
Some embodiments below illustrate specific possible configurations of the load unit, which is a load compensation unit that is one of a resistor, a capacitor, or a series arrangement of a resistor and a capacitor.
The capacitor can be a parallel plate capacitor, one electrode plate of the parallel plate capacitor is connected with the gate line, and the other electrode plate can be used as a part of other components as long as the parallel plate capacitor formed by the two electrode plates can form a load of the gate driving circuit.
The resistors are energy dissipation elements, and the resistance value of each resistor is selected according to the load of each grid circuit, so that the effect of balancing the load can be achieved.
Accordingly, a series arrangement of a resistor and a capacitor can also be used as an implementation of the load compensation unit.
Optionally, the load compensation unit is connected to a side of the gate line away from the gate circuit. Of course, the load compensation unit may also be connected to the side of the gate line close to the gate circuit. In some embodiments, the load compensation unit may be partially connected to a side of the gate line away from the gate circuit, and another portion of the load compensation unit is connected to a side of the gate line close to the gate circuit. In addition, although the load compensation units are arranged at different positions, the load compensation units at different positions can enable the loads of the gate drive circuits to be consistent, so that the screen splitting phenomenon is eliminated, and the display quality is improved.
Optionally, the capacitor is a multilayer capacitor, and the multilayer capacitor can improve a higher capacitance value under the condition of occupying a smaller area.
Fig. 19 and 20 are schematic cross-sectional views of an array substrate, and fig. 19 and 20 provide two possible alternative configurations of a multilayer capacitor, in the array substrate shown in fig. 19, the array substrate further includes a polysilicon layer PO, a first metal layer M1, and a second metal layer M2, wherein the first metal layer M1 is located on a side of the polysilicon layer PO facing away from a substrate, and the second metal layer M2 is located on a side of the first metal layer M1 facing away from the polysilicon layer PO;
the multilayer capacitor comprises a first polar plate, a second polar plate and a third polar plate which are oppositely arranged;
the first polar plate is electrically connected with the third polar plate, and the third polar plate is formed by the polycrystalline silicon layer PO;
the second plate is formed by the first metal layer M1, and the first metal layer M1 is also used for forming data lines of the array substrate;
the third plate is formed of the second metal layer M2.
In fig. 19, the multilayer capacitor formed by three layers of plates can effectively reduce the area of the capacitor compared to the capacitor formed by two layers of plates with the same capacitance.
In the array substrate shown in fig. 20, the array substrate further includes a polysilicon layer PO, a first metal layer M1, a second metal layer M2, a first conductive thin film layer I1, and a second conductive thin film layer I2; the first metal layer M1 is located on the side of the polysilicon layer PO facing away from the substrate, the second metal layer M2 is located between the first metal layer M1 and the first conductive thin film layer I1, and the second conductive thin film layer I2 is located on the side of the first conductive thin film layer I1 facing away from the substrate;
the multilayer capacitor comprises a fourth polar plate, a fifth polar plate, a sixth polar plate, a seventh polar plate and an eighth polar plate which are oppositely arranged;
the fourth polar plate, the sixth polar plate and the eighth polar plate are all electrically connected, and the fifth polar plate and the seventh polar plate are electrically connected;
the fourth polar plate is formed by the second conductive thin film layer I2;
the fifth polar plate is formed by the first conductive thin film layer I1;
the sixth polar plate is formed by a second metal layer M2;
the seventh polar plate is formed by a first metal layer M1, and the first metal layer M1 is also used for forming a data line of the array substrate;
the eighth plate is formed of a polysilicon layer PO.
In fig. 20, the multilayer capacitor is formed by five layers of plates, and similarly, the multilayer capacitor formed by five layers of plates can effectively reduce the area of the capacitor under the condition of the same capacitance value compared with the capacitor formed by two layers of plates.
Optionally, the polysilicon layer PO is further used for forming an active region of a thin film transistor, the first metal layer M1 is further used for forming a gate electrode and a gate line of the thin film transistor, the second metal layer M2 is further used for forming a source electrode and a drain electrode of the thin film transistor, and a data line, and the first conductive thin film layer I1 and the second conductive thin film layer I2 are respectively used for forming a common electrode layer and a pixel electrode layer of the array substrate.
It should be noted that, the polysilicon layer PO, the first metal layer M1, the second metal layer M2, the first conductive thin film layer I1, and the second conductive thin film layer I2 are all conductive layers with conductivity, so in order to avoid direct contact short circuit, an insulating layer (not shown in fig. 19 and 20) is further disposed between adjacent conductive layers, and when the adjacent conductive layers need to be electrically connected, the conductive layers can be implemented by vias penetrating through the insulating layers.
Correspondingly, an embodiment of the present application further provides a display panel, referring to fig. 21, where fig. 21 is a schematic cross-sectional structure diagram of the display panel, the display panel includes the array substrate 100 and the color filter substrate 200 according to any one of the embodiments, and the array substrate 100 is the array substrate 100 according to any one of the embodiments. In addition, fig. 21 illustrates a liquid crystal display panel as an example, and also illustrates a liquid crystal layer 300 and a support structure 400.
When the organic light emitting display panel is an organic light emitting display panel, the display panel can be formed by directly fixedly bonding the array substrate 100 to the color film substrate 200 after being packaged without including the liquid crystal layer 300 and the support structure 400.
To sum up, the embodiment of the present application provides an array substrate and a display panel, wherein, in the array substrate, because compensation unit in the non-display area with first gate line one-to-one, and compensation unit provides signal strength compensation or load compensation for at least two first gate lines that the load is the same, different compensation unit can provide the compensation of different degrees so to realize providing the purpose of different degrees of compensation to the gate line of the same load, realized reducing or eliminating the second display area with the display luminance difference of first display area alleviates or eliminates the purpose of the split screen phenomenon of second display area and first display area.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (13)

1. The array substrate is characterized by comprising a display area and a non-display area surrounding the display area; at least one edge of the array substrate is provided with at least one notch;
the display area comprises a first display area and second display areas positioned on two sides of the notch;
the second display areas are provided with a plurality of first gate lines, and the loads of the first gate lines positioned in the same row in two adjacent second display areas are the same;
the non-display area comprises compensation units, the compensation units correspond to the first gate lines one by one, and the compensation units provide load compensation for at least two first gate lines with the same load so as to reduce or eliminate the display brightness difference between the second display area and the first display area;
in the first display area, due to the attenuation of the scanning signals, the display brightness of the display pixels which are positioned in the same row and driven by the same gate line is gradually reduced; the compensation unit is used for providing compensation of different degrees for the first gate lines with the same load, and reducing or eliminating the difference between the display brightness of a plurality of positions sequentially arranged in the same row in two adjacent second display areas and the display brightness of the corresponding position in the first display area.
2. The array substrate of claim 1, wherein the second display area has a plurality of first gate lines extending along a first direction, and the first gate lines of the same row in adjacent second display areas have the same load;
the non-display area comprises a first frame area positioned on one side of the first direction of the second display area and a second frame area positioned on one side of the second direction of the second display area, and the first direction and the second direction are opposite and are parallel to each other;
the non-display area further comprises a gate driving circuit, the gate driving circuit is connected with the first gate line, the gate driving circuit comprises a first gate circuit arranged in the first frame area, and the first gate circuit is used for providing scanning signals for the first gate line.
3. The array substrate of claim 2,
the compensation unit comprises a first load compensation unit, the first load compensation unit is connected with the first grid circuit, the first load compensation unit is used for providing load compensation for scanning signals output by the first grid circuit, and values of the load compensation provided by the first load compensation unit connected with the first grid circuit arranged along the second direction are sequentially increased.
4. The array substrate of claim 2, further comprising:
a second gate circuit disposed in the second frame region;
the second display area also comprises a plurality of second gate lines which extend along a second direction and are connected with the second gate circuits, the loads of the second gate lines adjacent to the same row in the second display area are the same, and the second gate circuits are used for providing scanning signals for the second gate lines.
5. The array substrate of claim 4,
the compensation unit comprises a second load compensation unit, the second load compensation unit is connected with the second grid circuit, the second load compensation unit is used for providing load compensation for scanning signals output by the second grid circuit, and values of the load compensation provided by the second load compensation unit connected with the second grid circuit arranged along the first direction are sequentially increased.
6. The array substrate of claim 5, wherein the number of the notches is one;
the value of the load compensation provided by the second load compensation unit of the first second gate circuit arranged along the first direction is M times that of the load compensation provided by the second load compensation unit of the other second gate circuit;
the value of the load compensation provided by the first load compensation unit of the first gate circuit arranged along the second direction is M times that of the load compensation provided by the first load compensation unit of the other first gate circuit;
wherein, the value range of M is 0.1-0.5.
7. The array substrate of claim 1, wherein the second display area has a plurality of first gate lines and second gate lines extending along a first direction, and the first gate lines and the second gate lines in the same second display area have the same load;
the non-display area comprises a first frame area positioned on one side of the first direction of the second display area, a second frame area positioned on one side of the second direction of the second display area, a third frame area positioned on one side of the first direction of the first display area and a fourth frame area positioned on one side of the second direction of the first display area, and the first direction and the second direction are opposite and are parallel to each other;
the non-display area further comprises a grid driving circuit, and the grid driving circuit comprises a first grid circuit arranged in the first frame area and a second grid circuit arranged in the second frame area; the first gate circuit is connected to the first gate line for providing a scan signal to the first gate line, and the second gate circuit is connected to the second gate line for providing a scan signal to the second gate line.
8. The array substrate of claim 7,
the compensation unit comprises a first load unit and a second load unit, the first load unit is connected with the first grid circuit, the second load unit is connected with the second grid circuit, and the first load unit and the second load unit are used for providing load compensation; the value of load compensation provided by the first load units on two sides of the second display area close to the third frame area is smaller than the value of load compensation provided by the second load units; the value of the signal intensity compensation provided by the first load units at the two sides of the second display area close to the fourth frame area is greater than the value of the load compensation provided by the second load units.
9. The array substrate of claim 1, wherein the compensation unit is a load compensation unit, and the load compensation unit is one of a resistor, a capacitor, or a series connection of a resistor and a capacitor.
10. The array substrate of claim 9, wherein the capacitor is a multilayer capacitor.
11. The array substrate of claim 10, further comprising a polysilicon layer, a first metal layer and a second metal layer, wherein the first metal layer is located on a side of the polysilicon layer facing away from the substrate, and the second metal layer is located on a side of the first metal layer facing away from the polysilicon layer;
the multilayer capacitor comprises a first polar plate, a second polar plate and a third polar plate which are oppositely arranged;
the first polar plate is electrically connected with the third polar plate;
the second plate is formed by the first metal layer, and the first metal layer is also used for forming a data line of the array substrate;
the third polar plate is formed by the polysilicon layer, or the third polar plate is formed by the second metal layer.
12. The array substrate of claim 10, wherein the array substrate further comprises a polysilicon layer, a first metal layer, a second metal layer, a first conductive thin film layer and a second conductive thin film layer; the first metal layer is positioned on one side of the polycrystalline silicon layer, which is far away from the substrate, the second metal layer is positioned between the first metal layer and the first conductive thin film layer, and the second conductive thin film layer is positioned on one side of the first conductive thin film layer, which is far away from the substrate;
the multilayer capacitor comprises a fourth polar plate, a fifth polar plate, a sixth polar plate, a seventh polar plate and an eighth polar plate which are oppositely arranged;
the fourth polar plate, the sixth polar plate and the eighth polar plate are all electrically connected, and the fifth polar plate and the seventh polar plate are electrically connected;
the fourth polar plate is formed by the second conductive thin film layer;
the fifth polar plate is formed by the first conductive thin film layer;
the sixth polar plate is formed by a second metal layer;
the seventh polar plate is formed by a first metal layer, and the first metal layer is also used for forming a data line of the array substrate;
the eighth polar plate is formed by a polycrystalline silicon layer.
13. A display panel, comprising an array substrate and a color filter substrate which are oppositely arranged, wherein the array substrate is the array substrate according to any one of claims 1 to 12.
CN201811313132.4A 2018-11-06 2018-11-06 Array substrate and display panel Active CN109283726B (en)

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KR102646911B1 (en) * 2019-03-14 2024-03-14 삼성디스플레이 주식회사 Display device
CN109697952B (en) 2019-03-14 2020-08-21 京东方科技集团股份有限公司 Display panel, control method thereof and display device
CN110751926B (en) * 2019-10-31 2021-12-28 武汉天马微电子有限公司 Display panel and display device
CN110853512B (en) * 2019-11-11 2022-06-03 昆山国显光电有限公司 Display device and display panel thereof
CN111445798B (en) 2020-04-13 2022-05-31 武汉华星光电半导体显示技术有限公司 Display panel and manufacturing method thereof
CN112631459B (en) * 2020-12-25 2022-06-28 湖北长江新型显示产业创新中心有限公司 Display device and electronic equipment
CN113568231B (en) * 2021-09-18 2022-01-25 惠科股份有限公司 Array substrate, display panel and electronic equipment
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