CN109449167B - Display panel and display device - Google Patents
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- CN109449167B CN109449167B CN201811347183.9A CN201811347183A CN109449167B CN 109449167 B CN109449167 B CN 109449167B CN 201811347183 A CN201811347183 A CN 201811347183A CN 109449167 B CN109449167 B CN 109449167B
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- 239000003990 capacitor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 description 20
- 238000010168 coupling process Methods 0.000 description 20
- 238000005859 coupling reaction Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 239000010408 film Substances 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 235000019557 luminance Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to reduce the load difference of signal lines with different lengths. The display panel comprises a picture display area and a non-picture display area, wherein the picture display area comprises a first display area and a second display area; the picture display area comprises pixels; the display panel comprises a first signal line, a second signal line and a third signal line, wherein the first signal line comprises a first sub first signal line in a first display area and a second sub first signal line in a second display area, and the number of pixels connected with the first sub first signal line is greater than that of pixels connected with the second sub first signal line; the display panel comprises a capacitance compensation structure, wherein the capacitance compensation structure comprises a first conductive layer, a second conductive layer and a third conductive layer; the second conducting layer is positioned between the first conducting layer and the third conducting layer, the first conducting layer is connected with the third conducting layer, the first conducting layer is overlapped with the second conducting layer, and the second conducting layer is overlapped with the third conducting layer; the second sub-first signal line multiplexes the second conductive layer or the third conductive layer.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background of the invention ]
With the diversified design of the display panel, the special-shaped display panel is more and more widely applied. However, in the odd-shaped display panel, since the display area is irregular in shape, the lengths of the signal lines provided in the display area are also different. Therefore, the number of pixels required to be driven by the signal lines with the shorter length is less than that of pixels required to be driven by the signal lines with the longer length, so that the routing loads of different signal lines are inconsistent, the attenuation degrees of signals transmitted on different signal lines are different, and the display performance of the display panel is adversely affected.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a display panel and a display device, so as to reduce the load difference between signal lines with different lengths and improve the display performance of the display panel.
In one aspect, an embodiment of the present invention provides a display panel, where the display panel includes a picture display area and a non-picture display area, where the picture display area includes a first display area and a second display area;
the screen display area includes:
a plurality of pixels;
a plurality of first signal lines including first sub first signal lines and second sub first signal lines, the first sub first signal lines being positioned in the first display region, the second sub first signal lines being positioned in the second display region, wherein the number of pixels electrically connected to the first sub first signal lines is greater than the number of pixels electrically connected to the second sub first signal lines;
the display panel further comprises a plurality of capacitance compensation structures, wherein each capacitance compensation structure comprises a first conductive layer, a second conductive layer and a third conductive layer; wherein the second conductive layer is located between the first conductive layer and the third conductive layer, the first conductive layer is electrically connected with the third conductive layer, the first conductive layer overlaps with the second conductive layer, and the second conductive layer overlaps with the third conductive layer;
wherein the second sub-first signal line is multiplexed as the second conductive layer or the third conductive layer.
In another aspect, an embodiment of the present invention provides a display device, which includes the above display panel.
One of the above technical solutions has the following beneficial effects:
in the technical solution provided in the embodiment of the present invention, based on the relative position relationship among the first conductive layer, the second conductive layer, and the third conductive layer, a first coupling capacitor is formed between the facing areas of the first conductive layer and the second conductive layer, and a second coupling capacitor is formed between the facing areas of the second conductive layer and the third conductive layer, at this time, no matter the second sub-first signal line is multiplexed into the second conductive layer or the third conductive layer, the load capacitance of the second sub-first signal line can be compensated by the first coupling capacitor and the second coupling capacitor, so as to increase the load capacitance of the second sub-first signal line. Furthermore, when the second sub-first signal line is multiplexed as the third conductive layer, the first conductive layer is electrically connected to the second sub-first signal line, so that the routing length of the second sub-first signal line can be increased through the first conductive layer, the load resistance of the second sub-first signal line is compensated, and the increase of the load resistance of the second sub-first signal line is realized.
Therefore, by adopting the technical scheme provided by the embodiment of the invention, the load capacitance and the load resistance of the second sub-first signal line can be increased to a certain extent at the same time, or the load capacitance of the second sub-first signal line can be increased to a certain extent, so that the wiring load of the second sub-first signal line is increased, the load difference between the second sub-first signal line and the first sub-first signal line is reduced, the attenuation difference of signals transmitted on the second sub-first signal line and the first sub-first signal line is reduced, the display uniformity of the first display area and the second display area is improved, and the display performance of the display panel is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a top view of a display panel according to an embodiment of the present invention;
FIG. 2 is an enlarged partial schematic view of FIG. 1;
FIG. 3 is a cross-sectional view taken along line A1-A2 of FIG. 1;
FIG. 4 is a diagram illustrating the relationship among the first, second and third conductive layers according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating another relationship among the first, second and third conductive layers according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an inorganic layer provided in an embodiment of the present invention;
FIG. 7 is another cross-sectional view taken along the line A1-A2 of FIG. 1;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first and second may be used to describe the display regions in the embodiments of the present invention, the display regions should not be limited to these terms. These terms are only used to distinguish the display areas from each other. For example, the first display area may also be referred to as the second display area, and similarly, the second display area may also be referred to as the first display area without departing from the scope of embodiments of the present invention.
An embodiment of the present invention provides a display panel, as shown in fig. 1 and fig. 2, fig. 1 is a top view of the display panel provided in the embodiment of the present invention, fig. 2 is a partially enlarged schematic view of fig. 1, the display panel includes a picture display area 1 and a non-picture display area 2, and the picture display area 1 includes a first display area 3 and a second display area 4.
The picture display area 1 includes a plurality of pixels 5 and a plurality of first signal lines 6. The first signal lines 6 include first sub-first signal lines 7 and second sub-first signal lines 8, the first sub-first signal lines 7 are located in the first display area 3, the second sub-first signal lines 8 are located in the second display area 4, and the number of pixels 5 electrically connected to the first sub-first signal lines 7 is greater than the number of pixels 5 electrically connected to the second sub-first signal lines 8.
As shown in fig. 3, fig. 3 is a cross-sectional view taken along a1-a2 direction in fig. 1, the display panel further includes a plurality of capacitance compensation structures 9, and the capacitance compensation structures 9 include a first conductive layer 10, a second conductive layer 11, and a third conductive layer 12; the second conductive layer 11 is located between the first conductive layer 10 and the third conductive layer 12, the first conductive layer 10 is electrically connected with the third conductive layer 12, the first conductive layer 10 overlaps with the second conductive layer 11, and the second conductive layer 11 overlaps with the third conductive layer 12; the second sub-first signal line 8 is multiplexed into the second conductive layer 11 or the third conductive layer 12.
In the display panel provided in the embodiment of the present invention, based on the relative position relationship among the first conductive layer 10, the second conductive layer 11, and the third conductive layer 12, a first coupling capacitor is formed between the facing areas of the first conductive layer 10 and the second conductive layer 11, and a second coupling capacitor is formed between the facing areas of the second conductive layer 11 and the third conductive layer 12, at this time, no matter the second sub-first signal line 8 is multiplexed into the second conductive layer 11 or the third conductive layer 12, the load capacitance of the second sub-first signal line 8 can be compensated by the first coupling capacitor and the second coupling capacitor, so that the increase of the load capacitance of the second sub-first signal line 8 is realized. Further, when the second sub-first signal line 8 is multiplexed as the third conductive layer 12, since the first conductive layer 10 is electrically connected to the second sub-first signal line 8, the routing length of the second sub-first signal line 8 can be increased by the first conductive layer 10, so that the load resistance of the second sub-first signal line 8 is compensated, and the increase of the load resistance of the second sub-first signal line 8 is realized.
It can be seen that, with the display panel provided in the embodiment of the present invention, the load capacitance and the load resistance of the second sub-first signal line 8 can be increased to a certain extent at the same time, or the load capacitance of the second sub-first signal line 8 can be increased to a certain extent, so that the routing load of the second sub-first signal line 8 is increased, the load difference between the second sub-first signal line 8 and the first sub-first signal line 7 is reduced, the attenuation difference of signals transmitted on the second sub-first signal line 8 and the first sub-first signal line 7 is reduced, the display uniformity of the first display area 3 and the second display area 4 is improved, and the display performance of the display panel is improved.
Optionally, referring to fig. 3 again, the display panel includes a first substrate 13 and a second substrate 14 that are disposed opposite to each other, and a region corresponding to the non-image display region 2 in the first substrate 13 and the second substrate 14 is disposed in a non-hollow manner. The non-screen display area 2 is a light-transmitting area, and a camera module may be provided correspondingly.
The non-hollow-out arrangement means that the first substrate 13 and the second substrate 14 are not cut, that is, the display panel is not provided with a hole in the non-screen display region 2.
In the conventional display panel, in order to provide a camera assembly, the display panel is generally cut to form a hole, and the camera assembly is disposed at the hole. However, with the hole digging design, the periphery of the hole digging needs to be packaged, but the packaging process complexity of the arc-shaped edge of the hole digging is high, so that the packaging failure risk is high. In the embodiment of the present invention, the camera assembly is disposed corresponding to the non-image display area 2, and the area of the first substrate 13 and the second substrate 14 opposite to the non-image display area 2 is not cut, so that on the premise of ensuring normal imaging of the camera assembly, the cutting difficulty of the display panel is reduced, and the periphery of the non-image display area 2 does not need to be encapsulated, thereby avoiding the risk of encapsulation failure.
Alternatively, the first signal line 6 includes a scan line, a data line, or a fixed voltage signal line. Wherein the scanning lines extend in the row direction for supplying scanning signals to the pixels 5; the data lines extend in the column direction for supplying data signals to the pixels 5; the fixed voltage signal lines may include power supply voltage signal lines for supplying the power supply voltage signals to the pixels 5, and the power supply voltage signal lines may include first power supply voltage signal lines extending in a row direction and second power supply voltage signal lines extending in a column direction, and reference voltage signal lines extending in the row direction for supplying the reference voltage signals to the pixels 5.
When the first signal line 6 includes a scan line, since the number of the pixels 5 that the second sub-first signal line 8 needs to drive is small, and the wiring load is small, the on-time of the second sub-first signal line 8 is longer than the on-time of the first sub-first signal line 7, so that the data line charges the pixels 5 in the second display area 4 more sufficiently, and the image displayed by the display panel has the phenomena of cross striation, abnormal color, and the like. In the embodiment of the present invention, by compensating the routing load of the second sub-first signal line 8, the routing loads of the second sub-first signal line 8 and the first sub-first signal line 7 can be made to be consistent, thereby further ensuring that the charging states of the data lines to the pixels 5 in the first display area 3 and the second display area 4 are consistent, and improving the display uniformity.
When the first signal line 6 includes a data line, the second sub-first signal line 8 and the first sub-first signal line 7 can be made to have consistent routing loads by compensating the routing loads of the second sub-first signal line 8 and the first sub-first signal line 7, so that the attenuation degrees of the data signals transmitted through the second sub-first signal line 8 and the first sub-first signal line 7 are consistent, and the problem of different light-emitting luminances caused by different attenuation degrees of the data signals is solved.
When the first signal line 6 includes the fixed voltage signal line, the wiring load of the second sub-first signal line 8 and the wiring load of the first sub-first signal line 7 can be made to be consistent by compensating the wiring load of the second sub-first signal line 8, so that the attenuation degrees of the fixed voltage signal line during transmission on the second sub-first signal line 8 and the first sub-first signal line 7 are made to be the same, and the driving uniformity of the fixed voltage signal to the pixel 5 is improved.
Optionally, as shown in fig. 4, fig. 4 is a schematic diagram of film layer relationships of the first conductive layer, the second conductive layer, and the third conductive layer according to the embodiment of the present invention, the second sub-first signal lines 8 are multiplexed into the third conductive layer 12, and the second sub-first signal lines 8 are scanning lines. The pixel 5 comprises a thin film transistor 16 and a storage capacitor 17, wherein the storage capacitor 17 comprises a first polar plate 18 and a second polar plate 19 which are oppositely arranged; the second conductive layer 11 is disposed in the same layer as the first electrode plate 18.
With the above arrangement, on one hand, when the second sub-first signal line 8 is multiplexed as the third conductive layer 12, the capacitive load compensation can be performed on the second sub-first signal line 8 through the first coupling capacitor formed by the first conductive layer 10 and the second conductive layer 11 and the second coupling capacitor formed by the second conductive layer 11 and the second sub-first signal line 8, and the load resistance compensation can be performed on the second sub-first signal line 8 through the first conductive layer 10 electrically connected to the second sub-first signal line 8, so that the wiring load of the second sub-first signal line 8 is increased, and the load difference between the second sub-first signal line 8 and the first sub-first signal line 7 is reduced; on the other hand, the second conductive layer 11 can be formed by the same composition process as the first electrode plate 18 without adopting an additional composition process, so that the process flow is reduced, and the manufacturing cost is reduced; on the other hand, the second conductive layer 11 does not occupy an additional film layer, so that the thickness of the display panel is not affected, and the light and thin design of the display panel can be better realized.
Optionally, as shown in fig. 5, fig. 5 is another film layer relationship diagram of the first conductive layer, the second conductive layer, and the third conductive layer provided in the embodiment of the present invention, the second sub-first signal lines 8 are multiplexed as the second conductive layer 11, and the second sub-first signal lines 8 are scanning lines. The pixel 5 includes a thin film transistor 16 and a storage capacitor 17, wherein the thin film transistor 16 includes an active layer 20, a gate layer 21, and a source drain layer 22; the third conductive layer 12 is disposed in the same layer as the active layer 20.
With the above arrangement, on one hand, when the second sub-first signal line 8 is multiplexed as the second conductive layer 11, the second sub-first signal line 8 can be subjected to capacitive load compensation through the first coupling capacitor formed by the first conductive layer 10 and the second sub-first signal line 8 and the second coupling capacitor formed by the second conductive layer 11 and the third conductive layer 12, so that the routing load of the second sub-first signal line 8 is increased, and the load difference between the second sub-first signal line 8 and the first sub-first signal line 7 is reduced; on the other hand, the third conductive layer 12 can be formed by the same patterning process as the active layer 20 without adopting an additional patterning process, so that the process flow is reduced, and the manufacturing cost is reduced; on the other hand, the third conductive layer 12 does not occupy an additional film layer, so that the thickness of the display panel is not affected, and the light and thin design of the display panel can be better realized.
Referring to fig. 2 and fig. 3 again, the second display area 4 is located at two sides of the non-image display area 2, the first conductive layer 10 is disposed in the second display area 4, the first conductive layer 10 is electrically connected to the third conductive layer 12 in the second display area 4, and the first conductive layer 10 overlaps the second conductive layer 11 in the second display area 4.
With such an arrangement, on one hand, no matter the second conductive layer 11 or the third conductive layer 12 is the second sub-first signal lines 8, each second sub-first signal line 8 corresponds to one first conductive layer 10, which can ensure that each second sub-first signal line 8 is subjected to load compensation, thereby ensuring the display uniformity of the first display area 3 and the second display area 4; on the other hand, the first conductive layer 10 is only disposed in the second display area 4, and does not penetrate through the non-image display area 2, and when the non-image display area 2 is a light-transmitting area and the camera module is disposed correspondingly, the first conductive layer 10 can be prevented from affecting the light-transmitting property of the non-image display area 2, and the imaging quality of the camera module is improved.
Further, in order to ensure that the load capacitance of the second sub-first signal line 8 and the load capacitance of the first sub-first signal line 7 tend to be consistent, and reduce the load difference between the two, the total capacitance after the first coupling capacitance and the second coupling capacitance are connected in parallel may be equal to the load capacitance difference between the first sub-first signal line 7 and the second sub-first signal line 8.
In particular, according to
Wherein k is the constant of the electrostatic force and is the relative dielectric constant, d is the distance between two opposite polar plates of the capacitor, and S is the overlapping area between the two opposite polar plates of the capacitor, so that the first coupling capacitor
Wherein d is1Is the spacing, S, between the first conductive layer 10 and the second conductive layer 111A second coupling capacitor as an overlapping area between the first conductive layer 10 and the second conductive layer 11
Wherein d is2Is the distance between the second conductive layer 11 and the third conductive layer 12, S2Is the overlapping area between the second conductive layer 11 and the third conductive layer 12.
When the number of the second display regions 4 is two and the number of the pixels 5 to which the two second sub-first signal lines 8 whose extension lines are overlapped in the two second display regions 4 are electrically connected is equal, the difference in load capacitance between the first sub-first signal lines 7 and the second sub-first signal lines 8
Wherein N is1The number of pixels 5 corresponding to one first sub-first signal line 7, N2C is the equivalent parasitic capacitance of one pixel 5, and c is the number of pixels 5 corresponding to one second sub-first signal line 8.
Further, according to C1+C2D is derived as Δ C1、S1、d2、S2Satisfies the following conditions:
it should be noted that, with reference to fig. 2, the extension lines of the two second sub-first signal lines 8 are shown by dashed lines between the two second sub-first signal lines 8 in fig. 2, and the two second sub-first signal lines 8 whose extension lines are overlapped in the two second display areas 4 specifically refer to the two second sub-first signal lines 8 electrically connected to the pixels 5 in the same row or the same column.
Optionally, when the second sub-first signal line 8 is multiplexed as the third conductive layer 12, in order to ensure that the load resistance of the second sub-first signal line 8 and the load resistance of the first sub-first signal line 7 tend to be consistent, and reduce the load difference therebetween, the load resistance of the first conductive layer 10 may be equal to the load resistance difference between the first sub-first signal line 7 and the second sub-first signal line 8.
Specifically, the load resistance of the first conductive layer 10
Wherein R issFor the square resistance, l is the length of the first conductive layer 10, and w is the width of the first conductive layer 10. Load resistance difference between the first sub-first signal line 7 and the second sub-first signal line 8
Where r is the resistance of one pixel 5.
Further, from R ═ Δ R, it is derived that w and l satisfy:
in addition, when the first conductive layer 10 is only disposed in the second display region 4, since the first conductive layer 10 does not shield the non-screen display region 2, the material of the first conductive layer 10 may include an opaque metal material, or may include a transparent conductive material, such as one or more of indium tin oxide, indium zinc oxide, or indium gallium zinc oxide.
Optionally, when the non-image display area 2 is a light-transmitting area and the camera module is correspondingly disposed, in order to further improve the light transmittance of the non-image display area 2 and further improve the imaging quality of the camera module, the display panel further includes an inorganic layer, and the inorganic layer is hollowed in the non-image display area 2. Specifically, as shown in fig. 6, fig. 6 is a schematic structural diagram of the inorganic layer provided in the embodiment of the present invention, and the inorganic layer includes a buffer layer 23 disposed on a side of the active layer 20 opposite to the light emitting surface, a first insulating layer 24 disposed between the active layer 20 and the gate layer 21, and a second insulating layer 25 disposed between the gate layer 21 and the source drain layer 22.
Optionally, please refer to fig. 2 again, the second display area 4 is located at two sides of the non-frame display area 2; further, as shown in fig. 7, fig. 7 is another cross-sectional view taken along a direction a1-a2 in fig. 1, the first conductive layer 10 penetrates through the non-screen display region 2 and the second display region 4, the first conductive layer 10 is electrically connected to the third conductive layers 12 in the second display regions 4 on both sides, respectively, and the first conductive layer 10 overlaps with the second conductive layers 11 in the second display regions 4 on both sides, respectively.
It should be noted that, no matter whether the second sub-first signal lines 8 are multiplexed into the second conductive layer 11 or the third conductive layer 12, the two second sub-first signal lines 8 overlapping or electrically connected to the first conductive layer 10 are the two second sub-first signal lines 8 whose extension lines coincide.
With this arrangement, one first conductive layer 10 can perform load compensation on the second sub-first signal lines 8 of the second display regions 4 on both sides of the non-image display region 2, respectively, so as to reduce the load difference between the second sub-first signal lines 8 and the first sub-first signal lines 7 on both sides simultaneously.
Further, in order to ensure that the load capacitance of the second sub-first signal lines 8 on both sides and the load capacitance of the first sub-first signal line 7 tend to be consistent, and reduce the load difference between the two, the total capacitance after the first coupling capacitance and the second coupling capacitance are connected in parallel may be equal to the load capacitance difference between the first sub-first signal line 7 and the two second sub-first signal lines 8 on both sides.
In particular, according to
Wherein k is the constant of the electrostatic force and is the relative dielectric constant, d is the distance between two opposite polar plates of the capacitor, and S is the overlapping area between the two opposite polar plates of the capacitor, so that the first coupling capacitor
Wherein d is1' is the spacing, S, between the first conductive layer 10 and the second conductive layer 111' second coupling capacitance, which is an overlapping area between the first conductive layer 10 and the second conductive layer 11
Wherein d is2' is the space between the second conductive layer 11 and the third conductive layer 12, S2' is an overlapping area between the second conductive layer 11 and the third conductive layer 12.
When the number of the second display areas 4 is two and the number of the pixels 5 to which the two second sub-first signal lines 8 whose extension lines overlap in the two second display areas 4 are electrically connected is equal, the load capacitance difference Δ C' between the first sub-first signal line 7 and the two second sub-first signal lines 8 whose extension lines overlap is equal to (N)1-2×N2) X c, wherein N1The number of pixels 5 corresponding to one first sub-first signal line 7, N2C is the equivalent parasitic capacitance of one pixel 5, and c is the number of pixels 5 corresponding to one second sub-first signal line 8.
Further, according to C1′+C2'-. DELTA.C', deriving d1′、S1′、d2′、S2' satisfies:
optionally, when the second sub-first signal lines 8 are multiplexed into the third conductive layer 12, in order to ensure that the total load resistance of the two second sub-first signal lines 8 whose extension lines are overlapped and the load resistance of the first sub-first signal line 7 tend to be consistent, and reduce the load difference between the two, the load resistance of the first conductive layer 10 may be equal to the load resistance difference between the first sub-first signal line 7 and the two second sub-first signal lines 8.
Specifically, the load resistance of the first conductive layer 10
Wherein R issFor the square resistance, l 'is the length of the first conductive layer 10, and w' is the width of the first conductive layer 10. The load resistance difference Δ R' between the first sub-first signal line 7 and the two second sub-first signal lines 8 is (N)1-2×N2) Xr, where r is the equivalent resistance of one pixel 5.
Further, from R '═ Δ R', it is derived that w 'and l' satisfy:
in addition, when the first conductive layer 10 penetrates through the non-image display area 2, the non-image display area 2 is a light-transmitting area, and a camera module is correspondingly disposed, in order to reduce the influence of the first conductive layer 10 on the light-transmitting property of the non-image display area 2 and improve the imaging quality of the camera module, the material of the first conductive layer 10 may include a transparent conductive material, such as one or more of indium tin oxide, indium zinc oxide, or indium gallium zinc oxide.
As shown in fig. 8, fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device includes the display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 8 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
Because the display device provided by the embodiment of the invention comprises the display panel, the display device can compensate the wiring load of the second sub-first signal line 8 to a certain extent, reduce the load difference between the second sub-first signal line 8 and the first sub-first signal line 7, further reduce the attenuation difference of signals transmitted on the second sub-first signal line 8 and the first sub-first signal line 7, improve the display uniformity of the first display area 3 and the second display area 4, and improve the display performance of the display device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (12)
1. A display panel is characterized in that the display panel comprises a picture display area and a non-picture display area, wherein the picture display area comprises a first display area and a second display area;
the screen display area includes:
a plurality of pixels;
a plurality of first signal lines including first sub first signal lines and second sub first signal lines, the first sub first signal lines being positioned in the first display region, the second sub first signal lines being positioned in the second display region, wherein the number of pixels electrically connected to the first sub first signal lines is greater than the number of pixels electrically connected to the second sub first signal lines;
the display panel further comprises a plurality of capacitance compensation structures, wherein each capacitance compensation structure comprises a first conductive layer, a second conductive layer and a third conductive layer; wherein the second conductive layer is located between the first conductive layer and the third conductive layer, the first conductive layer is electrically connected with the third conductive layer, the first conductive layer overlaps with the second conductive layer, and the second conductive layer overlaps with the third conductive layer;
wherein the second sub-first signal line is multiplexed as the second conductive layer or the third conductive layer;
the second display areas are positioned at two sides of the non-picture display area, the number of the second display areas is two, and in the two second display areas, the number of the pixels electrically connected with the two second sub-first signal lines with superposed extension lines is equal;
the first conducting layer is arranged in the second display area, is electrically connected with the third conducting layer in the second display area and is overlapped with the second conducting layer in the second display area;
the second sub-first signal line is multiplexed into the third conductive layer, and the width w of the first conductive layer and the length l of the first conductive layer satisfy:
wherein N is1The number of the pixels electrically connected to one of the first sub-first signal lines, N2The number of the pixels electrically connected to one of the second sub-first signal lines, RsIs a square resistance, r is an equivalent resistance of one of the pixels;
or, the first conducting layer penetrates through the non-picture display area and the second display area, the first conducting layer is respectively and electrically connected with the third conducting layers in the second display areas on two sides, and the first conducting layer is overlapped with the second conducting layers in the second display areas on two sides;
the second sub first signal line is multiplexed into the third conductive layer, and the width w 'of the first conductive layer and the length l' of the first conductive layer satisfy:
2. the display panel according to claim 1, further comprising a first substrate and a second substrate disposed opposite to each other, wherein a region of the first substrate and the second substrate corresponding to the non-image display region is non-hollow.
3. The display panel according to claim 1, wherein the first signal line comprises a scan line, a data line, or a fixed voltage signal line.
4. The display panel according to claim 1, wherein the second sub-first signal lines are multiplexed into the third conductive layer, and the second sub-first signal lines are scan lines;
the pixel comprises a thin film transistor and a storage capacitor, wherein the storage capacitor comprises a first polar plate and a second polar plate which are oppositely arranged;
the second conducting layer and the first polar plate are arranged on the same layer.
5. The display panel according to claim 1, wherein a second sub-first signal line is multiplexed as the second conductive layer, and the second sub-first signal line is a scan line;
the pixel comprises a thin film transistor and a storage capacitor, wherein the thin film transistor comprises an active layer, a gate layer and a source drain layer;
the third conductive layer and the active layer are arranged on the same layer.
6. The display panel according to claim 1, wherein the first conductive layer is provided in the second display region;
an overlapping area S between the first conductive layer and the second conductive layer1A distance d between the first conductive layer and the second conductive layer1An overlapping area S between the second conductive layer and the third conductive layer2A distance d between the second conductive layer and the third conductive layer2Satisfies the following conditions:
where k is the constant of the electrostatic force, the relative dielectric constant, N1The number of the pixels electrically connected to one of the first sub-first signal lines, N2The pixel electrically connected with one of the second sub-first signal linesC is an equivalent parasitic capacitance of one of the pixels.
7. The display panel according to claim 6, wherein a material of the first conductive layer comprises a metal material; or the material of the first conducting layer is one or more of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
8. The display panel according to claim 1, wherein the display panel further comprises an inorganic layer, and the inorganic layer is hollowed out in the non-picture display region.
9. The display panel according to claim 8, wherein the picture display region is provided with a thin film transistor including an active layer, a gate layer, and a source drain layer;
the inorganic layer comprises a buffer layer arranged on one side of the active layer, which faces away from the light-emitting surface, a first insulating layer arranged between the active layer and the gate layer, and a second insulating layer arranged between the gate layer and the source drain layer.
10. The display panel according to claim 1, wherein the first conductive layer penetrates the non-screen display region and the second display region;
an overlapping area S between the first conductive layer and the second conductive layer1', a distance d between the first conductive layer and the second conductive layer1', an overlapping area S between the second conductive layer and the third conductive layer2', a distance d between the second conductive layer and the third conductive layer2' satisfies:
where k is the constant of the electrostatic force, the relative dielectric constant, N1The number of the pixels electrically connected to one of the first sub-first signal lines, N2C is the equivalent capacitance of one pixel, and c is the number of the pixels electrically connected to one second sub-first signal line.
11. The display panel according to claim 10, wherein a material of the first conductive layer is one or more of indium tin oxide, indium zinc oxide, or indium gallium zinc oxide.
12. A display device comprising the display panel according to any one of claims 1 to 11.
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| CN109976584B (en) * | 2019-03-28 | 2022-07-29 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof, and display device and driving method thereof |
| CN209434190U (en) * | 2019-05-05 | 2019-09-24 | 北京京东方技术开发有限公司 | A kind of array substrate, display panel and display device |
| CN110459572B (en) * | 2019-08-19 | 2023-01-06 | 京东方科技集团股份有限公司 | Display panel |
| WO2021184275A1 (en) * | 2020-03-18 | 2021-09-23 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN111477672B (en) * | 2020-05-20 | 2022-12-09 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof, display panel and display device |
| CN111769147B (en) * | 2020-06-28 | 2023-12-26 | 合肥维信诺科技有限公司 | Display panel and display device |
| CN114429959A (en) * | 2020-10-29 | 2022-05-03 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN112670327B (en) * | 2020-12-23 | 2022-07-29 | 武汉天马微电子有限公司 | Display panel and display device |
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