CN111769147B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN111769147B
CN111769147B CN202010600711.8A CN202010600711A CN111769147B CN 111769147 B CN111769147 B CN 111769147B CN 202010600711 A CN202010600711 A CN 202010600711A CN 111769147 B CN111769147 B CN 111769147B
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data line
display panel
resistance
data1
compensation
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CN111769147A (en
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李蒙蒙
范文志
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Hefei Visionox Technology Co Ltd
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Hefei Visionox Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel includes: a plurality of first data lines and a plurality of second data lines; a plurality of sub-pixels including anodes located at different film layers and overlapping projections with the first data line, and anodes located at different film layers and overlapping projections with the second data line; wherein the first data line further includes an RC compensating part so that an RC delay of the first data line is the same as an RC delay of the second data line. Compared with the prior art, the embodiment of the invention improves the display uniformity of the display panel.

Description

Display panel and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
Along with the continuous development of display technology, the application range of the display panel is wider and wider, and the requirements of people on the display panel are also higher and higher. Particularly, the display image quality of the display panel is always one of important indicators for quality measurement of the display panel by consumers and panel manufacturers.
The Organic Light-Emitting Diode (OLED) display panel has the advantages of high Light-Emitting brightness, light and thin volume, high response speed, easiness in realizing color display, large-screen display and the like, and has wide application prospect. However, the conventional OLED display panel has a problem of poor display uniformity, which affects the improvement of display quality of the display panel.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for improving the display uniformity of the display panel.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a display panel, comprising:
a plurality of first data lines and a plurality of second data lines;
a plurality of sub-pixels including anodes located at different film layers and overlapping projections with the first data line, and anodes located at different film layers and overlapping projections with the second data line;
wherein the first data line further includes an RC compensating part so that an RC delay of the first data line is the same as an RC delay of the second data line.
As can be seen from the above technical solution, in the embodiment of the present invention, the first data line includes an RC compensation unit, and the RC delay on the first data line and the second data line can be adjusted to be the same by adjusting the parasitic capacitance C1 or the resistance R1 on the first data line, so as to improve the uniformity of display of the display panel.
Further, the RC compensation part includes a capacitance compensation part, and the capacitance compensation part of the first data line overlaps with the projection of the anode. According to the technical scheme, if the RC delay of the first data line is smaller than that of the second data line, the capacitance compensation part of the first data line is arranged to compensate the overlapping area of the projection of the body part of the first data line and the anode, so that the parasitic capacitance of the first data line can be increased to increase the RC delay of the first data line, and the RC delay of the first data line is the same as that of the second data line, so that the display uniformity of the display panel is improved.
Further, the first data line further includes a body portion; the capacitance compensation part of the first data line comprises a first end and a second end, the first end of the capacitance compensation part of the first data line is in contact with the body part of the first data line, and the second end of the capacitance compensation part of the first data line forms an open circuit. The capacitance compensation part is arranged in such a way that on one hand, the overlapping area of the first data line and the anode is increased; on the other hand, since one end of the capacitance compensation portion is opened and no current flows through the capacitance compensation portion, the influence of the capacitance compensation portion on the resistance of the first data line is negligible. Therefore, the embodiment of the invention increases the parasitic capacitance of the first data line on the premise of not changing the resistance of the first data line.
Further, the second data line comprises a body part and a capacitance compensation part, and the capacitance compensation part of the second data line is not overlapped with the projection of the anode; the capacitance compensation part of the second data line and the capacitance compensation part of the first data line have equal resistances. The embodiment of the invention is provided with the second data line and also comprises a capacitance compensation part, which is beneficial to maintaining the same characteristics of the first data line, the second data line, and the like, namely increasing the parasitic capacitance of the first data line on the premise of unchanged other characteristics, and further ensuring the transmission uniformity of the data signals on the first data line and the second data line.
Further, the RC compensation part comprises a resistance compensation part, the first data line comprises a body part and the resistance compensation part, and the body part of the first data line is connected with the resistance compensation part in series. If the RC delay of the first data line is smaller than that of the second data line, the resistance R1 of the first data line is increased by setting the series resistance of the first data line, so that the RC delay of the first data line is increased, the difference between the RC delays of the first data line and the second data line is reduced, and the display uniformity of the display panel is improved. In addition, the PDL opening and the pixel arrangement mode of the display panel do not need to be changed, so that the embodiment of the invention has strong practicability.
Further, the resistance compensation portion of the first data line and the active layer are arranged in the same layer, preferably, the resistance compensation portion includes a semiconductor resistor, and the resistance compensation portion and the active layer of the transistor can be manufactured in the same process step, which is beneficial to saving the process flow.
Further, the second data line includes a body portion and a resistance compensation portion, and the body portion of the second data line is connected in parallel with the resistance compensation portion. The embodiment of the invention is provided with the second data line which also comprises a resistance compensation part and is arranged in parallel with the body part of the second data line so as to reduce the resistance of the second data line and further reduce the RC delay difference between the first data line and the second data line.
Further, the resistance compensation portion of the first data line does not overlap with the anode, and the line width of the resistance compensation portion of the first data line is smaller or larger than the line width of the body portion of the first data line. Wherein, the larger the line width of the data line is, the smaller the resistance value is; conversely, the smaller the line width of the data line, the larger the resistance value thereof. According to the embodiment of the invention, the resistor R1 of the first data line is adjusted by adjusting the line width of the first data line, so that the RC delay of the first data line is adjusted, the difference of the RC delays of the first data line and the second data line is reduced, and the display uniformity of the display panel is improved.
Further, the RC compensation part comprises a capacitance compensation part, the capacitance compensation part of the first data line is overlapped with the projection of the anode, and the RC delay difference between the first data line and the second data line is further reduced by arranging resistance compensation and capacitance compensation on the first data line, so that the display uniformity of the display panel is improved. In addition, the PDL opening and the pixel arrangement mode of the display panel do not need to be changed, so that the embodiment of the invention has strong practicability.
Correspondingly, the invention also provides a display device, which comprises: the display panel is provided in any embodiment of the invention.
According to the embodiment of the invention, the first data line comprises the RC compensation part, and the RC delay of the first data line and the RC delay of the second data line can be adjusted to be the same by adjusting the parasitic capacitance C1 or the resistance R1 of the first data line, so that the charging time of the data voltage on the first data line and the charging time of the data voltage on the second data line are the same, and then the charging time of the sub-pixel for providing the data voltage by the first data line and the charging time of the sub-pixel for providing the data voltage by the second data line are the same, thereby improving the display uniformity of the display panel.
Drawings
Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;
fig. 2 is a schematic circuit structure of a sub-pixel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view taken along line A-A of FIG. 7;
fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Embodiments of the present invention provide a display panel that may be applied to an Organic Light-Emitting Diode (OLED), a Micro Light-Emitting Diode display panel (Micro Light Emitting Diode, micro LED), or a quantum dot Light-Emitting Diode (Quantum Dot Light Emitting Diodes, QLED).
Fig. 1 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention. Referring to fig. 1, the display panel includes: a plurality of first DATA lines DATA1, a plurality of second DATA lines DATA2, and a plurality of subpixels (a first subpixel 100 and a second subpixel 200 are exemplarily shown in fig. 1). The sub-pixel includes an Anode electrode located at a different film layer from the first DATA line DATA1 and having an overlap in projection, and an Anode electrode located at a different film layer from the second DATA line DATA2 and having an overlap in projection. The first DATA line DATA1 further includes an RC compensating part (not shown in fig. 1), which can reduce an RC delay difference between the first DATA line DATA1 and the second DATA line DATA2 so that the RC delay of the first DATA line DATA1 and the RC delay of the second DATA line DATA2 are the same. It is understood that the data line and the anode are not in direct contact, and that the data line and the anode overlap in the embodiments of the present application refers to that the data line and the anode are located in different film layers and have overlapping projections on a plane parallel to the display panel.
In addition, it is conceivable that the RC delay between the first DATA line DATA1 and the second DATA line DATA2 is difficult to be made identical at the time of the implementation of the present application, and thus the same RC delay of the first DATA line DATA1 and the same RC delay of the second DATA line DATA2 referred to herein means that the RC delay difference between the first DATA line DATA1 and the second DATA line DATA2 is within an acceptable range, that is, the influence on the display effect of the display panel due to the RC delay difference is not visible to the naked eye.
Wherein, since the Anode and the first DATA line DATA1 are located in different film layers and overlap, a parasitic capacitance C1 exists between the Anode and the first DATA line DATA 1; similarly, since the Anode electrode and the second DATA line DATA2 are located at different film layers and overlap, a parasitic capacitance C2 exists between the Anode electrode and the second DATA line DATA 2. In addition, the first DATA line DATA1 itself has a resistance R1, and the second DATA line DATA2 itself has a resistance R2. The parasitic capacitance C1 of the first DATA line DATA1 and the parasitic capacitance C2 of the second DATA line DATA2 are different, and/or the resistance R1 of the first DATA line DATA1 and the resistance R2 of the second DATA line DATA2 are different, due to the pixel arrangement, the wiring, and the like.
The first sub-pixel 100 includes a pixel circuit and a light emitting device LED1, and the pixel circuit of the first sub-pixel 100 includes a driving transistor DTFT1 and a storage capacitor Cst1; the first DATA line DATA1 supplies a DATA signal to the first subpixel 100 through a pixel circuit. The second sub-pixel 200 includes a pixel circuit and a light emitting device LED2, and the pixel circuit of the second sub-pixel 200 includes a driving transistor DTFT2 and a storage capacitor Cst2; the second DATA line DATA2 supplies a DATA signal to the second subpixel 200 through a pixel circuit.
In the following, the second sub-pixel 200 is taken as an example, and the pixel circuit of the second sub-pixel 200 may be, for example, a 2T1C circuit or a 7T1C circuit. Fig. 2 is a schematic circuit structure of a sub-pixel according to an embodiment of the present invention. Referring to fig. 1 and 2, the pixel circuit 210 is a 2T1C circuit, the pixel circuit 210 includes a driving transistor DTFT2, a switching transistor STFT2, and a storage capacitor Cst2, a gate electrode of the switching transistor STFT2 of the pixel circuit 210 is electrically connected to the SCAN line SCAN, a source electrode of the switching transistor STFT2 is electrically connected to the second DATA line DATA2, the switching transistor STFT2 is turned on under control of a SCAN signal, a DATA signal is transmitted to a gate electrode of the driving transistor DTFT2, and the storage capacitor Cst2 is charged, and the driving transistor DTFT2 generates a driving current under control of a gate voltage, and the driving current drives the light emitting device LED2 to emit light. The light emitting device LED2 includes an Anode, and the Anode of the sub-pixel is the Anode of the light emitting device LED 2.
As can be seen from the above analysis, the parasitic capacitance C2 and the resistor R2 exist on the second DATA line DATA2, and thus, there is a certain charging time during the process of charging the second DATA line with the DATA voltage. Specifically, the charging formula of the DATA line DATA2 is vt=v0+ (Vu-V0) [1-exp (-t/R2 x C2) ], where Vt is a voltage value on the parasitic capacitor C2 at any time t, V0 is an initial voltage value on the parasitic capacitor C2, and Vu is a termination voltage value after the parasitic capacitor C2 is full. As can be seen from the charging formula, the product of the parasitic capacitance C2 and the resistance R2 determines the charging time of the second DATA line DATA 2. The charging delay on the second DATA line DATA2 slows down the speed of charging the storage capacitor Cst2 by the second DATA line DATA2, so that the display of the light emitting device LED2 is delayed. Meanwhile, since the RC delays on the first DATA line DATA1 and the second DATA line DATA2 are different, the display delay time of different sub-pixels is different, and the display panel has a problem of poor display uniformity.
The embodiment of the invention sets the first DATA line DATA1 to include the RC compensation part, and can adjust the RC delay on the first DATA line DATA1 and the second DATA line DATA2 by adjusting the parasitic capacitance C1 or the resistance R1 on the first DATA line DATA1, so that the RC delay difference between the first DATA line DATA1 and the second DATA line DATA2 can be reduced, and the charging time of the DATA voltage on the first DATA line DATA1 and the charging time of the DATA voltage on the second DATA line DATA2 are the same, thereby the charging time of the first sub-pixel 100 provided with the DATA voltage by the first DATA line DATA1 and the charging time of the second sub-pixel 200 provided with the DATA voltage by the second DATA line DATA2 are the same, and the display uniformity of the display panel is improved.
On the basis of the above embodiment, there are various manners of setting the RC compensating part, for example, if the parasitic capacitance C1 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 of the second DATA line DATA2, the magnitude of the parasitic capacitance C1 of the first DATA line DATA1 and the magnitude of the parasitic capacitance C2 of the second DATA line DATA2 are adjusted by setting the RC compensating part to be the same, or the magnitude of the resistance R1 of the first DATA line DATA1 and the resistance R2 of the second DATA line DATA2 are adjusted by setting the RC compensating part to ensure that the RC delays on the first DATA line DATA1 and the second DATA line DATA2 are the same; if the resistance R1 of the first DATA line DATA1 is smaller than the resistance R2 of the second DATA line DATA2, the magnitudes of the resistance R1 of the first DATA line DATA1 and the resistance R2 of the second DATA line DATA2 are adjusted by the setting of the RC compensation part, or the magnitudes of the parasitic capacitance C1 of the first DATA line DATA1 and the parasitic capacitance C2 of the second DATA line DATA2 are adjusted by the setting of the RC compensation part, so as to ensure that the RC delays on the first DATA line DATA1 and the second DATA line DATA2 are the same.
In the following embodiments, first, an adjustment mode in which the RC compensation unit compensates for parasitic capacitance on the first DATA line DATA1 will be described.
Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 3, in an embodiment of the present invention, alternatively, taking a delta pixel arrangement as an example, the first DATA line DATA1 supplies a DATA signal to the green sub-pixel G and the second DATA line DATA2 supplies a DATA signal to the blue sub-pixel B and the red sub-pixel R. Illustratively, the area where the body portion 11 of the first DATA line DATA1 overlaps the Anode electrode inode is smaller than the area where the second DATA line DATA2 overlaps the Anode electrode, so that the parasitic capacitance C1 of the body portion 11 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 on the second DATA line DATA2, and if the RC compensation portion is not provided, the RC delay on the first DATA line DATA1 is smaller than the RC delay on the second DATA line DATA 2. The embodiment of the present invention provides that the first DATA line DATA1 includes an RC compensation section including the capacitance compensation section 12. The capacitance compensation part 12 of the first DATA line DATA1 overlaps the Anode electrode. That is, the capacitance compensation portion 12 of the first DATA line DATA1 is used for compensating the overlapping area of the body portion of the first DATA line DATA1 and the Anode electrode, so as to facilitate increasing the parasitic capacitance C1 between the first DATA line DATA1 and the Anode electrode.
According to the embodiment of the invention, the parasitic capacitance C1 of the first DATA line DATA1 is increased by changing the wiring pattern of the first DATA line DATA1, and the RC delay of the first DATA line DATA1 is increased, so that the difference of the RC delays on the first DATA line DATA1 and the second DATA line DATA2 is reduced, and the display uniformity of the display panel is improved. In addition, the PDL opening and the pixel arrangement mode of the display panel do not need to be changed, so that the embodiment of the invention has strong practicability.
With continued reference to fig. 3, in one embodiment of the present invention, optionally, the capacitance compensation portion 12 of the first DATA line DATA1 includes a first end 12A and a second end 12B, and the first end 12A of the capacitance compensation portion 12 of the first DATA line DATA1 is in contact with the body portion 11 of the first DATA line DATA1, and the second end 12B of the capacitance compensation portion 12 of the first DATA line DATA1 forms an open circuit. The capacitance compensation section 12 is provided so as to increase the overlapping area of the first DATA line DATA1 and the Anode electrode; on the other hand, since one end of the capacitance compensation section 12 is open, no current flows through the capacitance compensation section 12, and thus the influence of the capacitance compensation section 12 on the resistance of the first DATA line DATA1 is negligible. Therefore, the embodiment of the present invention increases the parasitic capacitance C1 of the first DATA line DATA1 without changing the resistance of the first DATA line DATA 1.
In fig. 3, the capacitance compensation portion 12 outputting the first DATA line DATA1 is illustrated as a stripe, and the shape of the capacitance compensation portion 12 may be a circle, a triangle, or the like in other embodiments, and may be determined according to the layout design of the display panel in practical applications.
Fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 4, alternatively, the second DATA line DATA2 includes a body portion 21 and an RC compensating portion including a capacitance compensating portion 22, the capacitance compensating portion 22 of the second DATA line DATA2 not overlapping the Anode; the capacitance compensation section 22 of the second DATA line DATA2 and the capacitance compensation section 21 of the first DATA line DATA1 have equal resistances. Alternatively, the capacitance compensating portion 22 of the second DATA line DATA2 is equal in number, shape, and size to the capacitance compensating portion 12 of the first DATA line DATA 1. In the embodiment of the invention, the capacitance compensation part 12 is arranged on the first DATA line DATA1, and the capacitance compensation part 22 is correspondingly arranged on the second DATA line DATA2, so that the same characteristics of the resistances of the first DATA line DATA1 and the second DATA line DATA2 are maintained, namely, the parasitic capacitance C1 of the first DATA line DATA1 is increased, the RC delay of the first DATA line DATA1 is increased on the premise of keeping the other characteristics unchanged, and the charging speed of the DATA voltage signals on the first DATA line DATA1 and the second DATA line DATA2 to the storage capacitance Cst2 is further ensured to be consistent.
In fig. 3 and 4, delta pixel arrangements are exemplarily shown, and embodiments of the present invention are also applicable to other pixel arrangements such as diamond (diamond) pixel arrangements. According to different pixel arrangement modes, parasitic capacitances on the data lines are different, and a capacitance compensation part can be arranged according to requirements in practical application.
Fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 5, in an embodiment of the present invention, optionally, taking a diamond pixel arrangement as an example, the first DATA line DATA1 is located at an edge of the display panel, and the second DATA line DATA2 is located at a middle of the display panel. The body portion 11 of the first DATA line DATA1 overlaps only the red and blue sub-pixels R and B, and the body portion 21 of the second DATA line DATA2 overlaps not only the red and blue sub-pixels R and B but also the green sub-pixel G, so that the parasitic capacitance of the body portion 11 of the first DATA line DATA1 is smaller than that of the body portion 21 of the second DATA line DATA2, and if the RC compensation portion is not provided, the RC delay of the body portion of the first DATA line DATA1 is smaller than that of the second DATA line DATA 2. The embodiment of the present invention provides that the first DATA line DATA1 includes the capacitance compensation section 12. The capacitance compensation part 12 of the first DATA line DATA1 overlaps the Anode electrode. That is, the capacitance compensation part 12 of the first DATA line DATA1 is used to compensate the overlapping area of the body part 11 of the first DATA line DATA1 and the Anode electrode inode, thereby being beneficial to increasing the parasitic capacitance C1 between the first DATA line DATA1 and the Anode electrode inode, increasing the RC delay of the first DATA line DATA1, and making the charging speed of the DATA voltage signals on the first DATA line DATA1 and the second DATA line DATA2 to the storage capacitance Cst2 uniform.
With continued reference to fig. 5, on the basis of the above embodiments, optionally, corresponding to the first DATA line DATA1, the second DATA line DATA2 includes a body portion 21 and a capacitance compensation portion 22, and the capacitance compensation portion 22 of the second DATA line DATA2 does not overlap with the Anode electrode; the capacitance compensation section 22 of the second DATA line DATA2 and the capacitance compensation section 12 of the first DATA line DATA1 have equal resistances. Alternatively, the capacitance compensating portion 22 of the second DATA line DATA2 is equal in number, shape, and size to the capacitance compensating portion 12 of the first DATA line DATA 1.
The embodiment of the invention is arranged on the basis that the capacitance compensation part 21 is arranged on the first DATA line DATA1, and the capacitance compensation part 22 is also arranged on the second DATA line DATA2, so that the same resistance characteristics of the first DATA line DATA1 and the second DATA line DATA2 are maintained, namely, the parasitic capacitance C1 of the first DATA line DATA1 is increased, the RC delay of the first DATA line DATA1 is increased on the premise that other characteristics are unchanged, and the charging speed of the DATA voltage signals on the first DATA line DATA1 and the second DATA line DATA2 to the storage capacitor Cst2 is further ensured to be consistent.
Note that, the shape of the capacitance compensation portion 22 in fig. 5 is the same as that of the foregoing embodiments, and will not be described again here.
It should be noted that fig. 3 to 5 exemplarily show that only one capacitance compensation portion is provided on one data line, which is not a limitation of the present invention, and in other embodiments, a plurality of capacitance compensation portions may be provided on one data line as required.
Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 6, in an embodiment of the present invention, alternatively, taking an RGB pixel arrangement as an example, the first DATA line DATA11 supplies a DATA signal to the red sub-pixel R, the first DATA line DATA12 supplies a DATA signal to the green sub-pixel G, and the second DATA line DATA2 supplies a DATA signal to the blue sub-pixel B. The first DATA line DATA11 includes a body portion 111 and a capacitance compensation portion 112, and the first DATA line DATA12 includes a body portion 121 and a capacitance compensation portion 122. The overlapping area of the body portion 121 of the first DATA line DATA12 and the Anode electrode inode is smaller than the overlapping area of the body portion 111 of the first DATA line DATA11 and the Anode electrode inode, and thus the parasitic capacitance of the body portion 121 of the first DATA line DATA12 is smaller than the parasitic capacitance of the body portion 111 of the first DATA line DATA 11. If the RC compensation part is not provided, the RC delay of the first DATA line DATA12 is smaller than that of the first DATA line DATA 11. The overlap area of the body portion 111 of the first DATA line DATA11 and the Anode electrode inode is smaller than the overlap area of the second DATA line DATA2 and the Anode electrode inode, and the parasitic capacitance of the body portion 111 of the first DATA line DATA11 is smaller than the parasitic capacitance of the second DATA line DATA 2. If the RC compensation part is not provided, the RC delay of the first DATA line DATA11 is smaller than that of the second DATA line DATA 2.
The embodiment of the invention sets the capacitance compensation part 112 of the first DATA line DATA11 to overlap with the Anode Anode; the capacitance compensation part 122 of the first DATA line DATA12 overlaps the Anode electrode, and the number of the capacitance compensation parts 112 of the first DATA line DATA11 is smaller than the number of the capacitance compensation parts 122 of the first DATA line DATA 12. Then, the RC delay of the first DATA line DATA12 increases more, the RC delay of the first DATA line DATA11 increases less, and the RC delay of the second DATA line DATA2 does not increase, so that the RC delays of the first DATA line DATA12, the first DATA line DATA11, and the second DATA line DATA2 tend to be equal. As can be seen from the above analysis, the embodiment of the present invention determines the number of corresponding capacitance compensation portions according to the magnitude relation of the RC delay of the body portion of each data line, and the smaller the RC delay of the body portion of the data line, the greater the number of corresponding capacitance compensation portions, which is more beneficial for the RC delay on each data line to be equal.
In the above embodiments, the adjustment method of the RC compensation unit for compensating the parasitic capacitance on the first DATA line DATA1 is described, and the adjustment method of the RC compensation unit for compensating the resistance on the first DATA line DATA1 is described below.
For example, if the parasitic capacitance C1 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 of the second DATA line DATA2, the RC compensation part is set to increase the resistance R1 of the first DATA line DATA1 so that the resistance R1 of the first DATA line DATA1 is greater than the resistance R2 of the second DATA line DATA2, i.e., C1 < C2, and R1 > R2 so that the RC delay on the first DATA line DATA1 and the second DATA line DATA2 is the same. Therefore, when the parasitic capacitances on the first DATA line DATA1 and the second DATA line DATA2 are different, the embodiment of the invention is not limited to adjusting only the parasitic capacitances, and widens the adjustment concept.
Fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 7, in an embodiment of the present invention, alternatively, taking a delta pixel arrangement as an example, the first DATA line DATA1 supplies a DATA signal to the green sub-pixel G and the second DATA line DATA2 supplies a DATA signal to the blue sub-pixel B and the red sub-pixel R. Illustratively, the area where the body portion 11 of the first DATA line DATA1 overlaps the Anode electrode inode is smaller than the area where the second DATA line DATA2 overlaps the Anode electrode, so that the parasitic capacitance C1 of the body portion 11 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 on the second DATA line DATA2, and if the RC compensation portion is not provided, the RC delay on the first DATA line DATA1 is smaller than the RC delay on the second DATA line DATA 2. The embodiment of the invention provides that the first DATA line DATA1 comprises an RC compensation part, the RC compensation part comprises a resistance compensation part 13, and the body part 11 of the first DATA line DATA1 is connected with the resistance compensation part 13 in series. The resistance of the first DATA line DATA1 is the sum of the resistance of the body portion 11 and the resistance of the resistance compensation portion 13. That is, the resistance compensation part 13 of the first DATA line DATA1 serves to compensate for the resistance of the first DATA line DATA1, increasing the resistance of the first DATA line DATA 1.
According to the embodiment of the invention, the series resistance of the first DATA line DATA1 is changed to increase the resistance R1 of the first DATA line DATA1, so that the RC delay of the first DATA line DATA1 is increased, the difference of the RC delays on the first DATA line DATA1 and the second DATA line DATA2 is reduced, and the display uniformity of the display panel is improved. In addition, the PDL opening and the pixel arrangement mode of the display panel do not need to be changed, so that the embodiment of the invention has strong practicability.
In the above embodiments, it is exemplarily shown that the RC delay of the data line can be adjusted by adjusting the resistance value of the resistance compensation portion, but the present invention is not limited thereto, and in other embodiments, the RC delay of the data line can be adjusted by adjusting the number of the resistance compensation portions, and may be set as needed in practical applications.
With reference to fig. 7, on the basis of the above embodiments, optionally, the display panel includes the display area 31 and the fan-out area 32, and the resistance compensation portion is located in the fan-out area 32, so that the arrangement of the resistance compensation portion does not occupy the space of the display area 31, thereby improving the uniformity of display of the display panel on the basis of not affecting the wiring design and resolution of the display area 31.
In an embodiment of the present invention, alternatively, unlike the above-described embodiment, the embodiment of the present invention also provides the capacitance compensation part on the first DATA line DATA1 while providing the resistance compensation 13 on the first DATA line DATA1, and increases the overlap area between the first DATA line DATA1 and the anode while increasing the resistance of the first DATA line DATA1, thereby increasing the capacitance and further reducing the RC delay difference between the first DATA line DATA1 and the second DATA line DATA 2.
Fig. 8 is a schematic cross-sectional view taken along line A-A of fig. 7. Referring to fig. 10, on the basis of the above embodiments, the resistance compensation portion 12 of the first DATA line DATA1 is optionally provided in the same layer as the active layer, and the resistance compensation portion optionally includes a semiconductor resistor. The semiconductor resistor is arranged on the same layer as the active layer, so that the resistance value of the resistance compensation part can be accurately adjusted, and meanwhile, the resistance compensation part and the active layer of the transistor can be manufactured in the same process step, thereby being beneficial to saving the process flow.
In the above embodiments, it is exemplarily shown that the RC delay of the first DATA line DATA1 is smaller than that of the second DATA line DATA2, and thus the RC delay of the first DATA line DATA1 is increased by providing the RC compensation part so that the RC delay of the first DATA line DATA1 and the RC delay of the second DATA line DATA2 are the same. It is not limited to the present invention, and in other embodiments, when the RC delay of the first DATA line DATA1 is greater than the RC delay of the second DATA line DATA2, the RC delay of the first DATA line DATA1 may be reduced by providing an RC compensation part on the first DATA line DATA1 so that the RC delay of the first DATA line DATA1 is the same as the RC delay of the second DATA line DATA 2.
Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 9, taking a delta pixel arrangement as an example, the first DATA line DATA1 supplies a DATA signal to the green subpixel G, and the second DATA line DATA2 supplies a DATA signal to the blue subpixel B and the red subpixel R. The area where the body portion 11 of the first DATA line DATA1 overlaps the Anode electrode inode is smaller than the area where the second DATA line DATA2 overlaps the Anode electrode, so that the parasitic capacitance C1 on the first DATA line DATA1 is smaller than the parasitic capacitance C2 on the second DATA line DATA2, and if the RC compensation portion is not provided, the RC delay on the first DATA line DATA1 is larger than the RC delay on the second DATA line DATA 2.
In one embodiment of the present invention, optionally, the resistance compensation portion 1 of the first DATA line DATA1 does not overlap with the Anode electrode Anode, and the line width of the resistance compensation portion 13 of the first DATA line DATA1 is smaller than the line width of the non-overlapping portion of the second DATA line DATA2 and the Anode electrode Anode. The smaller the line width of the DATA line is, the larger the resistance value is, and the embodiment of the invention increases the resistance of the first DATA line DATA1 by reducing the line width of the partial area of the first DATA line DATA 1; meanwhile, the resistance compensating part 13 does not overlap the Anode electrode, thereby reducing the resistance of the first DATA line DATA1 without changing the parasitic capacitance on the first DATA line DATA1, reducing the RC delay of the first DATA line DATA1, and making the RC delays of the first DATA line DATA1 and the second DATA line DATA2 the same.
In the above embodiment, the manner of reducing the line width of the resistance compensation portion 13 of the first DATA line DATA1 to reduce the resistance of the first DATA line DATA1 is exemplarily shown, but the present invention is not limited thereto. In other embodiments, if the RC delay of the first DATA line DATA1 is greater than the RC delay of the second DATA line DATA2, the line width of the resistance compensation portion 13 of the first DATA line DATA1 may be increased to reduce the resistance of the first DATA line DATA 1.
Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 10, in one embodiment of the present invention, alternatively, unlike the above-described embodiment, the embodiment of the present invention provides that the body portion 21 of the second DATA line DATA2 is connected in parallel with the resistance compensation portion 23. The resistance of the second DATA line DATA2 is obtained by the resistance formula 1/r2=1/r21+1/R23 of the body portion 21 and the resistance of the resistance compensation portion 23, wherein R21 is the resistance of the body portion 21, and R23 is the resistance of the resistance compensation portion 23. The obtained resistance of the second DATA line DATA2 is smaller than the resistance of the main body portion 21. That is, the resistance compensating part 23 of the second DATA line DATA2 serves to compensate for the resistance of the second DATA line DATA2, reduce the RC delay of the second DATA line DATA2, and further make the RC delays of the first DATA line DATA1 and the second DATA line DATA2 the same.
The embodiment of the invention also provides a display device which can be a mobile phone, a tablet personal computer, a wearable device, a display screen of a household appliance, a television or the like. The display device comprises the display panel provided by any embodiment of the invention, and the technical principle and the generated effect are similar and are not repeated.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (9)

1. A display panel, comprising:
a plurality of first data lines and a plurality of second data lines;
a plurality of sub-pixels including anodes located at different film layers and overlapping projections with the first data line, and anodes located at different film layers and overlapping projections with the second data line; an area where the body portion of the first data line overlaps the anode electrode is smaller than an area where the second data line overlaps the anode electrode;
the first data line further comprises an RC compensation part, the RC compensation part comprises a capacitance compensation part, the capacitance compensation part of the first data line is overlapped with projection of the anode, and the anode is an anode of the sub-pixel electrically connected with the first data line; the RC compensation section is configured to compensate for an RC delay of the first data line itself so that the RC delay of the first data line is the same as the RC delay of the second data line.
2. The display panel of claim 1, wherein the capacitance compensation portion of the first data line includes a first end and a second end, the first end of the capacitance compensation portion of the first data line being in contact with the body portion of the first data line, the second end of the capacitance compensation portion of the first data line being formed as an open circuit.
3. The display panel according to claim 1, wherein the second data line includes a body portion and a capacitance compensation portion, the capacitance compensation portion of the second data line not overlapping with a projection of the anode; the capacitance compensation part of the second data line and the capacitance compensation part of the first data line have equal resistances.
4. The display panel according to claim 1, wherein the RC compensation part includes a resistance compensation part, the first data line includes a body part and the resistance compensation part, and the body part of the first data line is connected in series with the resistance compensation part.
5. The display panel according to claim 4, wherein the resistance compensation portion of the first data line is disposed in the same layer as the active layer.
6. The display panel according to claim 4, wherein the second data line includes a body portion and a resistance compensation portion, the body portion of the second data line being connected in parallel with the resistance compensation portion.
7. The display panel according to claim 4, wherein the resistance compensation portion of the first data line does not overlap with the projection of the anode electrode, and a line width of the resistance compensation portion of the first data line is smaller than a line width of the body portion of the first data line.
8. The display panel of claim 4, wherein the RC compensation part includes a capacitance compensation part, and the capacitance compensation part of the first data line overlaps with the projection of the anode.
9. A display device, comprising: the display panel of any one of claims 1-8.
CN202010600711.8A 2020-06-28 2020-06-28 Display panel and display device Active CN111769147B (en)

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