CN111769147A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN111769147A
CN111769147A CN202010600711.8A CN202010600711A CN111769147A CN 111769147 A CN111769147 A CN 111769147A CN 202010600711 A CN202010600711 A CN 202010600711A CN 111769147 A CN111769147 A CN 111769147A
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data line
resistance
display panel
data1
data
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CN202010600711.8A
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Chinese (zh)
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CN111769147B (en
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李蒙蒙
范文志
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Hefei Visionox Technology Co Ltd
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Hefei Visionox Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel includes: a plurality of first data lines and a plurality of second data lines; a plurality of sub-pixels, each sub-pixel comprising an anode, the anode and the first data line are located on different film layers and the projections overlap, and the anode and the second data line are located on different film layers and the projections overlap; wherein the first data line further includes an RC compensation part to make an RC delay of the first data line the same as an RC delay of the second data line. Compared with the prior art, the embodiment of the invention improves the display uniformity of the display panel.

Description

Display panel and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the continuous development of display technology, the application range of display panels is wider and wider, and the requirements of people on the display panels are higher and higher. In particular, the display quality of the display panel is always one of the important indicators for the quality of the display panel for consumers and panel manufacturers.
The Organic Light-Emitting Diode (OLED) display panel has the advantages of high luminance, thin and Light volume, high response speed, easy realization of color display and large screen display, and the like, and has a wide application prospect. However, the conventional OLED display panel has a problem of poor display uniformity, which affects improvement of display image quality of the display panel.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for improving the display uniformity of the display panel.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a display panel, comprising:
a plurality of first data lines and a plurality of second data lines;
a plurality of sub-pixels, each sub-pixel comprising an anode, the anode and the first data line are located on different film layers and the projections overlap, and the anode and the second data line are located on different film layers and the projections overlap;
wherein the first data line further includes an RC compensation part to make an RC delay of the first data line the same as an RC delay of the second data line.
As can be seen from the foregoing technical solutions, the first data line includes the RC compensation portion, and the parasitic capacitance C1 or the resistance R1 on the first data line can be adjusted to adjust the RC delays on the first data line and the second data line to be the same, so as to improve the uniformity of the display panel.
Further, the RC compensation part includes a capacitance compensation part, and there is an overlap between the capacitance compensation part of the first data line and the projection of the anode. According to the technical scheme, if the RC delay of the first data line is smaller than that of the second data line, the capacitance compensation part of the first data line is arranged to compensate the overlapping area of the body part of the first data line and the projection of the anode, so that the parasitic capacitance of the first data line can be increased, the RC delay of the first data line is identical to that of the second data line, and the display uniformity of the display panel is improved.
Further, the first data line further comprises a body portion; the capacitance compensation part of the first data line comprises a first end and a second end, the first end of the capacitance compensation part of the first data line is in contact with the body part of the first data line, and the second end of the capacitance compensation part of the first data line forms an open circuit. The capacitance compensation part is arranged in such a way that, on one hand, the overlapping area of the first data line and the anode is increased; on the other hand, since one end of the capacitance compensation portion is open, no current flows through the capacitance compensation portion, and thus the influence of the capacitance compensation portion on the resistance of the first data line is negligible. Therefore, the embodiment of the invention increases the parasitic capacitance of the first data line on the premise of not changing the resistance of the first data line.
Further, the second data line includes a body portion and a capacitance compensation portion, the capacitance compensation portion of the second data line does not overlap with a projection of the anode; the capacitance compensation part of the second data line and the capacitance compensation part of the first data line have equal resistance. The second data line also comprises the capacitance compensation part, which is beneficial to maintaining the same characteristics of the first data line and the second data line, such as resistance and the like, namely the parasitic capacitance of the first data line is increased on the premise that other characteristics are not changed, and the uniformity of data signals transmitted on the first data line and the second data line is further ensured.
Further, the RC compensation part includes a resistance compensation part, the first data line includes a body part and the resistance compensation part, and the body part of the first data line is connected in series with the resistance compensation part. If the RC delay of the first data line is smaller than the RC delay of the second data line, the embodiment of the invention increases the RC delay of the first data line by setting the series resistance of the first data line to increase the resistance R1 thereof, thereby being beneficial to reducing the difference between the RC delays of the first data line and the second data line and improving the display uniformity of the display panel. In addition, the embodiment of the invention does not need to change the PDL opening and the pixel arrangement mode of the display panel, so the embodiment of the invention has stronger practicability.
Further, the resistance compensation portion of the first data line and the active layer are arranged on the same layer, preferably, the resistance compensation portion comprises a semiconductor resistor, and the resistance compensation portion and the active layer of the transistor can be manufactured in the same process step, so that the process flow is saved.
Further, the second data line includes a body portion and a resistance compensation portion, and the body portion of the second data line is connected in parallel with the resistance compensation portion. The second data line also comprises a resistance compensation part and is arranged in parallel with the body part of the second data line so as to reduce the resistance of the second data line and further reduce the RC delay difference between the first data line and the second data line.
Further, the resistance compensation portion of the first data line does not overlap with the anode, and a line width of the resistance compensation portion of the first data line is smaller than or greater than a line width of the body portion of the first data line. The larger the line width of the data line is, the smaller the resistance value is; conversely, the smaller the line width of the data line, the greater its resistance value. According to the embodiment of the invention, the resistance R1 of the first data line is adjusted by adjusting the line width of the first data line, so that the RC delay of the first data line is adjusted, the difference between the RC delays of the first data line and the second data line is reduced, and the display uniformity of the display panel is improved.
Further, the RC compensation part comprises a capacitance compensation part, the capacitance compensation part of the first data line is overlapped with the projection of the anode, and the RC delay difference between the first data line and the second data line is further reduced by setting resistance compensation and capacitance compensation on the first data line, so that the display uniformity of the display panel is improved. In addition, the embodiment of the invention does not need to change the PDL opening and the pixel arrangement mode of the display panel, so the embodiment of the invention has stronger practicability.
Accordingly, the present invention also provides a display device comprising: a display panel as provided in any of the embodiments of the invention.
The embodiment of the invention provides that the first data line comprises the RC compensation part, the RC delays on the first data line and the second data line can be adjusted to be the same by adjusting the parasitic capacitance C1 or the resistor R1 on the first data line, so that the charging time of the data voltages on the first data line and the second data line is the same, and the charging time of the sub-pixel provided with the data voltage by the first data line and the charging time of the sub-pixel provided with the data voltage by the second data line are the same, thereby improving the uniformity of the display panel.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view taken along line A-A of FIG. 7;
fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It is to be further noted that, for the convenience of description, only a part of the structure relating to the present invention is shown in the drawings, not the whole structure.
Embodiments of the present invention provide a display panel, which may be suitable for an Organic Light-Emitting Diode (OLED) display panel, a Micro Light-Emitting Diode (Micro LED) display panel, or a Quantum Dot Light-Emitting Diode (QLED).
Fig. 1 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention. Referring to fig. 1, the display panel includes: a plurality of first DATA lines DATA1, a plurality of second DATA lines DATA2, and a plurality of subpixels (a first subpixel 100 and a second subpixel 200 are exemplarily shown in fig. 1). The sub-pixel includes an Anode electrode, the Anode electrode and the first DATA line DATA1 are located at different layers and the projections overlap, and the Anode electrode and the second DATA line DATA2 are located at different layers and the projections overlap. The first DATA line DATA1 further includes an RC compensating part (not shown in fig. 1) capable of reducing an RC delay difference between the first DATA line DATA1 and the second DATA line DATA2 so that the RC delay of the first DATA line DATA1 is the same as that of the second DATA line DATA 2. It is understood that the data line and the anode are not in direct contact in the present application, and the overlapping of the data line and the anode in the embodiments of the present application means that the data line and the anode are located on different film layers and overlap in projection on a plane parallel to the display panel.
In addition, it is conceivable that, in the implementation of the present application, it is difficult to make the RC delay between the first DATA line DATA1 and the second DATA line DATA2 completely the same, so that the RC delay of the first DATA line DATA1 and the RC delay of the second DATA line DATA2 are the same as each other in the present application means that the RC delay difference between the first DATA line DATA1 and the second DATA line DATA2 is within an acceptable range, that is, the influence on the display effect of the display panel due to the RC delay difference is not visible to the naked eye.
Because the Anode and the first DATA line DATA1 are located on different film layers and overlap, a parasitic capacitance C1 exists between the Anode and the first DATA line DATA 1; similarly, since the Anode and the second DATA line DATA2 are located on different layers and overlap, a parasitic capacitance C2 exists between the Anode and the second DATA line DATA 2. In addition, the first DATA line DATA1 itself has a resistor R1, and the second DATA line DATA2 itself has a resistor R2. Due to reasons such as pixel arrangement and trace shape, the parasitic capacitance C1 of the first DATA line DATA1 is different from the parasitic capacitance C2 of the second DATA line DATA2, and/or the resistance R1 of the first DATA line DATA1 is different from the resistance R2 of the second DATA line DATA 2.
The first sub-pixel 100 includes a pixel circuit and a light emitting device LED1, the pixel circuit of the first sub-pixel 100 includes a driving transistor DTFT1 and a storage capacitor Cst 1; the first DATA line DATA1 provides a DATA signal to the first subpixel 100 through the pixel circuit. The second sub-pixel 200 includes a pixel circuit and a light emitting device LED2, and the pixel circuit of the second sub-pixel 200 includes a driving transistor DTFT2 and a storage capacitor Cst 2; the second DATA line DATA2 provides a DATA signal to the second subpixel 200 through the pixel circuit.
In the following description, the second sub-pixel 200 is taken as an example, and the pixel circuit of the second sub-pixel 200 may be a circuit such as a 2T1C circuit or a 7T1C circuit. Fig. 2 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present invention. Referring to fig. 1 and 2, the pixel circuit 210 is a 2T1C circuit, the pixel circuit 210 includes a driving transistor DTFT2, a switching transistor STFT2 and a storage capacitor Cst2, a gate of the switching transistor STFT2 of the pixel circuit 210 is electrically connected to a SCAN line SCAN, a source of the switching transistor STFT2 is electrically connected to a second DATA line DATA2, the switching transistor STFT2 is turned on under the control of a SCAN signal, transmits a DATA signal to the gate of the driving transistor DTFT2 and charges the storage capacitor Cst2, and the driving transistor DTFT2 generates a driving current under the control of a gate voltage, and the driving current drives the light emitting device LED2 to emit light. The light emitting device LED2 includes an Anode electrode, and the Anode electrode of the sub-pixel is the Anode electrode of the light emitting device LED 2.
As can be seen from the above analysis, the parasitic capacitor C2 and the resistor R2 exist on the second DATA line DATA2, and thus, a certain charging time exists in the process of charging the second DATA line with the DATA voltage. Specifically, the charging formula of the DATA line DATA2 is Vt ═ V0+ (Vu-V0) × [1-exp (-t/R2 × C2) ], where Vt is the voltage value on the parasitic capacitor C2 at any time t, V0 is the initial voltage value on the parasitic capacitor C2, and Vu is the end voltage value after the parasitic capacitor C2 is full. As can be seen from the charging formula, the product of the parasitic capacitance C2 and the resistance R2 determines the charging time of the second DATA line DATA 2. The charging delay on the second DATA line DATA2 slows down the charging speed of the second DATA line DATA2 to the storage capacitor Cst2, causing a delay in the display of the light emitting device LED 2. Meanwhile, the display panel has a problem of poor uniformity due to different display delay times of different sub-pixels caused by different RC delays on the first DATA line DATA1 and the second DATA line DATA 2.
The embodiment of the invention provides that the first DATA line DATA1 includes the RC compensation part, the RC delay on the first DATA line DATA1 and the second DATA line DATA2 can be adjusted by adjusting the parasitic capacitance C1 or the resistance R1 on the first DATA line DATA1, the RC delay difference between the first DATA line DATA1 and the second DATA line DATA2 can be reduced, the charging time of the DATA voltage on the first DATA line DATA1 and the charging time of the DATA voltage on the second DATA line DATA2 are the same, the charging time of the first sub-pixel 100 supplied with the DATA voltage by the first DATA line DATA1 and the charging time of the second sub-pixel 200 supplied with the DATA voltage by the second DATA line DATA2 are the same, and the uniformity of the display panel display is improved.
In addition to the above embodiments, there are various arrangements of the RC compensation part, for example, if the parasitic capacitance C1 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 of the second DATA line DATA2, the parasitic capacitance C1 of the first DATA line DATA1 and the parasitic capacitance C2 of the second DATA line DATA2 are adjusted to be the same in size by the arrangement of the RC compensation part, or the resistance R1 of the first DATA line DATA1 and the resistance R2 of the second DATA line DATA2 are adjusted to be the same in size by the arrangement of the RC compensation part, so as to ensure that the RC delays on the first DATA line DATA1 and the second DATA line DATA2 are the same; if the resistance R1 of the first DATA line DATA1 is smaller than the resistance R2 of the second DATA line DATA2, the resistance R1 of the first DATA line DATA1 and the resistance R2 of the second DATA line DATA2 are adjusted to be the same by the setting of the RC compensation unit, or the parasitic capacitance C1 of the first DATA line DATA1 and the parasitic capacitance C2 of the second DATA line DATA2 are adjusted by the setting of the RC compensation unit, so as to ensure that the RC delays on the first DATA line DATA1 and the second DATA line DATA2 are the same.
In the following embodiments, first, an adjustment method of the RC compensation unit for compensating the parasitic capacitance on the first DATA line DATA1 will be described.
Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 3, in an embodiment of the invention, optionally, taking a delta pixel arrangement as an example, the first DATA line DATA1 provides DATA signals to the green sub-pixel G, and the second DATA line DATA2 provides DATA signals to the blue sub-pixel B and the red sub-pixel R. Illustratively, the area of the body part 11 of the first DATA line DATA1 overlapping the Anode electrode is smaller than the area of the second DATA line DATA2 overlapping the Anode electrode, so the parasitic capacitance C1 of the body part 11 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 on the second DATA line DATA2, and if no RC compensation part is provided, the RC delay on the first DATA line DATA1 is smaller than the RC delay on the second DATA line DATA 2. The embodiment of the invention provides that the first DATA line DATA1 includes an RC compensation part including the capacitance compensation part 12. The capacitance compensation part 12 of the first DATA line DATA1 overlaps the Anode electrode. That is, the capacitance compensation part 12 of the first DATA line DATA1 is used to compensate the overlapping area of the body part of the first DATA line DATA1 and the Anode electrode, thereby facilitating to increase the parasitic capacitance C1 between the first DATA line DATA1 and the Anode electrode.
The embodiment of the invention increases the parasitic capacitance C1 by changing the routing pattern of the first DATA line DATA1, and increases the RC delay of the first DATA line DATA1, thereby being beneficial to reducing the difference between the RC delays of the first DATA line DATA1 and the second DATA line DATA2 and improving the display uniformity of the display panel. In addition, the embodiment of the invention does not need to change the PDL opening and the pixel arrangement mode of the display panel, so the embodiment of the invention has stronger practicability.
With continued reference to fig. 3, in an embodiment of the invention, optionally, the capacitance compensation part 12 of the first DATA line DATA1 includes a first end 12A and a second end 12B, the first end 12A of the capacitance compensation part 12 of the first DATA line DATA1 is in contact with the body part 11 of the first DATA line DATA1, and the second end 12B of the capacitance compensation part 12 of the first DATA line DATA1 forms an open circuit. The capacitance compensation section 12 is configured such that, on the one hand, the overlapping area of the first DATA line DATA1 and the Anode electrode is increased; on the other hand, since one end of the capacitance compensation portion 12 is open, no current flows through the capacitance compensation portion 12, and thus the influence of the capacitance compensation portion 12 on the resistance of the first DATA line DATA1 is negligible. Therefore, the embodiment of the invention increases the parasitic capacitance C1 of the first DATA line DATA1 without changing the resistance of the first DATA line DATA 1.
It should be noted that, in fig. 3, the capacitance compensation portion 12 outputting the first DATA line DATA1 is shown as a bar, which is not a limitation of the present invention, and in other embodiments, the shape of the capacitance compensation portion 12 may be circular or triangular, and may be determined according to the layout design of the display panel in practical applications.
Fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 4, on the basis of the above embodiments, optionally, the second DATA line DATA2 includes a body portion 21 and an RC compensating portion including a capacitance compensating portion 22, the capacitance compensating portion 22 of the second DATA line DATA2 does not overlap with the Anode electrode; the capacitance compensation part 22 of the second DATA line DATA2 and the capacitance compensation part 21 of the first DATA line DATA1 have the same resistance. Alternatively, the capacitance compensation parts 22 of the second DATA line DATA2 may be equal in number, shape, and size to the capacitance compensation parts 12 of the first DATA line DATA 1. In the embodiment of the present invention, the capacitance compensation part 12 is disposed on the first DATA line DATA1, and the capacitance compensation part 22 is correspondingly disposed on the second DATA line DATA2, which is favorable for maintaining the same characteristics of the resistances of the first DATA line DATA1 and the second DATA line DATA2, i.e., under the premise that other characteristics are not changed, the parasitic capacitance C1 of the first DATA line DATA1 is increased, the RC delay of the first DATA line DATA1 is increased, and the speed of charging the storage capacitor Cst2 by the DATA voltage signals on the first DATA line DATA1 and the second DATA line DATA2 is further ensured to be the same.
In fig. 3 and 4, a delta pixel arrangement is exemplarily shown, and the embodiment of the present invention is also applicable to other pixel arrangements such as a diamond (diamond) pixel arrangement. The parasitic capacitance on each data line is different according to different pixel arrangement modes, and a capacitance compensation part can be arranged as required in practical application.
Fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 5, in an embodiment of the invention, optionally, taking the diamond pixel arrangement as an example, the first DATA line DATA1 is located at the edge of the display panel, and the second DATA line DATA2 is located at the middle of the display panel. The body part 11 of the first DATA line DATA1 overlaps only the red and blue sub-pixels R and B, and the body part 21 of the second DATA line DATA2 overlaps not only the red and blue sub-pixels R and B but also the green sub-pixel G, so that the parasitic capacitance of the body part 11 of the first DATA line DATA1 is smaller than that of the body part 21 of the second DATA line DATA2, and the body part RC delay of the first DATA line DATA1 is smaller than that of the second DATA line DATA2 if no RC compensating part is provided. The embodiment of the invention provides that the first DATA line DATA1 includes the capacitance compensation part 12. The capacitance compensation part 12 of the first DATA line DATA1 overlaps the Anode electrode. That is, the capacitance compensation part 12 of the first DATA line DATA1 is used to compensate the overlapping area of the body part 11 of the first DATA line DATA1 and the Anode electrode, thereby facilitating to increase the parasitic capacitance C1 between the first DATA line DATA1 and the Anode electrode, and increase the RC delay of the first DATA line DATA1, so that the DATA voltage signals on the first DATA line DATA1 and the second DATA line DATA2 are charged to the storage capacitor Cst2 at the same speed.
With continued reference to fig. 5, on the basis of the above-described embodiments, optionally, the second DATA line DATA2 includes the body portion 21 and the capacitance compensation portion 22, corresponding to the first DATA line DATA1, the capacitance compensation portion 22 of the second DATA line DATA2 not overlapping the Anode electrode; the capacitance compensation part 22 of the second DATA line DATA2 and the capacitance compensation part 12 of the first DATA line DATA1 have the same resistance. Alternatively, the capacitance compensation parts 22 of the second DATA line DATA2 may be equal in number, shape, and size to the capacitance compensation parts 12 of the first DATA line DATA 1.
The embodiment of the invention is arranged on the basis that the capacitance compensation part 21 is arranged on the first DATA line DATA1, and the capacitance compensation part 22 is also arranged on the second DATA line DATA2, which is beneficial to maintaining the same resistance characteristics of the first DATA line DATA1 and the second DATA line DATA2, i.e. under the premise that other characteristics are not changed, the parasitic capacitance C1 of the first DATA line DATA1 is increased, the RC delay of the first DATA line DATA1 is increased, and the speed of charging the storage capacitance Cst2 by the DATA voltage signals on the first DATA line DATA1 and the second DATA line DATA2 is further ensured to be consistent.
It should be noted that the shape of the capacitance compensation portion 22 in fig. 5 is the same as that of the previous embodiments, and is not described again here.
It should be noted that fig. 3-5 exemplarily show that only one capacitance compensation portion is disposed on one data line, but the present invention is not limited thereto, and in other embodiments, a plurality of capacitance compensation portions may be disposed on one data line as needed.
Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 6, in an embodiment of the invention, optionally, taking the RGB pixel arrangement as an example, the first DATA line DATA11 provides DATA signals to the red sub-pixel R, the first DATA line DATA12 provides DATA signals to the green sub-pixel G, and the second DATA line DATA2 provides DATA signals to the blue sub-pixel B. The first DATA line DATA11 includes a body part 111 and a capacitance compensation part 112, and the first DATA line DATA12 includes a body part 121 and a capacitance compensation part 122. An overlapping area of the body portion 121 of the first DATA line DATA12 and the Anode electrode is smaller than an overlapping area of the body portion 111 of the first DATA line DATA11 and the Anode electrode, however, a parasitic capacitance of the body portion 121 of the first DATA line DATA12 is smaller than a parasitic capacitance of the body portion 111 of the first DATA line DATA 11. If the RC compensation part is not provided, the RC delay of the first DATA line DATA12 is smaller than that of the first DATA line DATA 11. An overlapping area of the body portion 111 of the first DATA line DATA11 and the Anode electrode is smaller than an overlapping area of the second DATA line DATA2 and the Anode electrode, and a parasitic capacitance of the body portion 111 of the first DATA line DATA11 is smaller than a parasitic capacitance of the second DATA line DATA 2. If the RC compensation part is not provided, the RC delay of the first DATA line DATA11 is smaller than that of the second DATA line DATA 2.
The embodiment of the invention provides that the capacitance compensation part 112 of the first DATA line DATA11 is overlapped with the Anode electrode; the capacitance compensation part 122 of the first DATA line DATA12 overlaps the Anode electrode, and the number of the capacitance compensation parts 112 of the first DATA line DATA11 is less than the number of the capacitance compensation parts 122 of the first DATA line DATA 12. Then, the RC delay of the first DATA line DATA12 is increased more, the RC delay of the first DATA line DATA11 is increased less, and the RC delay of the second DATA line DATA2 is not increased, so that the RC delays of the first DATA line DATA12, the first DATA line DATA11, and the second DATA line DATA2 tend to be equal. As can be seen from the above analysis, in the embodiments of the present invention, the number of the corresponding capacitance compensation portions is determined according to the magnitude relationship of the RC delay of the main portion of each data line, and the smaller the RC delay of the main portion of the data line is, the larger the number of the corresponding capacitance compensation portions is, the more the RC delays on the data lines are favorably equalized.
In the above embodiments, the adjustment method of the RC compensation section for compensating the parasitic capacitance on the first DATA line DATA1 is explained, and the adjustment method of the RC compensation section for compensating the resistance on the first DATA line DATA1 is explained below.
For example, if the parasitic capacitance C1 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 of the second DATA line DATA2, the RC compensation part is configured to increase the resistance R1 of the first DATA line DATA1 so that the resistance R1 of the first DATA line DATA1 is greater than the resistance R2 of the second DATA line DATA2, i.e., C1 < C2, and R1 > R2, so that the RC delays on the first DATA line DATA1 and the second DATA line DATA2 are the same. Therefore, in the embodiment of the invention, when the parasitic capacitances on the first DATA line DATA1 and the second DATA line DATA2 are different, the adjustment is not limited to only adjusting the parasitic capacitances, and the adjustment concept is widened.
Fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 7, in an embodiment of the invention, optionally, taking a delta pixel arrangement as an example, the first DATA line DATA1 provides DATA signals to the green sub-pixel G, and the second DATA line DATA2 provides DATA signals to the blue sub-pixel B and the red sub-pixel R. Illustratively, the area of the body part 11 of the first DATA line DATA1 overlapping the Anode electrode is smaller than the area of the second DATA line DATA2 overlapping the Anode electrode, so the parasitic capacitance C1 of the body part 11 of the first DATA line DATA1 is smaller than the parasitic capacitance C2 on the second DATA line DATA2, and if no RC compensating part is provided, the RC delay on the first DATA line DATA1 is smaller than the RC delay on the second DATA line DATA 2. The embodiment of the invention provides that the first DATA line DATA1 includes the RC compensating part including the resistance compensating part 13, and the body part 11 of the first DATA line DATA1 is connected in series with the resistance compensating part 13. The resistance of the first DATA line DATA1 is obtained by summing the resistance of the body portion 11 thereof and the resistance of the resistance compensation portion 13. That is, the resistance compensation part 13 of the first DATA line DATA1 is used to compensate the resistance of the first DATA line DATA1, increasing the resistance of the first DATA line DATA 1.
The embodiment of the invention increases the resistance R1 of the first DATA line DATA1 by changing the series resistance of the first DATA line DATA 3578, and increases the RC delay of the first DATA line DATA1, thereby being beneficial to reducing the difference of the RC delays on the first DATA line DATA1 and the second DATA line DATA2 and improving the display uniformity of the display panel. In addition, the embodiment of the invention does not need to change the PDL opening and the pixel arrangement mode of the display panel, so the embodiment of the invention has stronger practicability.
It should be noted that, in the above embodiments, it is exemplarily shown that the RC delay of the data line can be adjusted by adjusting the resistance value of the resistance compensation unit, but the present invention is not limited thereto, and in other embodiments, the RC delay of the data line can be adjusted by adjusting the number of the resistance compensation units, and the RC delay can be set as needed in actual applications.
With reference to fig. 7, on the basis of the foregoing embodiments, optionally, the display panel includes the display area 31 and the fan-out area 32, and the resistance compensation portion is located in the fan-out area 32, so that the resistance compensation portion is disposed without occupying a space of the display area 31, and thus, on the basis of not affecting the wiring design and the resolution of the display area 31, the uniformity of display of the display panel is improved.
In an embodiment of the present invention, different from the above-described embodiment, optionally, in the embodiment of the present invention, the resistance compensation 13 is provided on the first DATA line DATA1, and the capacitance compensation part is also provided on the first DATA line DATA1, so that the resistance of the first DATA line DATA1 is increased, and the overlapping area between the first DATA line DATA1 and the anode is also increased, thereby increasing the capacitance, and further reducing the RC delay difference between the first DATA line DATA1 and the second DATA line DATA 2.
Fig. 8 is a schematic cross-sectional view taken along a-a in fig. 7. Referring to fig. 10, in the basis of the above embodiments, the resistance compensation part 12 of the first DATA line DATA1 may be disposed on the same layer as the active layer, and may include a semiconductor resistor. The semiconductor resistor arranged on the same layer as the active layer can accurately adjust the resistance value of the resistance compensation part, and meanwhile, the resistance compensation part and the active layer of the transistor can be manufactured in the same process step, so that the process flow can be saved.
In the above-described embodiments, it is exemplarily shown that the RC delay of the first DATA line DATA1 is smaller than that of the second DATA line DATA2, and thus the RC delay of the first DATA line DATA1 is increased by providing the RC compensation part so that the RC delay of the first DATA line DATA1 is the same as that of the second DATA line DATA 2. It is not limited to the present invention, and in other embodiments, the RC delay of the first DATA line DATA1 may be reduced by providing an RC compensation part on the first DATA line DATA1 when the RC delay of the first DATA line DATA1 is greater than that of the second DATA line DATA2, so that the RC delay of the first DATA line DATA1 is the same as that of the second DATA line DATA 2.
Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 9, taking the delta pixel arrangement as an example, the first DATA line DATA1 provides DATA signals to the green sub-pixel G, and the second DATA line DATA2 provides DATA signals to the blue sub-pixel B and the red sub-pixel R. The area of the body portion 11 of the first DATA line DATA1 overlapping the Anode electrode is smaller than the area of the second DATA line DATA2 overlapping the Anode electrode, so the parasitic capacitance C1 on the first DATA line DATA1 is smaller than the parasitic capacitance C2 on the second DATA line DATA2, and if no RC compensation portion is provided, the RC delay on the first DATA line DATA1 is larger than the RC delay on the second DATA line DATA 2.
In one embodiment of the present invention, optionally, the resistance compensation part 1 of the first DATA line DATA1 does not overlap the Anode electrode, and the line width of the resistance compensation part 13 of the first DATA line DATA1 is smaller than the line width of the non-overlapping portion of the second DATA line DATA2 and the Anode electrode. The smaller the line width of the DATA line is, the larger the resistance value of the DATA line is, and the embodiment of the invention increases the resistance of the first DATA line DATA1 by reducing the line width of the partial area of the first DATA line DATA 1; meanwhile, the resistance compensation part 13 does not overlap the Anode electrode, thereby reducing the resistance of the first DATA line DATA1 and reducing the RC delay of the first DATA line DATA1 without changing the parasitic capacitance on the first DATA line DATA1, so that the RC delays of the first DATA line DATA1 and the second DATA line DATA2 are the same.
In the above embodiment, the way of reducing the line width of the resistance compensation portion 13 of the first DATA line DATA1 to reduce the resistance of the first DATA line DATA1 is exemplarily shown, and is not a limitation of the present invention. In other embodiments, if the RC delay of the first DATA line DATA1 is greater than the RC delay of the second DATA line DATA2, the line width of the resistance compensation part 13 of the first DATA line DATA1 may be increased to decrease the resistance of the first DATA line DATA 1.
Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 10, in an embodiment of the present invention, alternatively, unlike the above-described embodiment, the embodiment of the present invention provides that the body portion 21 of the second DATA line DATA2 is connected in parallel with the resistance compensation portion 23. The resistance of the second DATA line DATA2 is obtained by using the resistance formula 1/R2 of 1/R21+1/R23 for the resistance of the body portion 21 and the resistance compensation portion 23, where R21 is the resistance value of the body portion 21 and R23 is the resistance value of the resistance compensation portion 23. The obtained resistance of the second DATA line DATA2 is smaller than the resistance of the body portion 21. That is, the resistance compensation part 23 of the second DATA line DATA2 compensates for the resistance of the second DATA line DATA2, reduces the resistance of the second DATA line DATA2, reduces the RC delay of the second DATA line DATA2, and further makes the RC delays of the first DATA line DATA1 and the second DATA line DATA2 the same.
The embodiment of the invention also provides a display device, which can be a display screen of a mobile phone, a tablet personal computer, a computer, wearable equipment, a household appliance or a television and the like. The display device comprises the display panel provided by any embodiment of the invention, and the technical principle and the generated effect are similar and are not described again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A display panel, comprising:
a plurality of first data lines and a plurality of second data lines;
a plurality of sub-pixels, each sub-pixel comprising an anode, the anode and the first data line are located on different film layers and the projections overlap, and the anode and the second data line are located on different film layers and the projections overlap;
wherein the first data line further includes an RC compensation part to make an RC delay of the first data line the same as an RC delay of the second data line.
2. The display panel according to claim 1, wherein the RC compensation part comprises a capacitance compensation part, and the capacitance compensation part of the first data line overlaps with a projection of the anode.
3. The display panel according to claim 2, wherein the first data line further comprises a body portion;
the capacitance compensation part of the first data line comprises a first end and a second end, the first end of the capacitance compensation part of the first data line is in contact with the body part of the first data line, and the second end of the capacitance compensation part of the first data line forms an open circuit.
4. The display panel according to claim 2, wherein the second data line includes a body portion and a capacitance compensation portion, and a projection of the capacitance compensation portion of the second data line does not overlap with a projection of the anode; the capacitance compensation part of the second data line and the capacitance compensation part of the first data line have equal resistance.
5. The display panel according to claim 1, wherein the RC compensating portion comprises a resistance compensating portion, wherein the first data line comprises a body portion and the resistance compensating portion, and wherein the body portion of the first data line is connected in series with the resistance compensating portion.
6. The display panel according to claim 5, wherein the resistance compensation portion of the first data line is disposed on the same layer as the active layer.
7. The display panel according to claim 5, wherein the second data line includes a body portion and a resistance compensation portion, and wherein the body portion of the second data line is connected in parallel with the resistance compensation portion.
8. The display panel according to claim 5, wherein the projection of the resistance compensation portion of the first data line and the anode do not overlap, and wherein a line width of the resistance compensation portion of the first data line is smaller than a line width of the body portion of the first data line.
9. The display panel according to claim 5, wherein the RC compensation part comprises a capacitance compensation part, and the capacitance compensation part of the first data line overlaps with a projection of the anode.
10. A display device, comprising: the display panel of any one of claims 1-9.
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