CN113885262B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN113885262B CN113885262B CN202111168481.3A CN202111168481A CN113885262B CN 113885262 B CN113885262 B CN 113885262B CN 202111168481 A CN202111168481 A CN 202111168481A CN 113885262 B CN113885262 B CN 113885262B
- Authority
- CN
- China
- Prior art keywords
- display area
- display
- display panel
- along
- data line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims description 28
- 239000004973 liquid crystal related substance Substances 0.000 claims description 9
- 230000007423 decrease Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 23
- 239000010408 film Substances 0.000 description 15
- 239000003990 capacitor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 230000001788 irregular Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The application discloses display panel and display device relates to and shows technical field, includes: the display device comprises a T-shaped display area, wherein the T-shaped display area comprises a first display area and second display areas adjacent to the first display area, and the number of the second display areas is 2; the second display areas are respectively positioned at two sides of the first display area along the first direction; along the second direction, the length of the first display area is longer than that of the second display area; the first direction and the second direction intersect; a plurality of data lines arranged along a first direction and extending along a second direction; the length of the data line positioned in the first display area is longer than that of the data line positioned in the second display area; the common electrode is positioned on one side of the film layer where the data line is positioned, which is close to the light emitting surface of the display panel; and the capacitance adjusting part is used for adjusting the storage capacitance generated between the data line and the common electrode in the first display area and/or the second display area. According to the display device, the capacitance adjusting part is arranged, so that the split screen phenomenon in the display area can be effectively improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the continuous development of display panels, the display effect requirements on the display panels are higher compared with those of large-size display panels when the display panels are arranged as special-shaped display panels.
In the prior art, for a liquid crystal display panel, a pixel electrode and a common electrode are both laid on an array substrate, wherein the array substrate further comprises a thin film transistor and various signal wires, and the lengths of the various signal wires in a display area are not uniform, so that storage capacitances formed between the signal wires and the common electrode are inconsistent, and the charging voltage of pixels in each display area is different, so that the display panel is easy to generate a split screen phenomenon, and the quality of the display panel is affected; therefore, there is a need for a display panel and a display device for improving the split-screen phenomenon of the display area in the display panel.
Disclosure of Invention
In view of this, the present application provides a display panel and a display device, which can effectively improve the split screen phenomenon in the display area by adopting a mode of providing a capacitance adjusting portion.
The application has the following technical scheme:
in a first aspect, the present application provides a display panel, comprising: the display device comprises a T-shaped display area, wherein the T-shaped display area comprises a first display area and second display areas adjacent to the first display area, and the number of the second display areas is 2; the second display areas are respectively positioned at two sides of the first display area along the first direction; along the second direction, the length of the first display area is longer than that of the second display area; the first direction and the second direction intersect;
a plurality of data lines arranged along a first direction and extending along a second direction; the length of the data line positioned in the first display area is longer than that of the data line positioned in the second display area;
the common electrode is positioned on one side of the film layer where the data line is positioned, which is close to the light emitting surface of the display panel;
and the capacitance adjusting part is used for adjusting the storage capacitance generated between the data line and the common electrode in the first display area and/or the second display area.
In a second aspect, the present application further provides a display device, including a display panel, where the display panel is a display panel provided by the present application.
Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:
the display panel and the display device provided by the application can adjust the size of the storage capacitor generated between the data line and the common electrode in the first display area, can also adjust the size of the storage capacitor generated between the data line and the common electrode in the second display area, and can also adjust the size of the storage capacitor generated between the data line and the common electrode in the first display area and the second display area at the same time so as to compensate for bad display effects caused by pixel charging voltage differences in different display areas due to the length differences of the data lines in the first display area and the second display area; therefore, the charging voltage of each pixel in the first display area and the second display area can be regulated, so that the storage capacitance generated between the data lines in the first display area and the second display area and the common electrode is consistent within the error allowable range, and the screen separation phenomenon of the first display area and the second display area can be effectively avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view of the display panel along A-A' of the embodiment of FIG. 1;
FIG. 3 is a schematic structural diagram of a common electrode according to an embodiment of the present disclosure;
FIG. 4 is a cross-sectional view of the common electrode along B-B' provided by the embodiment of FIG. 3;
FIG. 5 is a schematic diagram of another structure of a common electrode according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a virtual electrode pattern according to an embodiment of the present disclosure;
FIG. 7 is a cross-sectional view of the virtual electrode along line C-C' provided by the embodiment of FIG. 6;
FIG. 8 is a schematic structural diagram of a first compensation electrode pattern according to an embodiment of the present disclosure;
FIG. 9 is a cross-sectional view of the first compensation electrode pattern provided by the embodiment of FIG. 8, taken along the line D-D';
FIG. 10 is a schematic diagram of another structure of a first compensation electrode pattern according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 12 is a schematic diagram of a second compensation electrode pattern according to an embodiment of the present disclosure;
FIG. 13 is a cross-sectional view of the second compensation electrode pattern provided by the embodiment of FIG. 12, taken along E-E';
FIG. 14 is a schematic diagram of another structure of a second compensation electrode pattern according to an embodiment of the present disclosure;
fig. 15 is a schematic view of another structure of a display panel according to an embodiment of the disclosure;
fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same component by different names. The description and claims do not take the form of an element differentiated by name, but rather by functionality. As used throughout the specification and claims, the word "comprise" is an open-ended term, and thus should be interpreted to mean "include, but not limited to. By "substantially" is meant that within an acceptable error range, a person skilled in the art is able to solve the technical problem within a certain error range, substantially achieving the technical effect. Furthermore, the term "coupled" as used herein includes any direct or indirect electrical coupling. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical coupling to the second device, or through another device or coupling means coupled to ground. The description hereinafter sets forth the preferred embodiment for carrying out the present application, but is not intended to limit the scope of the present application in general, for the purpose of illustrating the general principles of the present application. The scope of the present application is defined by the appended claims. The same points between the embodiments are not described in detail.
The following detailed description refers to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic structural diagram of a display panel 100 according to an embodiment of the present application, fig. 2 is a cross-sectional view along A-A' of the display panel 100 according to the embodiment of fig. 1, referring to fig. 1 and 2, the display panel 100 according to the present application includes: a T-shaped display area 10 including a first display area 11 and a second display area 12 adjacent to the first display area 11, the second display area 12 being provided with 2; the second display areas 12 are respectively located at two sides of the first display area 11 along the first direction D1; along the second direction D2, the length D1 of the first display area 11 is greater than the length D2 of the second display area 12; the first direction D1 and the second direction D2 intersect;
a plurality of data lines 20 arranged along a first direction D1 and extending along a second direction D2; the length of the data line 20 located in the first display area 11 is longer than the length of the data line 20 located in the second display area 12;
the common electrode 30 is positioned at one side of the film layer where the data line 20 is positioned, which is close to the light emitting surface of the display panel 100;
and a capacitance adjusting part 40 for adjusting a storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11 and/or the second display area 12.
It should be noted that, the embodiment shown in fig. 1 only schematically illustrates the relative positional relationship between the first display area 11 and the second display area 12, and does not represent the actual size; the length of the data line 20 in the first display area 11 and the length of the second data line 20 do not represent the actual size; the display area in the embodiment shown in fig. 1 is a T-shaped display area, which is an irregular display area, and the display area with an irregular structure in the prior art causes the problem of difference of pixel charging voltages in each area. It should be noted that the scheme set in the present application is applicable to most of the irregular display panels 100; the embodiment shown in fig. 2 only schematically shows the relative positional relationship between the capacitance adjusting portion 40 and the data line 20, and does not represent the actual size.
Specifically, please continue to refer to fig. 1 and 2, the display panel 100 in this embodiment includes a T-shaped display area, wherein the T-shaped display area is an irregular display area, the display area is used for displaying a picture, a non-display area is further disposed around the display area, and the non-display area is used for setting various circuit structures; the T-shaped display area 10 includes a first display area 11 and a second display area 12, where the first display area 11 and the second display area 12 are adjacent, 2 second display areas 12 are provided, and the second display areas 12 are respectively located at two sides of the first display area 11 along the first direction D1; along the second direction D2, the length D1 of the first display area 11 is greater than the length D2 of the second display area 12, and one of two sides of the first display area 11 along the second direction D2 and one of two sides of the second display area 12 along the second direction D2 are flush, the first direction D1 and the second direction D2 intersect, alternatively, the first direction D1 and the second direction D2 are perpendicular.
Further, the embodiment further includes a plurality of data lines 20, the data lines 20 are arranged along the first direction D1, and extend along the second direction D2, and the length of the data lines 20 located in the first display area 11 is greater than the length of the data lines 20 located in the second display area 12; the display device further comprises a common electrode 30, wherein the common electrode 30 is positioned on one side of the film layer where the data line 20 is positioned, which is close to the light-emitting surface of the display panel, and the storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11 is different from the storage capacitance generated between the data line 20 and the common electrode 30 in the second display area 12, wherein the data line 20 in the first display area 11 is longer, and the storage capacitance generated between the data line 20 and the common electrode 30 is larger; in order to solve the above-mentioned technical problem, further, in this embodiment, a capacitance adjusting portion 40 is further provided, which can adjust the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11, and can also adjust the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the second display area 12, and can also adjust the sizes of the storage capacitances generated between the data line 20 and the common electrode 30 in the first display area 11 and the second display area 12 at the same time, so as to compensate for the bad display effect caused by the difference of the pixel charging voltages in different display areas due to the difference of the lengths of the data lines in the first display area and the second display area; in this way, the charging voltages of the pixels in the first display area and the second display area can be adjusted, so that the storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11 and the second display area 12 is consistent within the error allowable range, and the split screen phenomenon of the first display area 11 and the second display area 12 can be effectively avoided.
Alternatively, fig. 3 is a schematic structural diagram of the common electrode 30 provided in the embodiment of the present application, fig. 4 is a cross-sectional view along B-B' of the common electrode 30 provided in the embodiment of fig. 3, please refer to fig. 3 and fig. 4, in which, in the first display area 11, a plurality of hollow areas 31 are provided in the common electrode 30, and the common electrode 30 provided with the hollow areas 31 is multiplexed as the capacitance adjusting portion 40; along the direction D3 perpendicular to the light emitting surface of the display panel, the hollowed-out area 31 overlaps the data line 20 of the first display area 11.
It should be noted that, the embodiment shown in fig. 3 only schematically illustrates the relative positions of the hollow areas 31, and does not represent the actual dimensions of the hollow areas 31; the embodiment shown in fig. 4 only schematically illustrates the relative positional relationship between the hollowed-out area 31 and the data line 20, and does not represent the actual size.
Specifically, please continue to refer to fig. 3 and fig. 4, and referring to fig. 1, in the present embodiment, a plurality of hollow areas 31 are provided in the common electrode 30, the common electrode 30 is a whole-surface electrode, and extends through the first display area 11 to the second display area 12, the hollow areas 31 are located in the first display area 11, and the common electrode 30 is multiplexed as the capacitance adjusting portion 40; along the direction D3 perpendicular to the light emitting surface of the display panel, the hollowed-out area 31 overlaps the data line 20 of the first display area 11, and optionally, the hollowed-out area 31 overlaps the data line 20 of the first display area 11; in this way, the area of the overlapping region of the data line 20 and the common electrode 30 in the first display region 11 is reduced, the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the first display region 11 can be reduced, the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the first display region 11 and the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the second display region 12 are equal within the error allowance range, and further, the difference between the pixel charging voltage in the first display region 11 and the pixel charging voltage in the second display region 12 can be avoided, and the split phenomenon of the first display region 11 and the second display region 12 is avoided.
Optionally, as shown in fig. 3 and 4, along a direction D3 perpendicular to the light emitting surface of the display panel, the same data line 20 located in the first display area 11 corresponds to a plurality of hollow areas 31.
It should be noted that, the embodiment shown in fig. 3 only schematically illustrates the structure of the hollowed-out area 31, and does not represent the number and the size of the hollowed-out area 31.
Specifically, referring to fig. 3 and 4, in the present embodiment, along a direction D3 perpendicular to the light emitting surface of the display panel, the same data line 20 corresponds to the plurality of hollow areas 31; it may be understood that the plurality of hollow areas 31 corresponding to the same data line 20 in the common electrode 30 are arranged along the extending direction of the data line 20, and the plurality of hollow areas 31 can reduce the storage capacitance generated between the same data line 20 and the common electrode 30, further reduce the storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11, so that the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11 is equal to the size of the storage capacitance generated between the data line 20 and the common electrode 30 in the second display area 12, and the split phenomenon caused by the first display area 11 and the second display area 12 is avoided.
Optionally, as shown in fig. 3 and 4, along a direction D3 perpendicular to the light emitting surface of the display panel, the plurality of hollow areas 31 corresponding to the same data line 20 are uniformly arranged along the second direction D2.
Specifically, as shown in fig. 3 and 4, in the present embodiment, along a direction D3 perpendicular to the light emitting surface of the display panel, a plurality of hollow areas 31 corresponding to the same data line 20 are uniformly arranged along a second direction D2; further, the hollow areas 31 of the first display area 11 are uniformly arranged, so that on one hand, the process of the common electrode 30 can be accelerated, and the process of the display panel 100 can be saved; on the other hand, the storage capacitance generated between the same data line 20 and the common electrode 30 is uniform.
Alternatively, fig. 5 is a schematic diagram of another structure of the common electrode 30 provided in the embodiment of the present application, please refer to fig. 5, and refer to fig. 4, in which the same data line 20 located in the first display area 11 corresponds to a single hollowed-out area 31 along a direction D3 perpendicular to the light emitting surface of the display panel, and the hollowed-out area 31 extends along a second direction D2.
It should be noted that the embodiment shown in fig. 5 only schematically illustrates the structure of the single data line 20 corresponding to the single hollow area 31, and does not represent the size of the single hollow area 31.
Specifically, please refer to fig. 5, and referring to fig. 4, in the present embodiment, along a direction D3 perpendicular to the light emitting surface of the display panel, the same data line 20 corresponds to a single hollow area 31; it can be also understood that each data line 20 in the first display area 11 corresponds to one hollowed-out area 31, the number of hollowed-out areas 31 set in the first display area 11 is equal to the number of data lines 20, and the single hollowed-out area 31 can effectively save the processing time of the common electrode 30.
Optionally, fig. 6 is a schematic structural diagram of a dummy electrode pattern 41 provided in the embodiment of the present application, fig. 7 is a cross-sectional view along C-C' of the dummy electrode pattern 41 provided in the embodiment of fig. 6, please refer to fig. 6 and 7, which illustrate that the capacitance adjusting portion 40 includes a plurality of dummy electrode patterns 41 in the first display area 11, the dummy electrode patterns 41 are located between the common electrode 30 and the data line 20 along the direction D3 perpendicular to the light emitting surface of the display panel, and the dummy electrode patterns 41 overlap the data line 20 in the first display area 11.
It should be noted that, the embodiment shown in fig. 6 only schematically illustrates the relative positions of the virtual electrode patterns 41, and does not represent the actual dimensions; the embodiment shown in fig. 7 only schematically shows the relative positional relationship of the dummy electrode patterns 41 and the data lines 20, and does not represent the actual size.
Specifically, as shown in fig. 6 and 7, in the present embodiment, the capacitance adjusting portion 40 includes a plurality of dummy electrode patterns 41, the dummy electrode patterns 41 are located in the first display area 11 along the direction D3 perpendicular to the light emitting surface of the display panel, the dummy electrode patterns 41 are located between the common electrode 30 and the film layer where the data lines 20 are located, and the dummy electrode patterns 41 overlap the data lines 20 of the first display area 11, alternatively, the dummy electrode patterns 41 overlap the data lines 20 of the first display area 11; it can be understood that the dummy electrode plays a role of shielding, and the dummy electrode does not need to input a voltage signal, so that an overlapping area between the data line 20 and the common electrode 30 can be effectively reduced, a storage capacitance generated between the data line 20 and the common electrode 30 in the first display area 11 is reduced, and a split-screen phenomenon of the first display area 11 and the second display area 12 can be effectively improved.
Optionally, please continue to refer to fig. 6, and referring to fig. 7, the same data line 20 in the first display area 11 corresponds to a plurality of virtual electrode patterns 41 along a direction D3 perpendicular to the light emitting surface of the display panel.
It should be noted that, the embodiment shown in fig. 6 only schematically illustrates the structure of the dummy electrode patterns 41, and does not represent the number and the size of the hollowed-out areas 31.
Specifically, please refer to fig. 6, and referring to fig. 7, in this embodiment, along a direction D3 perpendicular to the light emitting surface of the display panel, the same data line 20 corresponds to a plurality of virtual electrode patterns 41, and the plurality of virtual electrode patterns 41 play a role in shielding, so that the overlapping area between the same data line 20 and the common electrode 30 is reduced, and further, the storage capacitance between the same data line 20 and the common electrode 30 is reduced, which can effectively adjust the pixel charging voltage difference between the first display area 11 and the second display area 12, and effectively improve the split-screen phenomenon between the first display area 11 and the second display area 12.
Alternatively, as shown in fig. 6, and in combination with fig. 7, along a direction D3 perpendicular to the light emitting surface of the display panel, the plurality of dummy electrode patterns 41 corresponding to the same data line 20 are uniformly arranged along the second direction D2.
Specifically, please refer to fig. 6, and referring to fig. 7, in the present embodiment, along a direction D3 perpendicular to the light emitting surface of the display panel, a plurality of virtual electrode patterns 41 corresponding to the same data line 20 are uniformly arranged along a second direction D2, on one hand, the virtual electrodes are uniformly arranged, so that the processing time of the display panel 100 can be effectively saved; on the other hand, the dummy electrodes are uniformly arranged, so that the shielding effect of the dummy electrodes is uniform, and further, the storage capacitance generated by the data line 20 and the common electrode 30 in the first display area 11 is uniform.
Optionally, fig. 8 is a schematic structural diagram of the first compensation electrode pattern 42 provided in the embodiment of the present application, fig. 9 is a sectional view along D-D' of the first compensation electrode pattern 42 provided in the embodiment of fig. 8, please refer to fig. 8 and fig. 9, and fig. 1 is combined to show that the capacitance adjusting portion 40 includes a plurality of first compensation electrode patterns 42, where the first compensation electrode patterns 42 are located on a side of a film layer where the data line 20 is located, which is away from the light-emitting surface of the display panel;
along the direction D3 perpendicular to the light emitting surface of the display panel, the first compensation electrode pattern 42 is located in the second display area 12, and the first compensation electrode pattern 42 overlaps the data line 20.
It should be noted that, the embodiment shown in fig. 8 only schematically illustrates the relative positional relationship of the first compensation electrode, and does not represent the actual size; the embodiment shown in fig. 9 only schematically shows the relative positional relationship of the first compensation electrode and the data line 20, and does not represent the actual size.
Specifically, as shown in fig. 8 and 9, and referring to fig. 1, in the present embodiment, the capacitance adjusting portion 40 includes a plurality of first compensation electrode patterns 42, where the first compensation electrode patterns 42 extend along the second direction D2 and are arranged along the first direction D1; along the direction D3 perpendicular to the light emitting surface of the display panel, the first compensation electrode pattern 42 is located in the second display area 12, the first compensation electrode pattern 42 is located at one side of the film layer where the data line 20 is located, which is away from the light emitting surface of the display panel, and the first compensation electrode pattern 42 overlaps the data line 20, optionally, the first compensation electrode pattern 42 overlaps the data line 20, and the first compensation electrode pattern 42 is connected with a fixed voltage, so that the first compensation electrode pattern 42 and the common electrode 30 generate a storage capacitor, which can compensate the pixel charging voltage of the second display area 12, and can effectively improve the split-screen phenomenon of the first display area 11 and the second display area 12.
Alternatively, as shown in fig. 8, the plurality of first compensation electrode patterns 42 are electrically connected to the 0V voltage.
Specifically, please continue to refer to fig. 8, in this embodiment, the first compensation electrode is connected in parallel and is electrically connected to the voltage of 0V; on the one hand, the first compensation electrodes are ensured to input the same voltage; on the other hand, the safety and reliability of the display panel 100 are ensured.
Alternatively, fig. 10 is a schematic diagram of another structure of the first compensation electrode pattern 42 according to the embodiment of the present application, please refer to fig. 10, in which the width of the first compensation electrode pattern 42 decreases along the first direction D1 along the direction in which the first display area 11 points to the second display area 12.
It should be noted that, the embodiment shown in fig. 10 only schematically illustrates a structural schematic diagram of the differential arrangement of the first compensation electrode, and does not represent the size of the first compensation electrode.
Specifically, please continue to refer to fig. 10, and fig. 9, and fig. 1, in this embodiment, the width of the first compensation electrode pattern 42 decreases along the first direction D1 along the direction in which the first display area 11 points to the second display area 12; it can be understood that the different first electrodes are differentiated according to the different loads of the data lines 20 of the second display area 12, and the wider the width of the first compensation electrode is, the larger the storage voltage is generated between the first compensation electrode and the common electrode 30, so that the split-screen phenomenon of the first display area 11 and the second display area 12 can be optimally improved.
Optionally, fig. 11 is a schematic structural diagram of another display panel 100 according to the embodiment of the present application, fig. 12 is a schematic structural diagram of a second compensation electrode pattern 43 according to the embodiment of the present application, fig. 13 is a cross-sectional view along E-E' of the second compensation electrode pattern 43 according to the embodiment of fig. 12, please refer to fig. 11-13, and further includes: a scanning line 50, the scanning line 50 extending along a first direction D1 and being arranged along a second direction D2; the scan line 50 includes a first scan line 51 and a second scan line 52, the first scan line 51 having a length smaller than that of the second scan line 52;
the capacitance adjusting portion 40 includes a plurality of second compensation electrode patterns 43, and the second compensation electrode patterns 43 are located at one side of the film layer where the scan lines 50 are located, which is away from the light emitting surface of the display panel 100;
along the direction D3 perpendicular to the light emitting surface of the display panel, the second compensation electrode pattern 43 overlaps the first scan line 51.
It should be noted that, the embodiment shown in fig. 11 only schematically illustrates the relative contrast relationship between the first scan line 51 and the second scan line 52, and the relative dimensional relationship, and does not represent the actual dimension; the embodiment shown in fig. 12 only schematically shows the relative positional relationship of the second compensation electrode pattern 43, and does not represent the actual size; the embodiment shown in fig. 13 only schematically shows the relative positional relationship of the second compensation electrode pattern 43 and the first scan line 51, and does not represent the actual size.
Specifically, as shown in fig. 11 to 13, the display panel 100 in the present embodiment further includes scan lines 50, where the scan lines 50 extend along a first direction D1 and are arranged along a second direction D2; alternatively, the scan line 50 includes a first scan line 51 and a second scan line 52, the first scan line 51 having a length smaller than that of the second scan line 52, thereby resulting in a load of the first scan line 51 being different from that of the second scan line 52; further, the capacitance adjusting portion 40 in the present embodiment includes a plurality of second compensation electrode patterns 43 extending in the first direction D1 and arranged in the second direction D2; along the direction D3 perpendicular to the light-emitting surface of the display panel, the second compensation electrode pattern 43 is located on the side of the film layer where the scan line 50 is located, which is away from the light-emitting surface of the display panel 100, and the second compensation electrode pattern 43 overlaps the first scan line 51; alternatively, the second compensation electrode pattern 43 overlaps the first scan line 51; in this way, the capacitance generated between the data line 20 and the second compensation electrode in the second display area 12 can be effectively compensated, and the split screen phenomenon of the first display area 11 and the second display area 12 can be effectively improved.
Alternatively, as shown in fig. 12, the plurality of second compensation electrode patterns 43 are electrically connected to the 0V voltage.
Specifically, please continue to refer to fig. 12, in this embodiment, the second compensation electrode is connected in parallel and is electrically connected to the voltage of 0V; on the one hand, the first compensation electrodes are ensured to input the same voltage; on the other hand, the safety and reliability of the display panel 100 are ensured.
Alternatively, fig. 14 is a schematic diagram of another structure of the second compensation electrode pattern 43 provided in the embodiment of the present application, please refer to fig. 14, and in combination with fig. 13, the width of the second compensation electrode pattern 43 along the second direction D2 decreases along the direction of the second scan line 52 pointing to the first scan line 51.
It should be noted that, the embodiment shown in fig. 14 only schematically illustrates a structural schematic diagram of the differential arrangement of the second compensation electrode, and does not represent the dimensions of the second compensation electrode.
Specifically, as shown in fig. 14, and in conjunction with fig. 13, in this embodiment, the width of the second compensation electrode pattern 43 along the second direction D2 decreases along the direction of the second scan line 52 pointing to the first scan line 51, which can be understood that the wider the width of the second compensation electrode near the scan line 50 with a larger length, the larger the storage voltage generated between the second compensation electrode pattern and the common electrode 30, the better the split screen phenomenon in different areas can be improved.
Optionally, fig. 15 is a schematic diagram of another structure of the display panel 100 according to the embodiment of the present application, please continue to refer to fig. 15, and further includes: a color film substrate 60, an array substrate 70, and a liquid crystal 80 between the color film substrate 60 and the array substrate 70;
the color film substrate 60 is provided with a light shielding layer 90;
the first compensation electrode pattern 42 and the second compensation electrode pattern 43 are both located on the array substrate 70; the first compensation electrode pattern 42 and the second compensation electrode pattern 43 overlap the light shielding layer 90 along a direction D3 perpendicular to the light emitting surface of the display panel.
Specifically, as shown in fig. 15, the display panel 100 in the present embodiment further includes a color film substrate 60, an array substrate 70, and a liquid crystal 80 disposed between the color film substrate 60 and the array substrate 70; the color film substrate 60 is provided with a shading layer 90, and the first compensation electrode pattern 42 and the second compensation electrode pattern 43 are both positioned on the array substrate 70; along the direction D3 perpendicular to the light emitting surface of the display panel, the first compensation electrode pattern 42 overlaps the light shielding layer 90, and the second compensation electrode pattern 43 overlaps the light shielding layer 90; thus, the first compensation electrode, the second compensation electrode and the light shielding layer 90 can share the same mask, so that the processing time of the display panel 100 can be effectively saved.
It should be noted that, the color film substrate 60 in this embodiment further includes red pixels, green pixels and blue pixels, and a black matrix is disposed between adjacent pixels; the array substrate 70 in this embodiment further includes a TFT thin film transistor and an insulating layer, which are not specifically mentioned herein.
Based on the same inventive concept, fig. 16 is a schematic structural diagram of a display device 200 provided in an embodiment of the present application, please refer to fig. 16, and further provides a display device 200, where the display device 200 includes a display panel 100, and the display panel 100 is the display panel 100 provided in any of the above embodiments of the present application, and the repetition is omitted.
It should be noted that, in the embodiments of the display device 200 provided in the embodiments of the present application, reference may be made to the embodiments of the display panel 100, and the display device 200 of the present application uses the liquid crystal display panel 100 (Liquid Crystal Display) device as an example, and the repetition is omitted. The display device 200 provided in the present application may be: any product or component with realistic functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
According to the embodiments, the beneficial effects of the application are as follows:
the display panel and the display device provided by the application can adjust the size of the storage capacitor generated between the data line and the common electrode in the first display area, can also adjust the size of the storage capacitor generated between the data line and the common electrode in the second display area, and can also adjust the size of the storage capacitor generated between the data line and the common electrode in the first display area and the second display area at the same time so as to compensate for bad display effects caused by pixel charging voltage differences in different display areas due to the length differences of the data lines in the first display area and the second display area; therefore, the charging voltage of each pixel in the first display area and the second display area can be regulated, so that the storage capacitance generated between the data lines in the first display area and the second display area and the common electrode is consistent within the error allowable range, and the split screen phenomenon generated in the first display area and the second display area can be effectively avoided.
While the foregoing description illustrates and describes the preferred embodiments of the present application, it is to be understood that this application is not limited to the forms disclosed herein, but is not to be construed as an exclusive use of other embodiments, and is capable of many other combinations, modifications and environments, and adaptations within the scope of the inventive concept described herein, through the foregoing teachings or through the skill or knowledge of the relevant arts. And that modifications and variations which do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.
Claims (17)
1. A display panel, comprising: the display device comprises a T-shaped display area, a first display area and a second display area, wherein the T-shaped display area comprises a first display area and 2 second display areas adjacent to the first display area; the second display areas are respectively positioned at two sides of the first display area along the first direction; the length of the first display area is longer than that of the second display area along the second direction; the first direction and the second direction intersect;
a plurality of data lines arranged along a first direction and extending along a second direction; the length of the data line in the first display area is longer than that of the data line in the second display area;
the common electrode is positioned on one side of the film layer where the data line is positioned, which is close to the light-emitting surface of the display panel;
and a capacitance adjusting part for adjusting a storage capacitance generated between the data line and the common electrode in the first display region and/or the second display region.
2. The display panel according to claim 1, wherein a plurality of hollowed-out areas are provided in the common electrode in the first display area, and the common electrode provided with the hollowed-out areas is multiplexed as the capacitance adjusting portion; along the direction perpendicular to the light-emitting surface of the display panel, the hollowed-out area is overlapped with the data line of the first display area.
3. The display panel according to claim 2, wherein the same data line in the first display area corresponds to a plurality of the hollow areas along a direction perpendicular to the light emitting surface of the display panel.
4. The display panel according to claim 3, wherein the plurality of hollowed-out areas corresponding to the same data line are uniformly arranged along the second direction along a direction perpendicular to the light-emitting surface of the display panel.
5. The display panel according to claim 2, wherein the same data line located in the first display area corresponds to a single hollowed-out area along a direction perpendicular to the light emitting surface of the display panel, and the hollowed-out area extends along a second direction.
6. The display panel according to claim 1, wherein the capacitance adjusting portion includes a plurality of dummy electrode patterns in the first display region, the dummy electrode patterns being located between the common electrode and the film layer where the data lines are located in a direction perpendicular to the light emitting surface of the display panel, the dummy electrode patterns overlapping the data lines of the first display region.
7. The display panel according to claim 6, wherein the same data line in the first display area corresponds to a plurality of the dummy electrode patterns along a direction perpendicular to the light-emitting surface of the display panel.
8. The display panel according to claim 7, wherein the plurality of dummy electrode patterns corresponding to the same data line are uniformly arranged along the second direction along a direction perpendicular to the light-emitting surface of the display panel.
9. The display panel according to claim 1, wherein the capacitance adjusting portion includes a plurality of first compensation electrode patterns, the first compensation electrode patterns being located at a side of the film layer where the data lines are located, the side facing away from the light emitting surface of the display panel;
along the direction perpendicular to the light emitting surface of the display panel, the first compensation electrode pattern is located in the second display area, and the first compensation electrode pattern overlaps the data line.
10. The display panel of claim 9, wherein a plurality of the first compensation electrode patterns are electrically connected to a voltage of 0V.
11. The display panel of claim 9, wherein the first compensation electrode pattern decreases in width in a first direction along a direction in which the first display region points toward the second display region.
12. The display panel of claim 1, further comprising: the scanning lines extend along a first direction and are arranged along a second direction; the scanning lines comprise first scanning lines and second scanning lines, and the length of the first scanning lines is smaller than that of the second scanning lines;
the capacitance adjusting part comprises a plurality of second compensation electrode patterns, and the second compensation electrode patterns are positioned at one side of the film layer where the scanning lines are positioned, which is away from the light emitting surface of the display panel;
and the second compensation electrode pattern is overlapped with the first scanning line along the direction vertical to the light emitting surface of the display panel.
13. The display panel of claim 12, wherein a plurality of the second compensation electrode patterns are electrically connected to a voltage of 0V.
14. The display panel of claim 12, wherein the second compensation electrode pattern decreases in width in a second direction along a direction in which the second scan line points to the first scan line.
15. The display panel of claim 9, further comprising: the liquid crystal display comprises a color film substrate, an array substrate and liquid crystal positioned between the color film substrate and the array substrate;
a shading layer is arranged in the color film substrate;
the first compensation electrode pattern is positioned on the array substrate; along the direction perpendicular to the light emitting surface of the display panel, the first compensation electrode pattern overlaps the light shielding layer.
16. The display panel of claim 12, further comprising: the liquid crystal display comprises a color film substrate, an array substrate and liquid crystal positioned between the color film substrate and the array substrate;
a shading layer is arranged in the color film substrate;
the second compensation electrode patterns are all positioned on the array substrate; and the second compensation electrode pattern is overlapped with the shading layer along the direction vertical to the light emitting surface of the display panel.
17. A display device comprising a display panel according to any one of claims 1-16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111168481.3A CN113885262B (en) | 2021-09-29 | 2021-09-29 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111168481.3A CN113885262B (en) | 2021-09-29 | 2021-09-29 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113885262A CN113885262A (en) | 2022-01-04 |
| CN113885262B true CN113885262B (en) | 2023-12-29 |
Family
ID=79005438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111168481.3A Active CN113885262B (en) | 2021-09-29 | 2021-09-29 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113885262B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115376416A (en) * | 2022-09-15 | 2022-11-22 | 厦门天马微电子有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020004278A (en) * | 2000-07-04 | 2002-01-16 | 구본준, 론 위라하디락사 | Liquid Crystal Display |
| JP2012042909A (en) * | 2010-08-19 | 2012-03-01 | Samsung Mobile Display Co Ltd | Liquid crystal display device integrated with touch screen panel |
| KR20130030128A (en) * | 2011-09-16 | 2013-03-26 | 엘지디스플레이 주식회사 | Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same |
| CN109584833A (en) * | 2019-01-21 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112764281A (en) * | 2021-01-28 | 2021-05-07 | Tcl华星光电技术有限公司 | Array substrate and display panel |
-
2021
- 2021-09-29 CN CN202111168481.3A patent/CN113885262B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020004278A (en) * | 2000-07-04 | 2002-01-16 | 구본준, 론 위라하디락사 | Liquid Crystal Display |
| JP2012042909A (en) * | 2010-08-19 | 2012-03-01 | Samsung Mobile Display Co Ltd | Liquid crystal display device integrated with touch screen panel |
| KR20130030128A (en) * | 2011-09-16 | 2013-03-26 | 엘지디스플레이 주식회사 | Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same |
| CN109584833A (en) * | 2019-01-21 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112764281A (en) * | 2021-01-28 | 2021-05-07 | Tcl华星光电技术有限公司 | Array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113885262A (en) | 2022-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10644038B2 (en) | Array substrate, display panel, and display device thereof | |
| CN111090202B (en) | Display panel and display device | |
| US8711317B2 (en) | Color image display device, color filter substrate, color pixel array substrate, and electronic device | |
| CN106773394B (en) | Array substrate, display panel and display device | |
| CN108563081B (en) | Display panel | |
| US8248552B2 (en) | Pixel array, polymer stabilized alignment liquid crystal display panel, and electro-optical apparatus | |
| CN109449167B (en) | Display panel and display device | |
| CN108445684A (en) | Array substrate, display panel and display device | |
| US10290273B2 (en) | Display pixel structure, array substrate, and display device | |
| US6956548B2 (en) | Display device | |
| US8508704B2 (en) | Pixel array | |
| US11778863B2 (en) | Display substrate, method for manufacturing display substrate, and display device | |
| US7514713B2 (en) | Liquid crystal display panel | |
| CN113985671B (en) | Array substrate and display device | |
| EP2757411B1 (en) | Array substrate and liquid crystal display panel | |
| US20210080791A1 (en) | Display device and display panel thereof, and manufacturing method for display device | |
| US10847109B2 (en) | Active matrix substrate and display panel | |
| US20210325740A1 (en) | Array substrate and display device | |
| CN113885262B (en) | Display panel and display device | |
| CN115497410A (en) | Display panel and display device | |
| CN108181750B (en) | Flexible display panel and flexible display device | |
| US20200319519A1 (en) | Liquid crystal display panel | |
| CN108711370B (en) | Display panel and display device thereof | |
| CN114994989B (en) | Array substrate and display device | |
| US11257879B2 (en) | Display panels and display devices thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |