CN210323697U

CN210323697U - Display panel, chip on film and display device

Info

Publication number: CN210323697U
Application number: CN201920884275.4U
Authority: CN
Inventors: 李嘉航; 温海霞; 顾毓波
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2019-06-11
Filing date: 2019-06-11
Publication date: 2020-04-14
Anticipated expiration: 2029-06-11

Abstract

The application discloses a display panel, a chip on film and a display device, wherein the display panel comprises a substrate, a chip on film, a first lead and a second lead; the display panel includes a display area and a non-display area. The first wires and the second wires are arranged correspondingly, the substrate and the chip on film are electrically connected through one-to-one corresponding binding of the first wires and the second wires, and the second wires are fanned out on a non-display area of the substrate to form a fanout area; the first leads form a parallel area for adjusting the resistance value of the first leads on the chip on film, and the parallel area comprises a plurality of first outgoing lines and at least one parallel part. The first outgoing lines correspond to the second leads one by one and are bound with the second leads; the parallel portion is connected with the corresponding first outgoing line, the parallel portion comprises at least two parallel leads, and the number of the parallel leads of each first lead is reduced from the two ends of the parallel area to the middle.

Description

Display panel, chip on film and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel, a chip on film and a display device.

Background

With the development and progress of science and technology, the display panel has a thin body, low power consumption, low radiation and other hot spots, so that the display panel becomes a mainstream product of the display and is widely applied. The Display panel includes a Thin film transistor-Liquid Crystal Display (TFT-LCD). The thin film transistor liquid crystal display refracts light rays of the backlight module to generate pictures by controlling the rotation direction of liquid crystal molecules, and has the advantages of thin body, electricity saving, no radiation and the like.

The display panel comprises a chip on film and a substrate. The substrate is provided with a plurality of wires such as scanning wires, data wires and the like, and the wires are connected with the chip on film in a binding manner in a non-display area of the substrate. The wires connected to the flip-chip usually have different lengths, which causes uneven impedance of each wire and affects the signal transmission quality.

SUMMERY OF THE UTILITY MODEL

The present application provides a display panel, a flip chip film and a display device, which have uniform impedance and improved signal transmission quality.

The application discloses a display panel, which comprises a substrate, a chip on film, a plurality of first wires and a plurality of second wires, wherein the chip on film is arranged on the periphery of the substrate and drives a display area of the substrate; the display panel includes a display area and a non-display area.

The first wires and the second wires are arranged correspondingly, the substrate and the chip on film are electrically connected through one-to-one corresponding binding of the first wires and the second wires, and the second wires are fanned out on a non-display area of the substrate to form a fanout area;

the first leads form a parallel area for adjusting the resistance value of the first leads on the chip on film, and the parallel area comprises a plurality of first outgoing lines and at least one parallel part. The first outgoing lines correspond to the second leads one by one and are bound with the second leads; the parallel portion is connected with the corresponding first outgoing line, the parallel portion comprises at least two parallel leads,

wherein the number of parallel leads of each first wire decreases from the two ends of the parallel region to the middle.

Optionally, the chip on film includes a chip and a flexible printed circuit board, the chip is disposed on the flexible printed circuit board, the parallel portion of the parallel region is disposed on the flexible printed circuit board, one end of the parallel portion is electrically connected to the chip, and the other end of the parallel portion is connected to the first outgoing line.

Optionally, the flexible printed circuit board has at least two layers, in each parallel connection portion, the first conducting wires in odd-numbered columns are arranged in one layer, and the first conducting wires in even-numbered columns are arranged in the other layer.

Optionally, the flexible printed circuit board has at least two layers, the parallel connection parts of the odd-numbered columns are arranged on one layer, and the parallel connection parts of the even-numbered columns are arranged on the other layer.

Optionally, the chip on film includes a chip and a flexible circuit board, the chip is disposed on the flexible circuit board, the first wire is fanned out on the flexible circuit board to form a circuit board fanout area, and the parallel portion of the parallel area is disposed on the flexible circuit board; the first conducting wire comprises a first fan-out lead and is formed in the circuit board fan-out area;

one end of a first fan-out lead of the circuit board fan-out area is connected with the chip, the other end of the first fan-out lead is correspondingly connected with the parallel part, and the other end of the parallel part is correspondingly connected with the first outgoing line; the first fan-out lead of at least one first wire in the middle of the parallel connection area is directly connected with the first outgoing line.

Optionally, the chip on film includes a chip and a flexible printed circuit board, the chip is disposed on the flexible printed circuit board, the parallel portion of the parallel region is disposed in the chip, and one end of the parallel portion is connected to the chip pin through the first outgoing line.

Optionally, the parallel portion includes a straight line segment and a curved curve segment, the curve segment and the straight line segment have at least two connection points to form a parallel lead, and a parallel lead is formed at one end close to the chip, and the curved density of the curve segment gradually increases from a side far away from the chip to a side close to the chip.

Optionally, the parallel connection part is rectangular, and the first wires of the parallel connection part are parallel to each other and have two ends communicated with each other.

The application also discloses a cover glass film for above-mentioned display panel, be provided with many first wires on the cover glass film, first wire with the second wire corresponds the setting, the base plate passes through with the cover glass film the one-to-one of first wire and second wire is bound and is realized electric connection, and is many the second wire is in fan-out formation fan-out area on the non-display area of base plate.

The first wires form a parallel area for adjusting the resistance of the first wires on the chip on film, and the parallel area comprises: the first lead wires are in one-to-one correspondence with the second lead wires, the first lead wires are bound with the second lead wires, and at least one parallel portion is connected with the corresponding first lead wires and comprises at least two parallel lead wires. Wherein the number of parallel leads of each first wire decreases from the two ends of the parallel region to the middle.

The application also discloses a display device, which comprises the display panel.

Because the substrate and the chip on film are bound through the one-to-one correspondence of the first wires and the second wires to realize the electrical connection, the resistance value can be adjusted through the parallel connection part with the parallel leads, the number of the parallel leads is reduced from the two sides to the middle of the parallel connection area, the more the number of the parallel leads is, the smaller the overall resistance value of the leads is, and the overall resistance value difference of the wires at the two ends and the middle wire of the fan-out area on the substrate is balanced. Meanwhile, the parallel connection part is arranged on the chip on film, so that the space of the chip on film is fully utilized, the wire density of a non-display area on the substrate is reduced, the film layer is coated uniformly, and the quality of the display panel is improved.

Drawings

The accompanying drawings, which are included to provide an alternative understanding of embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application;

FIG. 3 is an enlarged schematic view of section A of FIG. 2 of the present application;

FIG. 4 is a schematic diagram of a parallel portion disposed on a chip according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a parallel portion of an embodiment of the present application;

fig. 6 is another schematic diagram of a parallel portion of an embodiment of the present application.

Wherein, 1, a display device; 10. a display panel; 100. a substrate; 110. a display area; 120. a non-display area; 200. a chip on film; 210. a chip; 220. a flexible circuit board; 300. a first conductive line; 310. a first outgoing line; 320. a parallel connection section; 321. a straight line segment; 322. a curve segment; 323. folding the line segment; 330. a first fan-out lead; 400. a second conductive line; 500. a fan-out region; 600. a parallel region; 700. and a circuit board fan-out area.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.

Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The present application is described in detail below with reference to the figures and alternative embodiments.

Fig. 3 is an enlarged schematic view of a portion a in fig. 2, which is an embodiment of the present application, such as the display device shown in fig. 1 and the display panel shown in fig. 2. Specifically, a display device is disclosed, wherein the display device 1 includes a display panel 10, and the display panel 10 includes a substrate 100, a chip on film disposed around the substrate 100 and driving a display area 110 of the substrate 100, a plurality of first wires 300 disposed on the chip on film, and a plurality of second wires 400 disposed on a non-display area 120 of the substrate 100; the display panel 10 includes a display area 110 and a non-display area 120.

The first wires 300 and the second wires 400 are arranged correspondingly, the substrate 100 and the flip chip package are electrically connected by one-to-one corresponding binding of the first wires 300 and the second wires 400, and the plurality of second wires 400 are fanned out on the non-display area 120 of the substrate 100 to form a fanout area 500;

the plurality of first wires 300 form a parallel area 600 for adjusting the resistance of the first wires 300 on the chip on film, and the parallel area 600 includes a plurality of first outgoing lines 310310 and at least one parallel portion 320. The first outgoing lines 310310 correspond to the second wires 400 one by one and are tied to the second wires 400; the parallel portion 320 is connected to the corresponding first outgoing line 310310, the parallel portion 320 includes at least two parallel leads,

wherein the number of parallel leads of each first conductive line 300 decreases from both ends of the parallel region 600 to the middle. That is, the number of parallel leads of the first wire 300 at both ends of the parallel connection region 600 is greater than the number of parallel leads of the first wire 300 in the middle of the parallel connection region 600.

In the binding region of the display panel 10, the wires of the fan-out region 500 gradually lengthen from the middle of the fan-out region 500 to the wires at both ends, and the longer the wire is, the larger the resistance value of the wire is, and the different impedances between the wires are different, so that the difference exists when the wires transmit signals, which affects the display effect. The lengths of the conductive lines are generally adjusted by bending the conductive lines in the bonding region to balance the resistance values between the conductive lines. Since the space of the bonding area is very limited, the implementation design difficulty is high, and meanwhile, due to the excessive arrangement of the wires, the non-display area 120 on the substrate 100 is not uniformly coated with the film due to the excessive density of the wires, which affects the quality of the display panel 10.

Because the substrate 100 and the flip chip package are electrically connected by the one-to-one binding of the first wires 300 and the second wires 400, the resistance value of the substrate 100 and the flip chip package can be adjusted by the parallel portion 320 with the parallel leads, the number of the parallel leads is reduced from the two sides to the middle of the parallel area 600, the more the number of the parallel leads is, the smaller the overall resistance value of the leads is, and the overall resistance value difference between the leads at the two ends and the middle leads of the fan-out area 500 on the substrate 100 can be balanced. Meanwhile, the parallel portion 320 is disposed on the cover glass, so as to fully utilize the space of the cover glass, reduce the wire density of the non-display area 120 on the substrate 100, facilitate the uniform coating of the film layer, and improve the quality of the display panel 10.

Specifically, the chip on film further includes a chip 210 and a flexible circuit board 220, the chip 210 is disposed on the flexible circuit board 220, the parallel portion 320 of the parallel region 600 is disposed on the flexible circuit board 220, one end of the parallel portion 320 is electrically connected to the chip 210, and the other end is connected to the first outgoing line 310310. The space above the flexible printed circuit 220 is large, and the parallel connection part 320 is arranged on the flexible printed circuit 220, so that the space of the flexible printed circuit 220 can be fully utilized, and the design difficulty is reduced.

The flexible printed circuit 220 may have at least two layers, and in each of the parallel portions 320, the first conductive lines 300 in odd-numbered columns are disposed in one layer, and the first conductive lines 300 in even-numbered columns are disposed in another layer, and the first conductive lines 300 located in different layers are electrically connected. The first conductive lines 300 inside the parallel portion 320 are respectively disposed at different layers, and the density of the first conductive lines 300 per layer is reduced. Optionally, the first conductive lines 300 located in different layers may be correspondingly overlapped, so as to reduce the space occupied by the first conductive lines 300 as a whole.

The flexible circuit board 220 has at least two layers, the parallel connection parts 320 in odd-numbered columns are disposed in one layer, and the parallel connection parts 320 in even-numbered columns are disposed in the other layer. Each parallel portion 320 is arranged on the same layer as a whole, and disconnection is not easy to occur. Meanwhile, the structure is simple and the design difficulty is small.

The chip on film comprises a chip 210 and a flexible circuit board 220, wherein the chip 210 is arranged on the flexible circuit board 220, the first conducting wire 300 is fanned out on the flexible circuit board 220 to form a circuit board fanout area 700, and the parallel part 320 of the parallel area 600 is arranged on the flexible circuit board 220; the first conductor 300 includes a first fan-out lead 330 formed in the board fan-out area 700; one end of a first fan-out lead 330 of the circuit board fan-out area 700 is connected with the chip 210, the other end of the first fan-out lead is correspondingly connected with the parallel part 320, and the other end of the parallel part 320 is correspondingly connected with the first outgoing line 310310; the first fan-out lead 330 of at least one of the first conductors 300 in the middle of the parallel region 600 is directly connected to the first outgoing line 310310. First fan-out lead 330 is at circuit board fan-out area 500 fan-out, and through setting up circuit board fan-out area 700, parallel portion 320 is connected with chip 210 through circuit board fan-out area 500, and under the certain condition of chip 210 horizontal width, the horizontal space of arranging of increase parallel portion 320 reduces the design degree of difficulty of parallel portion 320, the space of make full use of flexible line way board 220.

The parallel portion 320 may have a rectangular shape, and the first conductive lines 300 of the parallel portion 320 are parallel to each other and have both ends connected. The first wire 300 has simple routing rule, is convenient for etching and wiring, and is beneficial to uniform coating of the film layer.

The parallel portions 320 have the same length, the coating is uniform, and the parallel portions 320 also have the length such that when the resistance of the second conductive line 400 of the substrate 100 is adjusted, only the number of parallel portions is considered, and the difference in resistance caused by the length inconsistency of the parallel portions 320 is not considered, so that the adjustment of the resistance is simple.

The interval between the first conductive lines 300 in the parallel portion 320 may be equal to the interval between the whole of each parallel portion 320. The first wires 300 in the whole parallel area 600 are uniformly distributed, the film layer is uniformly coated, and the influence among the first wires 300 is consistent, which is beneficial to the stability and consistency of signal transmission.

At least one of the first wires 300 in the middle of the parallel portion 320 is directly connected to the chip 210 and the second wire 400, and is a straight line, that is, the parallel portion 320 is not provided in at least one of the first wires 300 in the middle of the parallel portion 320.

Specifically, when the total number of the first conductive lines 300 in the parallel portion 320 is odd, the middle one of the first conductive lines 300 is a straight line, and the resistance value is adjusted based on the middle one of the first conductive lines 300, and the middle one of the first conductive lines 300 does not need to be connected in parallel, so that the space is saved, and the operation is simple.

Similarly, when the total number of the first wires 300 in the parallel portion 320 is even, the two first wires 300 at the middle are straight lines, and the resistance value is adjusted by using the first two wires at the middle as a reference, the two first wires 300 at the middle do not need to be arranged in parallel, so that the space is saved, and the operation is simple.

As shown in fig. 4, the parallel portion 320 of the parallel region 600 may be provided in the chip 210, and one end of the parallel portion 320 may be connected to the chip 210 pin through the first lead line 310310. Because the COF is flexible and easy to bend, and the parallel portion 320 has more first wires 300 and a more complex structure, the parallel portion 320 is integrated inside the chip 210, which can protect the parallel portion 320, and the parallel portion 320 is not easy to have the conditions of open circuit, open circuit or poor contact.

As shown in fig. 5, the parallel portion 320 may also include a straight line segment 321 and a curved line segment 322, where the curved line segment 322 and the straight line segment 321 have at least two connection points to form a parallel lead, and a parallel lead is formed at an end close to the chip 210, and a bending density of the curved line segment 322 gradually increases from a side away from the chip 210 to a side close to the chip 210. The parallel connection quantity of the parallel connection parts 320 is adjusted by adjusting the length of the straight line segments 321, the longer the straight line segments 321 are, the more the parallel connection quantity is, under the condition that the parallel connection quantity required to be achieved is certain, the bending density of one side close to the chip 210 is large, the length of the used straight line segments 321 is reduced, and the resistance value of the parallel connection parts 320 is favorably reduced. The straight line segment 321 and the curved line segment 322 of the parallel portion 320 shown in fig. 5 can also make full use of the vertical space, compared to that shown in fig. 4.

As shown in fig. 6, the parallel portion 320 may include a straight line segment 321 and a bent broken line segment 323, where the broken line segment 323 has at least two connection points with the straight line segment 321 to form a parallel lead, and the parallel lead is formed at one end close to the chip 210. Similarly, the broken line segment 323 may be set to have a bending density gradually increasing from the side away from the chip 210 to the side close to the chip 210. Compared to that shown in figure 4. Similarly, the parallel connection portion 320 shown in fig. 6 is a straight line segment 321 and a bent broken line segment 323, which can also make full use of the vertical space.

As another embodiment of the present application, a chip on film for the above display panel is further disclosed, the chip on film is provided with a plurality of first wires 300, the first wires 300 and the second wires 400 are correspondingly arranged, the substrate 100 and the chip on film are bound to each other through the one-to-one correspondence between the first wires 300 and the second wires 400 to realize electrical connection, and the second wires 400 are fanned out to form a fanout area 500 on the non-display area 120 of the substrate 100.

The plurality of first wires 300 form a parallel area 600 for adjusting the resistance of the first wires 300 on the chip on film, and the parallel area 600 includes: a plurality of first outgoing lines 310310 corresponding to the second conductive lines 400 one by one and bound to the second conductive lines 400, and at least one parallel portion 320 connected to the corresponding first outgoing line 310310, the parallel portion 320 including at least two parallel leads. Wherein the number of parallel leads of each first conductive line 300 decreases from both ends of the parallel region 600 to the middle.

The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-emitting diode) display panel, and the above solution can be applied thereto.

The foregoing is an alternative detailed description of the present application in conjunction with specific alternative embodiments, and the specific implementations of the present application should not be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.

Claims

1. A display panel, comprising:

a substrate including a display region and a non-display region;

the chip on film is arranged on the periphery of the substrate and drives the display area of the substrate;

a plurality of first wires arranged on the chip on film; and

a plurality of second wires disposed on the non-display region of the substrate;

the first wires form a parallel area for adjusting the resistance of the first wires on the chip on film, and the parallel area comprises:

the first outgoing lines correspond to the second leads one by one and are bound with the second leads; and

at least one parallel portion connected to the corresponding first outgoing line, the parallel portion including at least two parallel leads;

2. The display panel according to claim 1, wherein the chip on film includes a chip and a flexible wiring board, the chip is disposed on the flexible wiring board, a parallel portion of the parallel region is disposed on the flexible wiring board, one end of the parallel portion is electrically connected to the chip, and the other end is connected to the first lead line.

3. The display panel according to claim 2, wherein the flexible wiring board has at least two layers, and in each of the parallel connection portions, the first conductive lines of odd-numbered columns are provided in one of the layers, and the first conductive lines of even-numbered columns are provided in the other layer.

4. The display panel according to claim 2, wherein the flexible wiring board has at least two layers, the parallel portions of odd-numbered columns are provided in one layer, and the parallel portions of even-numbered columns are provided in the other layer.

5. The display panel of claim 1, wherein the flip-chip includes a chip and a flexible wiring board, the chip is disposed on the flexible wiring board, the first conductive lines are fanned out on the flexible wiring board to form a wiring board fanout area, and a parallel portion of the parallel area is disposed on the flexible wiring board;

the first conducting wire comprises a first fan-out lead and is formed in the circuit board fan-out area;

one end of a first fan-out lead of the circuit board fan-out area is connected with the chip, the other end of the first fan-out lead is correspondingly connected with the parallel part, and the other end of the parallel part is correspondingly connected with the first outgoing line;

the first fan-out lead of at least one first wire in the middle of the parallel connection area is directly connected with the first outgoing line.

6. The display panel of claim 1, wherein the chip on film comprises a chip and a flexible circuit board, the chip is disposed on the flexible circuit board, the parallel portion of the parallel region is disposed in the chip, and one end of the parallel portion is connected to a chip pin through the first outgoing line.

7. The display panel according to claim 2, wherein the parallel portion comprises a straight line segment and a curved line segment, the curved line segment and the straight line segment have at least two connection points to form a parallel lead, the parallel lead is formed at an end close to the chip, and the curved line segment has a bending density gradually increasing from a side away from the chip to a side close to the chip.

8. The display panel according to claim 2, wherein the parallel portion has a rectangular shape, and the first conductive lines of the parallel portion are parallel to each other and have both ends connected to each other.

9. A chip on film for use in the display panel of claim 1, wherein the chip on film is provided with a plurality of first wires, the first wires are arranged corresponding to the second wires, the substrate and the chip on film are electrically connected by one-to-one corresponding binding of the first wires and the second wires, and the plurality of second wires are fanned out in the non-display area of the substrate to form a fanout area;

10. A display device characterized in that it comprises a display panel according to any one of claims 1 to 8.